Quantum random number generator with crypto engine

Abstract

The invention relates to a random number generator (RNG) comprising an internal random number generator (iRG), a crypto engine (CE), and a data bus interface (DBIF) for a data bus (DB), and configured to generate a random bit data stream (RBS) whose random bits have random logical values ​​as defined by the NIST test. (Andrew Rukhin, Juan Soto, James Nechvatal, Miles Smid, Elaine Barker, Stefan Leigh, Mark Levenson, Mark Vangel, David Banks, Alan Heckert, James Dray, San Vo, "A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications," Special Publication 800-22 Revision 1a; National Institute of Standards and Technology; Technology Administration; US Department of Commerce; Revised: April 2010, Lawrence E. Bassham III)

Description

Field of invention

[0001] The invention is directed to a random number generator (ZZG) comprising an inner random number generator (iZG) and a crypto engine (KE) and a data bus interface (DBIF) for a data bus (DB) and which is configured to generate a random bit data stream (ZBS) whose random bits have random logical values ​​in the sense of the NIST test.

[0002] Andrew Rukhin, Juan Soto, James Nechvatal, Miles Smid, Elaine Barker, Stefan Leigh, Mark Levenson, Mark Vangel, David Banks, Alan Heckert, James Dray, San Vo "A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications" Special Publication 800-22 Revision 1a; National Institute of Standards and Technology; Technology Administration; US Department of Commerce; Revised:April 2010, Lawrence E Bassham III Preliminary remarks

[0003] The random number generator as described below includes an internal random number generator, the crypto engine and the data bus interface as well as various peripheral components such as voltage regulators, JTAG test interfaces, etc.

[0004] It is assumed that the inner random number generator comprises a quantum random number generator, and that the quantum random number generator comprises an entropy source fabricated monolithically in a semiconductor substrate, which in turn comprises a single-photon source and a photon detector. This enables, firstly, micro- and co-integration and a high random bit rate for encryption.

[0005] Such a respective hardware-based quantum random number generator comprises an entropy source manufactured monolithically in a semiconductor substrate, which comprises a single-photon source and a photon detector arranged perpendicular to each other and to the surface of the respective semiconductor substrate, which enables a particularly high random number data rate.

[0006] The respective quantum random number generator comprises means for operating the entropy source and means for generating quantum random numbers and / or quantum random bits depending on the entropy source output signal of the entropy source.

[0007] What's special about this quantum random number generator (QRNG) with crypto engine is that the single-photon source and the photon detector of the entropy source are arranged perpendicular to each other and to the surface of the quantum random number generator's semiconductor substrate, enabling a particularly high random number data rate and thus a rapid key exchange. This, in turn, is important for fending off attacks using AI and / or quantum computers.

[0008] This is new compared to the prior art, as the priority of 26 September 2023 of the German patent application DE 10 2023 126 115.0 is claimed, which shows this arrangement for the first time. (See Fig. 4 of the document presented here.)

[0009] Through this arrangement and the metal mirror 124, 134 above the arrangement of single-photon source 120 and photon detector 130, all photons exiting the substrate upward are reflected back toward photon detector 130. As a result, virtually all photons generated by single-photon source 120 pass through the photon detector. This enables a better photon yield and thus an increased random bit data rate.

[0010] The respective quantum random number generator preferably comprises additional means for operating the entropy source and means for generating quantum random numbers depending on the entropy source output signal of the entropy source.

[0011] A random bit data stream is considered random in the sense of the NIST test in the context of this document if it passes the following NIST test: Smid, Elaine Barker, et al. “A statistical test suite for random and pseudorandom number generators for cryptographic applications.” (2010). Downloadable from https: / / www.researchgate.net / profile / Salam-Ismaeel / post / Is_there_any_program_or_software_to_check_strength_of_cryptography_algorithm2 / attachment / 59d61de479197b807797be4a / AS%3A273823310516224%401442295972158 / download / NIST.pdf

[0012] The NIST Test Suite software can be downloaded from the following URL (as of filing date): https: / / csrc.nist.gov / CSRC / media / Projects / Random-Bit-Generation / documents / sts-2_1_2.zip

[0013] The version dated April 27, 2010 was used in the preparation of this document. General introduction and state of the art

[0014] [The present invention thus relates to the use of respective integrated quantum random number generators (iZG), in particular respective monolithic in a respective common semiconductor substrate in preferably the same material system, scalable and fully integrated photonic QRNG typically comprising a photon source and a detector for individual photons directly coupled to the photon source in a particularly compact and attack-proof design on a technology platform for semiconductor structuring that is open for a wide range of applications.According to the invention, the integrated quantum random number generator interacts with a crypto engine (KE), which firstly uses a first part of the random bits of the quantum random number generator, here the internal random number generator (iZG), for the generation of keys and signatures and secondly encrypts a second part of the random bits of the random bit data stream (ZBS) of the quantum random number generator (iZG) by means of the thus generated for use by other bus participants - e.g. a microcontroller MCU.

[0015] Random events and the determination of probabilities play a particularly prominent role in many areas of science and technology. For example, Monte Carlo simulations, the customization of transmitters and / or components, bus addressing methods, and secure encryption techniques rely heavily on the provision of random numbers. A general distinction is made between so-called pseudo-random numbers and true random numbers.

[0016] While pseudo-random numbers are generated using deterministic formulas by pseudo-random number generators (PRNGs), and are therefore not absolutely random, non-deterministic random number generators (TRNGs) for generating true random numbers are generally based on real, unpredictable processes such as thermal or atmospheric noise, rather than on artificially generated patterns of deterministic algorithms. However, even the results of such non-deterministic random number generators based on external parameters can, depending on the underlying random element, still tend slightly toward higher or even numbers due to weak correlations, for example, thus enabling at least partial predictability of the random numbers generated in this way.Such random number generators for truly random numbers (TRNG) can also be manipulated from the outside if their design is inadequate, for example in the case of thermal entropy sources for the random numbers.

[0017] Quantum random number generators (QRNGs), a special subgroup of TRNGs, are based on fundamental quantum processes for random number generation and are therefore, at least theoretically, not linked to other external factors and effects that influence statistics. According to current knowledge, they therefore do not have a so-called side channel that allows the random number generation process to be influenced. Quantum random number generators (QRNGs) therefore represent the currently best available source of true random numbers. Current digital QRNGs can deliver entropy rates (i.e., a sequence of bit values ​​with maximum randomness or entropy) of up to several hundred Mbps. A disadvantage of such devices, however, is their mechanical size and weight, making them suitable only for centralized random number generation in data centers.However, for good encryption in data networks, all network nodes should have their own random number sources and thus their own quantum random number generators.

[0018] The generated random numbers are required in both classical encryption methods and a variety of quantum computing and quantum cryptography methods to ensure secure key exchange (Secure / Quantum Key Distribution, SKD / QKD). Therefore, non-tamperable and fast QRNGs are essential for generating secure keys in cryptography.

[0019] Due to their particularly easy implementation, many QRNGs are realized as photonic QRNGs using the random properties of photons. A simple concept for generating random numbers in the state of the art is the behavior of a photon, which is either reflected or transmitted at a semitransparent beam splitter independently of other photons. Another approach is to utilize the random arrival times of photons at a photon detector. This distribution effect, based on intrinsic, fundamentally non-deterministically calculable photon statistics of the photons of a corresponding photon source, can also be used to generate truly random numbers. The arrival times of photons at a photon detector generally exhibit an exponential distribution.

[0020] Typically, a single incident photon in a photon detector (SPD) initially generates a detector pulse, which is then converted into a timestamped digital representation of the detection event in a time-to-digital converter (TDC) and can be further processed. The photon or entropy source in QRNGs is usually laser diodes (LDs) or simple light-emitting diodes (LEDs) that are highly attenuated to the single-photon level. Their emitted photons can then be recorded in a time-resolved manner as SPDs using one or more particularly sensitive single-photon avalanche diodes (SPADs).Such photon sources that simultaneously emit only a single photon or a few photons are also referred to as single-photon sources (SPS) in this application. However, they do not necessarily have to be true single-photon emitters, for example, based on a single isolated two-level system.

[0021] SPADs are a type of photodetector similar to photodiodes (PDs) and avalanche photodiodes (APDs), but with significantly increased sensitivity. SPADs can be read and evaluated digitally, even within a common integrated circuit.

[0022] If such an integrated detector circuit is excited by single photons, only one electron-hole pair is generated per exciting photon in the sensor-active region (absorption region). The excited electrons are drawn to the cathode by electric fields, and the excited holes are drawn to the anode. In a SPAD, the charge carriers drift through a so-called avalanche region, within which a charge avalanche is generated by enhanced impact ionization. These are thus highly sensitive photon-receiving elements that, upon activation, can provide a high amount of charge (approximately 105 - 106 electrons) with high temporal resolution.

[0023] A SPAD is typically operated in Geiger mode above its breakdown voltage, where a single photon is detected via the generated charge avalanche and subsequently registered as a single event. To reduce the dead time during registration, active or passive suppression or quenching of further charge carrier amplification can occur immediately after the onset of the avalanche formation. In addition to the SPAD, the integrated circuit can also include a so-called single-photon counter (SPC). In this case, instead of directly outputting a single detector pulse, an immediate statistical evaluation of the temporal distribution of the individual detected single-photon events is generally performed.

[0024] Statistical analysis performed in parallel with random number generation can, for example, be used to further secure the random number generation process against potential attacks. Particularly in the case of non-integrated photonic QRNGs constructed from individual components, the required transmission paths within the system offer a wide range of attack possibilities. Therefore, to increase security, such systems are implemented as compactly and isolated from their external environment as possible. In addition to avoiding potential attack scenarios, a further advantage of such compact QRNGs is that natural influences from outside the system that might impair random number generation can also be minimized to the greatest extent possible. Accordingly, compact QRNGs based on photon noise have typically been provided as hybrid integrated systems.

[0025] From EP 3 529 694 B1, an entropy source of an integrated quantum random number generator (iZG) with a PLC and one or more SPDs is also known, in which the PLC and the SPD(s) are arranged completely integrated in CMOS technology in a single semiconductor substrate in such a way that they are located directly next to each other in a horizontal direction parallel to the surface of the semiconductor substrate (see Fig. 1 with associated figure description). The SPS is provided by a suitably doped pn junction, so that it generates a detectable photon current when the photon source is suitably biased in the forward or reverse direction. The SPDs are intended to be SPADs, which are preferably produced through common manufacturing processes with the SPSs and have the same chemical structure.

[0026] The joint integration ensures that the photon flux generated by the SPS can flow directly to an adjacent SPAD through optical crosstalk within one and the same semiconductor material. Unlike other hybrid-integrated QRNGs known from the state of the art, it does not first have to overcome or tunnel through a possibly empty coupling gap that physically separates the two components. The integrated "side-by-side" configuration makes the QRNG presented in the publication more compact and structurally less complex than hybrid QRNGs of the same functional type. Furthermore, thanks to the integration of all components, the random number generator is significantly more robust and immune to external environmental influences as well as attempts at manipulation by external attackers.

[0027] However, it is still possible, at significantly increased expense, to interfere with, influence, and / or monitor the random number generation process during the QRNG's ongoing operation. Since the iZG disclosed in the publication essentially has a planar structure, individual photons could certainly be tapped or additionally introduced from above or below the plane of the substrate.

[0028] The horizontal juxtaposition of the structures is also not ideal in terms of efficiency and required space consumption. Efficiency is particularly limited by the required lateral distance between the SPS and the SPAD and the associated high absorption of photons in the semiconductor material. Furthermore, without special precautions, the photons emitted by the SPS are largely scattered into the material surrounding the SPS in an undirected manner, meaning that only a portion of the generated photons can be detected by an associated SPAD. While multiple SPADs can be arranged around a single SPS, increasing efficiency and thus the digital entropy rate through joint evaluation of the SPADs connected in this way, this significantly increases the space consumption of the entropy source of such an integrated quantum random number generator (iZG).On the other hand, even with a single emitter-detector pair, it must be ensured that undetectable photons cannot propagate uncontrollably within the substrate and cause disturbances elsewhere in the substrate. The associated lateral blocking regions therefore also increase the effective area consumption of the entropy source of such an integrated quantum random number generator (IQG).

[0029] An entropy source of such a monolithically integrated inner quantum random number generator (iZGs), also realized in CMOS technology (HV-CMOS), with a corresponding arrangement of a photon source and a photon detector next to each other, is also known from Khanmohammadi et al. (Khanmohammadi, Abbas, et al. “A monolithic silicon quantum random number generator based on measurement of photon detection time.” IEEE Photonics Journal 7.5 (2015): 1-13). A Si-LED, formed in a circular near-surface n-well between a central n++ region as the cathode and several p++ regions arranged around it as the anode, serves as the photon source and is enclosed in a circular ring by a SPAD as the photon detector (see Fig. 2 with associated figure description). The photons emitted by the SPS are thus detected from all sides in the plane, which allows for increased efficiency with reduced space requirements compared to the entropy source of such an internal quantum random number generator (iZGs) known from EP 3 52 694 B1. The SPS is thus directly integrated into the SPAD. However, individual photons can also be emitted into the substrate or extracted from its surface. Likewise, the injection of corresponding photons by an attacker to influence the statistics is also possible in this way.

[0030] Therefore, to further increase security and reduce space consumption, there is a need for further miniaturization of integrated QRNGs compared to the state of the art. The internal quantum random number generator (iZG) and its entropy source (EQ), in particular, should be largely protected against external attacks while achieving the highest possible efficiency and minimizing substrate losses. To avoid being limited by manufacturing technology constraints in the design of SoCs (System on Chip, SoC), the underlying manufacturing process should be as technology-open as possible and be based on the most widely applicable technology platform for semiconductor structuring.

[0031] All quantum random number generators presented here, as long as they are state-of-the-art and not the solution with a vertical entropy source presented here, have problems distributing random numbers securely against attacks by quantum computers and / or AI in a network. At the same time, many network nodes are single-chip solutions and therefore require a monolithically integrated quantum random number generator with a high quantum bit random rate and / or quantum random number rate. The quantum random number generator presented here with a vertical entropy source for high quantum bit random rates and / or quantum random number rates and a crypto engine can therefore also be part of a larger, particularly microintegrated, circuit that can perform additional tasks. Task

[0032] The proposal is therefore based on the task of creating a solution that does not have the above-mentioned disadvantages of the prior art and has further advantages.

[0033] This problem is solved by the technical teaching of the independent claims. Further embodiments may be the subject of subclaims. Solution to the task

[0034] A first aspect of the present disclosure relates to the respective node-specific integrated inner quantum random number generators, iZG. The entropy source EQ of such an integrated inner quantum random number generator iZG of a network node according to the invention of a subnetwork according to the invention of a network according to the invention preferably comprises at least one respective photon source and at least one photon detector, wherein the photon source and the photon detector are arranged one above the other in the vertical direction relative to the horizontal surface of a semiconductor substrate in the common substrate made of a semiconductor material. An entropy source EQ of an inner quantum random number generator iZG according to the invention can therefore also comprise a plurality of photon sources coupled to a single photon detector (e.g., to increase the photon rate or reliability) or a plurality of photon detectors coupled to a single photon source (e.g.,for monitoring purposes). An internal quantum random number generator iZG according to the invention can comprise one or more such entropy sources EQ. It is also possible to combine several photon sources and photon detectors into an entropy source EQ of a single internal quantum random number generator iZG.

[0035] In contrast to the prior art, the entropy source EQ of the internal quantum random number generator iZG does not feature a juxtaposition of the individual optoelectronic components. Rather, according to the invention, a photon source and a photon detector are compactly arranged one above the other relative to the surface of the substrate in the shared substrate made of a semiconductor material. Preferably, silicon is the semiconductor material. The use of direct semiconductors such as GaAs or combination semiconductors made of III / V semiconductor materials or even more complex semiconductor materials that can be produced by band-gap engineering is conceivable. This therefore preferably involves a particularly compact monolithic 3D integration with minimal space requirements for the internal quantum random number generator iZG, wherein the structures can preferably be formed in one piece.

[0036] In particular, an arrangement is preferred in which at least one photon detector of the one or more photon detectors is arranged lower than at least one photon source of the one or more photon sources in the respective semiconductor material (i.e. photon source on top, photon detector on the bottom) for improved shielding against external influences. In an alternative embodiment, however, the exemplary photon detector in question can also be arranged higher than the respective photon source in the semiconductor material (i.e. photon source on the bottom, photon detector on the top). For example, in addition to an inversion of the basic structural design during processing from the surface of the semiconductor substrate, an inverse arrangement of the elements can also be achieved by appropriate structuring from the back of the semiconductor substrate.In particular, structuring can be carried out on both sides, from the front side as well as from the back side of the semiconductor substrate.

[0037] The photon source is preferably a single-photon source (SPS), designed to provide only a single photon or a few photons at a time. Such photon sources that provide only a single photon or a few photons at a time are also referred to as single-photon sources in this application. However, they do not have to be true single-photon emitters, for example based on a single isolated two-level system; rather, conventional light sources can also be configured as SPSs by appropriately attenuating the emission or the supplied current. This is preferably a silicon LED or a PN junction in the semiconductor substrate, or a pip, pin, or nin structure in the semiconductor substrate, or a functionally equivalent semiconductor structure in the semiconductor substrate.

[0038] In the context of the present disclosure, a semiconductor substrate is understood to mean the entire semiconductor chip as a body in which a specific element structure is patterned into the semiconductor material, for example by means of CMOS, bipolar, BiCMOS, or other semiconductor process technologies, for example by forming differently doped wells or regions and / or oxidations and / or trench etching and / or undercutting. However, the structure formation can also be achieved additively by structured and / or unstructured application of further layers and structures or by a sequence of etching and application steps for such further layers and structures. Such methods are well known from microstructure technology and from microelectronics manufacturing processes. The document presented here refers to the relevant specialist literature.A corresponding semiconductor substrate can therefore comprise, in addition to a so-called carrier or base substrate (e.g., an unstructured single-crystal semiconductor substrate as a basis for the epitaxial growth of further semiconductor layers), a plurality of such epitaxially grown layers as well as other coatings. In this application, the semiconductor substrate is therefore understood as a material carrier for the semiconductor structures of an inventive internal quantum random number generator iZG or the entropy source of an inventive internal quantum random number generator iZG, and not as a simple carrier or base substrate for applying these structures.In this respect, the one-piece design of an internal quantum random number generator iZG according to the invention on top of one another in a common substrate made of a semiconductor material represents a distinction, in particular, from hybrid-integrated combinations (e.g. by means of flip-chip assembly) comprising at least one photon source and at least one photon detector, for example on a common submount as a carrier structure, which are integrated using conventional methods.

[0039] The photon source is preferably a light-emitting diode, preferably a PN diode, operated at an operating point below or close to the breakdown voltage. The use of pip, pin, and nin diodes as photon sources is conceivable. However, PN diodes are more common and generally more suitable. The photon source is particularly preferably a light-emitting avalanche Zener diode (Zener-avLED) operated at an operating point below or close to the breakdown voltage. The Zener-avLED preferably has a breakdown voltage of <10 V, more preferably a breakdown voltage of <8 V, and even more preferably a breakdown voltage of <7 V. This breakdown voltage can be very well adjusted using methods known from the prior art and can be precisely adjusted during the design phase using known component simulators by specifying the doping profiles and structures.The advantages of using a Zener avLED as a single-photon source are explained in more detail below. This new type of single-photon source allows for a high single-photon rate at a relatively low operating voltage, even below and in the range of the Zener breakdown voltage. With the desired design, the generated photons are preferably emitted in a directed manner into the interior of the substrate and thus toward the photon detector. This makes Zener avLEDs particularly suitable for use as a single-photon source in an entropy source (EQ) of an internal quantum random number generator (iZG). Preferably, the one or more photon detectors are one or more single-photon avalanche diodes (SPADs).These are detectors that are, due to their particularly high sensitivity with high amplification and low (dark) noise, in principle capable of detecting and proving individual photons.

[0040] A key idea of ​​the present invention is therefore to provide a particularly compact and secure integrated entropy source EG for a fully integrated internal quantum random number generator iZG in a quantum random number generator ZZG with a particularly compact and secure entropy source EQ for each network node of said subnetwork of the proposed network by arranging a Zener avLED and a SPAD one above the other in a common semiconductor substrate. This particularly compact and secure entropy source EQ enables a higher random number data rate than is usual in the prior art due to the vertical arrangement of the elements of the entropy source EQ. As a result, the proposed network has the capability of generating random numbers within the network with high quality and high security at a high data rate for the network as a whole.Thus, such a network, if it comprises a sufficient number of corresponding nodes with the proposed quantum random number generator, is superior to all networks with a central quantum random number generator and all networks with conventional inner quantum random number generators (iZG) with horizontal entropy sources.

[0041] One approach to improving the state-of-the-art entropy sources (EQ) for internal quantum random number generators (iZG) is to select a correspondingly broad technology platform. Integrated circuits based on bipolar CMOS-DMOS (BCD) technology on silicon offer great potential for SoC designs with the broadest possible range of potential applications. Highly efficient SPADs have already been successfully demonstrated and implemented using BCD technology. BCD technology allows for particularly effective and optimized integration of these SPADs with a wide range of other functional groups, such as digital and analog circuit components, particularly energy-efficient digital memory and switching elements, general power and driver electronics, as well as detector and sensor components.

[0042] The silicon-based PLCs known in the state of the art can, in principle, also be implemented in BCD technologies. However, due to the undirected emission of photons and their typically near-surface implementation, such Si-LEDs are not optimal for the realization of particularly efficient and attack-protected entropy sources (EQ) of internal quantum random number generators (iZGs). The near-surface implementation of the horizontal entropy sources from the state of the art also usually results in degradation in the case of a Si-LED used in avalanche operation. Since silicon, as an indirect semiconductor, is poorly suited for photon generation, and these can generally only be generated through further processes via additional interaction with the crystal lattice, the selection of possible alternative silicon-based photon sources is severely limited.In investigating Zener diodes provided in different layers by corresponding pn junctions in a BCD technology, which are optimized for a permanent operating point even in the breakdown region. A near-surface Zener diode was used as the emitter and an underlying simple pn diode without bias (zero bias) was used as the detector. The inventors were able to demonstrate that, contrary to the general expectation of the skilled person, in this configuration, strong electroluminescence with an efficiency of at least 0.03% can be observed at the breakdown voltage of the Zener diode in avalanche operation. Such Zener diodes are not typically intended for operation as optoelectronic components (LEDs) in the prior art.

[0043] In particular, the generated photons are preferentially emitted towards the lower pn diode, which can thus detect almost all emitted photons, which can also be demonstrated via a photocurrent in the inventive structure (cf. Fig. 4 to 7 with the corresponding figure descriptions). It was thus shown that the investigated Zener diode exhibits a low, yet significant, efficiency in the breakdown / Zener voltage range (approximately one detected photon per 3000 electrons of the Zener diode current). Therefore, it appears to be ideally suited as a single-photon source for the implementation of internal quantum random number generators (iZG) of quantum random number generators (ZZG) in silicon-based BCD technology. In particular, the preferential radiation toward the photon detector of the entropy source EQ offers significant advantages over the isotropic radiation of entropy sources of conventional photon sources used in internal quantum random number generators (iZG).The silicide commonly used in CMOS technology to reduce contact resistance between the metal contacts and the semiconductor silicide is both light-tight and mirror-smooth, allowing photons originally emitted upwards to be reflected back into the interior of the substrate by the silicide mirror, and thus toward the photon detector of the entropy source of the internal quantum random number generator (iZG). Accordingly designed Zener diodes operated as PLCs in avalanche mode are therefore referred to below as light-emitting avalanche Zener diodes (Avalanche Light Emitting Zener diodes, Zener-avLED), in contrast to the Si LEDs known from the prior art. However, the disclosure is not limited to the use of these preferred silicon LEDs. Rather, the use of other LED structures is also conceivable.In this context, the document presented here refers to the book Ohtsu, Motoichi, "Silicon Light-Emitting Diodes and Lasers." Nano-Optics and Nanophotonics (2016).

[0044] The Zener avLEDs provided in the BCD technology used here as an example emit photons with wavelengths from the visible spectral range and have a relatively low Zener operating voltage of usually less than 8 V. Since the radiation of a Zener avLED is also typically directed such that the photons are emitted preferentially in a vertical 30 direction, i.e. away from the surface into the substrate, a much stronger isolation of the PLC and the generated photons from the environment of the semiconductor material can be achieved when used in an iZG, and tapping or injecting photons at the detector surface is made significantly more difficult.

[0045] With a suitable design of the SPAD belonging to an entropy source EQ of an inner quantum random number generator iZG, the efficiency of random number generation by the quantum random number generator ZZG with the respective entropy source EQ of an inner quantum random number generator iZG of the quantum random number generator ZZG can be significantly increased and uncontrolled photon propagation in the semiconductor material can be largely prevented.

[0046] The second essential component for constructing a compact QRNG with the compact entropy source EQ of the internal quantum random number generator iZG is therefore the selection of a correspondingly adapted SPAD design for the entropy source EQ. Typically, these are also realized in BCD technologies close to the surface of the semiconductor substrate by appropriately forming p- or n-wells. Such near-surface SPADs are quite comparable to the prior art SPADs realized in CMOS technology. In principle, the horizontal entropy source known from EP 3 529 694 B1 could therefore also be realized in BCD technologies in a horizontal arrangement with the Zener avLEDs described above. However, as already described above, the Zener avLEDs advantageously emit the photons preferably in the direction into the substrate and vertically out of the substrate.A juxtaposition of a Zener avLED as a SPS and a near-surface SPAD, as derived from the prior art, could be implemented in principle, but not necessarily effectively. During the development of the technical teaching of the document presented here, it was recognized that when using Zener avLEDs, it is expedient to arrange the associated SPAD vertically below the Zener avLED relative to the horizontal surface of the semiconductor substrate.

[0047] In addition to the implementation of conventional n-SPADs and p-SPADs, BCD technology also enables the realization of completely new SPAD concepts, e.g. through the use of deep n- or p-doped layers in a BCD substrate in connection with the realization of the entropy source EQ.

[0048] A method for generating deep pn junctions in a BCD process, also recently developed by some of the inventors, made it possible to realize a particularly efficient, deep-lying single-photon avalanche diode ("deepSPAD") based on this method, which can be easily arranged directly below a Zener avLED configured to generate single photons. In contrast to the horizontal integration of an entropy source of an iQNRG based on CMOS technology according to the prior art, the combination of a Zener avLED with a deep-lying SPAD thus provides the essential components of a vertical entropy source EQ of an internal quantum random number generator iZG of the quantum random number generator ZZG, which is fully integrated in BCD technology according to the invention.

[0049] By vertically arranging a Zener avLED as the emitter and a deepSPAD implemented using extremely deep pn junctions as the receiver in the vertical entropy source EQ, a miniaturized, monolithic silicon-based entropy source EQ of a monolithically integrated inner quantum random number generator (iZG) of a quantum random number generator (ZZG) can be realized using BCD technologies. It features highly efficient optical coupling, high attack resistance, and low operating voltage. Thus, the BCD-based design of a vertical entropy source EQ of an inner quantum random number generator (iZG) presented here represents an optimal solution to the proposed subtask of monolithic integration of an entropy source EQ with a high random bit rate.In particular, vertical 3D integration can further increase the compactness of a vertical entropy source of the inner quantum random number generator iZG of the quantum random number generator ZZG and reduce the area consumption compared to conventional lateral 2D designs of the entropy source while simultaneously increasing the random bit data rate.

[0050] Preferably, a vertical entropy source EQ of an inner quantum random number generator iZG of a quantum random number generator ZZG is therefore formed in a BCD substrate in BCD technology.

[0051] Preferably, the BCD substrate comprises a carrier substrate and an epitaxial layer grown on the carrier substrate, wherein a deep pn junction located in the epitaxial layer is created between the carrier substrate and the epitaxial layer by diffusion of dopants introduced into a surface of the carrier substrate below the epitaxial layer.

[0052] The carrier substrate can preferably be a p-type substrate, as is common for CMOS technologies, for example. However, n-type substrates or intrinsic substrates can also be used. The substrate material can, in particular, be silicon. However, the processes are in principle also adaptable for other semiconductor materials. A typical dopant for forming a p-type region is boron. Phosphorus (P), arsenic (As), or antimony (Sb) can be used to form an n-type region. In silicon, for example, boron diffuses significantly further as a dopant than the heavy donors (P, As, or Sb). It can also be seen that the n-type regions created are largely dominant due to the higher doses used, i.e. an n-type region already doped with phosphorus can retain its existing conductivity type even after additional boron has been added.To provide the deep pn junctions, additional mask, lithography and epitaxy steps in the usual BCD process can sometimes be omitted.

[0053] Preferably, the first and second dopant have different diffusion properties in the carrier substrate and / or in the epitaxial layer. Preferably, the second dopant has greater mobility in the carrier substrate and / or in the epitaxial layer than the first dopant. Preferably, the first dopant and / or the second dopant are introduced maskless or via a mask process. For maskless introduction, a direct ion beam writing process, for example, can be used. In a mask process, the introduction is carried out using a previously provided mask, wherein the introduction is carried out, for example, via a chemical or physical deposition process or also by means of an ion beam writing process.Preferably, immediately after the introduction of the second dopant, in a plan view of the surface of the carrier substrate, the first region or the second region completely overlies the other region.

[0054] Preferably, the first region is a deep n-layer (NBL layer) and the second region is a deep p-layer (PBL layer).

[0055] Preferably, the photon detector of the entropy source EQ forms an avalanche region in a region around the deep pn junction and comprises an absorption region for converting photons into electron-hole pairs, wherein the absorption region is directly adjacent to the deep pn junction.

[0056] It is preferred that the deep pn junction is formed at least partially between a deep n-layer as the cathode and a deep p-layer directly adjacent to the deep n-layer. It is also preferred that the absorption region directly adjoins the deep p-layer and is essentially formed as a p-region. "Essentially" means that the absorption region can also be partially formed as an intrinsic region. It is further preferred that an anode formed as a p+ region directly adjoins the absorption region.

[0057] Preferably, a second deep pn junction (e.g., in the carrier substrate) formed below the deep pn junction of the photon detector located in the epitaxial layer is used as an additional photodetector for monitoring for external attacks. The method for producing deep pn junctions in a BCD process results in a second pn junction located below the first pn junction in some embodiments (see Fig. 3 with accompanying figure description). Due to its largely identical electronic properties, this can also be configured as a photodetector or single-photon avalanche diode. Since this additional photodetector is thus arranged below the actual QRNG arrangement, deeply buried in the semiconductor material, it can provide a protective function against photons injected from the back of the substrate of the quantum random number generator (ZZG).

[0058] These can be detected in close proximity to the entropy source EQ of an internal quantum random number generator (iZG) over a wide angular range. This allows external attacks to be detected with a high degree of probability.

[0059] Preferably, the top and / or bottom side of the substrate in the region of the entropy source EQ of the inner quantum random number generator iZG of the quantum random number generator ZZG is mirrored on one surface or comprises a light-blocking layer. Mirroring the surfaces of a substrate (e.g., by means of metallization or the application of dichroic layers) and the application of a light-blocking layer are known in the art and have already been discussed above. These approaches can also be used in an entropy source EQ according to the invention of an inner quantum random number generator iZG of a quantum random number generator ZZG according to the invention to shield against external photons ("shadowing") and to increase efficiency by backreflecting the photons generated by the associated photon source.Alternatively or additionally, a corresponding encapsulation can be carried out in the area of ​​the entropy source EQ of the inner quantum random number generator iZG of the quantum random number generator ZZG or this area can be surrounded by a metal box.

[0060] Preferably, the surface of the substrate is covered with a silicide layer in the region of the entropy source EQ of the inner quantum random number generator iZG of the quantum random number generator ZZG, and above it with a metallization layer. Preferably, the metallization is closed in the region of the entropy source EQ of the inner quantum random number generator iZG of the quantum random number generator ZZG. The metallization can act as a mirror coating for the interior and / or as a wavelength-independent shading layer for external photons. The same applies to a formed silicide layer.

[0061] Preferably, photons provided by the photon or single-photon source of the entropy source EQ of the inner quantum random number generator iZG of the quantum random number generator ZZG are prevented from escaping at the surface of the substrate and / or the back of the substrate of the quantum random number generator ZZG by a combination of at least one element each consisting of metal covers, sidewall contacts, and vias. These elements can achieve a largely complete shielding or encapsulation of the entropy source EQ of the inner quantum random number generator iZG of the quantum random number generator ZZG, which ensures not only external shielding but also high immunity to external interference.

[0062] Preferably, several entropy sources EQ according to the invention of the inner quantum random number generator iZG of the quantum random number generator ZZG or a multi-channel system of several inner quantum random number generators iZG of the quantum random number generator ZZG comprising a plurality of entropy sources EQ according to the invention of one or more inner quantum random number generators iZG of the quantum random number generator ZZG are realized on the same substrate in order to increase the data rate of the quantum random bits.Combined with compact shielding of the individual entropy sources EQ of the individual inner quantum random number generators iZG of the quantum random number generator ZZG, very high integration densities can be achieved with a large number of one or more densely packed and preferably decoupled entropy sources EQ of one or more inner quantum random number generators iZG of the quantum random number generator ZZG, thus resulting in high overall effective random bit rates and thus high effective random number rates. For state-of-the-art entropy sources EQ, the integration density and random bit rates are primarily limited by the structural juxtaposition of the individual components.

[0063] Preferably, an inner quantum random number generator iZG according to the invention and / or a quantum random number generator ZZG according to the invention comprise an electronic circuit for generating and outputting a digital random bit sequence and subsequently a digital random number sequence based on the statistical evaluation of the temporal sequence of signals (photon detector signals) of the one or more photon detectors.

[0064] A further aspect of the present invention therefore relates to an integrated electronic circuit (IC), comprising at least one entropy source EO according to the invention, an inner quantum random number generator iZG according to the invention, and a quantum random number generator ZZG according to the invention. In particular, these can be ICs for applications based on security-relevant chip-based systems (System on Chip, SoC).

[0065] Preferably, an inventive entropy source EQ of an inventive inner quantum random number generator iZG of an inventive quantum random number generator ZZG is placed in a pad frame (also referred to as a pad edge) of the integrated electronic circuit. Preferably, the electronic circuit of the inner quantum random number generator iZG of the quantum random number generator ZZG for generating and outputting a digital random number sequence is also located in the pad frame of the integrated circuit IC. In non-pad-determined integrated electronic circuits, the pad frame typically contains a large number of free areas, which, however, typically cannot be used for digital circuits or larger analog circuit blocks.Since a quantum random number generator ZZG according to the invention with an inner quantum random number generator iZG according to the invention and with an entropy source EG according to the invention and an electronic circuit according to the invention for generating and outputting a digital random number sequence is correspondingly small due to its extremely compact design, and the subsequent circuitry also typically comprises only a small number of gates, this type of inner quantum random number generator iZG can nevertheless be fully or at least partially integrated into a conventional pad frame. Due to the extremely compact design of the entropy source EG according to the invention of the inner random number generator iZG according to the invention in the quantum random number generator ZZG, these can also be implemented in existing designs for integrated electronic circuits in a space-saving manner and without major effort.This achieves a significant reduction in space requirements compared to conventional approaches for integrating quantum random number generators (QRNGs). The advantages of an inventive entropy source EG of the inventive inner random number generator iZG in the quantum random number generator ZZG can be fully exploited.

[0066] The advantages of an inventive entropy source EG of the inventive internal random number generator iZG in the quantum random number generator ZZG compared to known implementations in the prior art are primarily based on the further miniaturization of the entire random number generator structure and the resulting high degree of integration or miniaturization of the generated structures. Due to the complete isolation of the PLC and the associated SPAD from the environment, the security of random number generation can be significantly increased. The directed vertical radiation from the Zener avLED used as the PLC also contributes to increased security and to a significant increase in the efficiency of random number generation, resulting in an increase in the random bit rate and random number rate.

[0067] A second deep pn junction, formed below the pn junction of the SPAD using a novel BCD technology, can be used as an additional photodetector to monitor attacks, particularly from the back of the substrate of the quantum random number generator ZZG of the relevant node in the network according to the invention. The efficiency of the optical coupling into the associated SPADs, as well as the isolation and security, can be further increased through the use of internal metal and silicide mirrors. Compared to the prior art, only a relatively low operating voltage of < 8 V is required for the Zener avLED used as a photon source. Furthermore, since the absorption length of the emitted visible light in silicon is short (i.e., the associated absorption coefficient is high), very good optical isolation between adjacent elements can be achieved.This enables arrangement in an array with high cell density and a resulting correspondingly high generation or entropy rate.

[0068] The present application further relates to a random number generator ZZG, preferably implemented monolithically in CMOS technology, which preferably comprises a quantum random number generator ZZG with an entropy source, as described above, in an inner quantum random number generator iZG. The proposed random number generator ZZG preferably comprises an inner random number generator iZG, which generates a random bit data stream ZBS, a crypto engine KE, and a data bus interface DBIF, which, for example, has an I 2C interface. The proposed random number generator (ZZG) is preferably used to perform cryptographic operations in security-critical applications. The crypto engine (ZE) preferably comprises several common device components in all variants, which are described below before the specific features of the five most important variants are explained.

[0069] Preferably, the inner random number generator (iZG) within the random number generator (ZZG) is embodied as an inner quantum random number generator. Such a respective inner quantum random number generator of a respective network node of a network with distributed entropy generation preferably comprises an entropy source fabricated monolithically in a respective semiconductor substrate of the respective node, which comprises a single-photon source and a photon detector arranged perpendicular to each other and to the surface of the respective semiconductor substrate, enabling a particularly high random number data rate. The respective inner quantum random number generator preferably comprises respective means for operating the respective entropy source and preferably respective means for generating quantum random numbers and / or quantum random bits depending on the respective entropy source output signal of the vertical entropy source.These inner quantum random number generators are characterized by this very vertical arrangement of the photon source of the respective entropy source and the respective photon detector of the respective entropy source of the respective inner quantum random number generator relative to each other in the semiconductor substrate of the inner quantum random number generator. This ensures that the generated random numbers are truly random, unpredictable, and of high entropy, and can be generated by the inner quantum random number generator with a high random bit rate. Distributing these inner quantum random number generators across all nodes of the network creates a decentralized architecture that offers significant advantages in terms of the security, robustness, and scalability of the network. An inner quantum random number generator is an inner random number generator as defined in the document presented here.

[0070] Preferably, the respective internal quantum random number generators are each constructed in one piece. Preferably, the respective semiconductor substrate of the respective internal quantum random number generator comprises a respective entropy source, which is fabricated in the respective semiconductor substrate of the respective internal quantum random number generator, and means for converting the entropy source output signal of the entropy source into a random bit data stream. These means preferably comprise one or more of the following device parts: one or more analog amplifiers and / or filter circuits for conditioning the entropy output signal for subsequent analog-to-digital conversion; a single- or multi-bit analog-to-digital converter, which in the case of a single-bit analog-to-digital converter can be implemented by a comparator;one or more time-to-digital converters and / or one or more time-to-pseudo-random number converters for assigning a unique binary number to a time interval between two pulses of the entropy source; one or more entropy extraction devices for extracting one or more random bits from these binary numbers; one or more finite state machines for converting the data stream of random bits from the entropy extraction into random numbers; one or more interfaces for accessing these random numbers by one or more external computer systems and / or for controlling the internal quantum random number generator; one or more devices for performing and / or supporting a health check of one or more device parts and / or their interaction;one or more device parts for generating the internal operating voltages within the internal quantum random number generator for operating the various device parts of the internal quantum random number generator;

[0071] The present invention thus relates to the use of respective integrated quantum random number generators (iQRNGs) as random number generators (RSGs). Such an iQRNG preferably comprises an entropy source. Such an iQRNG, with its entropy source, is preferably constructed monolithically in a respective common semiconductor substrate, preferably in the same material system, in a scalable and fully integrated manner. Its entropy source preferably comprises a photon source and a detector for individual photons optically coupled directly to the photon source, in a particularly compact and attack-proof design on a technology platform for semiconductor structuring that is open to a wide range of applications.According to the invention, the network nodes of the proposed subnetwork of the network according to the invention have one or more such integrated quantum random number generators (iQRNG) and / or internal quantum random number generators, which are connected to one another via data lines. Quantum random number generators

[0072] Random events and the determination of probabilities play a particularly prominent role in many areas of science and technology. For example, Monte Carlo simulations and secure encryption methods rely heavily on the generation of random numbers. A general distinction is made between so-called pseudo-random numbers and true random numbers. While the former are generated using deterministic formulas by pseudo-random number generators (PRNGs), and are therefore not absolutely random, non-deterministic random number generators (TRNGs) for generating true random numbers are generally based on real, unpredictable processes such as thermal or atmospheric noise, rather than on artificially generated patterns by deterministic algorithms.However, even the results of such non-deterministic random number generators based on external parameters can, depending on the underlying random element, still tend slightly towards higher or even numbers due to weak correlations, for example, and thus enable at least a partial predictability of the random numbers generated in this way.

[0073] Quantum random number generators (QRNGs), a special subgroup of TRNGs, are based on fundamental quantum processes for random number generation and are therefore, at least theoretically, not dependent on other external factors and effects that influence statistics. Quantum random number generators thus represent the currently best available source of true random numbers. Current digital QNRGs can deliver entropy rates (i.e., a sequence of bit values ​​with maximum randomness or entropy) of up to several hundred Mbps.

[0074] The generated random numbers are required in both classical encryption methods and a variety of quantum computing and quantum cryptography methods to ensure secure key exchange (Secure / Quantum Key Distribution, SKD / QKD). Therefore, non-tamperable and fast QRNGs are essential for generating secure keys in cryptography.

[0075] Due to their particularly easy implementation, many QRNGs are realized as photonic QRNGs using the random properties of photons. A simple concept for generating random numbers is the behavior of a photon, which is either reflected or transmitted at a semitransparent beam splitter independently of other photons. Another approach is to utilize the random arrival times of photons at a photon detector. This distribution effect, based on intrinsic, fundamentally non-deterministically calculable photon statistics of the photons of a corresponding photon source, can also be used to generate truly random numbers. The arrival times of photons at a photon detector generally exhibit an exponential distribution.

[0076] Typically, a single incident photon in a photon detector (SPD) initially generates a detector pulse, which is then converted into a timestamped digital representation of the detection event in a time-to-digital converter (TDC) and can be further processed. The photon or entropy source in QRNGs is usually laser diodes (LDs) or simple light-emitting diodes (LEDs) that are highly attenuated to the single-photon level. Their emitted photons can then be recorded in a time-resolved manner as SPDs using one or more particularly sensitive single-photon avalanche diodes (SPADs).Such photon sources that simultaneously emit only a single photon or a few photons are also referred to as single-photon sources (SPS) in this application. However, they do not necessarily have to be true single-photon emitters, for example, based on a single isolated two-level system.

[0077] SPADs are a type of photodetector similar to photodiodes (PDs) and avalanche photodiodes (APDs), but with significantly increased sensitivity. SPADs can be read and evaluated digitally, even within a common integrated circuit.

[0078] If such an integrated detector circuit is excited by single photons, only one electron-hole pair is generated per exciting photon in the sensor-active region (absorption region). The excited electrons are drawn to the cathode by electric fields, and the excited holes are drawn to the anode. In a SPAD, the charge carriers drift through a so-called avalanche region, within which a charge avalanche is generated by enhanced impact ionization. These are therefore highly sensitive photon-receiving elements that, upon activation, generate a high amount of charge (approximately 10 5 - 10 6 electrons) with high temporal resolution.

[0079] A SPAD is typically operated in Geiger mode above its breakdown voltage, whereby a single photon is detected via the generated charge avalanche and subsequently registered as a single event. To reduce the dead time during registration, active or passive suppression or quenching of further charge carrier amplification can occur immediately after the onset of the avalanche formation. In addition to the SPAD, the integrated circuit can also include a so-called single-photon counter (SPC). In this case, instead of directly outputting a single detector pulse, an immediate statistical evaluation of the temporal distribution of the individual detected single-photon events is generally performed.

[0080] Statistical analysis performed in parallel with random number generation can, for example, be used to further secure the random number generation process against potential attacks. Particularly in the case of non-integrated photonic QRNGs constructed from individual components, the required transmission paths within the system offer a wide range of attack possibilities. Therefore, to increase security, such systems are implemented as compactly and isolated from their external environment as possible. In addition to avoiding potential attack scenarios, a further advantage of such compact QRNGs is that natural influences from outside the system that might impair random number generation can also be minimized to the greatest extent possible. Accordingly, compact QRNGs based on photon noise have typically been provided as hybrid integrated systems.

[0081] From EP 3 529 694 B1, an integrated quantum random number generator (iQRNG) with a PLC and one or more SPDs is also known, in which the PLC and the SPD(s) are completely integrated in CMOS technology in a single semiconductor substrate in such a way that they are arranged directly next to each other (see Fig. 1 with associated figure description). The SPS is provided by a suitably doped pn junction, so that it generates a detectable photon current when the photon source is suitably biased in the forward or reverse direction. The SPDs are intended to be SPADs, which are preferably produced through common manufacturing processes with the SPSs and have the same chemical structure.

[0082] The joint integration ensures that the photon flux generated by the SPS can flow directly to an adjacent SPAD through optical crosstalk within one and the same semiconductor material. Unlike other hybrid-integrated QRNGs known from the state of the art, it does not first have to overcome or tunnel through a possibly empty coupling gap that physically separates the two components. The integrated "side-by-side" configuration makes the QRNG presented in the publication more compact and structurally less complex than hybrid QRNGs of the same functional type. Furthermore, thanks to the integration of all components, the random number generator is significantly more robust and immune to external environmental influences as well as attempts at manipulation by external attackers.

[0083] However, it is still possible, at significantly increased expense, to interfere with, influence, and / or monitor the random number generation process during the QRNG's operation. Since the iQRNG disclosed in the publication essentially has a planar structure, individual photons could certainly be tapped or additionally introduced from above or below the plane of the substrate.

[0084] The horizontal juxtaposition of the structures is also not ideal in terms of efficiency and required space consumption. Efficiency is particularly limited by the required lateral distance between the SPS and the SPAD and the associated high absorption of the photons in the semiconductor material. Furthermore, without special precautions, the photons emitted by the SPS are largely scattered into the material surrounding the SPS, meaning that only a portion of the generated photons can be detected by an associated SPAD. While multiple SPADs can be arranged around a single SPS, increasing efficiency and thus the digital entropy rate through joint evaluation of the connected SPADs, this significantly increases the space consumption of such an iQRNG.On the other hand, even with a single emitter-detector pair, it must be ensured that undetectable photons cannot propagate uncontrollably within the substrate and cause interference elsewhere in the substrate. The associated lateral blocking regions therefore also increase the effective area consumption of the iQRNG.

[0085] An iQRNG, also realized in CMOS technology (HV-CMOS), with a corresponding arrangement of a photon source and a photon detector next to each other is also known from Khanmohammadi et al. (Khanmohammadi, Abbas, et al. “A monolithic silicon quantum random number generator based on measurement of photon detection time.” IEEE Photonics Journal 7.5 (2015): 1-13). A Si-LED, formed in a circular near-surface n-well between a central n++ region as the cathode and several p++ regions arranged around it as the anode, serves as the photon source and is surrounded by a SPAD as the photon detector (see Fig. 2 with associated figure description). The photons emitted by the SPS are thus detected from all sides of the plane, which allows for increased efficiency while requiring less space compared to the iQRNG known from EP 3 52 694 B1. The SPS is thus directly integrated into the SPAD. However, individual photons can also be emitted into the substrate or extracted from its surface. Likewise, the injection of corresponding photons by an attacker to influence the statistics is also possible in this way.

[0086] Therefore, to further increase security and reduce space consumption, there is a need for further miniaturization of integrated QRNGs compared to the state of the art. The iQRNG should be largely protected against external attacks while exhibiting the highest possible efficiency and the lowest possible substrate losses. To avoid being limited by manufacturing technology constraints in the design of SoCs (System on Chip, SoC), the underlying manufacturing process should be as technology-open as possible and be based on the most widely applicable technology platform for semiconductor structuring. Common parts of the crypto engine

[0087] All variants of the crypto engine include the following components: 1. Inner Random Number Generator (iRNG)

[0088] The inner random number generator, here the inner quantum random number generator (iZG), generates a random bit stream (ZBS) of random bits that are used in the crypto engine (KE) for key generation and other cryptographic operations. The vertical arrangement of the photon source and the photodetector in the entropy source (EQ) (401) of the inner random number generator (iZG) enables a particularly high random bit rate in the random bit stream (ZBS), which significantly improves the security of the cryptographic operations of the crypto engine (KE). 2. Description of the entropy source of an inner quantum random number generator in the form of the entropy source of an integrated quantum random number generator iQRNG

[0089] A first aspect of the present disclosure concerns the respective integrated quantum random number generators, iQRNGs. The entropy source of such an integrated quantum random number generator iQRNG preferably comprises a photon source and a photon detector for single photons, wherein the photon source and the photon detector are arranged vertically one above the other in a common substrate made of a semiconductor material. An entropy source of an iQRNG according to the invention can also comprise multiple photon sources coupled to a single photon detector (e.g., to increase the photon rate or reliability) or multiple photon detectors coupled to a single photon source (e.g., for monitoring purposes). An iQRNG according to the invention can comprise one or more such entropy sources. The combination of multiple photon sources and photon detectors to form an entropy source of a single iQRNG is also possible.

[0090] In contrast to the prior art, the entropy source of the iQRNG does not feature a juxtaposition of the individual optoelectronic components. Rather, according to the invention, a compact arrangement of a photon source and a photon detector is arranged one above the other in a common substrate made of a semiconductor material. The semiconductor material is preferably silicon. The use of direct semiconductors such as GaAs or combination semiconductors made of III / V semiconductor materials or even more complex semiconductor materials that can be produced by band-gap engineering is conceivable. This thus represents a particularly compact monolithic 3D integration with minimal space requirements for the iQRNG, whereby the structures can preferably be formed in one piece.

[0091] In particular, an arrangement is preferred in which at least one photon detector of the one or more photon detectors is arranged lower than at least one photon source of the one or more photon sources in the respective semiconductor material (i.e. photon source on top, photon detector on the bottom) for improved shielding against external influences. In an alternative embodiment, however, the exemplary photon detector in question can also be arranged higher than the respective photon source in the semiconductor material (i.e. photon source on the bottom, photon detector on the top). For example, in addition to an inversion of the basic structural design during processing from the surface of the semiconductor substrate, an inverse arrangement of the elements can also be achieved by appropriate structuring from the back of the semiconductor substrate.In particular, structuring can be carried out on both sides, from the front side as well as from the back side of the semiconductor substrate.

[0092] The photon source is preferably a single-photon source (SPS), designed to provide only a single photon or a few photons at a time. Such photon sources that provide only a single photon or a few photons at a time are also referred to as single-photon sources in this application. However, they do not have to be true single-photon emitters, for example based on a single isolated two-level system; rather, conventional light sources can also be configured as SPSs by appropriately attenuating the emission or the supplied current. This is preferably a silicon LED or a PN junction in the semiconductor substrate, or a pip, pin, or nin structure in the semiconductor substrate, or a functionally equivalent semiconductor structure in the semiconductor substrate.

[0093] In the context of the present disclosure, a semiconductor substrate is understood to mean the entire semiconductor chip as a body in which a specific element structure is patterned into the semiconductor material, for example by means of CMOS, bipolar, BiCMOS, or other semiconductor process technologies, for example by forming differently doped wells or regions and / or oxidations and / or trench etching and / or undercutting. However, the structure formation can also be achieved additively by structured and / or unstructured application of further layers and structures or by a sequence of etching and application steps for such further layers and structures. Such methods are well known from microstructure technology and from microelectronics manufacturing processes. The document presented here refers to the relevant specialist literature.A corresponding semiconductor substrate can therefore comprise, in addition to a so-called carrier or base substrate (e.g., an unstructured single-crystal semiconductor substrate as the basis for the epitaxial growth of further semiconductor layers), a plurality of such epitaxially grown layers as well as other coatings. The semiconductor substrate is therefore understood in this application as a material carrier for the semiconductor structures of an iQRNG according to the invention and not in the sense of a simple carrier or base substrate for applying these structures. In this respect, the integral formation of an iQRNG according to the invention, one above the other in a common substrate made of a semiconductor material, represents a distinction, in particular from hybrid integrated combinations using conventional methods (e.g.,by means of flip-chip assembly) consisting of at least one photon source and at least one photon detector, for example on a common submount as a carrier structure.

[0094] The photon source is preferably a light-emitting diode, preferably a PN diode, operated at an operating point below or close to the breakdown voltage. Particularly preferably, the photon source is a light-emitting avalanche Zener diode (Zener-avLED) operated at an operating point below or close to the breakdown voltage. The Zener-avLED preferably has a breakdown voltage of <10V, more preferably a breakdown voltage of <8V, and even more preferably a breakdown voltage of <7V. This breakdown voltage can be very accurately adjusted using methods known from the prior art and can be precisely adjusted during the design phase using known component simulators by specifying the doping profiles and structures. The advantages of using a Zener-avLED as a single-photon source are explained in more detail below.This new type of single-photon source allows for a high single-photon rate at a relatively low operating voltage, even below and in the range of the Zener breakdown voltage. With the desired design, the generated photons are preferably emitted in a directed manner into the interior of the substrate and thus toward the photon detector. This makes Zener avLEDs particularly suitable for use as a single-photon source in an entropy source of an iQRNG. Preferably, the one or more photon detectors are one or more single-photon avalanche diodes (SPADs). These are detectors that, due to their particularly high sensitivity with high gain and low (dark) noise, are in principle capable of detecting and proving individual photons.

[0095] A main idea of ​​the present invention is therefore to provide a particularly compact and secure integrated QRNG with a particularly compact and secure entropy source for each network node of said subnetwork of the proposed network by arranging a Zener avLED and a SPAD one above the other in a common semiconductor substrate, which enables a higher random number data rate than is usual in the prior art. As a result, the proposed network has the ability to generate random numbers with high quality and high security at a high data rate for the network as a whole. Thus, such a network, if it comprises a sufficient number of corresponding nodes with the proposed quantum random number generator, is superior to all networks with a central quantum random number generator and all networks with conventional iQRNGs.

[0096] One approach to improving the state-of-the-art iQRNG is to select a correspondingly broad technology platform. For SoC designs with the broadest possible range of potential applications, integrated circuits based on bipolar CMOS-DMOS (BCD) technology on silicon offer great potential. Highly efficient SPADs have already been successfully demonstrated and implemented using BCD technology. BCD technology allows for particularly effective and optimized integration of these SPADs with a wide range of other functional groups, such as digital and analog circuit components, particularly energy-efficient digital memory and switching elements, general power and driver electronics, and detector and sensor components.

[0097] The silicon-based PLCs known in the state of the art can, in principle, also be implemented in BCD technologies. However, due to the undirected emission of photons and their typically near-surface implementation, such Si LEDs are not optimal for the realization of particularly efficient and attack-protected iQRNGs. The near-surface implementation also usually results in degradation in the case of a Si LED used in avalanche operation. However, since silicon, as an indirect semiconductor, is poorly suited for photon generation, and these can generally only be generated through further processes via additional interaction with the crystal lattice, the selection of possible alternative silicon-based photon sources is severely limited.In investigating Zener diodes provided in different layers by corresponding pn junctions in a BCD technology, which are optimized for a permanent operating point even in the breakdown region. A near-surface Zener diode was used as the emitter and an underlying simple pn diode without bias (zero bias) was used as the detector. The inventors were able to demonstrate that, contrary to the general expectation of the skilled person, in this configuration, strong electroluminescence with an efficiency of at least 0.03% can be observed at the breakdown voltage of the Zener diode in avalanche operation. Such Zener diodes are not typically intended for operation as optoelectronic components (LEDs) in the prior art.

[0098] In particular, the generated photons are preferentially emitted towards the lower pn diode, which can thus detect almost all emitted photons, which can also be demonstrated via a photocurrent in the inventive structure (cf. Fig. 4 to 7 with the corresponding figure descriptions). It was thus shown that the investigated Zener diode exhibits a low, but nevertheless significant, efficiency in the breakdown / Zener voltage range (approximately one detected photon per 3000 electrons of the Zener diode current) and therefore appears to be ideally suited as a single-photon source for the realization of QRNGs in silicon-based BCD technology. Above all, the preferential radiation toward the detector offers significant advantages over the isotropic radiation in entropy sources of conventional photon sources used in iQRNGs. The silicide, commonly used in CMOS technology to reduce contact resistance between the metal contacts and the semiconductor, is both light-tight and mirror-smooth, so that even photons originally emitted upwards can be reflected back into the interior of the substrate by the silicide mirror.Accordingly designed and operated as SPS Zener diodes in avalanche mode are therefore also referred to below as light-emitting avalanche Zener diodes (Avalanche Light Emitting Zener diodes, Zener-avLED), in contrast to the Si-LEDs known from the state of the art.

[0099] The Zener avLEDs provided in the BCD technology used here as an example emit photons with wavelengths from the visible spectral range and have a relatively low Zener operating voltage of usually less than 8 V. Since the radiation of a Zener avLED is also typically directed such that the photons are emitted preferentially in a vertical 30 direction, i.e. away from the surface into the substrate, a much stronger isolation of the PLC and the generated photons from the environment of the semiconductor material can be achieved when used in an iQRNG, and tapping or injecting photons at the detector surface is made significantly more difficult.

[0100] With appropriate design of the SPAD belonging to an iQRNG, the efficiency of random number generation can be significantly increased and uncontrolled photon propagation in the semiconductor material can be largely prevented.

[0101] The second essential component for constructing a compact QRNG is therefore the selection of a suitably adapted SPAD design. Typically, these are also implemented near the surface in BCD technologies by appropriately forming p- or n-wells. Such near-surface SPADs are quite comparable to the prior art SPADs implemented in CMOS technology. In principle, the iQRNG known from EP 3 529 694 B1 with the Zener avLEDs described above could therefore also be implemented in BCD technologies. However, as already described above, the Zener avLEDs advantageously emit the photons preferably in the direction into the substrate. A juxtaposition of a Zener avLED as an SPS and a near-surface SPAD, as known from the prior art, could in principle be implemented, but not necessarily effectively.When using Zener avLEDs, it is advisable to place the corresponding SPAD below the Zener avLED.

[0102] In addition to the implementation of conventional n-SPADs and p-SPADs, BCD technology also enables the implementation of completely new SPAD concepts, including the use of deep n- or p-doped layers in a BCD substrate.

[0103] Using a method also recently developed by the inventors for generating deep pn junctions in a BCD process to provide a corresponding BCD substrate with deep pn junctions, a particularly efficient, deep-lying single-photon avalanche diode ("deepSPAD") was realized. This deepSPAD can be easily arranged directly below a Zener avLED configured to provide single photons. The combination of a Zener avLED in combination with a deep-lying SPAD thus provides the essential components of an iQRNG that is vertically integrated entirely using BCD technology, in contrast to the horizontal integration of an entropy source of an iQRNG based on CMOS technology according to the prior art.

[0104] By vertically arranging a Zener avLED as the emitter and a deepSPAD realized using extremely deep pn junctions as the receiver, a miniaturized entropy source of a quantum random number generator based on a monolithic silicon die can be realized in BCD technologies with highly efficient optical coupling, high attack resistance, and low operating voltage. Thus, the BCD-based iQRNG design presented here with the vertical entropy source represents an optimal solution to the inventive problem. In particular, the vertical 3D integration can further increase the compactness of an entropy source of an iQRNG and reduce the area consumption compared to conventional lateral 2D designs while simultaneously increasing efficiency.

[0105] Preferably, an entropy source of an iQRNG according to the invention is therefore formed in a BCD substrate using BCD technology.

[0106] Preferably, the BCD substrate comprises a carrier substrate and an epitaxial layer grown on the carrier substrate, wherein a deep pn junction located in the epitaxial layer is created between the carrier substrate and the epitaxial layer by diffusion of dopants introduced into a surface of the carrier substrate below the epitaxial layer.

[0107] The carrier substrate can preferably be a p-type substrate. However, n-type substrates or intrinsic substrates can also be used. The substrate material can in particular be silicon. However, the processes are in principle also adaptable for other semiconductor materials. A typical dopant for forming a p-type region is boron. Phosphorus (P), arsenic (As), or antimony (Sb) can be used to form an n-type region. In silicon, for example, boron as a dopant diffuses significantly further than the heavy donors (P, As, or Sb). It can also be seen that the n-type regions created are largely dominant due to the higher doses used, i.e. an n-type region already doped with phosphorus can retain its existing conductivity type even after additional boron has been added.To provide the deep pn junctions, additional mask, lithography and epitaxy steps in the usual BCD process can sometimes be omitted.

[0108] Preferably, the first and second dopant have different diffusion properties in the carrier substrate and / or in the epitaxial layer. Preferably, the second dopant has greater mobility in the carrier substrate and / or in the epitaxial layer than the first dopant. Preferably, the first dopant and / or the second dopant are introduced maskless or via a mask process. For maskless introduction, a direct ion beam writing process, for example, can be used. In a mask process, the introduction is carried out using a previously provided mask, wherein the introduction is carried out, for example, via a chemical or physical deposition process or also by means of an ion beam writing process.Preferably, immediately after the introduction of the second dopant, the first region or the second region completely overlies the other region in a plan view of the surface of the carrier substrate. Preferably, the first region is a deep n-type layer (NBL layer) and the second region is a deep p-type layer (PBL layer).

[0109] Preferably, the photon detector forms an avalanche region in a region around the deep pn junction and comprises an absorption region for converting photons into electron-hole pairs, wherein the absorption region is directly adjacent to the deep pn junction.

[0110] It is preferred that the deep pn junction is formed at least partially between a deep n-layer as the cathode and a deep p-layer directly adjacent to the deep n-layer. It is also preferred that the absorption region directly adjoins the deep p-layer and is essentially formed as a p-region. "Essentially" means that the absorption region can also be partially formed as an intrinsic region. It is further preferred that an anode formed as a p+ region directly adjoins the absorption region.

[0111] Preferably, a second deep pn junction (e.g., in the carrier substrate) formed below the deep pn junction of the photon detector located in the epitaxial layer is used as an additional photodetector for monitoring for external attacks. The method for producing deep pn junctions in a BCD process results in a second pn junction located below the first pn junction in some embodiments (see Fig. 3 with accompanying figure description). Due to its largely identical electronic properties, this can also be configured as a photodetector or single-photon avalanche diode. Since this additional photodetector is thus arranged below the actual QRNG arrangement, deeply buried in the semiconductor material, it can provide a protective function against photons injected from the back of the substrate.

[0112] These can be detected in close proximity to the QRNG over a wide angular range. This allows external attacks to be detected with a high degree of probability.

[0113] Preferably, the top and / or bottom side of the substrate in the region of the entropy source of the iQRNG is mirrored on one surface or this surface comprises a light-blocking layer. Mirroring the surfaces of a substrate (e.g., by means of metallization or the application of dichroic layers) and the application of a light-blocking layer are known in the art and have already been discussed above. These approaches can also be used in an entropy source according to the invention of an iQRNG according to the invention to shield against external photons ("shading") and to increase efficiency by reflecting back the photons generated by the associated photon source. Alternatively or additionally, appropriate encapsulation can also be provided in the region of the iQRNG or this region can be surrounded by a metal box.

[0114] Preferably, the surface of the substrate is covered with a silicide layer in the region of the entropy source of the iQRNG and with a metallization layer above it. Preferably, the metallization is closed in the region of the iQRNG. The metallization can act as a mirror coating for the interior and / or as a wavelength-independent shading for external photons. The same applies to a formed silicide layer.

[0115] Preferably, photons provided by the photon or single-photon source are prevented from escaping at the surface of the substrate and / or the back of the substrate by a combination of at least one element each consisting of metal covers, sidewall contacts, and vias. These elements can achieve a largely complete shielding or encapsulation of the iQRNG's entropy source, which not only provides external shielding but also ensures high immunity to external interference.

[0116] Preferably, several entropy sources of inventive iQRNGs according to the invention or a multi-channel QRNG system comprising a plurality of inventive iQRNGs with one or more entropy sources according to the invention are implemented on the same substrate in order to increase the data rate of the quantum random bits. Together with compact shielding of the individual entropy sources of the individual iQRNGs, very high integration densities can be achieved with a large number of one or more densely packed and preferably decoupled entropy sources of one or more iQRNGs, and thus overall high effective random number rates. In the case of entropy sources of iQRNGs in the prior art, the integration density is primarily limited by the structural juxtaposition of the individual components.

[0117] Preferably, an iQRNG according to the invention comprises an electronic circuit for generating and outputting a digital random number sequence based on the statistical evaluation of the temporal sequence of signals (photon detector signals) of the one or more photon detectors.

[0118] A further aspect of the present invention therefore relates to an integrated electronic circuit (IC) comprising at least one entropy source of an iQRNG according to the invention. In particular, these ICs can be used for applications based on security-relevant chip-based systems (System on Chip, SoC).

[0119] Preferably, an entropy source according to the invention of an iQRNG according to the invention is placed in a pad frame (also referred to as a pad edge) of the integrated electronic circuit. Preferably, the electronic circuit for generating and outputting a digital random number sequence is also located in the pad frame. In non-pad-determined integrated electronic circuits, the pad frame typically contains a large number of free areas, which, however, typically cannot be used for digital circuits or larger analog circuit blocks.However, since an iQRNG according to the invention with an entropy source according to the invention and an electronic circuit according to the invention for generating and outputting a digital random number sequence is correspondingly small due to its extremely compact design, and the subsequent circuitry also typically comprises only a small number of gates, this type of QRNG can nevertheless be fully or at least partially integrated into a conventional pad frame. Due to the extremely compact design of the iQRNG according to the invention, it can also be implemented in existing designs for integrated electronic circuits in a space-saving manner and without major effort. This significantly reduces space consumption compared to conventional approaches for integrating QRNGs. The advantages of an iQRNG according to the invention can thus be fully exploited.

[0120] The advantages of an iQRNG according to the invention over known implementations in the prior art are primarily based on the further miniaturization of the entire random number generator structure and the resulting high degree of integration and miniaturization of the generated structures. Due to the complete isolation of the PLC and the associated SPAD from the environment, the security of random number generation can be significantly increased. The directed vertical radiation from the Zener avLED used as the PLC also contributes to increased security and to a significant increase in the efficiency of random number generation, resulting in an increase in the random bit and random number rate.

[0121] A second deep pn junction, formed below the pn junction of the SPAD using a novel BCD technology, can be used as an additional photodetector to monitor attacks, particularly from the back of the iQRNG substrate of the relevant node in the network according to the invention. The efficiency of the optical coupling into the associated SPADs, as well as the isolation and security, can be further increased through the use of internal metal and silicide mirrors. Compared to the prior art, only a relatively low operating voltage of < 8 V is required for the Zener avLED used as a photon source. Furthermore, since the absorption length of the emitted visible light in silicon is short (i.e., the associated absorption coefficient is high), very good optical isolation between adjacent elements can be achieved.This enables arrangement in an array with high cell density and a resulting correspondingly high generation or entropy rate. 3. Encryption Unit (VE)

[0122] The encryption unit of the crypto engine KE processes a first random bit portion of the random bits of the random bit stream ZBS provided by the internal random number generator iZG in order to generate cryptographic keys based on this first random bit portion and to encrypt data that the random number generator ZZG (quantum random number generator) intends to send to other bus participants in the data bus network. Encryption in the crypto engine KE is preferably performed using computer- and / or machine-implemented algorithms. The crypto engine KE can, if necessary, be realized entirely as a computer-implemented device. In the case of computer-implemented algorithm components for encryption, their respective program code is preferably stored, at least temporarily, in a memory MEM of the crypto engine KE.When executing the computer-implemented algorithm parts, a CPU of the crypto engine KE reads the relevant program code in the memory MEM of the crypto engine KE and executes it. This has a technical effect in the form of secure encryption of data that the random number generator ZZG wants to send to another bus participant (e.g., MCU) via the data bus DB. This encrypted data can include a second random bit portion of the random bits of the random bit stream ZBS provided by the inner random number generator iZG. Preferably, the intersection of the first set of the first random bit portion of the random bits of the random bit stream ZBS provided by the inner random number generator iZG and the second set of the second random bit portion of the random bits of the random bit stream ZBS provided by the inner random number generator iZG is empty, so that no random bits can be sent from the random number generator ZZG to other bus participants (e.g.,MCU) of the data bus DB, which the random number generator ZZG used to encrypt its encrypted output data stream VZS. 4. Entropy module (WD)

[0123] The entropy module – also called watchdog WD – of the inner random number generator iZG monitors the entropy of the random bits of the random bit stream ZBS generated by the inner random number generator iZG or of random data derived therefrom. The entropy module WD preferably generates measured values ​​for typical parameters of the entropy of the random bits of the random bit stream ZBS of the inner random number generator iZG. Such measured values ​​can include, for example, mean value, standard deviation, etc. The entropy module WD preferably compares these measured values ​​with permissible value ranges and takes countermeasures if these measured values ​​lie outside these permissible value ranges. In this way, the entropy module WD ensures that sufficient randomness is present to guarantee secure cryptographic operations using the random bits of the random bit stream ZBS of the inner random number generator iZG. If necessary,The entropy module WD can also require reasonable deviations from randomness from a security perspective. For example, it can invert the random bit stream ZBS for the subsequent random bits of the random bit stream ZBS of the internal random number generator iZG whenever the internal random number generator iZG has generated a predetermined number of consecutive random bits in the random bit stream ZBS with the same logical content. This function of deliberately deviating from an ideal random bit stream ZBS can preferably be switched on and off via the data interface DBIF of the random number generator ZZG using an encrypted write command to a register or a flag of the random number generator ZZG or one of its device components.The entropy module WD preferably performs this monitoring using computer- and / or machine-implemented algorithms, with the respective program code of the computer-implemented algorithm components being stored in a memory MEM of the internal random number generator iZG and executed by a CPU of the internal random number generator iZG or the random number generator ZZG. The use of an entropy module WD in the random number generator ZZG has a technical effect in the form of increased security of the cryptographic processes of the crypto engine KE and improved usability of the random bits of the random bit stream ZBS of the internal random number generator iZG. 5. Filter module (EE)

[0124] The filter module (entropy extraction EE) of the internal random number generator iZG improves the statistical properties of the random bits of the random bit stream ZBS of the internal random number generator iZG by removing systematic patterns and ensuring the even distribution of the bits. Computer- and / or machine-implemented algorithms are also used here. The filter module EE is preferably part of the control logic CL. In the case of computer-implemented algorithm components, their program code is preferably stored at least temporarily in one or the memory MEM of the internal random number generator iZG and / or the random number generator ZZG. The CPU of the internal random number generator iZG executes the relevant program code in the memory MEM of the internal random number generator iZG when executing the corresponding algorithm components.The filter module achieves the technical effect of optimizing the random bits of the random bit stream ZBS for cryptographic applications. For example, the filter module EE can include a digital high-pass filter that limits the ideal white noise of an ideal random bit stream toward low frequencies, which has the effect of avoiding too many consecutive random bits in the random bit stream ZBS with the same logical content. 6. Interface unit (DBIF)

[0125] The interface unit (the data bus interface DBIF) of the random number generator ZZG enables preferably encrypted communication between the random number generator ZZG and external systems that are connected as bus participants to a shared data bus DB with the random number generator ZZG. The interface unit DBIF supports at least one, but preferably several, different communication protocols. This enables the use of the random number generator ZZG in different systems. For this purpose, the interface unit DBIF can preferably be configured via a voltage level at designated external terminals and / or via special cryptographic commands. The interface unit DBIF of the random number generator ZZG ensures that encrypted data can be securely transmitted by the random number generator ZZG and thus by the crypto engine KE.The communication protocols are controlled by computer- and / or machine-implemented algorithms and / or software programs. The program code of the computer-implemented algorithm components and / or the computer-implemented software components is preferably stored, at least temporarily, in one or more memories of the random number generator ZZG and / or the crypto engine KE. A CPU of the random number generator ZZG and / or the crypto engine KE executes this program code when communicating with other bus participants (e.g., MCU) of the connected data bus DB. In this way, the random number generator ZZG and / or the crypto engine KE achieve a technical effect in the form of secure data transmission between the random number generator ZZG and / or the crypto engine KE, on the one hand, and other bus participants (e.g., MCU) of the shared data bus DB, on the other.The data that the random number generator ZZG and / or the crypto engine KE transmits as part of the random number generator ZZG to other bus participants of the data bus DB can again include the said second random bit portion of the random bits of the random bit stream ZBS of the internal random number generator iZG and / or status information of the internal random number generator iZG and its device parts and / or status information of the crypto engine KE and / or status information of other device parts of the random number generator ZZG. The data that the random number generator ZZG and / or the crypto engine KE receive as part of the random number generator ZZG from other bus participants (e.g., MCU) via the data bus DB can again include the said control data for configuring the internal random number generator iZG and / or the crypto engine KE.The random number generator ZZG and / or the crypto engine KE and / or the inner random number generator iZG can comprise one or more CPU cores and / or one or more memories MEM, in which program code for the computer- and / or machine-implemented emulation of device parts of the random number generator ZZG and / or the crypto engine KE and / or the inner random number generator iZG and / or other device parts of the random number generator ZZG is stored, at least temporarily. Thus, such a CPU can be regarded as the CPU of the inner random number generator iZG and / or the random number generator ZZG and / or the crypto engine KE within the meaning of the document presented here. Thus, such a memory MEM can be regarded as the memory MEM of the inner random number generator iZG and / or the random number generator ZZG and / or the crypto engine KE within the meaning of the document presented here. 7. Function and interaction of the common device parts

[0126] The inner random number generator (RSG) of the random number generator ZZG typically continuously generates random bits of the random bit stream ZBS during operation. These random bits exhibit a high random bit rate of the random bit stream ZBS due to the vertical arrangement of the photon source and the photodetector in the entropy source WD. These random bits are preferably monitored by the entropy module (WD) using computer- and / or machine-implemented algorithms to ensure that they indeed exhibit high entropy, which is crucial for the security of the crypto engine KE and the random number generator ZZG.The monitored random bits of the entropy source are then filtered by the filter module (EE), which is also preferably controlled by computer and / or machine-implemented algorithms, to ensure that they do not contain any systematic patterns, are evenly distributed and do not include any random structures that would ultimately result in the random sending of messages in plaintext over a certain period of time.

[0127] A first filtered random bit portion of the filtered random bits is fed to the encryption unit (VE), which uses the filtered random bits of the first filtered random bit portion of the filtered random bits through computer- and / or machine-implemented algorithms to generate cryptographic keys and to encrypt data from the random number generator ZZG. The interface unit (DBIF) ensures the secure transmission of the encrypted data to external systems of other bus participants (e.g., MCU) of the external data bus DB through computer- and / or machine-implemented algorithms and / or software programs. The cooperation of these device components ensures a high level of security for the random number generator ZZG and the crypto engine KE as part of the random number generator ZZG, since the generated random bits are highly random and the cryptographic operations are therefore very difficult to compromise. First variant of the crypto engine: Standard crypto engine

[0128] This variant of the crypto engine is designed for general cryptographic applications. It includes all the common device components described above and provides a robust platform for performing encryption and decryption operations. Additional device parts:Key management unit (SWE)

[0129] This unit manages the generated cryptographic keys, stores them securely, and makes them available to the required processes. Management is preferably performed by computer- and / or machine-implemented algorithms, with the respective program code of the computer-implemented algorithm components preferably being stored at least temporarily in a memory MEM of the crypto engine KE and / or the random number generator ZZG. A CPU of the random number generator ZZG and / or the crypto engine KE typically executes this respective program code each time it executes a respective computer-implemented algorithm component. This serves the technical purpose of securely managing the keys of the crypto engine KE. Line control unit (LKE)

[0130] The line control unit LKE monitors the signals on the communication lines that run between the various modules of the random number generator ZZG and / or the crypto engine KE to ensure that data integrity is maintained. This is achieved, for example, by means of computer- and / or machine-implemented algorithms that achieve a technical effect in the form of increased data security. The respective program code of the computer-implemented algorithm components is preferably stored, at least temporarily, in a memory of the crypto engine KE and / or the random number generator ZZG. A CPU of the random number generator ZZG and / or the crypto engine KE typically executes this respective program code each time it executes a respective computer-implemented algorithm component. This serves the technical effect of securely managing the crypto engine keys.The performance control unit LKE can be part of a so-called watchdog WD of the random number generator ZZG, which monitors the correct function of the random number generator (health check) and, if necessary, detects attacks or measures the probability of an attack currently taking place and, if necessary, determines a corresponding measured value.

[0131] Advantages: This standard variant offers high security for general applications and is flexible in its use. The high random bit rate of the internal random number generator significantly increases the security of the generated keys.

[0132] Disadvantages: The standard variant does not offer special optimizations for specific cryptographic scenarios, as required in post-quantum cryptography. Second variant of the crypto engine: Post-Quantum Crypto Engine KE

[0133] This variant is specifically designed for the requirements of post-quantum cryptography. It contains additional components designed to protect the crypto engine against attacks by quantum computers and, potentially, modern artificial intelligence algorithms. Additional device parts Post-Quantum Coprocessor (PQC)

[0134] The post-quantum coprocessor PQK is a special processor designed to execute computer- and / or machine-implemented post-quantum cryptography algorithms. Preferably, the post-quantum coprocessor PQK is a device part of the crypto engine KE. However, the post-quantum coprocessor PQK can also be a device part of the random number generator ZZG and interact with the crypto engine KE. These algorithms are preferably computer- and / or machine-implemented. The respective program code of the computer-implemented algorithm components is preferably stored, at least temporarily, in a memory MEM of the crypto engine KE and / or the random number generator ZZG. A CPU of the random number generator ZZG and / or the crypto engine KE typically executes this respective program code.when it executes a respective computer-implemented algorithm component. The execution of the computer-implemented algorithms produces a technical effect in the form of increased resistance to quantum attacks. Particularly preferably, the crypto engine KE and / or the random number generator ZZG use one or more of the following methods for PQC encryption: 'BIKE1-L1-CPA', 'BIKE1-L3-CPA', 'BIKE1-L1-FO', 'BIKE1-L3-FO', 'Kyber512', 'Kyber768', 'Kyber1024', 'Kyber512-90s', 'Kyber768-90s', 'Kyber1024-90s', 'LEDAcryptKEM-LT12', 'LEDAcrypt-KEM-LT32', 'LEDAcryptKEM-LT52', 'NewHope-512-CCA', 'NewHope-1024-CCA', 'NTRU-HPS-2048-509', 'NTRU-HPS-2048-677', 'NTRU-HPS-4096-821', 'NTRU-HRSS-701', 'LightSaber-KEM', 'Saber-KEM', 'FireSaber-KEM', 'BabyBear', 'BabyBearEphem', 'Mama-Bear', 'MamaBearEphem', 'PapaBear', 'PapaBearEphem', 'FrodoKEM-640-AES', 'FrodoKEM-640-SHAKE', 'FrodoKEM-976-AES', 'FrodoKEM-976-SHAKE', 'FrodoKEM-1344-AES', 'FrodoKEM-1344-SHAKE',‚SIDH-p434', ‚SIDH-p503', ‚SIDH-p610', ,SIDH-p751', ‚SIDH-p434-compressed', ‚SIDH-p503-compressed', ‚SIDH-p610-compressed', ‚SIDH-p751-compressed', ‚SIKE-p434', ‚SIKE-p503', ‚SIKE-p610', ‚SIKE-p751', ‚SIKE-p434-compressed', ‚SIKE-p503-compressed','SIKE-p610-compressed','SIKE-p751-compressed'.,

[0135] Particularly preferably, the crypto engine KE and / or the random number generator ZZG uses one or more of the following PQC signature methods for signing data messages: 'DILITHIUM_2', 'DILITHIUM_3', 'DILITHIUM_4', 'MQDSS-31-48', MQDSS-31-64', SPHINCS+-Haraka-128f-robust', SPHINCS+-Haraka-128f-simple', 'SPHINCS+-Haraka-128s-robust', 'SPHINCS+-Haraka-128s-simple', 'SPHINCS+-Haraka-192f-robust', 'SPHINCS+-Haraka-192f-simple', 'SPHINCS+-Haraka-192s-robust', 'SPHINCS+-Haraka-192s-simple', 'SPHINCS+-Haraka-256f-robust', 'SPHINCS+-Haraka-256f-simple', 'SPHINCS+-Haraka-256s-robust', 'SPHINCS+-Haraka-256s-simple', 'SPHINCS+-SHA256-128f-robust', 'SPHINCS+-SHA256-128f-simple', 'SPHINCS+-SHA256-128s-robust', 'SPHINCS+-SHA256-128s-simple', 'SPHINCS+-SHA256-192f-robust', 'SPHINCS+-SHA256-192f-simple', 'SPHINCS+-SHA256-192s-robust', 'SPHINCS+-SHA256-192s-simple', 'SPHINCS+-SHA256-256f-robust', 'SPHINCS+-SHA256-256f-simple', 'SPHINCS+-SHA256-256s-robust','SPHINCS+-SHA256-256ssimple', 'SPHINCS+-SHAKE256-128f-robust', 'SPHINCS+-SHAKE256-128f-simple', 'SPHINCS+-SHAKE256-128s-robust', 'SPHINCS+-SHAKE256-128s-simple', 'SPHINCS+-SHAKE256-192f-robust', 'SPHINCS+-SHAKE256-192fsimple', 'SPHINCS+-SHAKE256-192s-robust', 'SPHINCS+-SHAKE256-192s-simple', 'SPHINCS+-SHAKE256-256f-robust', 'SPHINCS+-SHAKE256-256fsimple', 'SPHINCS+-SHAKE256-256s-robust', 'SPHINCS+-SHAKE256-256s-simple',m'picnic_L1_FS', 'picnic_L1_UR', 'picnic_L3_FS', 'picnic_L3_UR', 'picnic_L5_FS', 'picnic_L5_UR', 'picnic2_L1_FS', 'picnic2_L3_FS', 'picnic2_L5_FS', 'qTesla-pI', 'qTesla-p-III'.,

[0136] Preferably, a second random bit portion of the random bit stream s ZBS of the random number generator ZZG is used to generate the relevant signatures and keys. Quantum Resistant Key Generator (QRK)

[0137] This quantum-resistant key generator QRK is preferably part of the crypto engine KE and / or the random number generator ZZG and generates keys that are resistant to quantum attacks according to the current state of the art. The quantum-resistant key generator QRK preferably uses random bits from the first random bit portion of the random bits of the random bit stream ZBS of the internal random number generator (ZZG). The quantum-resistant key generator QRK preferably also operates with computer- and / or machine-implemented algorithms, the program code of which is preferably stored at least temporarily in a memory MEM of the crypto engine KE and / or in a memory MEM of the random number generator ZZG. The respective program code of the computer-implemented algorithm portions is preferably stored at least temporarily in a memory MEM of the crypto engine KE and / or in a memory MEM of the random number generator ZZG.A CPU of the random number generator (ZZG) and / or the crypto engine (KE) typically executes this respective program code each time it executes a respective computer-implemented algorithm component. Executing the algorithms produces a technical effect in the form of the generation of secure, quantum-resistant keys. Function and interaction

[0138] The inner random number generator (RSG) provides a high random bit rate of the random bit stream (ZBS), which is required for generating quantum-resistant keys. These keys are generated by the quantum-resistant key generator (QRK) and then used by the post-quantum coprocessor (PQK) to encrypt the data that the RSG and / or its crypto engine (KE) and / or their device components wish to transmit. The interface unit (DBIF) has been adapted to ensure the secure transmission of the quantum-resistant keys. Here, too, computer- and / or machine-implemented algorithms and / or software are preferably used.The crypto-engine KE and / or the random number generator preferably operate with computer- and / or machine-implemented algorithms, the program code of which is preferably stored at least temporarily in a memory MEM of the crypto-engine KE and / or in a memory MEM of the random number generator ZZG. The respective program code of the computer-implemented algorithm components is preferably stored at least temporarily in a memory MEM of the crypto-engine KE and / or in a memory MEM of the random number generator ZZG. A CPU of the random number generator ZZG and / or the crypto-engine KE typically executes this respective program code when it executes a respective computer-implemented algorithm component and / or software component.The execution of the computer and / or machine-implemented algorithms and / or software components produces a technical effect in the form of ensuring the security of the data transmission from and to the random number generator ZZG.

[0139] Advantages: This variant offers protection against future quantum attacks, making it ideal for long-term security-critical applications.

[0140] Disadvantages: The additional hardware requires more space and power, which can reduce efficiency in less safety-critical applications. Third variant of the crypto engine: High-performance crypto engine

[0141] This variant is designed for applications that require particularly high computing power, such as high-frequency trading systems or other time-critical applications. Additional device partsParallel Encryption Processor (PVP)

[0142] This parallel encryption processor (PVP) enables the crypto engine (KE) to perform multiple encryption operations simultaneously to minimize processing time. Parallel processing is preferably performed by computer- and / or machine-implemented algorithms. In the case of computer-implemented algorithm components, their program code is preferably stored, at least temporarily, in a memory (MEM) of the crypto engine (KE) and / or in a memory (MEM) of the random number generator (ZZG). A CPU of the crypto engine (KE) and / or of the random number generator (ZZG) executes this program code when executing the respective computer-implemented algorithm components. For this purpose, the random number generator (ZZG) can preferably also comprise more than one CPU and more than one internal random number generator (iZG). This typically has the technical effect of enabling the random number generator (ZZG) to process data more quickly. Fast Clock Line (STL)

[0143] A dedicated clock line STL preferably synchronizes the operations of the parallel encryption processor PVP with the other modules of the crypto engine KE and / or the random number generator ZZG to avoid delays. The fast clock line STL is also controlled by computer- and / or machine-implemented algorithms. A CPU of the crypto engine KE and / or the random number generator ZZG executes this program code when executing the respective computer-implemented algorithm components. For this purpose, the random number generator ZZG can preferably also comprise more than one CPU and more than one internal random number generator iZG. This typically has the technical effect of the desired synchronization. Function and interaction

[0144] The internal random number generator (RNG) provides the required random bits at a high random bit rate, which are passed directly to the parallel encryption processor (PVP). The parallel encryption processor (PVP) uses these random bits to perform parallel encryption operations, while the fast clock line (STL) ensures that the operations of the device components of the RNG run synchronously. The execution of parallel encryption by the parallel encryption processor (PVP) ensures a technical effect in the form of enabling the RNG to achieve increased processing speed.

[0145] Advantages: This variant offers extremely high computing power and allows the simultaneous execution of multiple cryptographic operations, which is advantageous in time-critical applications.

[0146] Disadvantages: The high complexity and energy consumption of this variant may be unnecessary in less demanding environments. Fourth variant of the crypto engine: Energy-efficient crypto engine

[0147] This variant is aimed at applications where energy consumption must be minimized, such as in mobile devices or IoT systems. Additional device parts Energy saving module (ESM)

[0148] This energy-saving module ESM monitors and regulates the energy consumption of the random number generator ZZG and the crypto engine KE of the random number generator ZZG by deactivating unused modules or reducing their power. Control is achieved, among other things, by computer- and / or machine-implemented algorithms. A CPU of the crypto engine KE and / or the CPU of the random number generator ZZG executes this program code when executing the relevant computer-implemented algorithm components. This typically has the technical effect of saving energy. It is conceivable that the random number generator ZZG receives, preferably encrypted, commands via the data bus DB to restrict or stop the generation of random bits. The random number generator ZZG can also have a power-down pin, for example, to reduce energy consumption.This is particularly advantageous because the entropy source of the internal random number generator (RSG) typically requires increased voltages. All of this has the technical effect of optimizing energy consumption. Low-Power Clock Line (NET)

[0149] The random number generator ZZG and / or the crypto engine KE may include a dedicated clock line operating at a lower frequency to further reduce energy consumption. Function and interaction

[0150] The internal random number generator (RNG) operates either in a low-power mode with lower power consumption and typically a lower random bit rate (which can then be zero) or in a normal operating mode with increased power consumption and a higher random bit rate. The low-power clock line ensures that only the necessary random bits are generated. The low-power clock line synchronizes the operations of the RNG and the crypto engine (KE) at low power consumption. The technical effect of this variant is a significant reduction in power consumption while maintaining the security of cryptographic operations.

[0151] Advantages: This variant is particularly suitable for use in battery-operated devices as it reduces energy consumption to a minimum.

[0152] Disadvantages: The reduced performance may not be sufficient in applications that require high computing power. Fifth variant of the crypto engine: Security-focused crypto engine

[0153] This variant is aimed at applications with the highest security requirements, such as government communications or military systems. Additional fixture parts

[0154] Security Monitor (SM): The security monitor SM (watchdog) of the random number generator ZZG continuously monitors the state of the internal random number generator iZG, the crypto engine KE and / or the other device components of the random number generator ZZG and can, in the event of an attack or error, shut down or reconfigure the random number generator ZZG and / or the crypto engine KE and / or other device components of the random number generator ZZG or put them into a secure mode and / or an emergency mode. Preferably, the security module SM signals one or more bus participants (e.g.MCU) on the data bus DB reports such an incident, for example via an interrupt line and / or via an interrupt line in conjunction with the setting of a specific register flag and / or via an interrupt in conjunction with the setting of a specific register value in a register of the random number generator ZZG and / or by setting a specific register and / or flag value in a register of the random number generator ZZG. Monitoring and control are carried out by computer- and / or machine-implemented algorithms. The program code of the computer-implemented algorithm parts is preferably stored at least temporarily in a memory MEM of the random number generator ZZG and / or the crypto engine KE of the random number generator ZZG. A CPU of the random number generator ZZG and / or the crypto engine KE of the random number generator ZZG preferably executes this program code when it executes the relevant algorithm part.This has the technical effect of improving and ensuring the security of the entire crypto engine (KE) and the random number generator (ZZG). Preferably, the security monitor (SM) is part of the aforementioned watchdog (WD), which performs the health check. Preferably, the security monitor (SM) is implemented entirely, or at least substantially, in hardware to reduce the risk of manipulation. Secured Communication Unit (GKE)

[0155] This secure communication unit (GKE) ensures encrypted and tap-proof communication across all external interfaces (e.g., DBIF). Encryption is preferably implemented using computer- and / or machine-implemented software programs, whose program code is stored in a memory (MEM) of the crypto engine (KE) and / or in a memory (MEM) of the random number generator (ZZG) and executed by a CPU to achieve a technical effect in the form of secure communication. Function and interaction

[0156] The internal random number generator (RSG) continuously supplies random bits, which are monitored for integrity by the security monitor SM. The secure communication unit GKE ensures that all external data transmissions via the data bus DB are encrypted and protected against eavesdropping attempts. The computer- and / or machine-implemented monitoring algorithms of the security monitor M and the GKE encryption software achieve a technical effect in the form of maximum security for the crypto engine KE and the random number generator RSG.

[0157] Advantages: This variant offers maximum protection against attacks and is ideal for highly security-critical applications.

[0158] Disadvantages: The complexity and associated costs may make this variant unsuitable for less safety-critical applications. Summary of the crypto engine description

[0159] In all of these variants, the random number generator (RNG) plays a central role, as feature A enables a particularly high random bit rate, which forms the basis for secure cryptographic operations. This high bit rate is particularly advantageous in the post-quantum crypto engine (KE) and the post-quantum random number generator (IZG), as it significantly increases security against quantum attacks. In the other variants, the high random bit rate also ensures improved security and efficiency by forming the basis for fast and secure key generation and encryption operations.

[0160] By implementing the algorithms and software programs on a CPU of the crypto engine KE and / or the random number generator ZZG and storing them in a memory MEM of the crypto engine KE and / or a memory MEM of the random number generator ZZG, specific technical effects are achieved in all variants that optimize the crypto engine KE and the random number generator ZZG for various security-critical applications. ConfigurationsRandom Number Generator (RNG)

[0161] The document presented here describes a random number generator (ZZG). The random number generator (ZZG) comprises an inner random number generator (iZG), a crypto engine (KE), and a data bus interface (DBIF) for a data bus (DB). Preferably, the inner random number generator (iZG) is configured to generate a random bit data stream (ZBS) whose random bits have random logical values ​​as defined by the NIST test and to transmit at least some of these random bits and / or data derived therefrom in encrypted form to other network participants via the data bus (DB) using the crypto engine (KE) and the data bus interface (DBIF). This improves the availability of random bits and / or random numbers and / or keys derived therefrom and / or authentication data in the network of network nodes connected to the data bus and / or networks accessible via it.

[0162] Preferably, other network nodes can access one or more random bits of the internal random number generator (iZG) and / or data derived therefrom, encrypted or unencrypted, via the data bus interface (DBIF), in order to obtain the necessary access to random bits and / or random numbers and / or keys and / or authentication data derived therefrom, without AI programs and / or quantum computers being able to monitor this.

[0163] For this purpose, one or more network nodes of the network can preferably configure the internal random number generator (iZG) and / or the crypto engine (KE) via the data bus interface (DBIF), for example, by setting or clearing register values, in order to adapt the properties of these device components to the task to be solved. This can, for example, affect the level of encryption security, since a high level of encryption can, for example, reduce the payload data rate g.

[0164] Preferably, the inner random number generator (IRG) comprises a TRNG (True Random Number Generator) for truly random bits to maximize the entropy quality of the random bits and / or random numbers. When used for key generation, this reduces the probability of a successful attack. Preferably, the RNG comprises an entropy source (EQ) that provides an entropy source output signal based on quantum processes, the signals of which convey randomness.For example, the temporal spacing of pulses on the entropy source output signal may be random, such that the first difference between a first temporal spacing of a first pair of two pulses of the entropy source output signal and the second difference between a second temporal spacing of a second, different pair of two pulses of the entropy source output signal, if different, are different in such a way that it cannot be predicted whether the first difference or the second difference is the greater of these two differences. For example, the entropy source may comprise a photon source that is maintained in an energetically excited state and therefore randomly emits photons, and a photon detector that randomly detects a portion of these photons and generates a pulse on the entropy source output signal upon detection of a photon.

[0165] Preferably, the inner random number generator (iZG) comprises a QRNG (Quantum Random Number Generator) or the inner random number generator (iZG) is such a QRNG (Quantum Random Number Generator), since for physical reasons this provides random numbers of maximum (best) entropy and is therefore optimal for key generation.

[0166] Preferably, the crypto engine (KE) and / or other device parts of the random number generator (ZZG) are configured toto transmit one or more self-generated keys to other bus participants (MCUs) on the data bus (DB) via the data bus interface (DBIF) of the random number generator (ZZG) in encrypted form or as public keys from one or more key pairs consisting of a public and private key and / or to receive one or more public keys from these other bus participants (MCUs) via the data bus (DB) and / or to keep previously agreed secret keys in a memory (MEM) of the crypto engine (KE) and / or the random number generator (ZZG) and to establish an encrypted connection based on these keys and to encrypt a second random bit portion of the random bits of the random bit data stream (ZBS) of the inner random number generator (iZG) and to transmit it in encrypted form to one or more other bus participants (MCUs) on the data bus (DB). This enables the quantum random number generator,to send the keys securely to other network participants within the network or to keep them available for use by them.

[0167] For this purpose, the crypto engine (KE) is preferably configured to use a first portion of the random bits of the random bit stream (ZBS) of the inner random number generator (iZG) for key generation. This means that the other random bits are not used for key generation, and no side channel is created.

[0168] Furthermore, the crypto engine (KE) is preferably configured to use one or more keys, in particular keys as described above, to encrypt a second random bit portion of the random bits of the random bit data stream (ZBS) of the internal random number generator (iZG) into encrypted random bits (VZS). This prevents the other random bits from being reused, thus preventing a side channel from being created.

[0169] Preferably, the crypto engine (KE) is configured to output one or more encrypted random bits (VZS) via the data bus interface (DBIF). The output can also be in the form of encrypted random numbers based on the random bits and / or encrypted sequences of randomly determined characters using the random bits and / or in the form of encrypted random data words based on the random bits. This enables the randomness generated by the random number generator (ZZG) to be distributed throughout the network. The crypto engine (KE) is connected to this network via the data bus interface (DBIF) and the data bus connected to it. For the purposes of this document, the data bus and / or the network can be fully or partially wired and / or wireless. Therefore, the data bus interface (DBIF) can comprise a wired interface for data and / or a wireless interface.For the purposes of this document, the data bus interface (DBIF) can therefore also comprise multiple interfaces to one or more data transmission channels. The term data bus, throughout this document, refers to a wireless and / or wired data transmission channel in a network that, at least temporarily, includes one or more additional network nodes that communicate with the random number generator (RNG) and / or the crypto engine (LE) via the data bus interface (DBIF).

[0170] Preferably, the internal random number generator (iZG) of the random number generator (ZZG) is configured to generate random bits with a high random bit rate, wherein the internal random number generator (iZG) has a vertical entropy source (EQ) preferably monolithically integrated into a common semiconductor substrate relative to the horizontal surface O of this common semiconductor substrate in order to enable the high random bit rate. Therefore, the semiconductor substrate preferably comprises at least one, preferably several, and most preferably all device components of the proposed random number generator (ZZG).Preferably, the plane of the PN junction of the photon source of the entropy source of the inner random number generator (iZG) and the plane of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG) are each firstly arranged parallel to the surface O of the semiconductor substrate and secondly arranged parallel to one another at different distances from the surface of the semiconductor substrate. As a result, the plane of the PN junction of the photon source of the entropy source of the inner random number generator (iZG) and the plane of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG) have a positive distance from one another that is different from 0.

[0171] Preferably, the projection of the border of the PN junction of the photon source of the entropy source of the inner random number generator (iZG) from the plane of the PN junction of the photon source of the entropy source of the inner random number generator (iZG) onto the plane of the surface O of the semiconductor substrate and the projection of the border of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG) from the plane of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG) onto the surface O of the semiconductor substrate overlap.

[0172] Preferably, as a first possibility, the projection of the border of the PN junction of the photon source of the entropy source of the inner random number generator (iZG) from the plane of the PN junction of the photon source of the entropy source of the inner random number generator (iZG) onto the plane of the PN junction of the photon detector lies entirely within the border of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG).

[0173] Preferably, as a second possibility, the projection of the border of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG) from the plane of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG) onto the plane of the PN junction of the photon source lies entirely within the border of the PN junction of the photon source of the entropy source of the inner random number generator (iZG).

[0174] As a second possibility, the projection of the border of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG) from the plane of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG) onto the plane of the PN junction of the photon source is particularly preferred, essentially congruent with the border of the PN junction of the photon source of the entropy source of the inner random number generator (iZG).

[0175] The previous three arrangements of these PN junctions, and especially the latter arrangement of PN junctions, ensure that a maximum number (approximately half) of the photons emitted by the PN junction of the photon source are emitted toward the PN junction of the photon detector. Furthermore, this ensures that a maximum number of photons emitted by the PN junction of the photon source toward the PN junction of the photon detector are detected by the PN junction of the photon detector. This increases the frequency of the random pulses on the entropy source output signal. This, in turn, maximizes the random bit rate.This allows the crypto engine (KE) to generate keys more quickly and / or exchange keys with other network nodes more quickly and / or provide more random bits and / or random numbers and / or random data words and / or random sequences of characters and / or longer sequences of characters to other network participants and / or other device components of the random number generator (RNG) and / or device components of devices in which the RNG is a part. This increases the resilience of the network nodes and the number of available random bits in the network. This increases the robustness of the network and its network nodes, including the RNG, against attacks using, for example, AI programs and / or quantum computers.

[0176] For example, a vertical entropy source (EQ) of the inner random number generator (iZG) may comprise a specific circuit configuration that utilizes an improved entropy source (EQ) to maximize the quality of the random bits. Such a circuit configuration may, for example, comprise a voltage source that reverse-biases the photon source to a relatively high voltage across the PN junction of the photon source, resulting in the emission of photons, and a voltage source that reverse-biases the photon detector via a second load resistor to a second voltage such that a received photon results in a pulsed current flow through the PN junction of the photon detector, resulting in a pulsed voltage drop across the PN junction, which can be digitized by a subsequent analog-to-digital converter (ADC) circuit.The other possible device components are described in conjunction with the description of the figures. This has the advantage that the circuit can be operated from a common power supply. The additional circuit components enable further technical advantages.

[0177] Preferably, the inner random number generator (iZG) comprises an entropy module (WD), in particular as part of a watchdog (WD), which is a technical advantage 1. Firstly, it enables the detection of technical defects of the internal random number generator (iZG) and their signalling to a higher-level computer system of the random number generator (ZZG) and / or other network nodes, and 2. Secondly, it enables the detection of attacks on the internal random number generator (iZG) and their signalling to a higher-level computer system of the random number generator (ZZG) and / or other network nodes, and 3. thirdly, the acquisition of state values ​​of device parts of the internal random number generator (iZG), such as voltage values ​​of the supply voltage of the entropy source (EQ), as well as their evaluation and the signaling of these state values ​​and / or these evaluations to a higher-level computer system of the random number generator (ZZG) and / or other network nodes and / or the reconfiguration of the random number generator (ZZG) depending on these state values ​​and / or evaluations (for example, switching to redundant additional entropy sources and / or voltage supplies of the internal random number generator (iZG)), and 4. fourthly, it enables the detection of attacks on the internal random number generator (iZG), for example on the basis of the recorded state values ​​and / or the evaluations derived therefrom, and the signalling of the recorded state values ​​and / or the evaluations derived therefrom to a higher-level computer system of the random number generator (ZZG) and / or other network nodes, and 5. Fifthly, countermeasures are enabled, for example after the detection of attacks on the internal random number generator (iZG), for example on the basis of the recorded state values ​​and / or the evaluations derived therefrom, and the signalling of these countermeasures to a higher-level computer system of the random number generator (ZZG) and / or other network nodes.

[0178] The internal random number generator (iZG) preferably comprises an entropy module (WD), in particular as part of a watchdog (WD), which monitors and evaluates the entropy of the random bits generated by the internal random number generator (iZG), for example by measuring the random bit data output stream of the random bit output signal of the entropy source and / or the entropy extraction of the internal random number generator (iZG). This measurement can be carried out, for example, by the entropy module (WD) counting the number of 1' bits and the number of 0' bits and comparing these two numerical values, for example by taking the difference, and detecting an error if this difference exceeds the specified maximum value too often. Various other functionally equivalent implementations with up-down counters, etc., are also conceivable here.Error counters can also be provided to prevent excessive, random deviations that are certain to occur from immediately triggering an error message. All of this ensures, in particular, the reliability of the cryptographic processes and / or the signature processes of the random number generator (RNG) and in the network nodes of the network connected via the data bus interface (DBIF).

[0179] In other implementations, the random number generator (RNG) may, for example, comprise a filter module that improves the statistical properties of the random bits to produce filtered random bits, in particular to ensure a uniform distribution of the random bits and / or high-pass properties of the spectrum of the random bit data stream (RBS). It may happen by chance that the correct signal from a correctly functioning entropy source (EQ) leads to a purely random generation of a very large number of consecutive random bits of a single logical value. This can lead to a loss of encryption capability. Therefore, it is useful to remove this so-called bias using a digital high-pass filter and / or a functionally equivalent device, so that for every predetermined number of random bits with an identical logical value, this logical value always changes.For example, the filter can also be designed so that the random bit data stream is inverted after n consecutive logical values ​​of the same logical value until n consecutive logical values ​​of the same logical value appear again, and this inversion is canceled by the filter module. This ensures that the random bits and / or random numbers and / or random data words and / or random sequences of characters are highly suitable for encryption purposes. The filter module can also, for example, be part of the entropy extraction or other device components of the random number generator (RNG).

[0180] Preferably, the vertical entropy source (EQ) and / or the internal random number generator (iZG) and / or the random number generator (ZZG) and / or the crypto engine (KE) and / or the data bus interface are implemented by an ASIC implementation and / or a monolithic microelectronic implementation. The data bus interface can be implemented, for example, using CMOS, BiCMOS, BCD, or GaAa technology, or other semiconductor technologies, and in particular as a microintegrated circuit (IC). This typically increases the performance and energy efficiency of the random number generator (ZZG) and optimizes its physical properties, such as bit data rate, as well as its vulnerability to attacks. It also makes the random number generator (ZZG) robust against high acceleration values, such as those encountered in projectiles during firing.Preferably, therefore, the random number generator has a design of this type that makes the random number generator robust against accelerations greater than 500g, preferably greater than 1000g, preferably greater than 200g, preferably greater than 5000g, preferably greater than 10000g, preferably greater than 20000g, preferably greater than 50000g, preferably greater than 10000g, preferably greater than 20000g, preferably greater than 50000g. Most preferably, the random number generator is cubic, as it then has a maximum area moment of inertia and maximum robustness against acceleration forces and acting torsional and bending moments. The document presented here therefore also discloses a projectile comprising such a preferably monolithically microintegrated random number generator (RNG) and a wireless data interface for encrypted, secure communication with one or more base stations.

[0181] Furthermore, in another embodiment, the random number generator (ZZG) preferably comprises a calibration unit for self-calibrating device components of the internal random number generator (iZG), such as one or the analog-to-digital converter and / or one or the digital-to-analog converter and / or one or more voltage sources and / or one or more reference voltage sources and / or one or more reference current sources and / or one or more electrical resistors and / or one or more diodes, etc., in order to ensure, in particular, the long-term stability and accuracy of the random bit generation and to detect short-term changes in such device components of the random number generator (ZZG). The calibration unit can therefore also be part of the watchdog (WD), which preferably performs the health check of the device.

[0182] Furthermore, in another embodiment of the random number generator (ZZG), the random number generator (ZZG) and / or the crypto engine (KE) are preferably modular in design and preferably have interchangeable encryption and internal random number generator modules by means of programming, in particular to enable simple adaptation to different cryptographic requirements and / or error states. In this way, the random number generator can, for example, in the event of attacks on individual device components of the random number generator (ZZG) and / or in the event of defects in individual device components of the random number generator (ZZG), replace these components with functional device components, for example by switching switches and / or switching matrices inserted into the signal path.For example, the watchdog (WD) and / or switching signals of a computer system of the random number generator (ZZG) and / or the crypto unit (KE) and / or a preferably encrypted command via a data interface from the network can trigger such a switching.

[0183] Furthermore, in another embodiment of the random number generator (RNG), the interface unit (data bus interface) (DBIF) of the RNG supports various communication protocols, preferably selectable by hardware or software programming, in particular to ensure interoperability in and / or with different external systems. This enables the use of identical instantiations of the proposed RNG in different application scenarios and simplifies the logistics of these device components, thus reducing costs.

[0184] Furthermore, in another embodiment of the random number generator (RNG), the crypto engine (KE) and / or the random number generator (RNG) are preferably integrated into a system-on-chip (SoC), particularly to provide a compact and powerful solution for embedded systems. This enables robust solutions against attacks and the influence of physical variables.

[0185] Furthermore, in another embodiment of the random number generator (RSG), the inner random number generator (IRG) functions, at least temporarily, as the inner random number generator (IRG) of the crypto engine (KE). This has the advantage that the crypto engine can, at least temporarily, use at least part of the random bit data stream of the inner random number generator (IRG) for key generation and / or authentication purposes and / or the encryption of data and the other random bits of the random bit data stream of the inner random number generator (IRG).

[0186] Furthermore, in another embodiment of the random number generator (ZZG), the crypto engine (KE) is preferably configured to use only a first random bit portion of the random bits of the random bit stream (ZBS) of the inner random number generator (iZG). This also has the advantage that the crypto engine can, at least temporarily, use at least a portion of the random bit data stream of the inner random number generator (iZG) for key generation and / or authentication purposes and / or the encryption of data and the other random bits of the random bit data stream of the inner random number generator (iZG).

[0187] Furthermore, in another embodiment of the random number generator (ZZG), the random number generator (ZZG) is configured to forward a second random bit portion of the random bits of the inner random number generator (iZG) to other bus participants (MCU) via the data bus (DB).This has the advantage that the random number generator (ZZG) can serve as a random number generator (ZZG) for other network nodes and / or their device parts in the network, which is typically connected wirelessly or wired via the data bus interface of the random number generator (ZZG), and that these network nodes of the network and / or their device parts can thus use one or more random bits and / or one or more random data words and / or one or more random numbers and / or one or more random sequences of characters generated by the random number generator (ZZG) for other computer- and / or machine-implemented methods which these network nodes execute in whole or in part.

[0188] Furthermore, in another embodiment of the random number generator (ZZG), the data bus (DB), if it is wired, is, for example, a serial bus, in order to enable, in particular, a flexible connection to different bus participants.

[0189] Furthermore, in another embodiment of the random number generator (RSG), the crypto engine (KE) is configured, for example, to encrypt data from the internal random number generator (IRG) that is sent to one or more other bus nodes (MCUs), in particular to ensure the security of the transmitted data. This data can, for example, within the meaning of the document presented here, comprise one or more random bits and / or one or more random data words and / or one or more random numbers and / or one or more random sequences of characters generated by the random number generator (RSG), and data derived therefrom.

[0190] Furthermore, in another embodiment of the random number generator (ZZG), the crypto engine (KE) is configured, for example, to decrypt encrypted data that the random number generator (ZZG) receives from one or more other bus users (MCU) and to make it available to device parts of the random number generator (ZZG), for example registers and / or control registers and / or flags, or to use it itself, in particular to enable secure data communication within the system comprising the random number generator (ZZG) and other bus users (MCU) of the data bus (DB) and / or other network nodes of the network.

[0191] Furthermore, in another embodiment of the random number generator (ZZG), the data sent to other bus users (MCU) from the random number generator (ZZG) and / or one or more of its device parts comprise one or more random bits of the internal random number generator (iZG) and / or status information of the internal random number generator (iZG), in particular to enable broad applicability of the random data. One or more random bits means that it can be, for example, one or more random bits and / or one or more random data words and / or one or more random numbers and / or one or more random sequences of characters generated by the random number generator (ZZG) and / or data based thereon.In the event of attacks on the random number generator (RNG) and / or its device components, it is advantageous if the RNG signals to the other network nodes in the network that the quality of the random bits is lower and transmits corresponding evaluation information. This enables the network nodes in the network, for example, to switch to random bits from other RNGs in the network and / or to start their own RNGs and / or computer- and / or machine-implemented methods for generating pseudorandom numbers as a replacement for the potentially corrupted random bits of the RNG.

[0192] Furthermore, in another embodiment of the random number generator (ZZG), the crypto engine (KE) is configured to decrypt encrypted control and / or configuration information for the internal random number generator (iZG) and / or other device parts of the random number generator (ZZG) and / or for the crypto engine (KE) itself, in particular to ensure secure and flexible control of the random number generator (ZZG) and / or its device parts. This enables secure control of the random number generator (ZZG) and the internal random number generator (iZG) and / or other device parts of the random number generator (ZZG) and / or the crypto engine (KE) by other network nodes of the network.

[0193] Furthermore, in another embodiment of the random number generator (ZZG), the status information of device parts of the inner random number generator (iZG) comprises a current operating mode and / or error messages in order to enable, in particular, precise monitoring and control of the random number generator (ZZG), in particular by the or a computer system of the random number generator (ZZG) and / or a computer system of a network node of the network.

[0194] Furthermore, in another embodiment of the random number generator (ZZG), the crypto engine (KE) is preferably configured to use a second random bit portion of the random bits of the random bit stream (ZBS) of the internal random number generator (iZG) for generating keys and / or signatures. This separates the otherwise used random bits of the first random bit portion of the random bits of the random bit stream (ZBS) of the internal random number generator (iZG) from the second random bit portion of the random bits of the random bit stream (ZBS) of the internal random number generator (iZG). The keys thus generated can be used to transmit the first random bit portion of the random bits of the random bit stream (ZBS) of the internal random number generator (iZG) and data based thereon to other network accounts in the network without weakening the encryption through the double use of random bits.As a prerequisite for the application of this technique, a high random bit data rate of the random bit stream (ZBS) of the inner random number generator (iZG) is required.

[0195] Furthermore, in another embodiment of the random number generator (ZZG), the crypto engine (KE) is preferably configured to encrypt data from the random number generator (ZZG) and / or device components of the random number generator (ZZG) using one or more of these keys. This allows the random number generator to securely make this data available to other network nodes in the network for use, and possibly analysis.

[0196] Furthermore, in another embodiment of the random number generator (ZZG), the crypto engine (KE) is preferably configured to encrypt data of the random number generator (ZZG) and / or device parts of the random number generator (ZZG) using one or more of the keys and a computer- and / or machine-implemented PQC encryption method. This prevents successful attacks on the communication of the random number generator (ZZG) using quantum computers and / or computer- and / or machine-implemented artificial intelligence methods.

[0197] Furthermore, in another embodiment of the random number generator (ZZG), the crypto engine (KE) is preferably configured to sign data from the random number generator (ZZG) and / or device components of the random number generator (ZZG) using one or more of the signatures. This enables the other network nodes of the network to authenticate the origin of the data they receive from the random number generator (ZZG) as data from the random number generator (ZZG). This can also be the identity of the random number generator. This can prevent a man-in-the-middle attack.

[0198] Furthermore, in another embodiment of the random number generator (RNG), the crypto engine (KE) is preferably configured to verify and / or authenticate data received from other bus nodes (MCU) in a predetermined and / or computer- or machine-implemented manner and / or randomly, in particular to ensure data integrity. This prevents the RNG from being reconfigured without authorization by control commands and thus also ensures this aspect of the security of the RNG and / or the network with its network nodes.

[0199] Furthermore, in another embodiment of the random number generator (RNG), the crypto engine (KE) is preferably configured to sign data that the RNG sends to other bus nodes (MCUs) with a signature. This also prevents the man-in-the-middle problem and thus also ensures this aspect of the security of the RNG and / or the network with its network nodes, since no device components inserted into the data transmission channel can then pose as a RNG.

[0200] Furthermore, in another embodiment of the random number generator (RNG), the crypto engine (KE) is preferably configured to decrypt encrypted data from other bus nodes (MCUs). This also prevents the RNG from being reconfigured without authorization by control commands and thus also ensures this aspect of the security of the RNG and / or the network with its network nodes.

[0201] Furthermore, in another embodiment of the random number generator (ZZG), the crypto engine (KE) is preferably configured so that the data of the other bus participants (MCU) can include random bits from other random number generators, in particular to increase flexibility when handling multiple random number generators. This allows the random number generator (ZZG), for example, to create a supply of random bits in a memory of the random number generator (ZZG) and then, for example, to provide a large number of random bits at a very short notice, for example upon request from a network node of the network and / or other device components, with an extremely high, burst-like random bit data rate. Of course, these random bits can then also include the random number generator's own random bits.When a technically trained person refers to the term random bits in this document, they always include the data that can be derived from them, such as random numbers, random data words and / or random sequences of characters and similar random data.

[0202] Furthermore, in another embodiment of the random number generator (ZZG), the crypto engine (KE) is preferably configured so that the data of the other bus participants (MCU) can include keys and / or signatures of other random number generators, in particular to increase flexibility when handling multiple random number generators. This prevents random data from unauthorized network nodes from being smuggled into the data sent by the random number generator. This is thus also a measure to prevent the man-in-the-middle problem.

[0203] Furthermore, in another embodiment of the random number generator (ZZG), the crypto engine (KE) and / or the random number generator (ZZG) and / or device parts of the random number generator (ZZG) are preferably configured to use keys and / or signatures and / or random bits of other random number generators a) for the generation of keys and / or signatures and / or random bits and / or b) for the use of keys and / or signatures and / or random bits and / or c) for which the encryption of data of the random number generator (ZZG) or of parts of the random number generator (ZZG) and / or d) to be used for signing data from the random number generator (RNG) and / or device components of the RNG. This enables, for example, the application of computer- and / or machine-implemented encryption algorithms such as the Diffie-Hellman key exchange method by these device components of the RNG. This makes the RNG compatible with common security technology methods.

[0204] Furthermore, in another embodiment of the random number generator (RNG), the RNG is preferably implemented as a hardware component as part of a microelectronic circuit, in particular an ASIC or an FPGA or a memory (DRAMs, flash memory, SRAMs or ROMs, or a processor (CPU)), in particular to ensure high performance and efficiency. This also increases resistance to attacks. For example, this embodiment of the RNG can be substantially embodied as a typically more or less freely programmable FPGA. In this case, the FPGA preferably comprises an entropy source. The entropy source of the FPGA is preferably implemented as a vertical entropy source. It is preferably a quantum-technological entropy source with a photon source and a photon detector, as already described several times in this document.Preferably, the FPGA comprises the necessary analog circuits (voltage sources and / or ADC) to operate the entropy source and to convert the signal from the entropy source (EQ) into a digitized signal for use in other gates and circuits of the FPGA. The other device parts of the proposed random number generator described in this document can therefore be provided as machine- and / or computer-implemented devices by the FPGA after its programming for use as a random number generator (RSG). An implementation of a device part and / or a method by programming an FPGA represents an FPGA-implemented device or an FPGA-implemented method within the meaning of this document. Such an FPGA-implemented device is a machine-implemented device within the meaning of the document presented here.Such a method implemented on an FPGA is a machine-implemented method within the meaning of the document presented here. The FPGA preferably comprises additional device components of the random number generator (RSG) and / or the internal random number generator (IRG). These can be circuit components of the FPGA that comprise these device components and are non-programmable, and programmable circuit components of the FPGA that comprise these device components as programmed FPGA-implemented device components.

[0205] The combination of the technical teaching presented here concerning random number generators with FPGAs has the technical advantage of increased flexibility of application possibilities and protectability of FPGA-based devices and device components.

[0206] Furthermore, in another embodiment of the random number generator (ZZG), the data interface (DBIF) preferably supports multiple hardware- or programmably selectable communication protocols, in particular to ensure compatibility with different bus participants. The data interface can establish the data connection to one or more wired or wireless data transmission channels and the associated network of network nodes. The flexibility of the data bus protocols increases the usability of the technical teaching presented here with regard to the proposed random number generator.

[0207] Furthermore, in another embodiment of the random number generator (ZZG), a data bus (DB) connected to the data interface (DBIF) as an exemplary wired data transmission channel is preferably a serial data bus, in particular a LIN data bus, with exactly one single-wire data line and one ground line. This has the advantage that the proposed random number generator can then be operated with very simple and inexpensive data buses.

[0208] Furthermore, in another embodiment of the random number generator (ZZG), a data bus (DB) which is connected to the data interface (DBIF) as an exemplary wired data transmission channel, for example, is preferably a serial differential data bus, in particular a CAN data bus, with exactly one first single-wire data line, exactly one second single-wire data line, and an optional ground line, which can be the body of a vehicle, for example, wherein the data is then preferably transmitted as a voltage difference signal of the difference between the potential of the first single-wire data line and the potential of the second single-wire data line. This has the advantage that the proposed random number generator can then be operated with widely used, interference-robust data buses such as the CAN bus or the CAN-FD bus.

[0209] Furthermore, in another embodiment of the random number generator (ZZG), the data bus interface (DBIF) and / or the crypto engine (KE) and / or a device of the random number generator (ZZG) preferably comprise an error detection and correction unit, in particular to increase the reliability of data communication. This ensures, for example, that no transmitted keys are lost and that communication between the random number generator (ZZG) on the one hand and other network nodes of the network on the other hand cannot collapse due to asynchronicity of the current key of a key set.

[0210] Furthermore, in another embodiment of the random number generator (ZZG), the crypto engine (KE) is configured to store at least a portion of the random bits after receiving them from the internal random number generator (iZG), particularly in a memory (MEM), in order to enable buffering for subsequent processing. This allows the crypto engine (KE) to temporarily use higher virtual internal random bit rates and to respond robustly to high loads.

[0211] Furthermore, in another embodiment of the random number generator (ZZG), the crypto engine (KE) is configured to process the random bits of the first random bit portion of the random bits of the random bit stream (ZBS) of the inner random number generator (iZG) in real time, in particular to ensure low latency in safety-critical applications.

[0212] Furthermore, in another embodiment of the random number generator (ZZG), the crypto engine (KE) and / or the inner random number generator (iZG) and / or the random number generator (ZZG) and / or other device parts of the random number generator (ZZG) have a modular and programmable architecture, in particular an FPGA device part, in order to facilitate, in particular, the dynamic adaptation of the random number generator to different security requirements. This dynamic adaptation can, for example, relate to the proportion of random bits used by the random number generator (ZZG) itself and made available to the network nodes of the network, and to data derived therefrom.

[0213] Furthermore, in another embodiment of the random number generator (ZZG), the crypto engine (KE) and / or the random number generator (ZZG) and / or the internal random number generator (iZG) and / or other device components of the random number generator (ZG) are preferably configurable through software updates of the computer system of the random number generator and / or an FPGA of the random number generator, in particular to enable adaptability to new cryptographic standards. In this case, the random number generator (ZZG) preferably executes a computer- and / or machine- and / or FPGA-implemented method for secure, typically encrypted software download or download of FPGA configuration data and / or similar information into the random number generator (ZZG).

[0214] Furthermore, in another embodiment of the random number generator (ZZG), the crypto engine (KE) and / or the random number generator (ZZG) and / or the internal random number generator (iZG) and / or other device parts of the random number generator (ZZG) are preferably integrated into a monolithic microcontroller system, in particular for use in embedded systems. For example, the computer core (CPU) of such a microcontroller system can at least temporarily execute computer- and / or machine- and / or FPGA-implemented methods that emulate one or more device parts of the random number generator (ZZG) and / or utilize the entropy source (EQ) and / or the random bit stream of the entropy source output signal or random bits of the internal random number data stream (iZG) and / or further execute other computer- and / or machine- and / or FPGA-implemented methods for other purposes.

[0215] Furthermore, in another embodiment of the random number generator (ZZG), the crypto engine (KE) and / or the random number generator (ZZG) and / or the internal random number generator (iZG) and / or other device parts of the random number generator (ZZG) preferably comprise an interface (JTAG) for diagnosis and maintenance, in particular a JTAG interface, in order to improve in particular the programmability and / or maintainability and / or testability of the random number generator (ZZG).

[0216] Furthermore, in another embodiment of the random number generator (ZZG), the crypto engine (KE) and / or the random number generator (ZZG) and / or the internal random number generator (iZG) and / or other device components of the random number generator (ZZG) are preferably equipped with a respective power-saving function, in particular to minimize energy consumption in portable or energy-efficient applications. The respective power-saving function is preferably controlled by means of a configuration command via the data bus (DB) and / or by signaling via a power-down connection of the random number generator (ZZG) and / or by initiation via a timer of the random number generator (ZZG). Crypto Engine (KE)

[0217] Furthermore, the document presented here describes a crypto engine (KE) as a device component for use in a previously described random number generator (RNG). According to the proposal, the crypto engine (KE) comprises an encryption unit that uses the random bits of the inner random number generator (IRG) to generate cryptographic keys and / or encrypt data. This has the advantage that the crypto engine (KE) can access the high data rate of the random bits of the inner random number generator and thus only needs to encrypt a small amount of payload data with the same key.

[0218] Furthermore, in another embodiment of the crypto engine (KE), the encryption unit for generating cryptographic keys is preferably configured to generate, in particular, secure keys for various cryptographic algorithms. This enables secure data communication between the random number generator (RNG) or the device of which the crypto engine is a part, and network nodes in the network.

[0219] Furthermore, in another embodiment of the crypto engine (KE), the encryption unit supports both symmetric and asymmetric encryption algorithms, in particular to ensure flexibility in the encryption of the data communication of the random number generator (RSG) and / or the crypto engine with network participants of a network in different types of applications depending on the encryption requirement of this application.

[0220] Furthermore, in another embodiment, the crypto engine (KE) comprises a memory module and / or a memory (MEM) for temporarily storing the random bits generated by the internal random number generator (ZZG), in particular to enable efficient data processing.

[0221] Furthermore, in another embodiment of the crypto engine (KE), the interface unit supports encrypted data transmission via one or more data bus interfaces (DBIF) via wired and / or wireless data transmission channels of the random number generator (ZZG), in particular to increase the security of the communication of the crypto engine (KE) and / or the random number generator (ZZG) with network nodes of the network.

[0222] Furthermore, in another embodiment of the crypto engine (KE), the crypto engine (KE) is, for example, modular in design and comprises, by means of programming, interchangeable encryption and internal random number generator modules, in particular to enable easy adaptation of the crypto engine to different cryptographic requirements, which may include, for example, operational and / or error and / or attack requirements. Uses

[0223] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a VPN system for secure key generation and management for encrypted VPN connections. This has the advantage that such secure key generation using the proposed device enables a high key exchange rate due to the high random bit data rate of the internal random number generator, thus increasing the ratio of the number of encryption bits to the number of useful bits in the data channel toward 1, which reduces the probability of a successful attack.

[0224] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in IoT networks to ensure the integrity and confidentiality of communication between IoT devices. The compact and inexpensive design of the described RNG enables the equipping of typically very price-sensitive IoT devices with state-of-the-art encryption technology. This is especially true if the RNG is a quantum random number generator (QNG), as proposed here.

[0225] Furthermore, the document presented here describes a use of the aforementioned random number generator (RNG) in cloud computing environments for secure data processing and storage in cloud environments. The technical teaching proposed here allows one or more individual server cabinets and / or one or more individual servers and / or even one or more individual storage units such as hard disks and / or SSDs and / or one or more individual memory modules to be provided with a proposed random number generator or to operate as such a random number generator, at least temporarily, if the corresponding device components are present in the device in question.Thus, the document presented here discloses a server farm with a plurality of servers, wherein the server farm comprises one or more of the random number generators presented here and / or the inner random number generators (iZG) presented here and / or one or more of the entropy sources (EQ) presented here, each with at least one photon source and at least one photon detector for the respective photons of the respective photon source and for the respective generation of the respective entropy source output signal and the respective downstream evaluation circuits for the respective extraction of the respective random bits from the respective entropy source output signal for use by device parts of the server farm.Preferably, the respective photon source of the respective entropy source (EQ) and the associated respective photon detector of the respective photon source are again arranged monolithically in at least one common, respective semiconductor substrate, as described, below the respective surface O of the respective semiconductor substrate vertically one above the other in order to maximize the respective random bit data rate.

[0226] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in financial transaction systems for the secure execution and verification of financial transactions. This preferably applies to mobile, transportable devices such as mobile phones, chip cards, VPN tokens, PCs, USB sticks, memory cards, key cards, etc. Due to their compact and robust design, such random number generators with a vertically monolithically integrated entropy source are particularly suitable for such applications and increase their security.

[0227] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in communication systems for the secure transmission of messages and data in communication networks. This primarily applies to mobile, transportable devices such as radios, telephones and telex machines, mobile phones, PCs, laptops, surf sticks, TV adapters, VPN tokens, USB sticks, memory cards, key cards, etc. Due to their compact and robust design, such random number generators with a vertically monolithically integrated entropy source are particularly suitable for such applications and increase their security. Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in conjunction with a microcontroller (MCU) to enable secure key generation and management.This enables secure software downloading into a microcontroller memory, secure encryption of data in a microcontroller memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the microcontroller, and secure data transfer to and from the microcontroller as well as individualization of the microcontroller using a random identity number.

[0228] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in conjunction with a CPU in an embedded system to ensure secure encryption and data transmission. This enables secure software downloads to the CPU's memory, secure encryption of data in the CPU's memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the CPU, secure data transmission to and from the CPU, and the individualization of the CPU using a random identity number.

[0229] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in conjunction with a sensor evaluation and control circuit to ensure the integrity and confidentiality of the sensor data. This enables secure software downloading into a memory of the sensor evaluation and control circuit, secure encryption of data in a memory of the sensor evaluation and control circuit, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the sensor evaluation and control circuit, secure data transfer to and from the sensor evaluation and control circuit, and individualization of the sensor evaluation and control circuit using a random identity number.

[0230] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in conjunction with a network node in a wired or wireless network to increase the security of communication protocols. This enables secure software downloading to a network node's memory, secure encryption of data in a network node's memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the network node, secure data transmission to and from the network node, and individualization of the network node using a random identity number.

[0231] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in conjunction with a chip card to enable secure authentication and data processing on the card. This enables secure software downloading to a chip card memory, secure encryption of data in a chip card memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the chip card, secure data transfer to and from the chip card, and individualization of the chip card using a random identity number.

[0232] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a network node in an IoT network to ensure secure communication between IoT devices. This enables secure software downloads to the IoT device's memory, secure encryption of data in the IoT device's memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the IoT device, secure data transfer to and from the IoT device, and individualization of the IoT device using a random identity number.

[0233] Furthermore, the document presented here describes a use of the aforementioned random number generator (RNG) in a cloud computing system to enable the encryption and secure storage of data in the cloud.

[0234] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a financial transaction system to ensure the security and confidentiality of transactions.

[0235] Furthermore, the document presented here describes a use of the aforementioned random number generator (RNG) in a communication system to enable the secure transmission of messages and data.

[0236] Furthermore, the document presented here describes a use of the above-described random number generator (RNG) in a portable device, in particular in a smartphone or a telephone or the like, in order to realize secure and energy-efficient encryption.

[0237] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in one or more sensors in a sensor network to ensure the authentication and integrity of the sensor data.

[0238] Furthermore, the document presented here describes a use of the above-described random number generator (RSG) in a vehicle control system and / or a vehicle network to ensure secure communication between the control units and / or with device parts of the vehicle.

[0239] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a weapon control system and / or a network within a weapon system to ensure secure communication between the device components of the weapon system, in particular between missiles, ship hulls, submersibles, spacecraft and / or satellites, autonomous vehicles, stationary weapons, etc., on the one hand, and among themselves and / or with base stations, on the other. The term "weapon control system" includes ammunition systems.This enables secure software downloading into a memory of the weapon control system, secure encryption of data in a memory of the weapon control system, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the weapon control system, and secure data transmission to and from the weapon control system as well as individualization of the weapon control system by means of a random identity number.

[0240] Furthermore, the document presented here describes a use of the aforementioned random number generator (ZZG) in a military equipment system for soldiers in order to ensure secure communication between the device components of the military equipment system and / or between the military equipment systems of different soldiers and / or between the military equipment systems of one or more soldiers on the one hand and one or more weapon systems and / or military networks on the other hand.This enables secure software downloading into a memory of the military equipment system, secure encryption of data in a memory of the military equipment system, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the military equipment system, and secure data transfer to and from the military equipment system as well as the individualization of the military equipment system by means of a random identity number.

[0241] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a medical device to protect the confidentiality of patient data and patient measurement values ​​from patient sensors and to ensure security. This enables secure software downloading into a medical device memory, secure encryption of data in a medical device memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the medical device, and secure data transfer to and from the medical device, as well as the individualization of the medical device using a random identity number.

[0242] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in an industrial automation system in a production process to ensure the security of control commands and data against attacks. This enables secure software downloading into a memory of the industrial automation system, secure encryption of data in a memory of the industrial automation system, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the industrial automation system, and secure data transmission to and from the industrial automation system, as well as the individualization of the industrial automation system using a random identity number.

[0243] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a smart home system to ensure the secure control and communication of smart home devices in a property or a fixed installation and / or in an infrastructure object. This enables secure software downloading to a smart home system memory, secure encryption of data in a smart home system memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the smart home system, secure data transmission to and from the smart home system, and individualization of the smart home system using a random identity number.

[0244] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in an infrastructure system to ensure the secure control and communication of the infrastructure system's device components (gas supply, drinking water supply, wastewater supply, power supply, district heating supply, etc.). This enables secure software downloading into an infrastructure system's memory, secure encryption of data in an infrastructure system's memory, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the infrastructure system, secure data transmission to and from the infrastructure system, and individualization of the infrastructure system using a random identity number.

[0245] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a microprocessor, comprising in particular an ALU (Arithmetic Logic Unit), an internal microprocessor data bus, a control unit, and registers for generating random numbers for cryptographic operations directly in the processor. This enables secure software downloading into a microprocessor memory, secure encryption of data in a microprocessor memory, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the microprocessor, secure data transfer to and from the microprocessor, and individualization of the microprocessor using a random identity number.

[0246] Furthermore, the document presented here describes a use of the aforementioned random number generator (RNG) in an FPGA (Field-Programmable Gate Array). The FPGA typically comprises configurable logic circuits and / or configurable logic blocks and / or configurable lookup tables and / or configurable and / or programmable connections. Furthermore, such an FPGA comprises, for example, auxiliary circuits such as voltage regulators and / or voltage converters and / or data interfaces and other device components. However, this not only enables configurable cryptographic functions in the FPGA and / or other uses of random bits and / or random numbers in the FPGA, particularly in real time.This enables secure software downloading into an FPGA memory, secure encryption of data in an FPGA memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents and / or configuration data of the FPGA, and secure data transfer to and from the FPGA as well as individualization of the FPGA using a random identity number.

[0247] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a DSP (digital signal processor), comprising, in particular, specialized MAC units (multiply-accumulate units) and pipeline architectures to enable secure signal processing in safety-critical applications. This enables secure software downloading into a DSP memory, secure encryption of data in a DSP memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the DSP, secure data transfer to and from the DSP, and individualization of the DSP using a random identity number.

[0248] Furthermore, the document presented here describes a use of the above-described random number generator (RSG) in an ASIC (Application-Specific Integrated Circuit) and / or a CMOS or BiCMOS or bipolar circuit, comprising in particular specialized circuits for cryptographic functions, in order to integrate dedicated, high-performance cryptographic functions.This enables secure software downloading into a memory of the ASIC and / or the CMOS or BiCMOS or bipolar circuit, secure encryption of data in a memory of the ASIC and / or the CMOS or BiCMOS or bipolar circuit, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the ASIC and / or the CMOS or BiCMOS or bipolar circuit, and secure data transfer to and from the ASIC and / or the CMOS or BiCMOS or bipolar circuit as well as the individualization of the ASIC and / or the CMOS or BiCMOS or bipolar circuit by means of a random identity number.

[0249] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a SoC (System-on-Chip) architecture, comprising, in particular, a microprocessor, one or more memories, one or more peripheral modules, and a data bus on a single microintegrated chip, particularly to create a compact and efficient solution for embedded systems. This enables secure software downloading into a SoC memory, secure encryption of data in a SoC memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the SoC, secure data transfer to and from the SoC, and individualization of the SoC using a random identity number.

[0250] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a GPU (Graphics Processing Unit), in particular comprising shader cores, texture units, and memory controllers, in particular to execute cryptographic calculations in parallel with graphics processing and / or in particular to execute computer- and / or machine-implemented AI methods. This enables secure software downloading into a GPU memory, secure encryption of data in a GPU memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the GPU, secure data transfer to and from the GPU, and individualization of the GPU using a random identity number.

[0251] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a network processor, comprising, in particular, packet processing units and protocol engines, particularly to support secure data transmissions and protocol processing. This enables secure software downloads to a memory of the network processor, secure encryption of data in a memory of the network processor, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the network processor, secure data transmission to and from the network processor, and individualization of the network processor using a random identity number.

[0252] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a security chip for smart cards, comprising, in particular, a cryptographic processing unit and secure memory areas to enable secure authentication and encryption operations. This enables secure software downloading into a memory of the security chip, secure encryption of data in a memory of the security chip, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the security chip, secure data transfer to and from the security chip, and individualization of the security chip using a random identity number.

[0253] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a TPM (Trusted Platform Module), comprising, in particular, a cryptographic coprocessor unit and a secure memory, in particular to support secure storage and authentication processes in computer platforms. This enables secure software downloading into a TPM memory, secure encryption of data in a TPM memory, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the TPM, secure data transfer to and from the TPM, and individualization of the TPM using a random identity number.

[0254] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in an IoT processor, including, in particular, integrated radio modules and / or power management units and / or sensor interfaces, to ensure the integrity and confidentiality of communication in networked devices and the measured values. This enables secure software downloading into an IoT processor memory, secure encryption of data in an IoT processor memory, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the IoT processor, secure data transmission to and from the IoT processor, and individualization of the IoT processor using a random identity number.

[0255] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a control chip for industrial control systems, comprising, in particular, specialized interfaces for industrial protocols and real-time controllers, in particular to ensure secure control commands and data processing. This enables secure software downloading into a memory of the control chip, secure encryption of data in a memory of the control chip, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the control chip, secure data transfer to and from the control chip, and individualization of the control chip using a random identity number.

[0256] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a communications processor for mobile devices, comprising, in particular, baseband processors, modem units, and signal coding units, in particular to ensure the security of voice and data transmissions. This enables secure software downloading into a memory of the communications processor, secure encryption of data in a memory of the communications processor, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the communications processor, secure data transmission to and from the communications processor, and individualization of the communications processor using a random identity number.

[0257] Furthermore, the document presented here describes a use of the aforementioned random number generator (RNG) in a wearable processor or a piece of clothing or accessory comprising a processor - here referred to as a wearable processor - comprising energy efficiency modules, wireless communication interfaces and integrated sensors to enable secure data processing and communication in wearable devices and / or smart clothing. This enables secure software downloading into a memory of the garment or accessory, secure encryption of data in a memory of the garment or accessory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the garment or accessory, and secure data transmission to and from the garment or accessory as well as the individualization of the garment or accessory.Accessories using a random identity number.

[0258] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a memory controller, comprising in particular memory management units, cache controllers, and memory bus interfaces, to ensure the encryption of data in memory components. This enables secure software downloading into a memory of the memory controller, secure encryption of data in a memory of the memory controller, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the memory controller, secure data transfer to and from the memory controller, and individualization of the memory controller using a random identity number.

[0259] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in an automotive processor, in particular including CAN bus interfaces and / or other automotive data bus interfaces, such as LIN bus interfaces, security modules, and real-time controllers, to ensure secure communication and control in vehicle networks. This enables secure software downloading into a memory of the automotive processor, secure encryption of data in a memory of the automotive processor, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the automotive processor, secure data transmission to and from the automotive processor, and individualization of the automotive processor using a random identity number.

[0260] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a control chip for medical devices, in particular comprising integrated signal processing units, communication interfaces, and security modules to ensure the confidentiality and integrity of patient data and / or patient measurement data. This enables secure software downloading into a memory of the control chip, secure encryption of data in a memory of the control chip, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the control chip, secure data transmission to and from the control chip, and individualization of the control chip using a random identity number.

[0261] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a control chip for drones and / or unmanned vehicles, floating bodies, missiles, or satellites, in particular comprising integrated flight and / or motion control units, communication modules, and sensor interfaces to ensure secure communication and control commands between the drone and the control unit. This enables secure software downloading into a memory of the control chip, secure encryption of data in a memory of the control chip, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the control chip, secure data transmission to and from the control chip, and individualization of the control chip using a random identity number.

[0262] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a processor for computer-implemented virtual machines, in particular comprising virtualization and memory management units, to enable the secure execution of virtual instances on a host system. This enables secure software downloading into a processor memory, secure encryption of data in a processor memory, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the processor, secure data transfer to and from the processor, and individualization of the processor using a random identity number.In particular, it enables computer-implemented customization of the computer-implemented virtual machines and variation of the virtual behavior of these computer-implemented virtual machines.

[0263] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in one or more processors of a processor system for executing computer-implemented models of virtual processors, in particular, including virtualization and memory management units, to enable the secure execution of virtual instances on a host system. This enables secure software downloading into the memory of one or more processors, secure encryption of data in the memory of one or more processors, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of one or more processors, secure data transfer to and from one or more processors, and the individualization of one or more processors using a random identity number.

[0264] Furthermore, the document presented here describes a use of the aforementioned random number generator (RNG) in a cryptocurrency mining chip, in particular, including specialized hashing engines, power management, and memory controllers to ensure the generation and verification of cryptographic hashes.

[0265] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a processor for edge computing, in particular, comprising specialized network modules, data processing units, and memory controllers to enable secure and decentralized data processing at the network edges. This enables secure software downloading to a processor memory, secure encryption of data in a processor memory, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the processor, secure data transfer to and from the processor, and individualization of the processor using a random identity number.

[0266] Furthermore, the document presented here describes a use of the aforementioned random number generator (RNG) in a processor for distributed ledger technologies (blockchain), in particular comprising specialized encryption units, memory management and network interfaces, in particular to ensure the security and integrity of the distributed transactions. Inner Random Number Generator (IRG)

[0267] The document presented here describes an inner random number generator (iZG) for a random number generator (ZZG) as described above. The inner random number generator described here comprises, according to the proposal, a means for generating random numbers with a high random bit rate, wherein the inner random number generator has a vertical entropy source (EQ) which enables the high random bit rate. The entropy source (EQ) is preferably embodied monolithically in a substrate. This is preferably a semiconductor substrate. For example, it can be a silicon or GaAs or III / V or II / VI substrate or another semiconducting mixed crystal substrate, with a silicon substrate being particularly preferred. It is preferably a substrate which has been processed in a CMOS or BiCMOS or bipolar process, such that it contains one or more CMOS components orone or more BiCMOS components or one or more bipolar components, which are preferably interconnected to form a microelectronic circuit. The entropy source (EQ) preferably comprises a first PN junction as a photon source and a second PN junction as a photon detector. Preferably,

[0268] Preferably, the internal random number generator (iZG) of the random number generator (ZZG) is configured to generate random bits by arranging the photon source relative to the photon detector at a high random bit rate. The internal random number generator (iZG) comprises a vertical entropy source (EQ), preferably monolithically integrated into a common semiconductor substrate, relative to the horizontal surface O of this common semiconductor substrate to enable the high random bit rate. Therefore, the semiconductor substrate preferably comprises at least one, preferably several, and most preferably all device components of the proposed random number generator (ZZG).Preferably, the plane of the PN junction of the photon source of the entropy source of the inner random number generator (iZG) and the plane of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG) are each arranged, firstly, parallel to the surface O of the semiconductor substrate (this orientation is only optional) and, secondly, parallel to each other at different distances from the surface of the semiconductor substrate. As a result, the plane of the PN junction of the photon source of the entropy source of the inner random number generator (iZG) and the plane of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG) have a positive distance from each other that is different from 0.

[0269] The alignment of the plane of the PN junction of the photon source of the entropy source of the inner random number generator (iZG) and the plane of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG) parallel to each other is particularly important for the high random bit rate and a core element of the invention in order to maximize the number of photons emitted by the PN junction of the photon source of the entropy source of the inner random number generator (iZG) and detected by the PN junction of the photon detector of the entropy source of the inner random number generator (iZG), and thus to maximize the random bit rate.

[0270] Such a vertical entropy source, with this parallel alignment of the plane of the PN junction of the photon source of the entropy source of the inner random number generator (iZG) and the plane of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG), is a vertical entropy source as defined in this document. The orientation relative to the surface of the semiconductor substrate, on the other hand, is merely an aid to understanding and is useful for improved manufacturability in the respective semiconductor manufacturing process (CMOS, BiCOMS, or bipolar).

[0271] Preferably, the projection of the border of the PN junction of the photon source of the entropy source of the inner random number generator (iZG) from the plane of the PN junction of the photon source of the entropy source of the inner random number generator (iZG) onto the plane of the surface O of the semiconductor substrate and the projection of the border of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG) from the plane of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG) onto the surface O of the semiconductor substrate overlap.

[0272] Preferably, as a first possibility, the projection of the border of the PN junction of the photon source of the entropy source of the inner random number generator (iZG) from the plane of the PN junction of the photon source of the entropy source of the inner random number generator (iZG) onto the plane of the PN junction of the photon detector lies entirely within the border of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG).

[0273] Preferably, as a second possibility, the projection of the border of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG) from the plane of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG) onto the plane of the PN junction of the photon source lies entirely within the border of the PN junction of the photon source of the entropy source of the inner random number generator (iZG).

[0274] As a second possibility, the projection of the border of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG) from the plane of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG) onto the plane of the PN junction of the photon source is particularly preferred, essentially congruent with the border of the PN junction of the photon source of the entropy source of the inner random number generator (iZG).

[0275] The previous three arrangements of these PN junctions, and especially the latter arrangement of PN junctions, ensure that a maximum number (approximately half) of the photons emitted by the PN junction of the photon source are emitted toward the PN junction of the photon detector. Furthermore, this ensures that a maximum number of photons emitted by the PN junction of the photon source toward the PN junction of the photon detector are detected by the PN junction of the photon detector. This increases the frequency of the random pulses on the entropy source output signal. This, in turn, maximizes the random bit rate.This allows the crypto engine (KE) to generate keys more quickly and / or exchange keys with other network nodes more quickly and / or provide more random bits and / or random numbers and / or random data words and / or random sequences of characters and / or longer sequences of characters to other network participants and / or other device components of the random number generator (RNG) and / or device components of devices in which the RNG is a part. This increases the resilience of the network nodes and the number of available random bits in the network. This increases the robustness of the network and its network nodes, including the RNG and the internal RNG, against attacks using, for example, AI programs and / or quantum computers.

[0276] Furthermore, in another embodiment of the inner random number generator (iZG), the vertical entropy source (EQ) comprises a vertical arrangement of a photon source (120) and a photon detector (130) that utilizes an improved entropy source (EQ). Such a vertical arrangement of a photon source (120) and a photon detector (130) has, within the meaning of the document presented here, the said parallel alignment of the plane of the PN junction of the photon source of the entropy source of the inner random number generator (iZG) and the plane of the PN junction of the photon detector of the entropy source of the inner random number generator (iZG) parallel to one another. This parallelism is characteristic of this vertical arrangement. This vertical arrangement of a photon source (120) and a photon detector (130) constitutes the said vertical entropy source within the meaning of the document presented here.The orientation relative to the surface of the semiconductor substrate, on the other hand, is merely an aid to understanding and is useful for improving manufacturability in the respective semiconductor manufacturing process (CMOS, BiCOMS, or bipolar). The advantage lies in the increased number of photons emitted by the photon source toward the photon detector and the increased proportion of these photons detected by the photon detector. This results in an increased random event rate of the entropy source output signal and thus an increased random bit rate of the internal random number generator (IDG).

[0277] Furthermore, in another embodiment of the inner random number generator (iZG), the improved vertical entropy source (EQ) is realized by the vertical arrangement of a semiconductor single-photon source (120) and a photon detector (130) perpendicular to the surface (O) of a semiconductor substrate within the semiconductor substrate, one above the other, which in particular enables maximum photon interaction between the single-photon source and the photon detector and results in simple manufacturability.The vertical arrangement of a semiconductor single-photon source (120) and a photon detector (130) perpendicular to the surface (O) of a semiconductor substrate within the semiconductor substrate is to be understood such that the plane of the PN junction of the photon source is arranged parallel to the plane of the PN junction of the photon detector, and that these planes are arranged parallel to the surface of the semiconductor substrate, so that the photon detector and the photon source are stacked vertically one above the other. If the projection of the edge of the PN junction of the photon detector from the plane of the photon detector into the plane of the photon source and the edge of the PN junction of the photon source intersect in the plane of the photon source, the arrangement of the photon source and the photon detector is considered vertical within the meaning of the document presented here. This is the most crucial feature for the high random bit rate.

[0278] Furthermore, in another embodiment of the internal random number generator (iZG), the internal random number generator (iZG) preferably comprises a filter module for processing the generated random numbers in order to improve their statistical properties. In particular, the filter module should, as described above, remove the bias. It can happen by chance that the correct signal from the correctly functioning entropy source (EQ) leads to a purely random generation of very many consecutive random bits of a single logical value. This can lead to a loss of encryption capability. Therefore, it is useful to remove this so-called bias using a digital high-pass filter and / or a functionally equivalent device, so that for every predetermined number of random bits with a logical value that is identical to one another, this logical value always changes.For example, the filter can also be designed so that the random bit data stream is inverted after n consecutive logical values ​​of the same logical value until n consecutive logical values ​​of the same logical value appear again, and this inversion is canceled by the filter module. This ensures that the random bits and / or random numbers and / or random data words and / or random character sequences are highly suitable for encryption purposes. The filter module can also, for example, be part of the entropy extraction or other device components of the internal random number generator (IRG).

[0279] Furthermore, in another embodiment of the inner random number generator (iZG), the filter module comprises a high-pass filter for removing the bias from the random bit stream, for example at the output of the entropy extraction and / or a low-pass filter and / or an XOR gate for reducing random systematic patterns in the random numbers.

[0280] Furthermore, in another embodiment, the inner random number generator (iZG) comprises an amplifier module that amplifies and / or filters the amplitude of the generated entropy source output signal of the entropy source (EQ) before it is used and / or digitized. This amplifier module can be part of an analog-to-digital converter of the inner random number generator (iZG). This improves the further processing of the signal thus generated.

[0281] Furthermore, in another embodiment, the inner random number generator (iZG) comprises an entropy module (WD)—also referred to as a watchdog in this document—that analyzes the random signal of the entropy extraction random bit stream after extraction from the entropy source output signal of the entropy source (EQ) and evaluates its entropy. This enables the detection of errors, defects, and attacks.

[0282] Furthermore, in another embodiment, the internal random number generator (iZG) comprises the vertical entropy source (EQ), in particular with a photon source (120) and photodetector (130) arranged vertically one above the other relative to the horizontal surface (O) of the substrate. This vertical entropy source (EQ) is implemented in a microintegrated circuit to optimize the performance of the internal random number generator (iZG). This reduces vulnerability, reduces costs, and increases the speed of the internal random number generator (iZG) and thus the random bit rate.

[0283] Furthermore, in another embodiment, the internal random number generator (iZG) comprises a memory module and / or a memory (MEM) for storing the generated random bits and / or random numbers. This enables the short-term output of random bits at a temporary random bit rate that would be higher than the random bit rate without these means for storing the random bits.

[0284] Furthermore, in another embodiment of the internal random number generator (iZG), the memory module and / or the memory (MEM) are or include a volatile or non-volatile memory. These are exemplary implementations for rework.

[0285] Furthermore, in another embodiment of the internal random number generator (iZG), the internal random number generator (iZG) is preferably configured for diagnosing and self-calibrating device components of the random number generation device of the internal random number generator (iZG). This check is preferably performed by the said watchdog (WD) in order to detect errors, defects, and / or attacks and, if necessary, to implement countermeasures (e.g., by switching to redundant device components) or to signal higher-level computer systems of the random number generator (ZZG) and / or network nodes of the network and / or to the crypto engine. Uses of the inner random number generator (IRG)

[0286] The document presented here describes the use of the aforementioned internal random number generator (iZG) in a VPN system for secure key generation and management for encrypted VPN connections. This has the advantage that such secure key generation using the proposed device enables a high key exchange rate due to the high random bit data rate of the internal random number generator, thus increasing the ratio of the number of encryption bits to the number of useful bits in the data channel toward 1, which reduces the probability of a successful attack.

[0287] Furthermore, the document presented here describes the use of the aforementioned inner random number generator (iRNG) in IoT networks to ensure the integrity and confidentiality of communication between IoT devices. The compact and inexpensive design of the described inner random number generator (iRNG) enables the equipping of typically very price-sensitive IoT devices with state-of-the-art encryption technology. This is especially true if the random number generator (RNG), as proposed here, is or includes a quantum random number generator.

[0288] Furthermore, the document presented here describes a use of the aforementioned internal random number generator (iZG) in cloud computing environments for secure data processing and storage in cloud environments. The technical teaching proposed here allows one or more individual server cabinets and / or one or more individual servers and / or even one or more individual storage units such as hard disks and / or SSDs and / or one or more individual memory modules to be provided with a proposed random number generator or to operate as such a random number generator, at least temporarily, when the corresponding device components are present in the device in question.Thus, the document presented here discloses a server farm with a plurality of servers, wherein the server farm comprises one or more of the random number generators presented here and / or the inner random number generators (iZG) presented here and / or one or more of the entropy sources (EQ) presented here, each with at least one photon source and at least one photon detector for the respective photons of the respective photon source and for the respective generation of the respective entropy source output signal and the respective downstream evaluation circuits for the respective extraction of the respective random bits from the respective entropy source output signal for use by device parts of the server farm.Preferably, the respective photon source of the respective entropy source (EQ) and the associated respective photon detector of the respective photon source are again arranged monolithically in at least one common, respective semiconductor substrate, as described, below the respective surface O of the respective semiconductor substrate vertically one above the other in order to maximize the respective random bit data rate.

[0289] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (IDG) in financial transaction systems for the secure execution and verification of financial transactions. This preferably applies to mobile, transportable devices such as mobile phones, chip cards, VPN tokens, PCs, USB sticks, memory cards, key cards, etc. Due to their compact and robust design, such random number generators with a vertically monolithically integrated entropy source are particularly suitable for such applications and increase their security.

[0290] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in communication systems for the secure transmission of messages and data in communication networks. This preferably applies to mobile, transportable devices such as radios, telephones and telex machines, mobile phones, PCs, laptops, surf sticks, TV adapters, VPN tokens, USB sticks, memory cards, key cards, etc. Due to their compact and robust design, such random number generators with a vertically monolithically integrated entropy source are particularly suitable for such applications and increase their security. Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in conjunction with a microcontroller (MCU) to enable secure key generation and management.This enables secure software downloading into a microcontroller memory, secure encryption of data in a microcontroller memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the microcontroller, and secure data transfer to and from the microcontroller as well as individualization of the microcontroller using a random identity number.

[0291] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in conjunction with a CPU in an embedded system to ensure secure encryption and data transmission. This enables secure software downloads to the CPU's memory, secure encryption of data in the CPU's memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the CPU, secure data transmission to and from the CPU, and the individualization of the CPU using a random identity number.

[0292] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in conjunction with a sensor evaluation and control circuit to ensure the integrity and confidentiality of the sensor data. This enables secure software downloading into a memory of the sensor evaluation and control circuit, secure encryption of data in a memory of the sensor evaluation and control circuit, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the sensor evaluation and control circuit, secure data transmission to and from the sensor evaluation and control circuit, and individualization of the sensor evaluation and control circuit using a random identity number.

[0293] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in conjunction with a network node in a wired or wireless network to increase the security of communication protocols. This enables secure software downloading to a network node's memory, secure encryption of data in a network node's memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the network node, secure data transmission to and from the network node, and individualization of the network node using a random identity number.

[0294] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in conjunction with a chip card to enable secure authentication and data processing on the card. This enables secure software downloading to a chip card memory, secure encryption of data in a chip card memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the chip card, secure data transfer to and from the chip card, and individualization of the chip card using a random identity number.

[0295] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in a network node in an IoT network to ensure secure communication between IoT devices. This enables secure software downloads to the IoT device's memory, secure encryption of data in the IoT device's memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the IoT device, secure data transfer to and from the IoT device, and individualization of the IoT device using a random identity number.

[0296] Furthermore, the document presented here describes the use of the aforementioned inner random number generator (iRNG) in a cloud computing system to enable the encryption and secure storage of data in the cloud.

[0297] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iRNG) in a financial transaction system to ensure the security and confidentiality of transactions.

[0298] Furthermore, the document presented here describes the use of the aforementioned inner random number generator (iZG) in a communication system to enable the secure transmission of messages and data.

[0299] Furthermore, the document presented here describes a use of the aforementioned internal random number generator (iZG) in a portable device, in particular in a smartphone or a telephone or the like, in order to realize secure and energy-efficient encryption.

[0300] Furthermore, the document presented here describes the use of the aforementioned inner random number generator (iZG) in one or more sensors in a sensor network to ensure the authentication and integrity of the sensor data.

[0301] Furthermore, the document presented here describes a use of the aforementioned internal random number generator (iZG) in a vehicle control system and / or a vehicle network to ensure secure communication between the control units and / or with device parts of the vehicle.

[0302] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in a weapon control system and / or a network within a weapon system to ensure secure communication between the device components of the weapon system. The term "weapon control system" includes ammunition systems. This enables secure software downloading into a memory of the weapon control system, secure encryption of data in a memory of the weapon control system, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the weapon control system, secure data transmission to and from the weapon control system, and individualization of the weapon control system using a random identity number.

[0303] Furthermore, the document presented here describes a use of the aforementioned internal random number generator (iZG) in a military equipment system for soldiers in order to ensure secure communication between the device components of the military equipment system and / or between the military equipment systems of different soldiers and / or between the military equipment systems of one or more soldiers on the one hand and one or more weapon systems and / or military networks on the other.This enables secure software downloading into a memory of the military equipment system, secure encryption of data in a memory of the military equipment system, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the military equipment system, and secure data transfer to and from the military equipment system as well as the individualization of the military equipment system by means of a random identity number.

[0304] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in a medical device to protect the confidentiality of patient data and patient measurement values ​​from patient sensors and to ensure security. This enables secure software downloading into a medical device memory, secure encryption of data in a medical device memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the medical device, and secure data transfer to and from the medical device, as well as the individualization of the medical device using a random identity number.

[0305] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in an industrial automation system in a production process to ensure the security of control commands and data against attacks. This enables secure software downloading into a memory of the industrial automation system, secure encryption of data in a memory of the industrial automation system, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the industrial automation system, and secure data transmission to and from the industrial automation system, as well as the individualization of the industrial automation system using a random identity number.

[0306] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in a smart home system to ensure the secure control and communication of smart home devices in a property or a fixed installation and / or in an infrastructure object. This enables secure software downloading to a smart home system memory, secure encryption of data in a smart home system memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the smart home system, secure data transmission to and from the smart home system, and individualization of the smart home system using a random identity number.

[0307] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in an infrastructure system to ensure the secure control and communication of the infrastructure system's device components (gas supply, drinking water supply, wastewater supply, power supply, district heating supply, etc.). This enables secure software downloading into an infrastructure system's memory, secure encryption of data in an infrastructure system's memory, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the infrastructure system, secure data transmission to and from the infrastructure system, and individualization of the infrastructure system using a random identity number.

[0308] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in a microprocessor, comprising in particular an ALU (Arithmetic Logic Unit), an internal microprocessor data bus, a control unit, and registers to generate random numbers for cryptographic operations directly in the processor. This enables secure software downloading into a microprocessor memory, secure encryption of data in a microprocessor memory, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the microprocessor, secure data transfer to and from the microprocessor, and individualization of the microprocessor using a random identity number.

[0309] Furthermore, the document presented here describes a use of the aforementioned internal random number generator (iZG) in an FPGA (Field-Programmable Gate Array). The FPGA typically comprises configurable logic circuits and / or configurable logic blocks and / or configurable lookup tables and / or configurable and / or programmable connections. Furthermore, such an FPGA comprises, for example, auxiliary circuits such as voltage regulators and / or voltage converters and / or data interfaces and other device components. However, this not only enables configurable cryptographic functions in the FPGA and / or other uses of random bits and / or random numbers in the FPGA, particularly in real time.This enables secure software downloading into an FPGA memory, secure encryption of data in an FPGA memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents and / or configuration data of the FPGA, and secure data transfer to and from the FPGA as well as individualization of the FPGA using a random identity number.

[0310] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in a DSP (digital signal processor), comprising, in particular, specialized MAC units (multiply-accumulate units) and pipeline architectures to enable secure signal processing in safety-critical applications. This enables secure software downloading into a DSP memory, secure encryption of data in a DSP memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the DSP, secure data transfer to and from the DSP, and individualization of the DSP using a random identity number.

[0311] Furthermore, the document presented here describes a use of the above-described inner random number generator (iZG) in an ASIC (Application-Specific Integrated Circuit) and / or a CMOS or BiCMOS or bipolar circuit, comprising in particular specialized circuits for cryptographic functions, in order to integrate dedicated, high-performance cryptographic functions.This enables secure software downloading into a memory of the ASIC and / or the CMOS or BiCMOS or bipolar circuit, secure encryption of data in a memory of the ASIC and / or the CMOS or BiCMOS or bipolar circuit, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the ASIC and / or the CMOS or BiCMOS or bipolar circuit, and secure data transfer to and from the ASIC and / or the CMOS or BiCMOS or bipolar circuit as well as the individualization of the ASIC and / or the CMOS or BiCMOS or bipolar circuit by means of a random identity number.

[0312] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in a SoC (System-on-Chip) architecture, comprising in particular a microprocessor, one or more memories, one or more peripheral modules, and a data bus on a single microintegrated chip, in particular to create a compact and efficient solution for embedded systems. This enables secure software downloading into a memory of the SoC, secure encryption of data in a memory of the SoC, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the SoC, secure data transfer to and from the SoC, and individualization of the SoC using a random identity number.

[0313] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in a GPU (Graphics Processing Unit), in particular comprising shader cores, texture units, and memory controllers, in particular to execute cryptographic calculations in parallel with graphics processing and / or in particular to execute computer- and / or machine-implemented AI methods. This enables secure software downloading into a GPU memory, secure encryption of data in a GPU memory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the GPU, secure data transfer to and from the GPU, and individualization of the GPU using a random identity number.

[0314] Furthermore, the document presented here describes a use of the aforementioned internal random number generator (iZG) in a network processor, comprising in particular packet processing units and protocol engines, in particular to support secure data transmissions and protocol processing. This enables secure software downloading into a memory of the network processor, secure encryption of data in a memory of the network processor, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the network processor, secure data transmission to and from the network processor, and individualization of the network processor using a random identity number.

[0315] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in a security chip for smart cards, comprising, in particular, a cryptographic processing unit and secure memory areas to enable secure authentication and encryption operations. This enables secure software downloading into a memory of the security chip, secure encryption of data in a memory of the security chip, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the security chip, secure data transfer to and from the security chip, and individualization of the security chip using a random identity number.

[0316] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in a TPM (Trusted Platform Module), comprising, in particular, a cryptographic coprocessor unit and a secure memory, in particular to support secure storage and authentication processes in computer platforms. This enables secure software downloading into a TPM memory, secure encryption of data in a TPM memory, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the TPM, secure data transfer to and from the TPM, and individualization of the TPM using a random identity number.

[0317] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in an IoT processor, comprising, in particular, integrated radio modules and / or power management units and / or sensor interfaces, to ensure the integrity and confidentiality of communication in networked devices and the measured values. This enables secure software downloading into an IoT processor memory, secure encryption of data in an IoT processor memory, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the IoT processor, secure data transmission to and from the IoT processor, and individualization of the IoT processor using a random identity number.

[0318] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in a control chip for industrial control systems, comprising, in particular, specialized interfaces for industrial protocols and real-time controllers, in particular to ensure secure control commands and data processing. This enables secure software downloading into a memory of the control chip, secure encryption of data in a memory of the control chip, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the control chip, secure data transfer to and from the control chip, and individualization of the control chip using a random identity number.

[0319] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in a communications processor for mobile devices, comprising in particular baseband processors, modem units, and signal coding units, in particular to ensure the security of voice and data transmissions. This enables secure software downloading into a memory of the communications processor, secure encryption of data in a memory of the communications processor, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the communications processor, secure data transmission to and from the communications processor, and individualization of the communications processor using a random identity number.

[0320] Furthermore, the document presented here describes a use of the aforementioned internal random number generator (iZG) in a wearable processor or a piece of clothing or accessory comprising a processor - here referred to as a wearable processor - comprising energy efficiency modules, wireless communication interfaces and integrated sensors in order to enable secure data processing and communication in wearable devices and / or in smart clothing. This enables secure software downloading into a memory of the garment or accessory, secure encryption of data in a memory of the garment or accessory, secure authentication of permission to write and / or read access to resources and / or memory and / or register contents of the garment or accessory, and secure data transmission to and from the garment or accessory as well as the individualization of the garment or accessory.Accessories using a random identity number.

[0321] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in a memory controller, comprising in particular memory management units, cache controllers, and memory bus interfaces, to ensure the encryption of data in memory components. This enables secure software downloads into a memory of the memory controller, secure encryption of data in a memory of the memory controller, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the memory controller, secure data transfer to and from the memory controller, and individualization of the memory controller using a random identity number.

[0322] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in an automotive processor, in particular comprising CAN bus interfaces and / or other automotive data bus interfaces, such as LIN bus interfaces, security modules, and real-time controllers, to ensure secure communication and control in vehicle networks. This enables secure software downloading into a memory of the automotive processor, secure encryption of data in a memory of the automotive processor, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the automotive processor, secure data transmission to and from the automotive processor, and individualization of the automotive processor using a random identity number.

[0323] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in a control chip for medical devices, in particular comprising integrated signal processing units, communication interfaces, and security modules to ensure the confidentiality and integrity of patient data and / or patient measurement data. This enables secure software downloading into a memory of the control chip, secure encryption of data in a memory of the control chip, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the control chip, secure data transmission to and from the control chip, and individualization of the control chip using a random identity number.

[0324] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in a control chip for drones and / or unmanned vehicles, floating bodies, missiles, or satellites, in particular comprising integrated flight and / or motion control units, communication modules, and sensor interfaces to ensure secure communication and control commands between the drone and the control unit. This enables secure software downloading into a memory of the control chip, secure encryption of data in a memory of the control chip, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the control chip, secure data transmission to and from the control chip, and individualization of the control chip using a random identity number.

[0325] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in a processor for computer-implemented virtual machines, in particular comprising virtualization and memory management units, to enable the secure execution of virtual instances on a host system. This enables secure software downloading into a processor memory, secure encryption of data in a processor memory, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the processor, secure data transfer to and from the processor, and individualization of the processor using a random identity number.In particular, it enables computer-implemented customization of the computer-implemented virtual machines and variation of the virtual behavior of these computer-implemented virtual machines.

[0326] Furthermore, the document presented here describes the use of the aforementioned internal random number generator (iZG) in one or more processors of a processor system for executing computer-implemented models of virtual processors, in particular comprising virtualization and memory management units, to enable the secure execution of virtual instances on a host system. This enables secure software downloading into the memory of one or more processors, secure encryption of data in the memory of one or more processors, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of one or more processors, secure data transfer to and from one or more processors, and the individualization of one or more processors using a random identity number.

[0327] Furthermore, the document presented here describes a use of the aforementioned internal random number generator (iZG) in a cryptocurrency mining chip, in particular, including specialized hashing engines, power management, and memory controllers to ensure the generation and verification of cryptographic hashes.

[0328] Furthermore, the document presented here describes the use of the aforementioned random number generator (RNG) in a processor for edge computing, in particular, comprising specialized network modules, data processing units, and memory controllers to enable secure and decentralized data processing at the network edges. This enables secure software downloading to a processor memory, secure encryption of data in a processor memory, secure authentication of permission for write and / or read access to resources and / or memory and / or register contents of the processor, secure data transfer to and from the processor, and individualization of the processor using a random identity number.

[0329] Furthermore, the document presented here describes a use of the aforementioned random number generator (RNG) in a processor for distributed ledger technologies (blockchain), in particular comprising specialized encryption units, memory management and network interfaces, in particular to ensure the security and integrity of the distributed transactions. List of characters Fig. 1 shows a schematic representation of a first embodiment of an entropy source EQ of an inner random number generator iZG of the random number generator ZZG according to the prior art in plan view; Fig. 2 shows a schematic representation of a second embodiment of an entropy source EQ of an inner random number generator iZG of the random number generator ZZG according to the prior art in a side view; Fig. 3 shows a schematic representation of a BCD substrate provided by a method for providing deep pn junctions in a BCD process and a TCAD representation of the resulting dopant distribution; Fig. 4 shows a schematic representation of an exemplary first embodiment of an inventive entropy source EQ of an inner random number generator iZG of the random number generator ZZG; Fig. 5 shows a schematic representation of an exemplary second embodiment of an inventive entropy source EQ of an inner random number generator iZG of the random number generator ZZG; Fig. 6 shows a schematic representation of an exemplary third embodiment of an inventive entropy source EQ of an inner random number generator iZG of the random number generator ZZG; Fig. 7 shows a graphical representation of the dependence of a) the SPAD current and b) the ratio between SPAD current and Zener current as a function of the Zener blocking voltage at different SPAD blocking voltages (less than, equal to, greater than the breakdown voltage) within an entropy source EQ according to the invention of an internal random number generator iZGs according to the invention; Fig. 8 shows a schematic representation of an exemplary electronic circuit of a quantum random number generator ZZG for generating and outputting a digital random number sequence; Fig. 9 shows a schematic representation of an exemplary layout of an integrated electronic circuit of an inventive entropy source EQ of an inner random number generator iZG of the random number generator ZZG with an inventive entropy source EQ of an inventive inner random number generator iZG in the pad frame in plan view.v Description of the charactersPreliminary remarks

[0330] Detailed embodiments will now be described, which are illustrated by way of example in the accompanying drawings. The effects and features of these embodiments will be described with reference to the accompanying drawings. Throughout the drawings, like reference numerals designate like elements, and redundant descriptions are omitted. The present disclosure may be embodied in various forms and should not be construed as limited only to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art.

[0331] Therefore, methods, elements, and techniques that are not necessary for a person skilled in the art to fully understand the aspects and features of the present disclosure may not be described. In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity.

[0332] As used herein, the term "and / or" includes all combinations of one or more of the listed elements. Furthermore, the use of "may" in describing embodiments of the present disclosure refers to "one or more embodiments of the present disclosure." In the following description of embodiments, the singular terms may also include the plural, unless the context clearly indicates otherwise.

[0333] Although the terms "first" and "second" are used to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present disclosure. Terms such as "at least one of," when preceded by a list of elements, modify the entire list, not just the individual elements of the list.

[0334] Terms such as "substantially," "approximately," and similar terms are used as approximations rather than degrees, and are intended to account for inherent variations in measured or calculated values ​​that will be recognized by those skilled in the art. When the term "substantially" is used in connection with a characteristic that can be expressed by a numerical value, unless otherwise defined, the term "substantially" means a range of at least + / - 5% of the value centered on the value. Description of Figure 1

[0335] Fig. Figure 1 shows a schematic representation of a first embodiment of an entropy source EQ of an internal random number generator iZG according to the prior art, in a top view. The illustration is based on a corresponding figure in EP 3 529 694 B1 and shows the surface O of an associated substrate 110, into which the entropy source EQ is integrated. A circular photon source 120 with a pn junction configured to provide photons is supplied with current via a corresponding contact and is thereby excited to emit individual photons 128. To detect the emitted photons 128, an associated photon detector 130 in the form of a SPAD is arranged next to the photon source 120.However, as in conventional hybrid approaches for photonic QNRGs, the photon source 120 and the photon detector 130 continue to be structurally and functionally separate elements that are simply arranged next to each other for integration in a common substrate.

[0336] A current pulse generated by the photon detector 130 upon absorption of a photon 128 can then first be registered and evaluated in an associated electronic sampling means 152, in particular to generate a bit sequence based on the number of photons detected in the photon detector 130. Furthermore, an electronic post-processing means 154 is provided, which is to be configured to process the binary sequences of the electronic sampling means 152 in such a way that a so-called "whitening" operation is performed. This whitening operation is to comprise a plurality of compression operations designed to improve the statistical properties of the generated binary sequences. The post-processing step is to increase the entropy level of the entropy source EQ.However, it must be ensured that the compression operations used do not lead to a fundamental predictability of the generated random numbers by introducing deterministic dependencies in the application.

[0337] To increase the efficiency of random number generation, i.e., the effective entropy rate, the photonic part of the entropy source EQ on the surface O of the substrate 110 is protected by a light-blocking layer 150 ("light inhibitor filter"), which serves to shade it from external light. The light-blocking layer 150 can be provided, in particular, by a metallization layer that can be applied directly during the production process, for example, using CMOS technology, as the last metallization level. This is intended to shield the photon detector 130 from external light and make it sensitive only to those photons that pass through the substrate 110 due to crosstalk from the photon source 120.In addition, the metallization layer is also intended to improve the optical coupling of the photons 128 emitted by the photon source 120 by reflecting them inwards and thus preventing them from exiting the surface O of the substrate 110.

[0338] A disadvantage of such a side-by-side arrangement of the optical components is the distance between the components, which reduces the coupling strength due to the low illumination angle and the potential photon absorption in the various materials. Furthermore, despite the partially applied light-blocking layer 150, there is still the potential for optical access and thus an attack from the surface O of the substrate 110 or even from the back of the substrate. This can be used, for example, to specifically inject or extract additional photons, ultimately influencing and compromising the counting statistics and thus the entropy of the generated random numbers.Furthermore, the illustration also shows that the individual photons 128 are emitted isotropically distributed in all spatial directions, so that only a fraction of the photons 128 can be detected by the photon detector 130 and thus statistically evaluated. This significantly reduces the efficiency of random number generation and, on the other hand, results in a large number of photons 128 being emitted unused into the substrate 110, where they may also be extracted elsewhere by observers or attackers or cause interference. Description of Figure 2

[0339] Fig. Figure 2 shows a schematic representation of a second embodiment of an entropy source EQ of a random number generator ZZG according to the prior art in a side view in cross-section. The representation is based on a corresponding figure from Khanmohammadi et al. (A. Khanmohammadi, R. Enne, M. Hofbauer and H. Zimmermann, "A Monolithic Silicon Quantum Random Number Generator Based on Measurement of Photon Detection Time," in IEEE Photonics Journal, vol. 7, no. 5, pp. 1-13, Oct. 2015, Art. no. 7500113). In this example, too, the basic structure of a horizontal juxtaposition of a photon source 120 (Si-LED) along the surface O, which is configured to emit individual photons 128, and a photon detector 130 (SPAD) is clearly visible. In contrast to the Fig. In the arrangement shown in Figure 1, however, the photon source 120 is provided as a circular central element, which is essentially completely surrounded by a correspondingly adapted, circular-ring-shaped photon detector 130. The common radial axis of symmetry R lies accordingly at the center of the entropy source EQ of the quantum random number generator ZZG formed in this way. The photon source 120 is realized by an n-well formed in a deep n-well ("deep n well"), which is supplied with current via an n++ region introduced into the surface O of the substrate 110 ("p-substrate") centrally around the radial axis of symmetry R as cathode 122 and a p++ region arranged adjacent to it as anode 124.Outside the deep n-well, the photon detector 130 is also contacted to the surface O via an introduced n++ region as cathode 132 and a p++ region arranged further away from the radial axis of symmetry R as anode 134. Below the cathode 132, a p-well ("p well") is connected. Below the anode 134, however, a p-well ("p well") is formed in a deep p-well ("deep p well"). The photon source 120 is provided as an element within the structure of the photon detector 130, so that, in contrast to the . Fig. 1 these form a structural and functional unit.

[0340] In this example of an entropy source of a quantum random number generator ZZG according to the prior art, the photons 128 are emitted essentially from all sides into the substrate 110, so that the already described embodiment according to Fig. 1 described disadvantages regarding security against observers or attackers and the reduced efficiency, ie the reduced random bit data rate, also apply. Due to the specific design as a circular ring arrangement and the structural connection of the photon detector 130 with the photon source 120, Fig. 1, however, the integration density can be further increased. In addition to a lower area requirement for forming the entropy source EQ of the quantum random number generator ZZG, this also includes increased security against attacks and increased efficiency in random number generation or the entropy rate as advantages. This is particularly related to the fact that the reduction of all distances reduces the loss of photons 128 due to material absorption and unfavorable emission directions. Furthermore, the area for potential attacks is reduced. Apart from this, however, it is still possible in principle to couple out or inject individual photons 128, particularly at the surface O and also at other locations on the substrate 110, in order to influence the counting statistics by attackers.Such a juxtaposition of the two optical components of the entropy source EQ of a quantum random number generator ZZG therefore has some disadvantages that have so far prevented particularly secure, compact and reliable random number generation for SoC applications. Description of Figure 3

[0341] Fig. 3 shows a schematic representation of a BCD substrate 110 provided with a method for providing deep pn junctions 50 and 52 in a BCD process and a TCAD representation of the resulting dopant distribution. An embodiment of a method for producing deep pn junctions 50 and 52 in a BCD process comprises providing a carrier substrate 10; introducing a first dopant to form a first region 22 (e.g., NBL) of the first conductivity type (negative for NBL) into a surface S of the carrier substrate 10; introducing a second dopant to form a second region 32 (e.g.,PBL) of the second conductivity type (positive for PBL) into the surface S of the carrier substrate 10, wherein the first region 22 (NBL) and the second region 32 (PBL) at least partially overlap; growing an epitaxial layer 40 on the surface S of the carrier substrate 10, wherein the first region 22 (NBL) and the second region 32 (PBL) spread by diffusion of the first dopant and the second dopant in the epitaxial layer 40 and thereby form a pn junction 50 lying in the epitaxial layer.

[0342] The document presented here defines a BCD process as a semiconductor manufacturing process for producing BiCMOS circuits. Wikipedia (https: / / de.wikipedia.org / wiki / Bipolar-CMOS-Technik) states: "Bipolar CMOS technology (BiCMOS technology) is a semiconductor manufacturing method that combines two originally separate circuit technologies, namely circuits made up of bipolar transistors (BJTs) and CMOS logic gates (complementary metal-oxide semiconductors) based on metal-oxide-semiconductor field-effect transistors (MOSFETs), into a single integrated circuit.[1] More recently, the bipolar processes have been extended to compound semiconductors with high electron mobility, such as silicon germanium." A BCD substrate, as defined in this document, is a semiconductor crystal piece (typically referred to as a die) or a semiconductor wafer that has been processed using a BCD process.

[0343] In the illustration, the first region 22 is a deep NBL layer and the second region 32 is a deep PBL layer. However, the sequence can be reversed, so that the first region 22 can also be a deep PBL layer and the second region 32 a deep NBL layer. By appropriately adjusting the diffusion lengths of the individual dopants, the layer sequence of the pn junctions 50 and 52 can also be reversed. For example, Fig. 3 the NBL and PBL layers at the pn junction 50 and 52 are also swapped.

[0344] The described method differs from the conventional methods for providing BCD substrates 110 according to the prior art in particular in that the first region 22 (NBL) and the second region 32 (PBL) at least partially overlap.

[0345] In particular, immediately after the introduction of the second dopant, in a plan view of the surface S of the carrier substrate 10, the first region 22 or the second region 32 can completely overlie the other region (32, 22). Therefore, in the embodiment shown, immediately after the introduction of the second dopant to form the second region 32 (PBL), the second region 32 lies completely in the first region 22 (NBL) in a plan view of the surface S of the carrier substrate. In order to form a pn junction 50 located in the epitaxial layer, the first and second dopants preferably have different diffusion properties in the carrier substrate 10 and / or in the epitaxial layer 40.In particular, the second dopant in the second region 32 (PBL), as shown, may have a higher diffusion mobility (and thus diffusion length) in the carrier substrate 10 and in the epitaxial layer 40 than the first dopant in the first region 22 (NBL).

[0346] To enhance diffusion, the carrier substrate 10 can be heated after the introduction of the first dopant and / or the second dopant. Furthermore, after the growth of the epitaxial layer 40, the carrier substrate 10 can be heated to enhance dopant diffusion. In the method presented, the first dopant and / or the second dopant can be introduced either maskless or using a mask process. In the BCD wafer shown, a complete overlay of the first region 22 (NBL) with a single second region 32 (PBL) can be assumed. Conventionally, however, the first and second regions 22 and 32 are formed spatially separate from one another. In particular, their distance is generally chosen to be at least large enough that even after the individual dopants have diffused out, no overlapping regions are created.

[0347] The TCAD (Technology Computer-Aided Design, TCAD) representation shown below the schematic diagram shows the dopant distribution within the contacted BCD substrate 110 for simulating a corresponding integrated diode structure. Due to the double structure shown in this embodiment, with an upper pn junction 50 in the epitaxial layer 40 and a lower pn junction 52 in the carrier substrate 10, the side view shown shows an effective constriction of the n-type region NBL enclosed in the area of ​​the pn junctions 50 and 52 by the two p-type regions PBL surrounding this n-type region NBL. Both pn junctions 50 and 52 can be configured to provide mutually independent SPADs with a doping density and field strength distribution suitable for generating an avalanche effect.

[0348] By means of corresponding BCD substrates 110 for further use in BCD technologies, particularly deep-lying SPADs (“deepSPADs”) can thus be produced. In particular, sufficient installation space remains above the provided SPADs for the integration of further optoelectronic components. According to the invention, therefore, in particular, a Zener avLED formed above the deep-lying SPAD can be used to realize a particularly compact, vertically constructed iZG, in which individual photons 128 are emitted by the Zener avLED preferably in the direction of the upper pn junction 50 and are thus provided for detection by a SPAD formed directly below the Zener avLED at the upper pn junction 50 as a photon detector (see Fig. 4 with corresponding figure description). Description of Figure 4

[0349] Fig. 4 shows a schematic representation of an exemplary first embodiment of an inventive entropy source EQ of an inventive internal random number generator iZG of an inventive random number generator ZZG, which here is a quantum random number generator (QRNG) 200. The shown integrated entropy source EQ of the quantum random number generator ZZG comprises a photon source 120 and a photon detector 130, wherein the photon source 120 and the photon detector 130 are arranged vertically one above the other opposite the horizontal surface in a common substrate made of a semiconductor material.

[0350] Vertical means that, firstly, the projection of the edge of the PB junction 50 of the photon detector 130 from the plane of the PN junction 50 of the photon detector 130 into the plane of the PN junction 161 of the photon source 120 overlaps with the edge of the PN junction 161 of the photon source 120 and that the plane of the PN junction 50 of the photon detector 130 is parallel with a distance greater than 0 to the plane of the PN junction 161 of the photon source 120.

[0351] Preferably, the photon source 120 is a single-photon source (SPS), which is preferably configured to provide only single or a few photons 128 at a time. Preferably, the photon source 120 is a light-emitting avalanche Zener diode (Zener-avLED) operating at an operating point below or near the breakdown voltage. Preferably, the photon detector 130 is a single-photon avalanche diode (SPAD).

[0352] The entropy source EQ (401) is preferably formed in a BCD substrate 110 using BCD technology. A BCD substrate, as defined in this document, is a semiconductor substrate processed using a BCD process. BCD generally stands for Bipolar CMOS Double Diffused MOS technology. Wikipedia quotes: "One type of BiCMOS technology is Bipolar CMOS DMOS (BCD) technology, which combines BiCMOS with DMOS (double-diffused MOS), a type of power MOSFET technology. BCD technology combines three processes for fabricating semiconductor components on a power IC (Power Integrated Circuit): Bipolar for precise analog functions, CMOS for digital design, and DMOS for power electronics and high-voltage elements. [...] There are two types of BCD: High-Voltage BCD and High-Density BCD. They have a wide range of applications, such as:Silicon-on-Insulator (SOI) BCDs, which are used in medical electronics, automotive safety, and audio technology." Preferably, the BCD substrate 110 comprises a carrier substrate 10; and an epitaxial layer 40 grown on the carrier substrate 10, wherein a deep pn junction 50 lying in the epitaxial layer was created between the carrier substrate 10 and the epitaxial layer 40 by diffusion of dopants introduced into a surface S of the carrier substrate 10 below the epitaxial layer 40 (see . Fig. 3). Preferably, the photon detector 130 forms an avalanche region in a region around the deep pn junction 50 and comprises an absorption region PW / HPW with a high-voltage p-type well HPW and a p-type well PW for converting photons into electron-hole pairs. The absorption region PW / HPW directly adjoins the regions NBL and PBL forming the deep pn junction 50. The fully developed high-voltage p-type well HPW enables optimal connection of the deep pn junction 50 from the anode.

[0353] It is preferred • that the deep pn junction 50 is formed at least partially between a deep n-layer NBL as a cathode (with the associated cathode terminal 132) and a deep p-layer PBL directly adjoining the deep n-layer NBL, • that the absorption region PW / HPW is directly adjacent to the deep p-layer PBL and is essentially designed as a p-region (optionally comprising an intrinsic region), and • that an anode designed as a p+ region (with the associated anode connection 134) is directly connected to the absorption region PW / HPW.

[0354] In the illustrated embodiment, the respective anode terminals 124 and 134 of the photon source 120 and the photon detector 130 are electrically connected by means of the metallization cover in the second metallization MET2. These can then be electrically contacted, for example, via the shared second metallization MET2 on the surface O of the BCD substrate 110. A shared and continuous second metallization MET2 can also provide shading to shield the entire installation space of the entropy source below against unintentional radiation and radiation radiated for attack purposes.

[0355] The PN junction 161 of the photon source 120 is located in the contact area between a) the n+ region N+, which is electrically connected by the cathode terminal 122 and the contacts CONT of the photon source 120 and which forms the cathode of the photon source 120, and b) the PBODY region, which is electrically connected to the anode terminal 134 of the photon source 120 via the P-well PW, the p+ region P+, and a contact CONT.

[0356] Preferably, this PN diode of the photon source 120 is reverse biased during operation, for example by a voltage converter (e.g. 408 in Fig. 8) until breakdown by means of a first supply voltage V ENT1 biased. Due to the breakdown, the PN junction 161 of the photon source 120 then emits individual photons 128. Damage to the photon source 120 is avoided by suitable current limitation, for example, by a series resistor R1 or a corresponding active transistor circuit in the aforementioned exemplary voltage converter 408. Regions of the photon source 120 that serve as series resistor R1 for the actual PN junction 161 can also serve as series resistor R1.

[0357] The first PN junction 50 of the photon detector 130 is located in the junction between the second region (32, PBL) and the first region 22 (NBL) buried in the substrate in the epitaxial layer.

[0358] Preferably, this PN diode of the first PN junction 50 of the photon detector 130 is reverse biased during operation, for example by a voltage converter (e.g. 408 in Fig. 8) by means of the second entropy supply voltage V ENT2of the photon detector 130 is biased to breakdown. Upon detection of a photon 128, an electron-hole pair is created, which is accelerated in the electric field and swells into a larger charge packet due to the avalanche effect. Due to this avalanche effect, the photon detector 130 then generates a current pulse at its first PN junction 50. By suitable current limitation, for example by a second load resistor R2 or a corresponding active transistor circuit in the aforementioned exemplary voltage converter 408, damage to the first PN junction 50 of the photon detector 130 is avoided. Regions of the photon detector 130 that serve as the second load resistor R2 for the actual first PN junction 50 of the photon detector 130 can also serve as the second load resistor R2.

[0359] The common anode contact 124, 134 of the photon source 120 and the PN junction 50 of the photon detector 130 is connected in the example via the P-well PW and thus the regions HPW and the anode PBODY of the photon source 120, as well as the anode PBL of the photon detector and is preferably at the reference potential GND.

[0360] The cathode terminal 132 of the PN junction 50 of the photon detector 130 is connected, for example, via a load resistor R2 to the monitored second positive supply voltage V ENT2of the photon detector 130. Upon detection of a photon 128, an electric current flows through the reverse-biased PN junction 50 of the photon detector 130. This results in a voltage drop across the load resistor R2 in the form of a typically rapidly rising and then exponentially falling voltage pulse on the entropy source output signal 405. The ADC 403 then evaluates this entropy source output signal 405. The ADC 403 can also include amplifiers and / or filters for conditioning the entropy source output signal 405. The load resistor R2 also limits the current through the PN junction 50 of the photon detector 130.

[0361] The cathode terminal 122 of the photon source 120 is connected, for example, via a first load resistor R1 to the monitored first positive supply voltage V ENT1the photon source 120. The first load resistor R1 limits the current through the PN junction 161 of the photon source 120. Upon emission of a photon 128, the reverse current of the reverse-biased PN junction 161 of the photon source 120 exhibits a spike-like increase. This reverse current increase leads to a voltage pulse across the first load resistor R1. This voltage pulse can be evaluated. For example, the ADC 403 can be configured, using an ADC-internal correlation device, to evaluate only those pulses on the entropy source output signal 405 that correlate with a voltage pulse at the first load resistor R1 on the optional signal 422. Only those pulses on the entropy source output signal 405 that correlate with an emission of a photon by the photon source 120 are pulses of the photon detector 130. This increases the quality of the entropy of entropy source 401.

[0362] Typically, the supply voltages (V ENT1 , V ENT2 ) for the photon source 120 and the photon detector 130 are different.

[0363] The associated cathode contacts 122 and 132 are each individually configured, by way of example, and can be electrically contacted via a first associated metallization MET1. The entropy source EG (401) according to the invention can be configured as a circular structure (corresponding to a spatial rotation of the illustrated plane around an imaginary central axis in the vertical direction). However, other configurations of the illustrated structure are also possible. Description of Figure 5

[0364] Fig. Figure 5 shows a schematic representation of an exemplary second embodiment of an entropy source EQ (401) according to the invention of an inner quantum random number generator iZG according to the invention of a quantum random number generator ZZG according to the invention. The embodiment shown largely corresponds to that shown in the Fig. 4 shown first embodiment. The reference numerals and their respective assignment to individual features therefore apply accordingly. In comparison to Fig. 4, the high-voltage p-well HPW was structurally replaced by a tapered high-voltage p-well HPW and a weakly n-doped or intrinsic epitaxial region NEPI. The high-voltage p-well HPW of the absorption region PW / HPW merely forms a narrow channel between the Fig. The deep pn junction 50 is formed by the upper p-well PW shown in Figure 2 and the deep p-layer PBL. The area surrounding the channel is defined by the lightly n-doped or intrinsic epitaxial region NEPI. The deep pn junction 50 can be connected from the anode through the channel without an additional punch through the lightly n-doped or intrinsic epitaxial region NEPI. Description of Figure 6

[0365] Fig. Figure 6 shows a schematic representation of an exemplary third embodiment of an entropy source EQ (401) of an inner quantum random number generator iZG of an inventive quantum random number generator ZZG. The embodiment shown largely corresponds to that shown in Fig. 5. The reference numerals and their respective assignment to individual features therefore apply accordingly. In comparison to Fig. 4, the channel-shaped high-voltage p-well HPW in the absorption region PW / HPW was omitted and the weakly n-doped or intrinsic epitaxial region NEPI extends over the entire lower region. In this respect, compared to the Fig. 4 the high-voltage p-well HPW is structurally replaced by a weakly n-doped or intrinsic epitaxial region NEPI.

[0366] The deep pn junction 50 is thus only connected after an additional punch through the weakly n-doped or intrinsic epitaxial region NEPI from the anode, which results in a decoupling of possibly several cells arranged next to one another in parallel. Description of Figure 7

[0367] Fig. Figure 7 shows a graphical representation of the dependence of a) the SPAD current and b) the ratio between SPAD current and Zener current as a function of the Zener reverse voltage at various SPAD reverse voltages (less than, equal to, or greater than the breakdown voltage) within an entropy source EQ (401) according to the invention. The dependence shown under a) clearly shows that the SPAD current increases exponentially with the Zener reverse voltage in the range from 5.6 V to 6.6 V. This applies to all operating modes of the SPAD, i.e., below its own breakdown voltage (< VBD, linear range), near the breakdown voltage (~VBD, avalanche range), as well as above the breakdown voltage (> VBD), and thus also in Geiger operation.

[0368] The lower curve shown under b) (< VBD) shows that the measured current ratio between the SPAD current and the Zener current for various Zener reverse voltages in the range 5.8 to 6.6 V is approximately 1:4000. In the SPAD breakdown voltage range (~VBD), the ratio increases to values ​​around 1:10. This is due to the so-called multiplication factor of the SPAD, which leaves the linear range in the breakdown voltage range. The upper curve shows the corresponding ratio for the SPAD operated above the corresponding breakdown voltage (> VBD) (approximately 1:1). This means that when the SPAD is operated above the corresponding breakdown voltage (> VBD), the generated photocurrent and the Zener current of the Zener avLED are approximately equal, and a clear measurement signal can be measured by coupling photons to the SPAD. Description of Figure 8

[0369] Fig. Figure 8 shows a schematic representation of an exemplary electronic circuit of an inner quantum random number generator iZG for generating and outputting a digital random number sequence by means of a finite state machine 404.8. The shown entropy source 401 (referred to as EQ in the remainder of the text) can in particular be a photon source 120 and a photon detector 130 of a proposed entropy source EQ (401) of the inner quantum random number generator iZG, wherein the device parts of the entropy source EQ (401) of the inner quantum random number generator iZG are connected to the supply voltage lines V ENT1 and V ENT2 ,, which is connected to a voltage converter 408 (reference symbol VSUP in Fig. 10) is connected to a reference potential on a reference potential line GND. An entropy source 401 (reference symbol EQ of the Fig. 10) is preferably used as a voltage signal in an analog-to-digital converter (ADC) 403, which is connected via a reference voltage line V REF is first digitized and then transferred as a digital output signal 407 to a pulse extension circuit 406. The supply voltage lines V ENT1 , V ENT2 and the reference voltage line V REF are monitored via a voltage monitor 413, with both the voltage converter 408 and the voltage monitor 413 being supplied with voltage via a positive supply voltage line VDD relative to the reference potential on the reference potential line GND. The voltage converter 408 is connected to the voltage monitor 413 via a voltage converter line 421.

[0370] Pulse extension circuit 406 may, in particular, be a monostable multivibrator (MF). The monostable multivibrator can be used to extend a pulse on the line of the digital output signal 407 of the ADC 403 depending on a certain predetermined system clock, for example, to a time length of at least one clock period of the system clock.

[0371] A synchronized voltage signal 415, e.g., a pulse with a specific minimum length, is then output by the pulse extension circuit 406 and transferred to a time-to-pseudo-random-number converter (TPRC) 404.3. This can be composed of one or more stages. For example, the TPRC 404.3 can comprise an analog instrument, a time-to-analog converter (TAC), and / or an analog-to-pseudo-random-number converter (APRC), which together can also provide a TPRC 404.3a. The pseudorandom number generator of the TPRC 404.3 can comprise a feedback shift register which, depending on the design, shifts its values ​​one place to the left or right with each clock pulse of the system clock and feeds the feedback value of a given feedback polynomial into the released bit.The feedback polynomial can preferably be a simple primitive feedback polynomial. The TPRC 404.3 can be directly connected to an internal data bus 419. The output signal 410 of the TPRC 404.3 can also be fed to an entropy extraction 404.4. Instead of the TPRC, a time-to-digital converter (TDC) can also be used, which is typically a binary start-stop counter that is started with a first pulse of the synchronized voltage signal 415 and stopped with a second pulse of the synchronized voltage signal 415. The disadvantage of such a TDC, however, is its slowness and chip area, and the fact that an attacker can measure its success.

[0372] Starting with a starting value of the pseudorandom number generator (a so-called seed value), exactly one pseudorandom number of the pseudorandom number generator can be bijectively assigned to each clock pulse of the system clock starting from a falling edge of the synchronized voltage signal 415, ie the time position of the relevant clock pulse of the system clock after the falling edge of the synchronized voltage signal 415 can then be deduced from the value of the pseudorandom number.

[0373] Instead of a conventional digital counter as in the prior art, a pseudorandom number generator can thus be used. The advantage is that even if an attacker successfully introduces a disturbance into the synchronized voltage signal 415, the randomness of the quantum random bit at the output 411 of the entropy extraction 404.4 is only marginally disturbed, since the attacker would have to know the corresponding feedback polynomial. This can preferably be randomly selected from a multitude of possibilities. The same applies to the seed value of the pseudorandom number generator, which an attacker would then also have to determine. A further advantage of a pseudorandom number generator instead of a simple digital counter is the smaller space requirement of the feedback logic using a simple primitive feedback polynomial compared to a binary counter.If the linear feedback shift register of the pseudorandom number generator is long enough, each clock pulse between two pulses of the entropy source output signal 405, typically generated as a voltage signal by the entropy source 401, is typically assigned a unique pseudorandom number.

[0374] Entropy extraction 404.4 can be used to determine an error (i.e., an undesired state) in the output signal 410 of TPRC 404.3. For this purpose, entropy extraction 404.4 can, in particular, comprise two linear feedback shift registers that can be compared with one another via a comparator. Conventional binary counters can therefore be dispensed with here as well. Depending on the register depth, feedback can also be achieved using simple primitive polynomials as feedback polynomials. The length of the linear feedback shift registers can be freely adjustable. Long shift registers generally have a lower data rate and improved random statistics. Shorter shift registers, on the other hand, allow a higher data rate but exhibit a poorer random distribution.The use of shift registers here has the advantage of requiring fewer gates than in the prior art, reducing the logic depth of the circuits, and thus allowing for a higher clock rate. This reduces the probability of two identical numbers occurring and increases the random bit rate.

[0375] A corresponding method for entropy extraction EE can provide that two values ​​of the output signal 410 of the TPRC 404.3 are first determined and stored in the shift register of the entropy extraction EE 404.4. If two values ​​are stored in the shift register of the entropy extraction 404.4 (EE), the entropy extraction 404.4 (EE) can compare these two values. The values ​​in the shift registers of the entropy extraction 404.4 (EE) thus comprise a first value and a second value, both of which were determined by the TPRC 404.3. The entropy extraction 404.4 (EE) can then evaluate the two values. If the first value is smaller than the second value and the difference between the first value and the second value is greater than a minimum difference ε, the entropy extraction 404.4 (EE) can set the value of its output 411 to a first logical value.If the first value is greater than the second value and the difference between the first and second values ​​is greater than the minimum difference ε, the entropy extraction 404.4 (EE) can set its output 411 to a second logical value that is different from the first logical value. If the difference between the first and second values ​​is smaller than the minimum difference ε, the entropy extraction 404.4 (EE) can discard the first and second values.

[0376] Preferably, particularly when an error occurs, the entropy extraction 404.4 (EE) causes a so-called watchdog 404.5 (WD) to increment an error counter by a first error counter increment. The first error counter increment can be negative. Conversely, the entropy extraction 404.4 (EE) can decrement the error counter of the watchdog 404.5 (WD) by a second error counter increment if the difference between the first value and the second value is greater than the minimum difference ε. The second error counter increment can be equal to the first error counter increment.

[0377] The watchdog 404.5 (WD) is also connected to the internal data bus 419 as a transport medium for the random bit stream ZBS. The internal data bus 419 can, for example, be connected to a crypto engine KE and / or one or more memories MEM and / or one or more CPUs. In addition, the watchdog 404.5 (WD) can be connected to the voltage monitor 413 via one or more, preferably digital, input / output signal lines 414. The watchdog 404.5 (WD) preferably monitors the voltage values ​​determined by the voltage monitor 413. It has proven useful if the voltage monitor 413 not only determines and monitors the voltages in the internal quantum random number generator iZG, but also other voltages within the respective application circuit. The voltage monitor 413 can, for example, be an ADC.

[0378] However, in this example, the actual task of watchdog 404.5 (WD) is to monitor the entropy quality of the quantum random number RN at the output 411 of entropy extraction 404.4 (EE). The watchdog 404.5 (WD) can preferably detect at least three defined error cases. The watchdog 404.5 (WD) can forward valid quantum random bits 411, generating a seed value S 412, to an optional additional linear feedback shift register as a backup pseudorandom number generator (PRNG) 404.6. Preferably, the watchdog 404.5 (WD) prevents the use of the valid quantum random bits by a finite state machine 404.8. This is connected here, for example, to the internal data bus 419. If an error occurs, the Watchdog 404.5 (WD) can set certain error bits for further evaluation, which another bus participant (e.g.a microcontroller (MCU)) can read and / or write via an external data bus DB, a data bus interface DBIF and the internal data bus 419.

[0379] For example, if the watchdog 404.5 (WD) has detected an error in the quantum random number generator ZZG and / or the internal quantum random number generator iZG, it can preferably put the quantum random number generator ZZG and / or the internal quantum random number generator iZG into an emergency state. For this purpose, the watchdog 404.5 (WD) preferably sets a selection signal 416 of a signal multiplexer 404.7 arranged downstream of the random number generation, so that the signal multiplexer 404.7 applies the pseudorandom number PRN of the optional PRNG 404.6 in the form of a stream of pseudorandom bits via a pseudorandom signal line 417 to the input of the finite state machine 404.8 as a replacement for the at least potentially erroneous random number RN of the output 411 of the entropy extraction 404.4 instead of the random numbers RN at the output 411 of the entropy extraction 404.4.

[0380] When an error in the entropy occurs, the watchdog 404.5 can, for example by means of an interrupt signal, cause a CPU (computer core) of the random number generator ZZG to execute a computer- and / or machine-implemented method for correcting or containing the error, the program code of which is preferably located in a memory of the control device of the random number generator ZZG and which the CPU (computer core) of the random number generator ZZG accesses when executing the computer- and / or machine-implemented method for correcting or containing the error.

[0381] The optional, additional linear feedback shift register of the PRNG 404.6 can be configured to generate pseudorandom numbers PRN. The seed value S 412 preferably comprises the last valid quantum random bits of the output 411 of the entropy extraction 404.4. The watchdog 404.5 then preferably applies these last valid quantum random bits 411 to the input of the optional PRNG 404.6. The seed value S can thus be used as a random, secure starting value for a generator polynomial of the feedback of the optional additional linear feedback shift register of the PRNG 404.6 for generating the pseudorandom number PRN and signaling it via the pseudorandom signal line 417. The generator polynomial and the degree of the generator polynomial are preferably freely selectable. The optional backup pseudo-random number generator can enable the provision of secure random numbers, at least temporarily, in the event of an error.

[0382] The finite-state machine 404.8 is responsible for receiving the random number RN or the pseudorandom number PRN at the output of the signal multiplexer 404.7 and writing the corresponding quantum random numbers, typically in the form of quantum random data words 418, via a pseudorandom signal line 417 into a volatile memory (RAM) or a FIFO (First In - First Out) memory 404.9 as memory (MEM). If the write operation is successful, the finite-state machine 404.8 can set a finish flag 404.10 via the internal data bus 419. A processor (MCU), for example, can then access the volatile memory (RAM) or a FIFO (First In - First Out) memory 404.9 and read the random number, for example, for encryption. Description of Figure 9

[0383] Fig. 9 shows a schematic representation of an exemplary layout of an integrated electronic circuit 500 of a quantum random number generator ZZG with an inventive entropy source EQ of an inventive internal

[0384] A top view of the quantum random number generator iZG in the pad frame 503. The integrated electronic circuit 500, for example, a microcontroller with a CPU, has, for example, an inner region 505 in which the essential subcircuits of the integrated electronic circuit 500 are located. Typically, the inner region 505 is surrounded by a wiring region 504, in which, above all, supply voltage lines, data bus lines, and other lines can be routed.

[0385] The wiring area 504 and the inner area 505 of the integrated electronic circuit 500 are typically surrounded by the pad frame 503 (also referred to as pad edge), which includes the connection pads 502 (connection areas) for the electrical bonds or other electrical connections.

[0386] Preferably, an entropy source (EQ) according to the invention of an inner quantum random generator iZG according to the invention, as described for example in Fig.8, or a corresponding quantum random number generator ZZG, can be placed entirely or at least substantially in the pad frame 503, since the gaps between the individual connection pads 502 are often not filled with electronic circuit components. However, these gaps must still be processed during the manufacture of the integrated electronic circuit 500 and therefore cause unnecessary manufacturing costs. Placing inventive entropy sources EQ, inventive internal quantum random number generators iZG, or corresponding quantum random number generators ZZG entirely or at least substantially in the pad frame 503 therefore significantly reduces the additional costs for their provision.

[0387] In particular, at least the photon source 120 and the photon detector 130 (entropy source 401 (EQ)) can preferably be placed in the pad frame 503 between two connection pads 502. Furthermore, an ADC 403, a voltage converter 408 for supplying power to the entropy source 403 (EQ), a pulse extension circuit 406, and / or analog components of a quantum random generator ZZG according to the invention (e.g., an amplifier) ​​can also be placed in the pad frame 503 between two connection pads 502. Description of Figure 10

[0388] The entropy source EQ(401) generates a noise signal as entropy source output signal 402, which the internal quantum random number generator iZG converts into a random bit data stream RN. The combinational logic CL preferably comprises digital filters and / or a digital entropy extraction unit (404.4, EE) that extract the random bit stream ZBS(RN) and feed it to the crypto engine KE, preferably via an internal data bus 419.

[0389] The crypto engine KE encrypts a first random bit portion of the random bit data stream ZBS into an encrypted random bit data stream VZS using a key in its memory MEM. An external computer system MCU can then retrieve encrypted random bits as encrypted random numbers via a data bus DB and a data interface DBIF. Preferably, the crypto engine KE also decrypts encrypted commands from the external computer system MCU to the random number generator ZZG, which the external computer system MCU sends to the random number generator ZZG via the data bus DB and the DBIF interface. It forwards the decrypted commands to the device components of the random number generator or uses them itself if it is the recipient of such a command. This allows the external computer system to securely control the random number generator ZZG.

[0390] Preferably, a watchdog WD (404.5) or a similar device DIAG for diagnosing the device parts of the quantum random number generator ZZG monitors the entropy of the random bit stream ZBS, the operating voltages of the entropy source EQ and the supply voltage unit VSUP (408) for the entropy source EQ (401) and the externally applied supply voltages and the supply voltage device CLV for the supply voltages of the digital device parts for correct function or correct values.

[0391] Additional monitoring circuits (SUP) can detect further anomalies. A voltage pre-regulator (VS) can supply the other voltage regulators (CLV, VSUP) with electrical power and maintain a constant current to eliminate side-channel interference. The voltage pre-regulator (VS) preferably diverts excess current to a current sink, such as an electrical resistor, when not needed. This allows the device to consume a constant current without revealing any information about its internal processes through its current consumption over time. A JTAG test interface enables fabrication testing. Miscellaneous

[0392] The above description is not exhaustive and does not limit this disclosure to the examples shown. Other variations to the disclosed examples can be understood and practiced by those of ordinary skill in the art, based on the drawings, the disclosure, and the claims. The indefinite articles "a" or "an" and their inflections do not exclude a plurality, while the mention of a certain number of elements does not exclude the possibility of more or fewer elements being present. A single unit may perform the functions of several elements mentioned in the disclosure, and conversely, several elements may perform the function of one unit. Numerous alternatives, equivalents, variations, and combinations are possible without departing from the scope of the present disclosure.

[0393] Unless otherwise stated, all features of the present invention can be freely combined with one another. This applies to the entire document presented here. The features described in the description of the figures can also be freely combined with the other features as features of the invention, unless otherwise stated. A restriction of individual features of the exemplary embodiments to combination with other features of the exemplary embodiments is expressly not intended. Furthermore, physical features of the device can be reformulated to also be used as method features, and method features can be reformulated to be used as physical features of the device. Such a reformulation is therefore automatically disclosed.

[0394] In the foregoing detailed description, reference is made to the accompanying drawings. The examples in the description and drawings should be considered illustrative and not limiting of the specific example or element described. Multiple examples may be derived from the foregoing description and / or drawings and / or the claims by modifying, combining, or varying certain elements. Furthermore, examples or elements not described verbatim may be derived from the description and / or drawings by a person skilled in the art. List of reference symbols 10 Carrier substrate 22 first area (e.g. NBL) 32 second area (e.g. PBL) 40 epitaxial layer 50 first pn junction (e.g. upper pn junction of a double structure) 52 second pn junction (e.g. lower pn junction of a double structure) 110 Substrat 120 photon source (e.g. single photon source, SPS) 122 Cathode (n+, photon source) 124 anode (p+, photon source) 128 photons 130 Single-photon detector (e.g. single-photon avalanche diode, SPAD) 132 Cathode connection (n+, single photon detector) 134 Anode connection (p+, single photon detector) 150 light blocking layer 152 means of electronic recording 154 Means of electronic post-processing 160 photon detector 161 PN transition of the photon source 120 401 Entropy source of the iQRNG 400 Quantum random number generator (e.g. based on an entropy source 401) 401 Entropy Source (e.g. iQRNG) 403 Analog-to-Digital Converter (ADC) 404.3 Time-to-Pseudo-Random-Number Converter (TPRC) 404.4 Entropy extraction 404.5 Watchdog (1130) 404.6 Pseudo-random number generator (PRNG, e.g. linear feedback shift register) 404.7 Signal Multiplexer 404.8 Finite State Machine (FSM) 404.9 volatile memory (RAM) / FIFO memory (First In - First Out) 404.10 Finish Flag 405 Entropy source output signal (Entropy source) 406 Pulse extension circuit (e.g. monoflop, MF) 407 Output signal (ADC) 408 voltage converter 410 Output signal (TPRC) 411 Output (Entropy Extraction) 412 Seed Value S 413 Voltage Monitor 414 digital input / output signal lines 415 synchronized voltage signal (e.g. pulse with a minimum length) 416 Selection signal 417 Pseudorandom signal line 418 quantum random data words (which usually represent quantum random numbers or are parts of such quantum random numbers) 419 internal data bus 420 Interrupt signal (preferably for signaling the provision of a random number or the fulfillment of an error condition to controller 9) 421 voltage transformer cable 422 optional signal 500 electronic circuits (Integrated Circuits, ICs) 501 semiconductor die 502 connection pads (connection surfaces) 503 pad frame 504 wiring area 505 inner area CL combinatorial logic CLV Supply voltage device CLV for the supply voltages of the digital device parts of the random number generator ZZG CONT Contact DB Data bus DB (The data bus DB is used here as an example for a general wireless and / or wired data transmission channel in the network.) DBIF Data Interface DBIF The (data interface DBIF stands here as an example for one or more interfaces to one or more wired and / or wireless data transmission channels in the network.) DIAG device DIAG for diagnosis (possibly part of WD, 404.5) EE Entropy Extraction 404.4, EQ Entropy Source H(V)PW high-voltage p-type well H(V)NW high-voltage n-type well iZG internal random number generator (here an internal quantum random number generator iQRNG) iQRNG internal quantum random number generator (here an internal random number generator iZG) JTAG test, programming and configuration interface JTAG KE Crypto Engine N+ n+ area NBL deep n-layer (n-type buried layer) NEPI weakly n-doped or (approximately) intrinsic epitaxial region MCU external computer system MCU (The external computer system is an example of a network node in the network) MEM memory MEM of the crypto engine KE MET1, MET2 metallization O Surface (substrate, e.g. a BCD substrate) P+ p+ area PBL deep p-layer (p-type buried layer) PBODY p-doped region (p-type body) poly polysilicon layer PRN pseudorandom number PW p-well R radial axis of symmetry R1 first working resistor R2 second working resistor RN Random bit data stream (e.g. 1-bit random number) (output signal of entropy extraction 404.4) S Surface (carrier substrate, e.g. a BCD substrate) STI isolation area (“shallow trench isolation”) VDD positive supply voltage line GND reference potential line V ENT1 Supply voltage line of the photon source 120 of the e...

Claims

[1] Random Number Generator (RNG) wherein the random number generator (RSG) comprises an inner random number generator (IRG) and wherein the random number generator (ZZG) comprises a crypto engine (KE) and wherein the random number generator (ZZG) comprises a data bus interface (DBIF) for a data bus (DB) and wherein the inner random number generator (iZG) is configured to generate a random bit stream (ZBS) whose random bits have random logical values ​​in the sense of the NIST test. [2] Random number generator (ZZG) according to claim 1, wherein one or more random bits of the inner random number generator (iZG) can be accessed in encrypted or unencrypted form via the data bus interface (DBIF). [3] Random number generator (ZZG) according to claim 1 or 2, wherein the internal random number generator (iZG) and / or the crypto engine (KE) can be configured via the data bus interface (DBIF). [4] Random number generator (ZZG) according to one of claims 1 to 3, wherein the inner random number generator (iZG) is a TRNG (True Random Number Generator) for real random bits. [5] Random number generator (ZZG) according to one of claims 1 to 4, wherein the inner random number generator (iZG) is a QRNG (Quantum Random Number Generator). [6] Random number generator (ZZG) according to one of claims 1 to 5, wherein the crypto engine (KE) and / or other device parts of the random number generator (ZZG) are configured to to transmit one or more self-generated keys to other bus participants (MCU) on the data bus (DB) via the data bus interface (DBIF) of the random number generator (ZZG) in encrypted form or as a public key from one or more key pairs consisting of a public and private key and / or to receive one or more public keys from these other bus participants (MCU) via the data bus (DB) and / or to keep previously agreed secret keys in a memory (MEM) of the crypto engine (KE) and / or the random number generator (ZZG) and to establish an encrypted connection on the basis of these keys and to encrypt a second random bit portion of the random bits of the random bit data stream (ZBS) of the inner random number generator (iZG) and to transmit it in encrypted form to one or more other bus users (MCU) on the data bus (DB). [7] Random number generator (ZZG) according to one of claims 1 to 6, wherein the crypto engine (KE) is configured to use a first part of the random bits of the random bit data stream (ZBS) of the inner random number generator (iZG) for generating keys. [8] Random number generator (ZZG) according to claim 7, wherein the crypto engine (KE) is configured to use one or more keys, in particular keys according to claim 6, for encrypting a second random bit portion of the random bits of the random bit data stream (ZBS) of the inner random number generator (iZG) to form encrypted random bits (VZS). [9] Random number generator (ZZG) according to claim 8, wherein the crypto engine (ZE) is configured to output the encrypted random bits (VZS) via the data bus interface (DBIF). [10] Random number generator (ZZG) according to one of claims 1 to 9, wherein the inner random number generator (iZG) is configured to generate random bits with a high random bit rate and wherein the inner random number generator (iZG) has a vertical entropy source relative to the horizontal surface O of a semiconductor substrate to enable the high random bit rate. [11] Random number generator (ZZG) according to one of claims 1 to 10, wherein a vertical entropy source EQ of the inner random number generator (iZG) comprises a specific circuit configuration that uses an improved entropy source EQ, in particular to maximize the quality of the random bits. [12] Random number generator (ZZG) according to one of the preceding claims, wherein the inner random number generator (iZG) comprises an entropy module (WD), in particular as part of a watchdog (WD), which is designed to monitor and evaluate the entropy of the random bits generated by the inner random number generator (iZG), in particular to ensure the reliability of the cryptographic processes and / or the signature processes. [13] Random number generator (ZZG) according to one of the preceding claims, further comprising a filter module which is configured to improve the statistical properties of the random bits to filtered random bits, in particular to ensure a uniform distribution of the random bits and / or high-pass properties of the spectrum of the random bit data stream (ZBS). [14] Random number generator (ZZG) according to one of the preceding claims, wherein the vertical entropy source (EQ) and / or the inner random number generator (iZG) is implemented by an ASIC implementation and / or monolithic microelectronic implementation, in particular in CMOS technology and in particular as a microintegrated circuit (IC), in order to optimize in particular the performance and energy efficiency of the random number generator (ZZG). [15] Random number generator (ZZG) according to one of the preceding claims, further comprising a calibration unit for self-calibration of device parts of the inner random number generator (iZG), such as analog-to-digital converters and / or digital-to-analog converters and / or voltage sources and / or reference voltage sources and / or reference current sources, etc., in order to ensure in particular the long-term stability and accuracy of the random bit generation. [16] Random number generator (ZZG) according to one of the preceding claims, wherein the random number generator (ZZG) and / or the crypto engine (KE) are of modular construction and comprise interchangeable encryption and internal random number generator modules by means of programming, in particular to enable simple adaptation to different cryptographic requirements. [17] Random number generator (ZZG) according to one of the preceding claims, wherein the interface unit (data bus interface) (DBIF) of the random number generator (ZZG) supports various communication protocols, preferably selectable by hardware or software programming, in particular to ensure interoperability in and / or with different external systems. [18] Random number generator (ZZG) according to one of the preceding claims, wherein the crypto engine (KE) and / or the random number generator (ZZG) is integrated into a system-on-chip (SoC), in particular to provide a compact and powerful solution for embedded systems. [19] Random number generator (ZZG) according to one of the preceding claims, wherein the inner random number generator (iZG) is configured to function at least temporarily as the inner random number generator (iZG) of the crypto engine (KE). [20] Random number generator (ZZG) according to the preceding claim, wherein the crypto engine (KE) is configured to use only a first random bit portion of the random bits of the random bit stream (ZBS) of the inner random number generator (iZG). [21] Random number generator (ZZG) according to the preceding claim, wherein the random number generator (ZZG) is configured to forward a second random bit portion of the random bits of the inner random number generator (iZG) to other bus users (MCU) via the data bus (DB). [22] Random number generator (ZZG) according to one of the preceding claims, wherein the data bus (DB) is a serial bus, in particular to enable a flexible connection to different bus participants. [23] Random number generator (ZZG) according to one of the preceding claims, wherein the crypto engine (KE) is configured to encrypt data of the internal random number generator (iZG) sent to one or more other bus users (MCU), in particular to ensure the security of the transmitted data. [24] Random number generator (ZZG) according to one of the preceding claims, wherein the crypto engine (KE) is configured to decrypt encrypted data which the random number generator (ZZG) receives from one or more other bus users (MCU) and to make it available to device parts of the random number generator (ZZG) or to use it itself, in particular to enable secure data communication within the system comprising the random number generator (ZZG) and other bus users (MCU) of the data bus (DB). [25] Random number generator (ZZG) according to one of the preceding claims, wherein the data sent to other bus users (MCU) from the random number generator (ZZG) and / or one or more of its device parts comprise one or more random bits of the inner random number generator (iZG) and / or status information of the inner random number generator (iZG), in particular to enable a broad applicability of the random data. [26] Random number generator (ZZG) according to one of the preceding claims, wherein the crypto engine (KE) is configured to decrypt encrypted control and / or configuration information for the inner random number generator (iZG) and / or other device parts of the random number generator (ZZG) and / or for the crypto engine (KE) itself, in particular to ensure secure and flexible control of the random number generator (ZZG) and / or its device parts. [27] Random number generator (ZZG) according to the preceding claim, wherein the status information of device parts of the inner random number generator (iZG) comprises a current operating mode and / or error messages, in particular to enable precise monitoring and control of the random number generator (ZZG). [28] Random number generator (ZZG) according to one of the preceding claims, wherein the crypto engine (KE) is configured to use a second random bit portion of the random bits of the random bit stream (ZBS) of the internal random number generator (iZG) for generating keys and / or generating signatures. [29] Random number generator (ZZG) according to one of the preceding claims, wherein the crypto engine (KE) is configured to encrypt data of the random number generator (ZZG) and / or of device parts of the random number generator (ZZG) by means of one or more of the keys. [30] Random number generator (ZZG) according to the preceding claim, wherein the crypto engine (KE) is configured to encrypt data of the random number generator (ZZG) and / or of device parts of the random number generator (ZZG) by means of one or more of the keys and by means of a computer- and / or machine-implemented PQC encryption method. [31] Random number generator (ZZG) according to one of the preceding three claims, wherein the crypto engine (KE) is configured to sign data of the random number generator (ZZG) and / or of device parts of the random number generator (ZZG) by means of one or more of the signatures. [32] Random number generator (ZZG) according to one of the preceding claims, wherein the crypto engine (KE) is configured to verify and / or authenticate data received from other bus users (MCU) in a predetermined manner and / or by a computer- or machine-implemented algorithm and / or randomly, in particular to ensure the integrity of the data. [33] Random number generator (ZZG) according to one of the preceding claims, wherein the crypto engine (KE) is configured to sign data that the random number generator (ZZG) sends to other bus users (MCU) with a signature. [34] Random number generator (ZZG) according to one of the preceding claims, wherein the crypto engine (KE) is configured to decrypt encrypted data from other bus users (MCU). [35] Random number generator (ZZG) according to the preceding claim, wherein the crypto engine (KE) is configured so that the data of the other bus users (MCU) can include random bits of other random number generators, in particular to increase the flexibility in dealing with multiple random number generators. [36] Random number generator (ZZG) according to the two preceding claims, wherein the crypto engine (KE) is configured so that the data of the other bus participants (MCU) can include keys and / or signatures of other random number generators, in particular to increase the flexibility in dealing with multiple random number generators. [37] Random number generator (ZZG) according to the three preceding claims, wherein the crypto engine (KE) and / or the random number generator (ZZG) and / or device parts of the random number generator (ZZG) are configured to use keys and / or signatures and / or random bits of other random number generators - a) for the generation of keys and / or signatures and / or random bits and / or - b) for the use of keys and / or signatures and / or random bits and / or - c) for which the encryption of data of the random number generator (ZZG) or of parts of the random number generator (ZZG) and / or - d) to be used for the signing of data of the random number generator (RRG) and / or of parts of the device of the random number generator (RRG). [38] Random number generator (ZZG), in particular according to one of the preceding claims, wherein the random number generator (ZZG) is designed at least in essential parts as a hardware implementation as part of a microelectronic circuit, in particular an ASIC or an FPGA or a memory (DRAMs, flash memories, SRAMs or ROMS) or a processor (CPU), in particular to ensure high performance and efficiency and In particular, this embodiment of the random number generator (ZZG) is essentially in the form of an FPGA and wherein in particular the FPGA comprises an entropy source and wherein in particular the FPGA comprises further device parts of the random number generator (ZZG) and / or the inner random number generator (iZG). [39] Random number generator (ZZG) according to one of the preceding claims, The data interface (DBIF) supports several hardware- or programmably selectable communication protocols, in particular to ensure compatibility with different bus participants. [40] Random number generator (ZZG) according to one of the preceding claims, wherein a data bus (DB) is a serial data bus, in particular a LIN data bus, with exactly one single-wire data line and one ground line. [41] Random number generator (ZZG) according to one of the preceding claims, wherein a data bus (DB) is a serial differential data bus, in particular a CAN data bus, with exactly one first single-wire data line, exactly one second single-wire data line and an optional ground line, which can be, for example, the body of a vehicle. [42] Random number generator (ZZG) according to one of the preceding claims, wherein the data bus interface (DBIF) and / or the crypto engine (KE) and / or a device of the random number generator (ZZG) comprise an error detection and error correction unit, in particular to increase the reliability of the data communication. [43] Random number generator (ZZG) according to one of the preceding claims, wherein the crypto engine (KE) is configured to store at least some of the random bits after receipt from the internal random number generator (iZG), in particular in a memory (MEM), in order to enable buffering for subsequent processing operations. [44] Random number generator (ZZG) according to one of the preceding claims, wherein the crypto engine (KE) is configured to process the random bits of the first random bit portion of the random bits of the random bit stream (ZBS) of the inner random number generator (iZG) in real time, in particular to ensure a low latency in safety-critical applications. [45] Random number generator (ZZG) according to one of the preceding claims, wherein the crypto engine (KE) and / or the inner random number generator (iZG) and / or the random number generator (ZZG) and / or other device parts of the random number generator (ZZG) have a modular and programmable architecture, in particular an FPGA device part, in order to facilitate in particular the adaptation of the random number generator to different security requirements. [46] Random number generator (ZZG) according to one of the preceding claims, wherein the crypto engine (KE) and / or the random number generator (ZZG) and / or the internal random number generator (iZG) and / or other device parts of the random number generator (ZG) are configurable by software updates, in particular to enable adaptability to new cryptographic standards. [47] Random number generator (ZZG) according to one of the preceding claims, wherein the crypto engine (KE) and / or the random number generator (ZZG) and / or the internal random number generator (iZG) and / or other device parts of the random number generator (ZZG) are integrated into a monolithic microcontroller system, in particular to be used in embedded systems. [48] ​​Random number generator (ZZG) according to one of the preceding claims, wherein the crypto engine (KE) and / or the random number generator (ZZG) and / or the internal random number generator (iZG) and / or other device parts of the random number generator (ZZG) comprise an interface (JTAG) for diagnosis and maintenance, in particular a JTAG interface, in order to improve in particular the maintainability and / or testability of the random number generator (ZZG). [49] Random number generator (ZZG) according to one of the preceding claims, wherein the crypto engine (KE) and / or the random number generator (ZZG) and / or the internal random number generator (iZG) and / or other device parts of the random number generator (ZZG) are equipped with a respective power-saving function, in particular to minimize energy consumption in portable or energy-efficient applications, In particular, the respective power saving function is activated by means of a configuration command via the data bus (DB) and / or by signaling via a power-down connection of the random number generator (ZZG) and / or by initiation via a timer of the random number generator (ZZG). [50] Crypto engine (KE) for use in a random number generator (RSG) according to one or more of the preceding claims relating to a random number generator (RSG), comprising: an encryption unit that uses the random bits of the inner random number generator (RNG) to generate cryptographic keys and / or encrypt data, [51] Crypto engine (KE) according to claim 50, wherein the encryption unit for generating cryptographic keys is configured to generate, in particular, secure keys for various cryptographic algorithms. [52] Crypto engine (KE) according to one of the preceding claims 50 to 51, wherein the encryption unit is configured to support both symmetric and asymmetric encryption algorithms, in particular to ensure flexibility in application. [53] Crypto engine (KE) according to one of the preceding claims 50 to 52, further comprising a memory module and / or a memory (MEM) for temporarily storing the generated random bits of the internal random number generator (ZZG), in particular to enable efficient data processing. [54] Crypto engine (KE) according to one of the preceding claims 50 to 53, wherein the interface unit is configured to support encrypted data transmission via the data bus interface (DBIF) of the random number generator (ZZG), in particular to increase the security of the communication. [55] Crypto engine (KE) according to one of the preceding claims 50 to 54, wherein the crypto engine (KE) is modular and comprises interchangeable encryption and internal random number generator modules by means of programming, in particular to enable easy adaptation to different cryptographic requirements. [56] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a VPN system, in particular for secure key generation and key management for encrypted VPN connections. [57] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in IoT networks, for ensuring the integrity and confidentiality of communication between IoT devices. [58] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in cloud computing environments, in particular for secure data processing and storage in cloud environments. [59] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in financial transaction systems, in particular for the secure execution and verification of financial transactions. [60] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in communication systems, in particular for the secure transmission of messages and data in communication networks. [61] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in conjunction with a microcontroller (MCU), in particular to enable secure key generation and management. [62] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in conjunction with a CPU in an embedded system, in particular to ensure secure encryption and data transmission. [63] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in conjunction with a sensor evaluation and control circuit, in particular to ensure the integrity and confidentiality of the sensor data. [64] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG), in connection with a network node in a wired or wireless network, in particular to increase the security of the communication protocols. [65] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in conjunction with a chip card, in particular to enable secure authentication and data processing on the card. [66] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a network node in an IoT network, in particular to ensure secure communication between the IoT devices. [67] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a cloud computing system, in particular to enable the encryption and secure storage of data in the cloud. [68] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a financial transaction system, in particular to ensure the security and confidentiality of the transactions. [69] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a communication system, in particular to enable the secure transmission of messages and data. [70] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a portable device, in particular in a smartphone or a telephone or the like, in particular to implement secure and energy-efficient encryption. [71] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in one or more sensors in a sensor network, in particular to ensure the authentication and integrity of the sensor data. [72] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a vehicle control system and / or a vehicle network, in particular to ensure secure communication between the control units and / or with device parts of the vehicle. [73] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a weapon control system and / or a network within a weapon system, in particular to ensure secure communication between the device parts of the weapon system. [74] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a military equipment system for soldiers, in particular to ensure secure communication between the device parts of the military equipment system and / or between the military equipment systems of different soldiers and / or between the military equipment systems of one or more soldiers on the one hand and one or more weapon systems and / or military networks on the other hand. [75] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a medical device, in particular to protect the confidentiality of patient data and patient measurement values ​​from patient sensors and to ensure security. [76] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in an industrial automation system in a production process, in particular to ensure the security of the control commands and data against attacks. [77] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a smart home system, in particular to ensure the security of the control and communication of the smart home devices in a property or a fixed installation and / or in an infrastructure object. [78] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in an infrastructure system, in particular to ensure the security of the control and communication of the device parts of the infrastructure system (gas supply, drinking water supply, waste water supply, power supply, district heating supply, etc.). [79] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a microprocessor, comprising in particular an ALU (Arithmetic Logic Unit), an internal microprocessor data bus, a control unit and registers, in particular for generating random bits and / or random numbers for cryptographic operations directly in the processor. [80] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in an FPGA (Field-Programmable Gate Array), comprising in particular - in particular configurable logic circuits and / or - in particular configurable logic blocks and / or - especially configurable lookup tables and / or - in particular configurable and / or programmable connections and - in particular voltage regulators and / or in particular voltage converters and / or in particular data interfaces - in particular to enable configurable cryptographic functions in the FPGA and / or other uses of random bits and / or random numbers in the FPGA, in particular in real time. [81] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a DSP (Digital Signal Processor), comprising in particular specialised MAC units (Multiply-Accumulate Units) and pipeline architectures, in particular to enable secure signal processing in safety-critical applications. [82] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in an ASIC (Application-Specific Integrated Circuit) and / or a CMOS or BiCMOS or bipolar circuit, comprising in particular specialised circuits for cryptographic functions, in particular for integrating dedicated, high-performance cryptographic functions. [83] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a SoC (System-on-Chip) architecture, comprising in particular a microprocessor, one or more memories and one or more peripheral modules and a data bus on a single micro-integrated chip, in particular to create a compact and efficient solution for embedded systems. [84] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a GPU (Graphics Processing Unit), in particular comprising shader cores, texture units and memory controllers, in particular to carry out cryptographic calculations in parallel with graphics processing and / or in particular to carry out computer- and / or machine-implemented AI methods. [85] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a network processor, comprising in particular packet processing units and protocol engines, in particular to support secure data transmissions and protocol processing. [86] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a security chip for smart cards, comprising in particular a cryptographic processing unit and secure memory areas, in particular to enable secure authentication and encryption operations. [87] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a TPM (Trusted Platform Module), comprising in particular a cryptographic coprocessor unit and a secure memory, in particular to support secure storage and authentication processes in computer platforms. [88] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in an IoT processor, comprising in particular integrated radio modules and / or energy management units and / or sensor interfaces, in particular to ensure the integrity and confidentiality of the communication in networked devices and of the measured values. [89] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a control chip for industrial control systems, comprising in particular specialised interfaces for industrial protocols and real-time controllers, in particular to ensure secure control commands and / or data processing. [90] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a communication processor for mobile devices, comprising in particular baseband processors, modem units and signal coding units, in particular to ensure the security of voice and / or data transmissions. [91] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a wearable processor or a piece of clothing or accessory that includes a processor - here called a wearable processor - in particular comprising energy efficiency modules, wireless communication interfaces and integrated sensors, in particular to enable secure data processing and communication in wearable devices and / or in smart clothing. [92] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a memory controller, comprising in particular memory management units, cache controllers and memory bus interfaces, in particular to ensure the encryption of data in memory modules. [93] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in an automotive processor, in particular comprising CAN bus interfaces and / or other automotive data bus interfaces, such as LIN bus interfaces, security modules and real-time controllers, in particular to ensure secure communication and control in vehicle networks. [94] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a control chip for medical devices, in particular comprising integrated signal processing units, communication interfaces and security modules, in particular to ensure the confidentiality and integrity of patient data and / or patient measurement data. [95] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a control chip for drones and / or unmanned vehicles, floating bodies, missiles or satellites, in particular comprising integrated flight and / or movement control units, communication modules and sensor interfaces, in particular to ensure secure communication and control commands between the drone and the control device. [96] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a processor for computer-implemented virtual machines, in particular comprising virtualization and memory management units, in particular to enable the secure execution of virtual instances on a host system. [97] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in one or more processors of a processor system for executing computer-implemented models of virtual processors, in particular comprising virtualization and memory management units, in particular to enable the secure execution of virtual instances on a host system. [98] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a cryptocurrency mining chip, in particular comprising specialised hashing engines, power supply management and memory controllers, in particular to ensure the generation and verification of cryptographic hashes. [99] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a processor for edge computing, in particular comprising specialised network modules, data processing units and memory controllers, in particular to enable secure and decentralised data processing at the network edges. [100] Use of the random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG) in a processor for distributed ledger technologies (blockchain), in particular comprising specialised encryption units, memory management and network interfaces, in particular to ensure the security and integrity of the distributed transactions. [101] Internal random number generator (iZG) for a random number generator (ZZG) according to one of the preceding claims relating to a random number generator (ZZG), comprising a means for generating random numbers with a high random bit rate, wherein the internal random number generator has a vertical entropy source (EQ) which in particular enables the high random bit rate. [102] inner random number generator (iZG) according to claim 101, wherein the vertical entropy source (EQ) comprises a vertical arrangement of a photon source (120) and a photon detector (130), which is in particular designed to use an improved entropy source (EQ). [103] inner random number generator (iZG) according to claim 102, wherein the improved vertical entropy source (EQ) is realized by the vertical arrangement of a semiconductor single-photon source (120) and a photon detector (130) perpendicular to the surface (O) of a semiconductor substrate within the semiconductor substrate one above the other, which in particular enables a maximum photon interaction between the single-photon source and the photon detector. [104] inner random number generator (iZG) according to one of the preceding claims relating to an inner random number generator (iZG), further comprising a filter module for processing the generated random numbers, in particular to improve their statistical properties. [105] inner random number generator (iZG) according to the preceding claim, wherein the filter module comprises a high-pass filter, in particular for removing the bias from the random bit stream, and / or a low-pass filter and / or an XOR gate, in particular for reducing random systematic patterns in the random numbers. [106] inner random number generator (iZG) according to one of the preceding claims relating to an inner random number generator (iZG), comprising an amplifier module which in particular amplifies and / or filters the amplitude of the generated entropy source output signal of the entropy source (EQ), in particular before it is used and / or digitized. [107] inner random number generator (iZG) according to one of the preceding claims relating to an inner random number generator (iZG), further comprising an entropy module (WD) which is arranged to analyse the random signal of the random bit stream of the entropy extraction after the extraction from the entropy source output signal of the entropy source (EQ) and to evaluate its entropy. [108] inner random number generator (iZG) according to one of the preceding claims relating to an inner random number generator (iZG), wherein the vertical entropy source (EQ), in particular with vertically arranged photon source (120) and photodetector (130) relative to the horizontal surface (O) of the substrate, is implemented in a microintegrated circuit in order to optimize the performance of the inner random number generator (iZG). [109] Internal random number generator (iZG) according to one of the preceding claims relating to an internal random number generator (iZG), further comprising a memory module and / or a memory (MEM) for storing the generated random bits and / or random numbers. [110] internal random number generator (iZG) according to the preceding claim, wherein the memory module and / or the memory (MEM) are or comprise a volatile or non-volatile memory. [111] inner random number generator (iZG) according to the preceding claim, wherein the inner random number generator (iZG) is arranged for diagnosis and self-calibration of device parts of the random number generation device of the inner random number generator (iZG). [112] Use of the inner random number generator (iZG) according to one of the preceding claims relating to an inner random number generator (iZG) in a VPN system, in particular for secure key generation and key management for encrypted VPN connections, or in IoT networks, in particular to ensure the integrity and confidentiality of communication between IoT devices, or in cloud computing environments, in particular for secure data processing and storage in cloud environments, or in financial transaction systems, in particular for the secure execution and verification of financial transactions, or in communication systems, in particular for the secure transmission of messages and data in communication networks, or in conjunction with a microcontroller (MCU), in particular to enable secure key generation and management, or in conjunction with a CPU in an embedded system, in particular to ensure secure encryption and data transmission, or in conjunction with a sensor evaluation and control circuit, in particular to ensure the integrity and confidentiality of the sensor data, or in connection with a network node in a wired or wireless network, in particular to increase the security of the communication protocols, or in conjunction with a chip card, in particular to enable secure authentication and data processing on the card, or in a network node in an IoT network, in particular to ensure secure communication between the IoT devices, or in a cloud computing system, in particular to enable the encryption and secure storage of data in the cloud, or in a financial transaction system, in particular to ensure the security and confidentiality of transactions, or in a communications system, in particular to enable the secure transmission of messages and data, or in a portable device, in particular in a smartphone or a telephone or the like, in particular to implement secure and energy-efficient encryption, or in one or more sensors in a sensor network, in particular to ensure the authentication and integrity of the sensor data, or in a vehicle control system and / or a vehicle network, in particular to ensure secure communication between the control units and / or with device parts of the vehicle, or in a weapon control system and / or a network within a weapon system, in particular to ensure secure communication between the device components of the weapon system, or in a military equipment system for soldiers, in particular to ensure secure communication between the device components of the military equipment system and / or between the military equipment systems of different soldiers and / or between the military equipment systems of one or more soldiers on the one hand and one or more weapon systems and / or military networks on the other hand, or in a medical device, in particular to protect the confidentiality of patient data and patient measurement values ​​from patient sensors and to ensure safety, or in an industrial automation system in a production process, in particular to ensure the security of control commands and data against attacks, or in a smart home system, in particular to ensure the security of the control and communication of smart home devices in a property or a fixed installation and / or in an infrastructure object, or in an infrastructure system, in particular to ensure the safety of the control and communication of the components of the infrastructure system (gas supply, drinking water supply, wastewater supply, electricity supply, district heating supply, etc.), or in a microprocessor, in particular comprising an ALU (Arithmetic Logic Unit), an internal microprocessor data bus, a control unit and registers, in particular to generate random numbers for cryptographic operations directly in the processor, or in an FPGA (Field-Programmable Gate Array), comprising in particular - configurable logic circuits and / or - configurable logic blocks and / or - configurable lookup tables and / or - configurable and / or programmable connections and - in particular voltage regulators and / or in particular voltage converters and / or in particular data interfaces - to enable, in particular, configurable cryptographic functions in the FPGA and / or other uses of random bits and / or random numbers in the FPGA, in particular in real time, or in a DSP (Digital Signal Processor), comprising in particular specialised MAC units (Multiply-Accumulate Units) and pipeline architectures, in particular to enable secure signal processing in safety-critical applications, or in an ASIC (Application-Specific Integrated Circuit) and / or a CMOS or BiCMOS or bipolar circuit, comprising in particular specialised circuits for cryptographic functions, in particular to integrate dedicated, high-performance cryptographic functions, or in a SoC (System-on-Chip) architecture, comprising in particular a microprocessor, one or more memories and one or more peripheral modules and a data bus on a single micro-integrated chip, in particular to create a compact and efficient solution for embedded systems, or in a GPU (Graphics Processing Unit), in particular comprising shader cores, texture units and memory controllers, in particular to execute cryptographic calculations in parallel with graphics processing and / or in particular to execute computer and / or machine-implemented AI methods, or in a network processor, comprising in particular packet processing units and protocol engines, in particular to support secure data transmissions and protocol processing, or in a security chip for smart cards, comprising in particular a cryptographic processing unit and secure memory areas, in particular to enable secure authentication and encryption operations, or in a TPM (Trusted Platform Module), comprising in particular a cryptographic co-processor unit and a secure memory, in particular to support secure storage and authentication processes in computer platforms, or in an IoT processor, comprising in particular integrated radio modules and / or energy management units and / or sensor interfaces, in order to ensure in particular the integrity and confidentiality of communication in networked devices and the measured values, or in a control chip for industrial control systems, comprising in particular specialised interfaces for industrial protocols and real-time controllers, in particular to ensure secure control commands and / or data processing, or in a communications processor for mobile devices, comprising in particular baseband processors, modem units and signal coding units, in particular to ensure the security of voice and / or data transmissions, or. in a wearable processor or a piece of clothing or accessory that includes a processor - here called a wearable processor - in particular comprising energy efficiency modules, wireless communication interfaces and integrated sensors, in particular to enable secure data processing and communication in wearable devices and / or in smart clothing, or in a memory controller, comprising in particular memory management units, cache controllers and memory bus interfaces, in particular to ensure the encryption of data in memory modules, or in an automotive processor, in particular comprising CAN bus interfaces and / or other automotive data bus interfaces, such as LIN bus interfaces, security modules and real-time controllers, in particular to ensure secure communication and control in vehicle networks, or in a control chip for medical devices, in particular comprising integrated signal processing units, communication interfaces and security modules, in particular to ensure the confidentiality and integrity of patient data and / or patient measurement data, or in a control chip for drones and / or unmanned vehicles, floating bodies, missiles or satellites, in particular comprising integrated flight and / or motion control units, communication modules and sensor interfaces, in particular to ensure secure communication and control commands between the drone and the control unit, or in a processor for computer-implemented virtual machines, in particular comprising virtualization and memory management units, in particular to enable the secure execution of virtual instances on a host system, or in one or more processors of a processor system for executing computer-implemented models of virtual processors, in particular comprising virtualization and memory management units, in particular to enable the secure execution of virtual instances on a host system, or in a cryptocurrency mining chip, in particular comprising specialised hashing engines, power supply management and memory controllers, in particular to ensure the generation and verification of cryptographic hashes, or a processor for edge computing, in particular comprising specialised network modules, data processing units and memory controllers, in particular to enable secure and decentralised data processing at the network edges, or in a processor for distributed ledger technologies (blockchain), in particular comprising specialized encryption units, memory management and network interfaces, in particular to ensure the security and integrity of distributed transactions.

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