PIXEL CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME

Abstract

A pixel circuit includes: a compensation circuit (10) connected to a data line (DL), a first gate line (GL1), and a second gate line (GL2), and configured to alternately receive first and second voltages via the data line (DL), a first gate signal via the first gate line (GL1), and a second gate signal via the second gate line (GL2); a light-emitting element (EL); a driving element (DT) including a gate electrode configured to receive the second voltage via the compensation circuit (10), the driving element (DT) being configured to generate a current to drive the light-emitting element (EL);and a switching element (ST) including a gate electrode configured to receive the second gate signal via the compensation circuit (10) and configured to switch a current path between the driving element (DT) and the light-emitting element (EL). The light-emitting element (EL), the driving element (DT), and the switching element (ST) may be connected in series between a first power line and a second power line.

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority and privilege to Korean Patent Application No. 10-2023-0192176, filed on December 27, 2023. BACKGROUND area

[0002] The present disclosure relates to a pixel circuit and a display device including the same. Description of the related art

[0003] Electroluminescent display devices are roughly divided into inorganic light-emitting display devices and organic light-emitting display devices based on the material of the emission layer. An active matrix type organic light-emitting display device contains an organic light-emitting diode (hereinafter referred to as "OLED") that emits light itself and has the advantages of fast response speed and high luminous efficiency, brightness, and a wide viewing angle. In the organic light-emitting display device, the OLED is formed on each of the pixels. The organic light-emitting display device has a fast response time and excellent luminous efficiency, luminosity, and an excellent viewing angle. It also has an excellent contrast ratio and color reproduction, being able to display black grayscale to full black.

[0004] In recent years, thanks to advances in technology that allows flexible bending or folding, display devices are approaching the implementation of next-generation displays such as rollable displays, foldable displays, bendable displays, sliding displays, and stretchable displays. Such flexible displays can be used not only for mobile devices such as smartphones and tablet PCs, but also for televisions, vehicles, wearable devices, and so on, and their application areas are becoming increasingly broad.

[0005] A stretchable display device can enlarge or reduce the screen size and can be freely changed into a variety of shapes. To improve the performance of a stretchable display, a pixel circuit that operates stably even when a display panel is deformed and the display panel has a high degree of stretch is required. SUMMARY

[0006] Accordingly, the present disclosure is directed to a pixel circuit and a display device incorporating the same that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.

[0007] The present disclosure provides a highly reliable pixel circuit suitable for a stretchable display device and a display device including this pixel circuit.

[0008] The objects of the present disclosure are not limited to the objects described above, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

[0009] To achieve these objects and other advantages of the present disclosure, as embodied and generally described herein, a pixel circuit may include: a compensation circuit connected to a data line, a first gate line, and a second gate line, the compensation circuit configured to alternately receive a first and a second voltage via the data line, a first gate signal via the first gate line, and a second gate signal via the second gate line; a light-emitting element; a driving element including a gate electrode configured to receive the second voltage via the compensation circuit, the driving element configured to generate a current to drive the light-emitting element based on the second voltage;and a switching element including a gate electrode configured to receive the second gate signal via the compensation circuit, wherein the switching element is configured to switch a current path between the driving element and the light-emitting element based on the second gate signal. The light-emitting element, the driving element, and the switching element may be connected in series between a first power line and a second power line.

[0010] In some embodiments, the compensation circuit may include: a capacitor connected between a first node and a second node; a first switching element connected between the data line and the first node and configured to turn on in response to a gate-on voltage of the first gate signal to electrically connect the data line to the first node; a second switching element connected between the second node and a third node and configured to turn on in response to the gate-on voltage of the first gate signal to electrically connect the second node to the third node; a third switching element connected to the first node and configured to turn on in response to a gate-on voltage of the second gate signal to apply the first voltage to the first node; and a fifth switching element,connected to a fourth node and configured to turn on in response to the gate-on voltage of the first gate signal to apply the first voltage to the fourth node. The switching element may include a fourth switching element connected between the third node and the fourth node and configured to turn on in response to the gate-on voltage of the second gate signal to electrically connect the third node to the fourth node. The driving element may include a gate electrode connected to the second node, a first electrode connected to the first power line and configured to receive a pixel driving voltage, and a second electrode connected to the third node. The light-emitting element may include an anode electrode connected to the fourth node and a cathode electrode,connected to the second power line and configured to receive a cathode voltage. The first voltage may be a reference voltage or the cathode voltage, and the second voltage is a data voltage of pixel data. The data line may be configured to receive the data voltage of the pixel data after receiving the reference voltage or the cathode voltage.

[0011] In some embodiments, the first node may be configured to receive the reference voltage simultaneously via the data line and the first switching element and via the third switching element during a horizontal period.

[0012] In some embodiments, the second node, the third node, and the fourth node are configured to receive the reference voltage when the reference voltage is applied to the first node.

[0013] In some embodiments, a drive period of the pixel circuit may include a first phase in which the pixel circuit is configured to be initialized, a second phase in which the capacitor is configured to receive a threshold voltage of the drive element and the data voltage, and a third phase in which the light-emitting element is configured to emit light. The first gate signal may be configured to be at the gate-on voltage in the first phase and the second phase, and at the gate-off voltage in the third phase. The second gate signal may be configured to be at the gate-off voltage in the second phase, and at the gate-on voltage in the first and third phases.The first, second, and fifth switching elements are configured to turn on in response to the gate-on voltage of the first gate signal and to turn off in response to the gate-off voltage of the first gate signal. The third and fourth switching elements may be configured to turn on in response to the gate-on voltage of the second gate signal and to turn off in response to the gate-off voltage of the second gate signal. The one horizontal period may include first-phase and second-phase periods. The data line may be configured to be at the reference voltage in the first phase and at the data voltage in the second phase.

[0014] In some embodiments, the first switching element may include a gate electrode configured to receive the first gate signal, a first electrode connected to the data line, and a second electrode connected to the first node. The second switching element may include a gate electrode configured to receive the first gate signal, a first electrode connected to the second node, and a second electrode connected to the third node. The third switching element may include a gate electrode configured to receive the second gate signal, a first electrode connected to the first node, and a second electrode configured to receive the reference voltage.The fourth switching element may include a gate electrode configured to receive the second gate signal, a first electrode connected to the third node, and a second electrode connected to the fourth node. The fifth switching element includes a gate electrode configured to receive the first gate signal, a first electrode configured to receive the reference voltage, and a second electrode connected to the fourth node.

[0015] In some embodiments, the first node may be configured to receive the cathode voltage simultaneously via the data line and the first switching element as well as via the third switching element during a horizontal period.

[0016] In some embodiments, the second node, the third node, and the fourth node may be configured to receive the cathode voltage when the cathode voltage is applied to the first node.

[0017] In some embodiments, a drive period of the pixel circuit may include a first phase in which the pixel circuit is configured to be initialized, a second phase in which the capacitor is configured to receive a threshold voltage of the drive element and the data voltage, and a third phase in which the light-emitting element is configured to emit light. The first gate signal may be configured to be at the gate-on voltage in the first phase and the second phase, and at the gate-off voltage in the third phase. The second gate signal may be configured to be at the gate-off voltage in the second phase and at the gate-on voltage in the first and third phases.The first, second, and fifth switching elements may be configured to turn on in response to the gate-on voltage of the first gate signal and to turn off in response to the gate-off voltage of the first gate signal. The third and fourth switching elements may be configured to turn on in response to the gate-on voltage of the second gate signal and to turn off in response to the gate-off voltage of the second gate signal. The one horizontal period may include first-phase and second-phase periods. The data line may be configured to be at the cathode voltage in the first phase and at the data voltage in the second phase.

[0018] In some embodiments, the first switching element may include a gate electrode configured to receive the first gate signal, a first electrode connected to the data line, and a second electrode connected to the first node. The second switching element may include a gate electrode configured to receive the first gate signal, a first electrode connected to the second node, and a second electrode connected to the third node. The third switching element may include a gate electrode configured to receive the second gate signal, a first electrode connected to the first node, and a second electrode configured to receive the cathode voltage.The fourth switching element may include a gate electrode configured to receive the second gate signal, a first electrode connected to the third node, and a second electrode connected to the fourth node. The fifth switching element may include a gate electrode configured to receive the first gate signal, a first electrode configured to receive the cathode voltage, and a second electrode connected to the fourth node.

[0019] In some embodiments, the first voltage may be a constant voltage, wherein the first voltage is a reference voltage or a cathode voltage. The second voltage may be a data voltage corresponding to the pixel data. During a horizontal period, the compensation circuit may be further configured to receive the first voltage via the data line and then receive the second voltage via the data line.

[0020] In some embodiments, the one horizontal period may include a horizontal idle period and a horizontal active period. During the horizontal idle period, the compensation circuit may be further configured to receive the first voltage, rather than the second voltage, via the data line to initialize the pixel circuit. During the horizontal active period, the compensation circuit may be further configured to receive the second voltage via the data line to write the pixel data to the pixel circuit.

[0021] In some embodiments, the one horizontal period may include a horizontal idle period and a horizontal active period. During the horizontal idle period, the first gate signal and the second gate signal may be at a gate-on voltage. During the active horizontal period, the first gate signal may be at the gate-on voltage and the second gate signal may be at a gate-off voltage.

[0022] In another aspect of the present disclosure, a display device may include: a display panel including a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of pixel circuits, wherein at least one of the pixel circuits is the pixel circuit described above; a data driver configured to output the first and second voltages; a gate driver configured to supply at least one gate signal to the gate lines; and a control circuit configured to control the data driver and the gate driver.The plurality of data lines may include the data line described above, the plurality of gate lines may include the first gate line and second gate line described above, the at least one gate signal may include the first gate signal and second gate signal described above, and the plurality of power lines may include the first power line and second power line described above.

[0023] In some embodiments, the compensation circuit includes a capacitor connected between a first node and a second node, a first switching element connected between the data line and the first node and configured to turn on in response to a gate-on voltage of the first gate signal to electrically connect the data line to the first node, a second switching element connected between the second node and a third node and configured to turn on in response to the gate-on voltage of the first gate signal to electrically connect the second node to the third node, a third switching element connected to the first node and configured to turn on in response to a gate-on voltage of the second gate signal to apply the first voltage to the first node, and a fifth switching element,which is connected to a fourth node and configured to turn on in response to the gate-on voltage of the first gate signal to apply the first voltage to the fourth node, wherein the switching element includes a fourth switching element connected between the third node and the fourth node and configured to turn on in response to the gate-on voltage of the second gate signal to electrically connect the third node to the fourth node, the driving element includes a gate electrode connected to the second node, a first electrode connected to the first power line and configured to receive a pixel driving voltage, and a second electrode connected to the third node, the light-emitting element includes an anode electrode connected to the fourth node and a cathode electrode,which is connected to the second power line and is configured to receive a cathode voltage. The first voltage contains a reference voltage or the cathode voltage, and the second voltage contains a data voltage of pixel data.

[0024] In some embodiments, the control circuit may be configured to transmit initialization data as a digital signal to the data driver. The data driver may be configured to output the first voltage in response to the initialization data.

[0025] In some embodiments, the control circuit may be configured to update the initialization data every horizontal period. The first voltage may have a voltage level corresponding to the initialization data.

[0026] In some embodiments, the display panel may include: a plurality of circuit portions in which the pixel circuits are arranged; and a plurality of stretchable wires electrically connecting the plurality of circuit portions. The stretchable wires may include the data lines, the gate lines, and the power lines.

[0027] In some embodiments, the display device may further include a switching circuit configured to alternately select one of the first and second voltages and supply the selected first or second voltage to the data lines.

[0028] In some embodiments, the switching circuit may be further configured to select and supply the first voltage to the data line within a horizontal period and then select and supply the second voltage to the data line.

[0029] The pixel circuit according to embodiments of the present disclosure may be able to stably drive the light-emitting element without short-circuiting the data voltage and the initialization voltage during initialization, without being affected by the deviation of the threshold voltage of the driving element and the voltage drop of the source. Furthermore, the pixel circuit according to exemplary embodiments of the present disclosure may perform initialization, threshold voltage sampling, and light emission with relatively few gate signals, thereby reducing the number of wires in the display panel.

[0030] Accordingly, exemplary embodiments of the present disclosure can implement a highly reliable pixel circuit. The elongation of the stretchable display device can be improved by reducing the number of wires that affect elongation in the stretchable display device.

[0031] The advantages and effects according to the present disclosure are not limited to those described above, and additional advantages and effects are included in or can be achieved by the present disclosure.

[0032] Additional features and aspects of the disclosure will be set forth in the description which follows, and in part will be obvious from the description or may be learned by practice of the inventive concepts contained herein. Other features and aspects of the inventive concepts may be realized and attained by the structure particularly pointed out in, or obvious from, the written description, the claims, and the appended drawings.

[0033] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and are intended to provide further explanation of the claimed disclosures. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in this application, illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings: Fig. 1 is a circuit diagram schematically illustrating a pixel circuit according to an exemplary embodiment of the present disclosure; Fig. 2 is a circuit diagram illustrating a pixel circuit according to an exemplary embodiment of the present disclosure; Fig. 3A and Fig. 3B are diagrams showing exemplary methods for driving a pixel circuit; Fig. 4A to 4D are diagrams illustrating exemplary methods for stepping a pixel circuit; Fig. 5 is a circuit diagram illustrating a pixel circuit according to another exemplary embodiment of the present disclosure; Fig. 6A and Fig. 6B are waveform diagrams illustrating exemplary methods for driving a pixel circuit; Fig. 7 is a waveform diagram illustrating an output voltage from a data driver according to an exemplary embodiment of the present disclosure; Fig. 8A and Fig. 8B are diagrams illustrating an exemplary switching circuit connected to a data line; Fig. 9 is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure; Fig. 10A and Fig. 10B are diagrams illustrating other examples of a display device; Fig. 11 is a diagram illustrating an example of circuit parts and stretch wires of a stretchable display device; Fig. 12 is a diagram illustrating a frame period and a horizontal period according to an exemplary embodiment of the present disclosure; Fig. 13 illustrates an exemplary interconnection line between a timing controller and source drive ICs at an EPI interface; Fig. 14 is a waveform diagram illustrating an example of a multi-phase internal clock generated by source drive ICs; Fig. 15 is a waveform diagram illustrating an example of a signal transmission protocol for an EPI interface; Fig. 16 is a diagram illustrating an example of one (1) data packet in an EPI interface; and Fig. Figure 17 is a diagram illustrating an example of a signal transmitted during a horizontal idle period. DETAILED DESCRIPTION

[0035] Advantages and features of the present disclosure, and the methods for carrying them out, will become apparent from the embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0036] The shapes, dimensions, areas, lengths, thicknesses, ratios, angles, numbers, and the like illustrated in the drawings, which describe various embodiments of the present disclosure, are given by way of example only. Therefore, the present disclosure is not limited to such details illustrated in the drawings. Like reference numerals generally refer to like elements throughout the specification unless otherwise noted.

[0037] If a detailed description of a relevant known function or configuration might unnecessarily obscure aspects of the present disclosure, a detailed description of such known function or configuration may be omitted or briefly discussed in the following description.

[0038] When a term such as "comprises," "has," "contains," or "consists of" is used, one or more other elements may be added, unless the term is used with a more restrictive term such as "only." An element described in a singular form may include a plurality of elements, and vice versa, unless the context clearly indicates otherwise.

[0039] When designing an element, it should be assumed that the element contains a normal range of error or tolerance, even if there is no explicit description of such error or tolerance.

[0040] When a positional relationship between two elements is described using a term such as "on", "over", "under", "beside", "connected to", "coupled with", "crossing", "intersecting" or similar, one or more other elements may be located between the two elements unless the term is used with a more restrictive term such as "more immediately" or "more directly".

[0041] If a temporal relationship is described using terms such as “after,” “subsequent,” “adjacent,” “before,” or similar, it may contain a non-consecutive case unless it is used with a restrictive term such as “immediately” or “immediately.”

[0042] Although the terms "first," "second," and the like may be used herein to describe various elements, these elements should not be interpreted as being limited by these terms, as they are not intended to define a particular nature, order, sequence, ranking, or number of such elements. These terms are used only to refer to one element separately from another. For example, a first element could be referred to as a second element, and a second element could similarly be referred to as a first element, without departing from the scope of the present disclosure.

[0043] The features of the various embodiments of the present disclosure may be partially or fully coupled or combined with one another and may be operated, interconnected, or jointly controlled in various ways, as would be readily understood by those skilled in the art. The embodiments of the present disclosure may be practiced independently of one another or jointly and associated with one another.

[0044] A pixel circuit and a gate drive circuit of a display device may include a plurality of transistors. The transistors may be embodied as thin-film transistors (TFTs). The transistors may be implemented as an oxide thin-film transistor (TFT) containing an oxide semiconductor, a low-temperature polysilicon TFT (LTPS TFT) containing a low-temperature polysilicon, and the like.

[0045] A transistor is a three-electrode device containing a gate, a source, and a drain. The source is an electrode that supplies charge carriers to the transistor. In a transistor, charge carriers begin to flow from the source. The drain is an electrode through which charge carriers exit the transistor. In a transistor, charge carriers flow from a source to a drain. Because the charge carriers are electrons, in an n-channel transistor, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. In an n-channel transistor, current flows from the drain to the source. In a p-channel transistor (p-channel metal oxide semiconductor (PMOS)), the source voltage is higher than the drain voltage because the charge carriers are holes, allowing holes to flow from the source to the drain. Since holes flow from the source to the drain in the p-channel transistor, current flows from the source to the drain.It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed according to an applied voltage. Therefore, the present disclosure is not limited to a specific notation of a source and drain of a transistor. In the following description, the source and drain of a transistor may be interchangeably referred to as the first and second electrodes.

[0046] A gate signal fluctuates between a gate-on voltage and a gate-off voltage. A transistor turns on in response to a gate-on voltage and turns off in response to a gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate-high voltage VGH and the gate-off voltage may be a gate-low voltage VGL. In the case of a p-channel transistor, the gate-on voltage may be the gate-low voltage VGL and the gate-off voltage may be the gate-high voltage VGH.

[0047] The pixel circuit according to one or more embodiments of the present disclosure may be initialized to an initialization voltage. The initialization voltage may be either the reference voltage or the cathode voltage.

[0048] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0049] Fig. 1 is a circuit diagram schematically illustrating a pixel circuit according to an embodiment of the present disclosure.

[0050] As in Fig. As shown in Figure 1, a pixel circuit may include a light-emitting element EL, a driving element DT, a switching element ST, and a compensation circuit 10. The switching element ST and the driving element DT may be implemented as p-channel transistors, but are not limited thereto.

[0051] The light-emitting element EL may be a light-emitting element such as, but not limited to, an OLED or a micro-LED. The light-emitting element EL may include an anode electrode, a light-emitting layer, and a cathode electrode. The light-emitting element EL, the drive element DT, and the switching element ST may be connected in series between a VDD node P1, to which a pixel drive voltage VDD is applied, and a VSS node P2, to which a cathode voltage VSS is applied. The VDD node P1 may be connected to a first power line commonly connected to some or all of the pixels on a display panel. The VSS node P2 may be connected to a second power line commonly connected to some or all of the pixels of the display panel.

[0052] The driving element DT can drive the light-emitting element EL by generating a current for driving the light-emitting element EL according to a gate-source voltage.

[0053] The switching element ST can switch the current path between the pixel drive voltage VDD and the cathode voltage VSS in response to a second gate signal EM to regulate the emission time of the light-emitting element EL. The switching element ST can, for example, be a fourth switching element T4 included in the Fig. 2 to 8 is illustrated.

[0054] The compensation circuit 10 may be connected to a data line DL, to which a first voltage V1 and a second voltage V2 are alternately applied, a first gate line GL1, to which a first gate signal SCAN is applied, and a second gate line GL2, to which a second gate signal EM is applied. The first voltage V1 may, for example, be a reference voltage Vref, as shown in the Fig. 2 to 8A, which can be a constant voltage. The reference voltage Vref can be interpreted as an initialization voltage. The second voltage V2 can, for example, be a data voltage Vdata of the Fig. 2 to 8B. The compensation circuit 10 may be connected to a constant voltage node P3 to which a third voltage V3 is applied. The constant voltage node P3 may be connected to a third power line commonly connected to some or all of the pixels of the display panel. The third voltage V3 may be a constant voltage, e.g., the reference voltage Vref or the cathode voltage VSS, as shown in FIGS. Fig. 2 to 8B.

[0055] Compensation circuit 10 may include a plurality of switching elements and capacitors. Compensation circuit 10 may receive the data voltage Vdata of the pixel data, the first gate signal SCAN, and the second gate signal EM, and apply the data voltage Vdata to the gate electrode of the drive element DT. Furthermore, compensation circuit 10 may control the switching element ST by applying the second gate signal EM to the gate electrode of the switching element ST.

[0056] Fig. 2 is a circuit diagram illustrating a pixel circuit according to an exemplary embodiment of the present disclosure.

[0057] As in Fig. As illustrated in Figure 2, the pixel circuit according to an exemplary embodiment of the present disclosure may include a light-emitting element EL, a compensation circuit 10, a fourth switching element T4, a driving element DT, and a capacitor Cst. The compensation circuit may include a plurality of switching elements T1, T2, T3, T5, and a capacitor Cst. The switching elements T1 to T5 and the driving element DT may be implemented as, but are not limited to, p-channel transistors.

[0058] The pixel circuit can be supplied with a data voltage Vdata and the gate signals SCAN and EM. The gate signals SCAN and EM can contain pulses that oscillate between a gate-on voltage VGL and a gate-off voltage VGH. First, second, and fifth switching elements T1, T2, and T5 can be turned on and off depending on the voltage of the first gate signal SCAN. Third and fourth switching elements T3 and T4 can turn on and off in response to the voltage of the second gate signal EM.

[0059] A constant voltage (or a DC voltage) may be applied to the pixel circuit, e.g., a pixel drive voltage VDD, a cathode voltage VSS, a reference voltage Vref, or the like. The reference voltage Vref may be interpreted as an initialization voltage. The constant voltages applied to the pixel circuit may be set to VDD > Vref > VSS, but the present disclosure is not limited thereto. The gate-off voltage VGH may be set to a voltage lower than the pixel drive voltage VDD and lower than the maximum voltage of the data voltage Vdata, but is not limited thereto. The gate-on voltage VGL may be set to a voltage lower than the minimum voltage of the cathode voltage VSS and the data voltage Vdata, but is not limited thereto.The data voltage Vdata has a dynamic range (DR) between a voltage equal to or higher than the cathode voltage VSS and a voltage lower than the pixel drive voltage VDD. The reference voltage Vref can be set to a specific voltage within a range of the data voltage. For example, a voltage applied to the pixel circuit can be set as follows: VDD = 12V, VSS = 0V, Vref = 2V, VGH = 10V, VGL = -10V, Vdata = 0V to 9V, and the like, but is not limited to this.

[0060] The light-emitting element EL can be embodied as a light-emitting element such as an OLED, an inorganic LED such as a microLED, or the like. The OLED can include an organic compound layer formed between an anode electrode and a cathode electrode. The organic compound layer can include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode electrode of the light-emitting element EL can be connected to a fourth node D. The cathode electrode of the OLED can be connected to a VSS node (or a second power node) P2, to which the cathode voltage VSS is applied.The micro-LED can, among other things, have a vertical structure in which the electrodes are arranged above and below a semiconductor chip in which the light-emitting element EL is integrated. The semiconductor chip in which the light-emitting element EL is integrated can, for example, be implemented in a lateral structure or a flip-chip structure.

[0061] The drive element DT can drive the light-emitting element EL by supplying a current generated according to the gate-source voltage Vgs to the light-emitting element EL. The drive element DT can include a gate electrode connected to a second node B, a first electrode connected to the VDD node P1 to which the pixel drive voltage VDD is applied, and a second electrode connected to a third node C.

[0062] The capacitor Cst may be connected between a first node A and the second node B. The first node A may be connected to a second electrode of the first switching element T1, a first electrode of the third switching element T3, and a first electrode of the capacitor Cst. The second node B may be connected to a second electrode of the capacitor Cst, a gate electrode of the driving element DT, and a first electrode of the second switching element T2. The capacitor Cst may be charged with a data voltage Vdata compensated by an amount equal to a threshold voltage Vth of the driving element DT. Since the data voltage Vdata at each of the sub-pixels can be compensated by the threshold voltage Vth of the driving element DT, characteristic variations of the driving element in each of the sub-pixels can be compensated to be driven with uniform driving characteristics.

[0063] The switching elements T1 to T5 can turn on according to the gate-on voltage VGL applied to their gate electrodes and turn off according to the gate-off voltage VGH.

[0064] A first switching element T1 may turn on in response to the gate-on voltage VGL of the first gate signal SCAN. When the first switching element T1 is turned on, the data voltage Vdata may be applied to the first node A. The first switching element T1 may include a gate electrode connected to a first gate line GL1 to which the first gate signal SCAN is applied, a first electrode connected to the data line DL, and a second electrode connected to the first node A. The first gate signal SCAN may be generated as a pulse of the gate-on voltage VGL. The pulse width of the first gate signal SCAN may be set to approximately one horizontal period (1H).

[0065] A second switching element T2 may turn on in response to the gate-on voltage VGL of the first gate signal SCAN. When the second switching element T2 is turned on, the second node B and the third node C may be electrically connected so that the driving element DT is driven as a diode. The second switching element T2 may include a gate electrode connected to the first gate line GL1, a first electrode connected to the second node B, and a second electrode connected to the third node C.

[0066] A third switching element T3 may turn on in response to the gate-on voltage VGL of the second gate signal EM. When the third switching element T3 is turned on, the reference voltage Vref may be applied to the first node A. The third switching element T3 may include a gate electrode connected to a second gate line GL2 to which the second gate signal EM is applied, a first electrode connected to the first node A, and a second electrode connected to a Vref node P3.

[0067] A fourth switching element T4 may turn on in response to the gate-on voltage VGL of the second gate signal EM. When the fourth switching element T4 is turned on, the third node C may be electrically connected to the fourth node D. The fourth switching element T4 may include a gate electrode connected to the second gate line GL2, a first electrode connected to the third node C, and a second electrode connected to the fourth node D.

[0068] A fifth switching element T5 may turn on in response to the gate-on voltage VGL of the first gate signal SCAN. When the fifth switching element T5 is turned on, the reference voltage Vref may be applied to the fourth node D. The fifth switching element T5 may include a gate electrode connected to the first gate line GL1, a first electrode connected to the Vref node P3, and a second electrode connected to the fourth node D.

[0069] A control period of Fig. The example pixel circuit shown in Figure 2 can be divided into a first phase (or initialization phase, INI), in which the pixel circuit is initialized, a second phase (or sampling phase, SAM), in which the pixel data is written into the pixel circuit and a threshold voltage Vth of the driving element DT is sampled, and a third phase (or emission phase, EMI), in which the light-emitting element EL is driven, as shown, for example, in Fig. 3A and Fig. 3B. One (1) horizontal period (1H) can be divided into a first phase INI1 / INI2 and a second phase SAM. The respective durations of the first phase INI1 / INI2 and the second phase SAM can be appropriately selected based on the results of reliability experiments of the pixel circuit. For example, without limitation, the first phase INI1 and the second phase SAM can be set to half a horizontal duration, as shown in Fig. 3A, or the second phase SAM can be set to a longer duration compared to the first phase INI2, as shown in Fig. 3B. A hold phase HOLD can be set between the second phase SAM and the third phase EMI, but the hold phase can also be omitted.

[0070] As in Fig. 3A and Fig. As shown in Figure 3B, a voltage of the first gate signal SCAN may be the gate-on voltage VGL in the first and second phases INI1 / INI2 and SAM, and the gate-off voltage VGH in the third phase EMI. A voltage of the second gate signal EM may be the gate-off voltage VGH in the second phase SAM, and the gate-on voltage VGL in the first and third phases INI1 / INI2 and EMI. During the hold phase HOLD, the voltage of the first and second gate signals SCAN and EM may be the gate-off voltage VGH.

[0071] A voltage on the data line DL can combine the reference voltage Vref in the first phase INI1 / INI2 and the data voltage Vdata in the second phase SAM for one horizontal period (1H). By repeating the first phase INI1 / INI2 and the second phase SAM in each horizontal period, the data voltage Vdata corresponding to the pixel data value can be supplied to the data line in each pixel row.

[0072] Fig. Figure 4A is a circuit diagram illustrating the current flow of the example pixel circuit and the voltages of the main nodes in the first phase INI1 / INI2.

[0073] As in Fig. 3A, Fig. 3B and Fig. As shown in Figure 4A, in the first phase INI1 / INI2, the voltage of the first and second gate signals SCAN and EM may be the gate-on voltage VGL. Therefore, in the first phase INI1 / INI2, the second to fifth switching elements T2 to T5 and the drive element DT may be turned on to initialize the first to fourth nodes A to D and the capacitor Cst.

[0074] In the first phase INI1 / INI2, the reference voltage Vref can be applied to the data line DL. In the first phase INI1 / INI2, the voltage of the first to fourth nodes A, B, C, and D can be the reference voltage Vref. In this case, the data line DL and the Vref node P3 can be short-circuited, and the capacitor Cst can be initialized to 0 V because the voltages of the first and second nodes A and B are equal to the reference voltage Vref.

[0075] The light-emitting element EL may be in the off state in the first phase INI1 / INI2 because the voltage difference between the reference voltage Vref and the cathode voltage VSS may be lower than the threshold voltage of the light-emitting element EL in the first phase INI1 / INI2.

[0076] Meanwhile, when the data voltage Vdata of the pixel data is applied to the data line DL in the first phase INI1 / INI2, the data voltage Vdata and the reference voltage Vref at the first node A may be short-circuited, and thus the capacitor Cst may be unstably initialized. In the present disclosure, the reference voltage Vref may be applied to the data line DL in the first phase INI1 / INI2, so that the reference voltage Vref is applied to the capacitor Cst, thereby initializing the voltage of the capacitor Cst to 0 V equally in all pixels.

[0077] Fig. Figure 4B is a circuit diagram illustrating current flow of the exemplary pixel circuit and the voltages of the main nodes in the second phase SAM.

[0078] As in Fig. 3A, Fig. 3B and Fig. As shown in Figure 4B, in the second phase SAM, the threshold voltage Vth of the drive element DT and the data voltage Vdata of the pixel data may be applied to the capacitor Cst. In the second phase SAM, the pixel data may be written to the pixel circuit, the threshold voltage Vth of the drive element DT may be sampled, and the data voltage Vdata compensated by the drive voltage Vth may be stored in the capacitor Cst.

[0079] In the second phase SAM, the data voltage Vdata of the pixel data may be applied to the data line DL, and the voltage of the first gate signal SCAN may be the gate-on voltage VGL. The voltage of the second gate signal EM may be the gate-off voltage VGH. Therefore, in the second phase SAM, the first, second, and fifth switching elements T1, T2, and T5 may be turned on, while the third and fourth switching elements T3 and T4 are turned off.

[0080] At the end of the second phase SAM, the voltage of the first node A may be the data voltage Vdata of the pixel data, and the voltage of the third node B may be a voltage of VDD - Vth. Where "Vth" is the threshold voltage of the drive element DT. In the second phase SAM, the voltage of the third node C may be VDD.

[0081] A HOLD phase can be set between the second SAM phase and the third EMI phase. During the HOLD phase, the voltage of the gate signals SCAN and EM can correspond to the gate-off voltage VGH. Since the first to fifth switching elements T1 to T5 are turned off in this case, the first, second, and fourth nodes A, B, and D can be set to the floating state to maintain their respective voltages from the previous step. This is, for example, Fig. 4C illustrates.

[0082] Fig. Figure 4D is a circuit diagram illustrating the current flow of the pixel circuit and the voltages of the key nodes in the third phase of EMI.

[0083] As in Fig. 3A, Fig. 3B and Fig. As shown in Figure 4D, in the third phase EMI, the voltage of the first gate signal SCAN may be the gate off voltage VGH, and the voltage of the second gate signal EM may be the gate on voltage VGL. Therefore, in the third phase EMI, the first, second, and fifth switching elements T1, T2, and T5 may be turned off, while the third and fourth switching elements T3 and T4 may be turned on.

[0084] In the third phase of EMI, the reference voltage Vref can be applied to the first node A, and thus the data voltage Vdata can be transferred to the second node B through coupling with the capacitor. In this case, the voltage of the first node A can be a voltage of (Vref - Vth), and the voltage of the second node B can be a voltage of VDD - Vth + (Vref - Vdata). In the third phase EMI, the light-emitting element EL can emit light in response to a current from the driving element DT. In the third phase EMI, the current (I) flowing through the light-emitting element EL can be represented as I=k(VDD−(VDD−Vth+(Vref−Vdata))−Vth)2=k(Vdata−Vref)2.

[0085] Where k is a constant value. Therefore, the light-emitting element EL can emit light with a luminance corresponding to a luminance value (or a grayscale value) of the pixel data without being affected by the deviation of the threshold voltage Vth of the driving element DT and the deviation of the constant voltages VDD, VSS, and Vref in the third phase EMI.

[0086] Fig. 5 is a circuit diagram illustrating a pixel circuit according to another embodiment of the present disclosure. In Fig. 5 are the components which are essentially the same as in the example of Fig. 2, are provided with the same reference numerals, and a detailed description thereof can be omitted. Fig. 6A and Fig. 6B are connected to the Fig. The exemplary pixel circuit shown in Figure 5 is applied.

[0087] As in Fig. 5, Fig. 6A and Fig. 6B, the third to fifth switching elements T3, T4 and T5 can initialize the first to fourth nodes A, B, C and D and the capacitor Cst with the cathode voltage VSS. Therefore, the Fig. 5 shown example pixel circuit does not have a power line that is connected to the Fig. 2 is connected to the Vref node P3.

[0088] The third and fourth switching elements T3 and T4 may turn on in response to the gate-on voltage VGL of the second gate signal EM in the first and third phases INI1 / INI2 and EMI. The third switching element T3 may turn off in response to the gate-off voltage VGL of the second gate signal EM in the second phase SAM and the HOLD period. The third switching element T3 may include a gate electrode connected to the second gate line GL2 to which the second gate signal EM is applied, a first electrode connected to the first node A, and a second electrode connected to the VSS node P2. The fourth switching element T4 may include a gate electrode connected to the second gate line GL2, a first electrode connected to the third node C, and a second electrode connected to the fourth node D.

[0089] The fifth switching element T5 can turn on in response to the gate-on voltage VGL of the first gate signal SCAN in the first and second phases INI1 / INI2 and SAM. The fifth switching element T5 can turn off in response to the gate-off voltage VGH of the first gate signal SCAN in the hold phase HOLD and the third phase EMI. The fifth switching element T5 can include a gate electrode connected to the first gate line GL1 to which the first gate signal SCAN is applied, a first electrode connected to the VSS node P2, and a second electrode connected to the fourth node D.

[0090] In the first phase INI1 / INI2, a voltage of the first and second gate signals SCAN and EM may be the gate-on voltage VGL. Therefore, in the first phase INI1 / INI2, the second to fifth switching elements T2 to T5 and the drive element DT may turn on to initialize the first to fourth nodes A to D and the capacitor Cst.

[0091] In the first phase INI1 / INI2 of the Fig. In the example pixel circuit shown in Figure 5, the cathode voltage VSS can be applied to the data line DL. In the first phase INI1 / INI2, the respective voltages of the first to fourth nodes A, B, C, and D can be initialized to the cathode voltage VSS.

[0092] The light-emitting element EL may be in the off state in the first phase INI1 / INI2 because the voltage difference between the reference voltage Vref and the cathode voltage VSS may be lower than the threshold voltage of the light-emitting element EL in the first phase INI1 / INI2. In the first phase INI1 / INI2 of the Fig. In the example pixel circuit shown in Figure 5, the cathode voltage VSS can be applied to the data line DL, and thus the cathode voltage VSS can be applied via the capacitor Cst.

[0093] As apparent from the above embodiments of the present disclosure, in the first phase INI1 / INI2 in which the pixel circuit is initialized according to an exemplary embodiment of the present disclosure, the reference voltage Vref may be applied to the first node A via the data line DL and the first switching element T1 and simultaneously via the third switching element T3, or the cathode voltage VSS may be applied to the first node A via the data line DL and the first switching element T1 and simultaneously via the third switching element T3. Therefore, the same initialization voltage (either Vref or VSS) may be applied to the first node A via two paths when the pixel circuit is initialized.

[0094] As in Fig. 6A and Fig. As shown in Figure 6B, the voltage of the first gate signal SCAN may be the gate-on voltage VGL in the first and second phases INI1 / INI2 and SAM, and the gate-off voltage VGH in the third phase EMI. A voltage of the second gate signal EM may be the gate-off voltage VGH in the second phase SAM, and the gate-on voltage VGL in the first and third phases INI1 / INI2 and EMI. During the hold phase HOLD, the respective voltages of the first and second gate signals SCAN and EM may be the gate-off voltage VGH.

[0095] A voltage on the data line DL may combine the cathode voltage VSS in the first phase INI1 / INI2 and the data voltage Vdata in the second phase SAM for one horizontal period (1H). By repeating the first phase INI1 / INI2 and the second phase SAM in each horizontal period, the data voltage Vdata corresponding to the pixel data value can be supplied to the data line in each pixel row.

[0096] Fig. 7 is a waveform diagram illustrating an output voltage from a data driver according to an exemplary embodiment of the present disclosure.

[0097] As in Fig. As illustrated in Figure 7, in each horizontal period, the data driver may supply the initialization voltage Vref / VSS for the pixel circuit to the data line DL, followed by the data voltage Vdata to the data line.

[0098] The data driver can output the initialization voltage Vref / VSS and the data voltage Vdata to the data line DL in synchronization with a timing signal having a cycle of one horizontal period, such as a source output enable signal SOE. The data driver can output the initialization voltage Vref / VSS in response to a logic high (H) voltage of the source output enable signal SOE and can output the data voltage Vdata in response to a logic low (L) voltage of the source output enable signal SOE. The timing signal having a cycle of one horizontal period is not limited to the source output enable signal SOE.

[0099] Fig. 8A and Fig. 8B are diagrams illustrating an example switching circuit connected to a data line.

[0100] As in Fig. 8A and Fig. As shown in Figure 8B, a switching circuit SW may be connected to the data line DL. The switching circuit SW may output the initialization voltage Vref / VSS followed by the data voltage Vdata. The initialization voltage Vref / VSS applied to the data line DL via the switching circuit SW may be the same voltage as the reference voltage Vref (or the cathode voltage VSS) applied to the pixel circuit, or it may be set to a voltage appropriately adjusted taking into account the characteristics of the display panel. The switching circuit SW may, but is not limited to, operate in cycles such as one horizontal period, one-half horizontal period, one-third horizontal period, and one-quarter horizontal period in synchronization with a timing signal generated in the timing controller or the data driver.

[0101] The switching circuits SW can be arranged on each data output channel of an integrated circuit (IC) in which the data driver is integrated. The switching circuit SW can be arranged outside the data driver. For example, the switching circuit SW can be arranged in a non-display area of the display panel. The switching circuit SW can alternately select the initialization voltage Vref / VSS and the data voltage Vdata to supply the same to the data line DL. Within a horizontal period after the initialization voltage Vref / VSS is applied to the data lines DL via the switching circuit SW, the data voltage Vdata can be applied to the data lines DL.

[0102] Fig. 9 is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure. Fig. 10A and Fig. 10B are diagrams illustrating other examples of the display device.

[0103] As in Fig. 9 to 10B, a display device according to exemplary embodiments of the present disclosure may include a display panel 100, a display panel driving circuit for writing pixel data to the pixels 101 of the display panel 100, and a power supply 140 for generating power to drive the pixels 101 and the display panel driving circuit.

[0104] A substrate of the display panel 100 may be, but is not limited to, a plastic substrate, a thin glass substrate, or a metal substrate. For a stretchable display device, the substrate of the display panel may be made of a stretchable insulating material, e.g., a silicone rubber such as polydimethylsiloxane (PDMS), polyurethane (PU), or an elastomer such as polytetrafluoroethylene (PTFE).

[0105] The display panel 100 may, but need not, be a rectangular-shaped panel having a length along the X-axis (or the first direction), a width along the Y-axis (or the second direction), and a thickness along the Z-axis (or the third direction). For example, at least a portion of the display panel 100 may have a curved perimeter.

[0106] A display area AA of the display panel 100 may include a pixel array for displaying an input image thereon. The pixel array may include a plurality of data lines 102, a plurality of gate lines 103 crossing the data lines 102, and the pixels 101 arranged in a matrix form. The display panel 100 may further include power lines commonly connected to the pixels 101. The power lines may be connected to constant voltage nodes P1, P2, and P3 of the pixel circuits to supply the pixels 101 with constant voltages VDD, VSS, and Vref, respectively, to drive the pixels 101. The power lines may be implemented as long strips of wiring along the first or second direction, or as mesh wiring in which the wiring in the first direction and the wiring in the second direction are electrically connected.The power lines may further include a VGL line and a VGH line connected to a gate driver 120. A gate-on voltage VGL may be applied to the VGL line and a gate-off voltage VGH may be applied to the VGH line.

[0107] Each of the pixels 101 may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color implementation. Each of the pixels may also include a white sub-pixel. Each sub-pixel may include a pixel circuit that drives a light-emitting element. Each of the pixel circuits may be connected to the data lines, the gate lines, and the power lines. Hereinafter, a "pixel" may be understood to have the same meaning as a "sub-pixel." The pixel circuit may be one of the Fig. 1 to 8B.

[0108] The pixels can be arranged as true-color pixels and Pentile pixels. A Pentile pixel can achieve higher resolution than a true-color pixel by driving two subpixels with different colors as a pixel 101 using a preset pixel rendering algorithm. The pixel rendering algorithm can compensate for insufficient color representation in each pixel with the color of the light emitted by its adjacent pixel.

[0109] The pixel array may include a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln may include a row of pixels arranged along the row direction (X-axis direction) in the pixel array of the display panel 100. The pixels arranged in a pixel row may share one or more of the gate lines 103. The sub-pixels arranged in the column direction Y along the data line direction may share the same data line 102. A horizontal period is a time calculated by dividing one frame period by the total number of pixel rows L1 to Ln.

[0110] The display panel 100 can be implemented with a non-transparent or a transmissive display panel. The transmissive display panel can be used for a transparent display device in which an image is displayed on a screen and an actual object is visible in the background. The display panel 100 can be implemented as a flexible display panel.

[0111] The power supply 140 can generate constant voltages (or direct current (DC) voltages) for driving the pixel array and the display panel drive circuit of the display panel 100 using a DC-to-DC converter. The DC-to-DC converter can include a charge pump, a regulator, a buck converter, a boost converter, and the like. The power supply 140 can output constant voltages, such as a gamma reference voltage, a gate-on voltage VGL, a gate-off voltage VGH, a pixel drive voltage VDD, a cathode voltage VSS, a reference voltage Vref, etc., by adjusting the level of a DC input voltage applied by a host system 200. The gamma reference voltage can be supplied to the data driver 110. A dynamic range of the data voltage output from the data driver 110 may be determined by a voltage range of the gamma reference voltage.The dynamic range of the data voltage can be the range of voltages between the highest gray level voltage and the lowest gray level voltage.

[0112] The gate-on voltage VGL and the gate-off voltage VGH may be supplied to a level shifter 150 and the gate driver 120. The constant voltages, such as the pixel drive voltage VDD, the cathode voltage VSS, and the reference voltage Vref, may be supplied to the pixels 101 via the power lines commonly connected to the pixels 101.

[0113] The pixel drive voltage VDD may be supplied to the display panel 100 from a main power source in the host system 200. In this case, the power supply 140 does not need to output the pixel drive voltage VDD.

[0114] The display panel drive circuit may write the pixel data of the input image to the pixels of the display panel 100 under the control of the timing controller 130. The display panel drive circuit may include the data driver 110 and the gate driver 120.

[0115] The display panel driving circuit may further include a touch sensor driver for driving touch sensors. The touch sensor driver is Fig. 9 to Fig. 10B. The data driver 110 and the touch sensor driver may be integrated into a single driver integrated circuit (IC). In a mobile terminal or a portable terminal, the timing controller 130, the power supply 140, the level shifter 150, the data driver 110, the touch sensor driver, and the like may be integrated into a driver integrated circuit (DIC), such as in the Fig. 10A and Fig. 10B shown.

[0116] The data driver 110 may receive the pixel data of the input image as a digital signal from the timing device 130 and output the data voltage. The data driver 110 may output the data voltages by converting the pixel data of the input image into a gamma compensation voltage using a digital-to-analog converter (DAC). The gamma reference voltage may be divided into the gamma compensation voltage for each gray level by a voltage division circuit in the data driver 110, which is supplied to the DAC. The DAC may generate the data voltages as gamma compensation voltages corresponding to the gray level values of the pixel data. The data voltages output by the DAC may be output from the respective data output channels of the data driver 110 to the data lines 102 via the output buffers.

[0117] Initialization data REF may be provided to data driver 110 as a digital signal from timing controller 130. In this case, data driver 110 may output initialization voltage Vref / VSS in response to initialization data REF. Initialization data REF may indicate the voltage level of initialization voltage Vref / VSS.

[0118] The gate driver 120 may be formed on the display panel 100 together with a TFT array of the pixel array and the wires. The gate driver 120 may be arranged in the non-display area NA of the display panel 100 outside the display area AA, or at least a part of it may be arranged in the display area AA.

[0119] The gate driver 120 may include a plurality of shift registers for sequentially shifting pulses of the gate signals. The gate driver 120 may be arranged in one or both of a left non-display area NA and a right non-display area NA outside the display area AA in the display panel 100 to supply the gate signals to the gate lines 103 in a single supply method. In the single supply method, the gate signals may each be applied to one end of the gate lines. The gate driver 120 may be arranged in both the left non-display area NA and the right non-display area NA of the display panel 100 to apply the gate signals to the gate lines 103 in a double supply method. In the double supply method, the gate signals are simultaneously applied to both ends of the respective gate lines 103.At least some circuits of the gate driver 120 may be arranged within the display area AA.

[0120] The gate driver 120 may sequentially output pulses of the gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 may sequentially supply the gate signals to the gate lines 103 by shifting the pulses of the gate signals using the shift registers. The gate driver 120 may use a plurality of shift registers to output a plurality of gate signals with different phases, pulse widths, etc. The gate signals may include the first gate signal SCAN and the second gate signal EM, as described above.

[0121] Timing controller 130 may receive from host system 200 the pixel data of the input image and a timing signal synchronized with the pixel data. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since a vertical period and a horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The data enable signal DE may have a cycle of one horizontal period (1H).

[0122] The timing controller 130 may control the data driver 110 and the gate driver 120 by generating signals or timing information to control the operating timing of the data driver 110 and the gate driver 120 based on the timing signals (e.g., Vsync, Hsync, and DE) received from the host system 200.

[0123] A gate timing signal generated by timing controller 130 may be input to the shift register of gate driver 120 via level shifter 150. Level shifter 150 may receive the gate timing signal and generate a pulse and a shift clock to supply to the shift registers in gate driver 120. An input signal to level shifter 150 may be a signal having a digital voltage signal level, and an output signal of level shifter 150 may be an analog voltage signal fluctuating between gate-on voltage VGL and gate-off voltage VGH. The data timing signal generated by timing controller 130 may be transmitted to data driver 110. Data driver 110 may generate source output enable signal SOE from the received data timing signal.

[0124] The host system 200 may scale an image signal from a video source to match the resolution of the display panel 100 and transmit the scaled image signal along with the timing signal to the timing controller 130. In a mobile system, the host system 200 may be implemented with an application processor (AP). The host system 200 may transmit the pixel data of the input image to the driver integrated circuit (DIC), which may be included, for example, in the Fig. 10A and Fig. 10B, via a MIPI (Mobile Industry Processor Interface). The host system 200 may be electrically connected to the driver integrated circuit (DIC) via a flexible printed circuit, e.g., a flexible printed circuit (FPC), as shown in Fig. 10A. The drive IC (DIC) can be mounted on the display panel 100 during a chip-on-glass (COG) process, such as in Fig. 10A. The drive IC (DIC) may be electrically connected to the wires on the display panel 100 as a chip-on-film (COF) structure mounted on a flexible circuit sheet, such as in Fig. 10B shown.

[0125] The timing controller 130 or the host system 200 may enter a power-saving mode to reduce the power consumption of the display device when a still image or "always on display" (AOD) data is input. In a normal mode, the pixels 101 may have a refresh rate of 60 Hz, 144 Hz, 240 Hz, or the like. The refresh rate is the frequency at which pixel data is written to the pixels 101. In the power-saving mode, the refresh rate of the pixels 101 may be reduced to a frequency lower than 60 Hz, for example, to 1 Hz to 30 Hz. When the refresh rate is 1 Hz, a first frame of 60 frames per second may be a refresh frame, and the next 59 frames may be hold frames.After a data voltage Vdata of the pixel data is loaded into the pixels 101 during a refresh frame period, the pixels 101 may retain the data voltage loaded in a previous refresh frame without reloading the data voltage Vdata during the continuous subsequent hold frame periods to maintain an emitting state.

[0126] The exemplary switching circuit SW, which is shown in the Fig. 8A and Fig. 8B may be located in the non-display area NA of the display panel 100 or in a data output channel of the data driver 110.

[0127] Fig. 11 is a diagram showing an example of circuit parts and stretch wires of a stretchable display device.

[0128] As in Fig. 11, a display panel of the stretchable display device may include a plurality of circuit portions 162 spaced apart on a stretchable substrate, and stretchable wires 164 and 166 electrically connecting the circuit portions 162.

[0129] The data lines 102, gate lines 103, power lines and clock lines connected to the shift register of the gate driver 120 (see e.g. Fig. 9-10B), may be implemented as stretchable wires 164 and 166 disposed on the stretchable substrate.

[0130] The stretchable wires 164 and 166 may include a plurality of first directional stretchable wires 164 and a plurality of second directional stretchable wires 166. The first directional stretchable wires 164 may extend along the first direction X to electrically connect the adjacent circuit parts 162 in the first direction X. The second directional stretchable wires 166 may extend along the second direction Y to electrically connect the adjacent circuit parts 162 in the second direction Y. The stretchable wires 164 and 166 may be implemented as a sufficiently stretchable wiring structure, such as zigzag wiring or wavy wiring. In a mesh-shaped wiring, the first directional stretchable wires 164 and the second directional stretchable wires 166 may be connected at the circuit part 162.

[0131] In the display area AA, each of the circuit parts 162 can contain one or more pixel circuits. The circuits in the gate driver 120 can be distributed among the circuit parts 162 arranged in the non-display area NA and / or in the display area AA. If the switching circuit SW is arranged in the non-display area NA of the display panel 100, the switching circuit SW can be arranged in the circuit part 162 in the non-display area NA.

[0132] Fig. 12 is a diagram illustrating a frame period and a horizontal period according to an exemplary embodiment of the present disclosure.

[0133] Fig. 13 is a diagram illustrating an exemplary interconnection line structure between a timing controller and driver ICs at an EPI interface. Fig. Figure 14 is a waveform diagram illustrating an example of a multi-phase internal clock generated by driver ICs. A driver IC may include the data driver 110. In Fig. 13 “GIP” stands for the gate driver 120.

[0134] As in the Fig. 12, Fig. 13 and Fig. As shown in Figure 14, a vertical synchronization signal (Vsync) may define a frame period. A horizontal synchronization signal Hsync may define a horizontal period (1H). A data enable signal DE may define an effective data portion containing pixel data to be written to the pixels. One pulse of the data enable signal DE may be synchronized with the pixel data to be written to the pixels 101 of the display panel 100. One pulse cycle of the data enable signal DE may be one horizontal period (1H).

[0135] A frame period can be divided into an active period AT, in which the pixel data of the input image is written into the pixels 101, and a vertical idle period VB without pixel data.

[0136] The timing control device TCON can send data to the data driver 110 of the control ICs SIC1 to SIC4 via the embedded point-to-point clock interface (EPI). Although Fig. 13 illustrates four control ICs, 100 additional control ICs can be added depending on the size and resolution of the display panel.

[0137] The EPI interface can connect the timing device TCON and the control ICs SIC1 to SIC4 in a point-to-point manner, as in Fig. 13 to minimize the number of wires required in the transmission lines between the timing controller TCON and the drive ICs SIC1 to SIC4. The transmission lines that connect the timing controller TCON and the drive ICs SIC1 to SIC4 in a point-to-point manner may include data line pairs. In the EPI interface, signals with a built-in clock may be transmitted over a data line pair. The signals with a built-in clock may include control data for controlling the data drivers of the drive ICs SIC1 to SIC4 and the gate driver GIP, as well as pixel data to be written to the pixels to display the input image in the display area AA. Therefore, the EPI interface may not require separate clock and control lines because the signals including clock, control data, and pixel data are transmitted serially over the same line pair.

[0138] For the EPI interface, each of the drive ICs SIC1 to SIC4 can include a clock and data recovery (CDR) circuit. The timing control circuit TCON can send a clock training pattern signal (or preamble signal) to the drive ICs SIC1 to SIC4 so that the phase and frequency of the clock to be recovered can be locked in the drive ICs SIC1 to SIC4. When the clock training pattern signal and the clock bit, which are sequentially received in the data signal DATA, are input via the data line pair, the drive ICs SIC1 to SIC4 can recover the clock from the clock bit to generate a multi-phase internal clock CDR CLK, as in Fig. 14 shown. In Fig. In Figure 14, "0011" is an example of a clock bit transmitted serially to the control ICs SIC1 to SIC4. The clock bit can be encoded between data packets.

[0139] When the internal clock CDR CLK is locked in phase and frequency, the drive ICs SIC1 to SIC4 can return a high logic level lock signal LOCK to the timing control device TCON, indicating the stable output state. The lock signal LOCK can be transmitted sequentially from a first drive IC SIC1 to a fourth drive IC SIC4, and the lock signal LOCK can be fed back from the fourth drive IC SIC4 to the timing control device TCON via a lock feedback line.

[0140] In a signal transmission protocol of the EPI interface, the timing controller TCON can send the clock training pattern signal to the drive ICs SIC1 to SIC4 before sending the control data and the pixel data of the input image. The drive ICs SIC1 to SIC4 can recover the clock from the DATA signal received over the data line pair by performing clock training when the clock training pattern signal is received to generate an internal clock, and can send the lock signal LOCK to the timing controller TCON to establish a data connection with the timing controller TCON when the phase and frequency of the internal clock are stably fixed in all the drive ICs SIC1 to SIC4.

[0141] In response to the lock signal LOCK received from the last drive IC SIC4, the timing control device TCON can encode the control data and the pixel data and begin transmitting them to the drive ICs SIC1 to SIC4 via the data line pair. The DATA signal output by the timing control device TCON can be converted into a differential signal via a transmit end buffer of the timing control device TCON and transmitted to the drive ICs SIC1 to SIC4 via the data line pair. The line pair can include a first line over which a forward phase signal of the differential signal is transmitted and a second line over which a reverse phase signal of the differential signal is transmitted.

[0142] The drive ICs SIC1 to SIC4 can restore the control data by sampling control data bits from the signal DATA received via the data line pair according to an internal clock timing, and can restore a data timing signal, a gate drive control signal, and the like from the restored control data.

[0143] The drive ICs SIC1 to SIC4 can sample bits of pixel data from the DATA signal received over the line pair according to the internal clock timing and then convert the bits of the sampled pixel data into parallel data using a latch. The drive ICs SIC1 to SIC4 can convert the pixel data into a data voltage and output it via an output buffer. The data voltage can be supplied to the data lines of the display panel 100.

[0144] Fig. Figure 15 is a waveform diagram illustrating an example of a signal transmission protocol for an EPI interface.

[0145] As in Fig. As illustrated in Figure 15, in a first phase (I), the timing controller TCON may transmit a clock training pattern signal C / T at a constant frequency to the drive ICs SIC1 to SIC4. When a high logic level (H) lock signal LOCK is input via the lock feedback line, in a second phase (II), the timing controller TCON may convert the DATA signal encoded in the signal format defined by the EPI interface protocol into the differential signal and begin transmitting it over the line pair. In the second phase (II), a control data packet CTRL may be sent to the drive ICs SIC1 to SIC4.

[0146] After the second phase Phase-II, the timing control device TCON may perform a third phase Phase-III when the lock signal LOCK is maintained at a high logic level to transmit video data packets containing the pixel data DATA of the input image to the control ICs SIC1 to SIC4.

[0147] In Fig. 15, "Tlock" is a delay time until the lock signal LOCK is inverted to the high logic level (H). During the delay time Tlock, the clock training pattern signal C / T can be sent to the drive ICs SIC1 to SIC4 to lock the frequency and phase of the internal clock recovered by performing the clock training process in the drive ICs SIC1 to SIC4.

[0148] The timing control unit TCON can re-execute the first phase Phase-I to resume clock training for the drive ICs SIC1 to SIC4 when a latch signal LOCK of low logic level (L) is input from the last drive IC SIC4, and can transmit the clock training pattern signal C / T to the drive ICs SIC1 to SIC4. If the latch signal LOCK in any of the drive ICs SIC1 to SIC4 is inverted to a low logic level (L) in an unexpected situation during the execution of the second phase Phase-II or the third phase Phase-III, the timing control unit TCON can execute the first phase Phase-I and transmit the clock training pattern signal C / T to the drive ICs SIC1 to SIC4 even when the Phase-II or Phase-III is being executed. In this case, the control data CTRL and the pixel data DATA are not received by the control ICs SIC1 to SIC4.

[0149] Fig. Figure 16 is a diagram illustrating an example of one (1) data packet in the EPI interface.

[0150] As in Fig. As illustrated in Figure 16, a data packet of the DATA signal sent to the control ICs SIC1 to SIC4 may include data bits and clock bits EPI CLK allocated before and after the data bits. The transmission time for one bit may be one UI (Unit Interval) time. The one UI may vary depending on the resolution of the display panel 100 or the number of data bits.

[0151] The EPI CLK clock bits can be allocated by 4 UI between adjacent data packets, and their logical value can be set to "0 0 1 1 (or LLHH)", but is not limited to this. If the number of bits per color in 4 sub-color data is 10 bits, a data packet containing one pixel can contain 40 UI data bits and 4 UI clock bits. If the number of data bits is 8 bits and the pixel data includes R, G, and B data without white data W, a data packet can contain 24 UI data bits, including 8 bits of R sub-pixel data, 8 bits of G sub-pixel data, and 8 bits of B sub-pixel data, as well as 4 UI clock bits.

[0152] Fig. Figure 17 is a diagram illustrating an example of a signal transmitted during a horizontal idle period.

[0153] As in Fig. As illustrated in Figure 17, a horizontal period (1H) can be divided into a horizontal idle period HB, during which no pixel data is transmitted, and a horizontal active period HA, during which pixel data DATA is transmitted. The control data packets can be transmitted to the control ICs SIC1 to SIC4 in the horizontal idle period HB.

[0154] The first phase (Phase-I) and the second phase (Phase-II) may be performed during the horizontal idle period HB. The horizontal idle period HB may correspond to an interval with a low logic level of the data activation signal DE. During the horizontal idle period HB, one or more control data packets CTRL may be transmitted. As described in the Fig. 15 and Fig. As shown in Figure 17, initialization data REF indicating the level of the initialization voltage Vref / VSS may be encoded in the control data packets CTRL.

[0155] The data driver of the drive ICs SIC1 to SIC4 can sample and latch the initialization data REF and supply the initialization data REF to the DAC, which outputs the initialization voltage Vref / VSS at the level specified by the initialization data REF. Since the initialization data REF is updated every horizontal period, the initialization voltage Vref / VSS can be applied as the same or different voltages for each pixel line L1 to Ln. When the initialization data REF is 4-bit data, the initialization voltage Vref / VSS can be selected from voltages divided into 16 steps. In this way, the initialization voltage Vref / VSS can be applied as the optimal voltage depending on the position of the display panel 100.For example, the reference voltage Vref may increase with increasing distance from the control IC, taking into account the voltage drop of the voltage applied to the power line of the display panel.

[0156] According to one or more embodiments of the present disclosure, the display device can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, slidable devices, variable devices, electronic organizers, electronic books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation devices, vehicle navigation devices, vehicle display devices, vehicle devices, theater devices, cinema display devices, televisions, wallpaper devices, signage devices, gaming devices, laptops, monitors, cameras, camcorders, and home appliances, etc.Furthermore, the display device according to one or more exemplary embodiments of the present disclosure may be applied to organic light-emitting lighting devices or inorganic light-emitting lighting devices.

[0157] The objects to be achieved by the present disclosure, the means for achieving the objects, and the effects of the present disclosure described above do not define essential features of the claims. Therefore, the scope of the claims is not limited to the above description of the present disclosure.

[0158] It will be apparent to those skilled in the art that the present disclosure is not limited by the above-described embodiments and the accompanying drawings, and that various substitutions, modifications, and variations can be made in the present disclosure without departing from the scope of the disclosures. Therefore, the above embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope or technical concept of the present disclosure. The scope of the present disclosure should be interpreted based on the following claims and their equivalents, and the present disclosure is intended to cover all modifications and variations of this disclosure that fall within the scope of the claims and their equivalents. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] KR 10-2023-0192176

[0001]

Claims

[1] A pixel circuit comprising: a compensation circuit (10) connected to a data line (DL), a first gate line (GL1) and a second gate line (GL2), wherein the compensation circuit (10) is arranged to alternately receive a first and a second voltage via the data line (DL), a first gate signal via the first gate line (GL1) and a second gate signal via the second gate line (GL2); a light-emitting element (EL); a drive element (DT) including a gate electrode configured to receive the second voltage via the compensation circuit (10), wherein the drive element (DT) is configured to generate a current for driving the light-emitting element (EL) based on the second voltage; and a switching element (ST) including a gate electrode configured to receive the second gate signal via the compensation circuit (10), wherein the switching element (ST) is configured to switch a path of the current between the drive element (DT) and the light-emitting element (EL) based on the second gate signal, wherein the light-emitting element (EL), the driving element (DT) and the switching element (ST) are connected in series between a first power line and a second power line. [2] The pixel circuit according to claim 1, wherein the compensation circuit (10) contains: a capacitor (Cst) connected between a first node (A) and a second node (B); a first switching element (T1) connected between the data line (DL) and the first node (A) and configured to turn on in response to a gate-on voltage of the first gate signal to electrically connect the data line (DL) to the first node (A); a second switching element (T2) connected between the second node (B) and a third node (C) and configured to turn on in response to the gate-on voltage of the first gate signal to electrically connect the second node (B) to the third node (C); a third switching element (T3) connected to the first node (A) and configured to turn on in response to a gate-on voltage of the second gate signal to apply the first voltage to the first node (A); and a fifth switching element (T5) connected to a fourth node (D) and configured to turn on in response to the gate-on voltage of the first gate signal to apply the first voltage to the fourth node (D); the switching element (ST) includes a fourth switching element (T4) connected between the third node (C) and the fourth node (D) and configured to turn on in response to the gate-on voltage of the second gate signal to electrically connect the third node (C) to the fourth node (D); the drive element (DT) includes a gate electrode connected to the second node (B), a first electrode connected to the first power line configured to receive a pixel drive voltage, and a second electrode connected to the third node (C); the light-emitting element (EL) includes an anode electrode connected to the fourth node (D) and a cathode electrode connected to the second power line configured to receive a cathode voltage; the first voltage is a reference voltage or the cathode voltage and the second voltage is a data voltage of pixel data; and the data line (DL) is configured to receive the data voltage of the pixel data after receiving the reference voltage or the cathode voltage. [3] The pixel circuit according to claim 2, wherein during a horizontal period, the first node (A) is arranged to receive the reference voltage simultaneously via the data line (DL) and the first switching element (T1) as well as via the third switching element (T3). [4] The pixel circuit according to claim 3, wherein the second node (B), the third node (C) and the fourth node (D) are arranged to receive the reference voltage when the reference voltage is applied to the first node (A). [5] The pixel circuit according to claim 3 or 4, wherein: a driving period of the pixel circuit includes a first phase in which the pixel circuit is configured to be initialized, a second phase in which the capacitor (Cst) is configured to receive a threshold voltage of the driving element (DT) and the data voltage, and a third phase in which the light-emitting element (EL) is configured to emit light; the first gate signal is arranged to be at gate-on voltage in the first phase and the second phase and at gate-off voltage in the third phase; the second gate signal is arranged to be at the gate-off voltage in the second phase and at the gate-on voltage in the first and third phases; the first, second and fifth switching elements (T1, T2, T5) are configured to turn on in response to the gate-on voltage of the first gate signal and to turn off in response to the gate-off voltage of the first gate signal; the third and fourth switching elements (T3, T4) are arranged to turn on in response to the gate-on voltage of the second gate signal and to turn off in response to the gate-off voltage of the second gate signal; the one horizontal period contains periods of the first phase and the second phase; and the data line (DL) is configured so that it is at the reference voltage in the first phase and at the data voltage in the second phase. [6] The pixel circuit of claim 5, wherein: the first switching element (T1) includes a gate electrode configured to receive the first gate signal, a first electrode connected to the data line (DL), and a second electrode connected to the first node (A); the second switching element (T2) includes a gate electrode configured to receive the first gate signal, a first electrode connected to the second node (B), and a second electrode connected to the third node (C); the third switching element (T3) includes a gate electrode configured to receive the second gate signal, a first electrode connected to the first node (A), and a second electrode configured to receive the reference voltage; the fourth switching element (T4) includes a gate electrode configured to receive the second gate signal, a first electrode connected to the third node (C), and a second electrode connected to the fourth node (D); and the fifth switching element (T5) includes a gate electrode configured to receive the first gate signal, a first electrode configured to receive the reference voltage, and a second electrode connected to the fourth node (D). [7] The pixel circuit according to any one of claims 2 to 6, wherein during a horizontal period, the first node (A) is arranged to receive the cathode voltage simultaneously via the data line (DL) and the first switching element (T1) as well as via the third switching element (T3). [8] The pixel circuit according to claim 7, wherein the second node (B), the third node (C) and the fourth node (D) are arranged to receive the cathode voltage when the cathode voltage is applied to the first node (A). [9] The pixel circuit according to claim 7 or 8, wherein: a driving period of the pixel circuit includes a first phase in which the pixel circuit is configured to be initialized, a second phase in which the capacitor (Cst) is configured to receive a threshold voltage of the driving element (DT) and the data voltage, and a third phase in which the light-emitting element (EL) is configured to emit light; the first gate signal is arranged to be at the gate-on voltage in the first phase and the second phase and at the gate-off voltage in the third phase; the second gate signal is arranged to be at the gate-off voltage in the second phase and at the gate-on voltage in the first and third phases; the first, second and fifth switching elements (T1, T2, T5) are arranged to turn on in response to the gate-on voltage of the first gate signal and to turn off in response to the gate-off voltage of the first gate signal; the third and fourth switching elements (T3, T4) are arranged to turn on in response to the gate-on voltage of the second gate signal and to turn off in response to the gate-off voltage of the second gate signal; the one horizontal period contains periods of the first phase and the second phase; and the data line (DL) is configured so that it is at the cathode voltage in the first phase and at the data voltage in the second phase. [10] The pixel circuit of claim 9, wherein: the first switching element (T1) includes a gate electrode configured to receive the first gate signal, a first electrode connected to the data line (DL), and a second electrode connected to the first node (A); the second switching element (T2) includes a gate electrode configured to receive the first gate signal, a first electrode connected to the second node (B), and a second electrode connected to the third node (C); the third switching element (T3) includes a gate electrode configured to receive the second gate signal, a first electrode connected to the first node (A), and a second electrode configured to receive the cathode voltage; the fourth switching element (T4) includes a gate electrode configured to receive the second gate signal, a first electrode connected to the third node (C), and a second electrode connected to the fourth node (D); and the fifth switching element (T5) includes a gate electrode configured to receive the first gate signal, a first electrode configured to receive the cathode voltage, and a second electrode connected to the fourth node (D). [11] The pixel circuit according to any one of claims 1 to 10, wherein: the first voltage is a constant voltage, wherein the first voltage is a reference voltage or a cathode voltage; the second voltage is a data voltage corresponding to the pixel data; and during a horizontal period, the compensation circuit (10) is further configured to receive the first voltage via the data line (DL) and then to receive the second voltage via the data line (DL). [12] The pixel circuit of claim 11, wherein: the one horizontal period contains a horizontal idle period and a horizontal active period; during the horizontal idle period, the compensation circuit (10) is further configured to receive the first voltage, and not the second voltage, via the data line (DL) to initialize the pixel circuit; and during the horizontal active period, the compensation circuit (10) is further configured to receive the second voltage via the data line (DL) in order to write the pixel data into the pixel circuit. [13] The pixel circuit of claim 11, wherein: the one horizontal period contains a horizontal idle period and a horizontal active period; during the horizontal idle period, the first gate signal and the second gate signal are at a gate-on voltage; and During the horizontal active period, the first gate signal is at the gate-on voltage and the second gate signal is at a gate-off voltage. [14] A display device comprising: a display panel including a plurality of data lines (DL), a plurality of gate lines (GL1, GL2), a plurality of power lines, and a plurality of pixel circuits, at least one of the pixel circuits being the pixel circuit of claim 1; a data driver (110) configured to output the first and second voltages; a gate driver (120) configured to supply at least one gate signal to the gate lines (GL1, GL2); and a control circuit configured to control the data driver (110) and the gate driver (120), wherein the plurality of data lines (DL) includes the data line (DL), the plurality of gate lines (GL1, GL2) includes the first gate line (GL1) and the second gate line (GL2), the at least one gate signal includes the first gate signal and the second gate signal, and the plurality of power lines includes the first power line and the second power line. [15] The display device according to claim 14, wherein the compensation circuit (10) contains: a capacitor (Cst) connected between a first node (A) and a second node (B); a first switching element (T1) connected between the data line (DL) and the first node (A) and configured to turn on in response to a gate-on voltage of the first gate signal to electrically connect the data line (DL) to the first node (A); a second switching element (T2) connected between the second node (B) and a third node (C) and configured to turn on in response to the gate-on voltage of the first gate signal to electrically connect the second node (B) to the third node (C); a third switching element (T3) connected to the first node (A) and configured to turn on in response to a gate-on voltage of the second gate signal to apply the first voltage to the first node (A); and a fifth switching element (T5) connected to a fourth node (D) and configured to turn on in response to the gate-on voltage of the first gate signal to apply the first voltage to the fourth node (D); the switching element (ST) includes a fourth switching element (T4) connected between the third node (C) and the fourth node (D) and configured to turn on in response to the gate-on voltage of the second gate signal to electrically connect the third node (C) to the fourth node (D); the drive element (DT) includes a gate electrode connected to the second node (B), a first electrode connected to the first power line configured to receive a pixel drive voltage, and a second electrode connected to the third node (C); the light-emitting element (EL) includes an anode electrode connected to the fourth node (D) and a cathode electrode connected to the second power line configured to receive a cathode voltage; and the first voltage contains a reference voltage or the cathode voltage, and the second voltage contains a data voltage of pixel data. [16] The display device according to claim 14 or 15, wherein the control circuit is arranged to transmit initialization data to the data driver (110) as a digital signal; and the data driver (110) is configured to output the first voltage in response to the initialization data. [17] The display device according to claim 16, wherein: the control circuit is arranged to update the initialization data in each horizontal period; and the first voltage has a level corresponding to the initialization data. [18] The display device according to any one of claims 14 to 17, wherein the display panel includes: a plurality of circuit parts in which the pixel circuits are arranged; and a plurality of expandable wires electrically connecting the plurality of circuit parts, and where the stretchable wires contain the data lines (DL), the gate lines (GL1, GL2) and the power lines. [19] A display device according to any one of claims 14 to 18, further comprising: a switching circuit configured to alternately select one of the first voltage and the second voltage and supply the selected one of the first voltage and the second voltage to the data lines (DL). [20] The display device according to claim 19, wherein the switching circuit is further configured to) within a horizontal period of time select and supply the first voltage to the data line (DL) and then select and supply the second voltage to the data line (DL).

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