DISPLAY DEVICE AND CONTROL METHOD THEREOF

Abstract

A display device and a driving method thereof. The display device comprises a display module including a display panel (150) configured to display an image, a driver (130, 140) configured to drive the display panel (150), a timing controller (120) configured to control the driver (130, 140), and a power supply (180) configured to supply power for driving the display module. The display module operates in an order of drive preparation, which includes operating a basic configuration required for operation of a device, drive wait compensation, which includes scanning at least one gate line (GL1, ..., GLm) to compensate for a drive wait state of the display panel (150), and normal driving, which includes displaying an image on the display panel (150).

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of Korean Patent Application No. 10-2023-0197064, filed on December 29, 2023. AREA

[0002] The present disclosure relates to a display device and a driving method thereof. DESCRIPTION OF THE RELATED TECHNOLOGY

[0003] In line with advances in information technology, the market for display devices, which serve as a connecting medium between a user and information, is growing. Accordingly, the use of display devices such as light-emitting displays (LEDs), quantum dot displays (QDDs), and liquid crystal displays (LCDs), etc., is increasing.

[0004] The above-mentioned display devices comprise a display panel having subpixels, a driver configured to generate a drive signal for driving the display panel, a power supply configured to generate power to be supplied to the display panel or the driver, etc.

[0005] In such display devices, when a driving signal such as a scanning signal and a data signal, etc., is supplied to the sub-pixels formed on the display panel, light is transmitted or directly emitted from selected sub-pixels, and thus an image can be displayed. OVERVIEW

[0006] Accordingly, the present disclosure is directed to a display device and a driving method thereof that substantially obviate one or more problems due to limitations and disadvantages of the related art.

[0007] An object of the present disclosure is not only to eliminate a problem of brightness variations (spots on the screen or line- or block-shaped spots) caused by distortion of threshold voltage information that may occur when a display device is not driven (or remains driven) for a long period of time, but also to appropriately compensate for brightness variations in accordance with various environments and conditions, thereby improving compensation accuracy and compensation reliability.

[0008] Objects of the present disclosure are not limited to the object described above, and other objects of the present disclosure not yet described will be more clearly understood by those skilled in the art from the following detailed description.

[0009] To achieve these objects and other advantages, and in accordance with the purpose of the disclosure as embodied and broadly described herein, there are provided a display device according to claim 1, a driving method according to claim 11, and a display device according to claim 17. Further embodiments are described in the dependent claims.In one aspect of the present disclosure, a display device includes a display module having a display panel configured to display an image, a driver configured to drive the display panel, and a timing controller configured to control the driver, and a power supply configured to supply power to drive the display module, wherein the display module operates in an order of drive preparation comprising operating a basic configuration required for operation of a device, drive wait compensation comprising scanning at least one gate line to compensate for a drive wait state of the display panel, and normal driving comprising displaying an image on the display panel.

[0010] The display module may perform the drive wait compensation when a sampling flag defined in the timing controller is in an active state.

[0011] The display module may further perform drive preparation compensation between the drive waiting compensation and the normal drive for scanning all gate lines of the display panel.

[0012] The sampling flag may enter an inactive state after the drive wait compensation is performed.

[0013] The sampling flag can remain inactive during normal control.

[0014] The sampling flag may enter an inactive state after the drive wait compensation and the drive preparation compensation are executed.

[0015] The scanning flag may be regenerated to have the active state when the display device deviates from a use waiting state of the display panel.

[0016] The scanning flag may be regenerated to have the active state when the display device deviates from a final compensation execution state of the display panel.

[0017] In another aspect of the present disclosure, a driving method of a display device including a display module having a display panel configured to display an image, a driver configured to drive the display panel, and a timing controller configured to control the driver, and a power supply configured to supply power to drive the display module includes drive preparation including operating a basic configuration required for operating a device included in the display module, drive wait compensation including scanning at least one gate line to compensate for a drive wait state of the display panel, and normal driving including displaying an image on the display panel.

[0018] The driving method may further comprise performing drive preparation compensation between the drive waiting compensation and the normal drive for scanning all the gate lines of the display panel.

[0019] Drive wait compensation can be executed when a sampling flag defined in the timing control is in an active state. The sampling flag can transition to an inactive state after drive wait compensation is executed.

[0020] The scanning flag may be regenerated to have the active state when the display device deviates from a use waiting state of the display panel or a final compensation execution state of the display panel.

[0021] The present disclosure has an effect that can eliminate a problem of brightness fluctuation (screen spots or spots in line form or block form) caused by distortion of threshold voltage information that may occur when the display device is held (or left) for a long period of time without being driven. Furthermore, the present disclosure has an effect that can improve compensation accuracy by performing compensation per pixel based on a threshold voltage compensation value that is updated along with driving of the light-emitting display device, even when the light-emitting display device is held (or left) for a long period of time without being driven.Furthermore, the present disclosure has an effect that can improve compensation reliability of the light-emitting display device by forcibly performing final compensation when a situation in which the light-emitting display device is held (or left) without being driven for a long time is repeated or when the final compensation is not appropriately performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the disclosure and, together with the description, serve to explain the principle of the disclosure. In the drawings: Fig. 1 is a block diagram schematically illustrating a light-emitting display device; Fig. 2 is a configuration diagram schematically showing a Fig. 1 represents the subpixel displayed; Fig. 3 is a diagram showing a pixel consisting of subpixels; Fig. 4 and Fig. 5 are diagrams explaining a configuration of a gate-in-panel type scanning driver; Fig. 6 is a diagram showing an arrangement example of the gate-in-panel type scanning driver; Fig. 7 is a diagram illustrating a subpixel, a data driver, and a timing controller according to one embodiment; Fig. 8 is a diagram briefly explaining a method for sampling a threshold voltage of a drive transistor according to an embodiment; Fig. 9 is a conceptual diagram explaining a drive wait compensation method according to a first embodiment; Fig. 10 is a flowchart explaining the drive wait compensation method according to the first embodiment; Fig. 11 is a block diagram explaining generation of a sampling flag for drive wait compensation according to the first embodiment; Fig. 12 is an explanatory diagram explaining a scan line for drive wait compensation according to the first embodiment; Fig. 13 is a conceptual diagram explaining whether or not the drive wait compensation according to the first embodiment has been executed and a change of the sampling flag; Fig. 14 is a conceptual diagram explaining a modification of the first embodiment; Fig. 15 is a conceptual diagram explaining a drive wait compensation method according to a second embodiment; Fig. 16 is a flowchart explaining the drive wait compensation method according to the second embodiment; Fig. 17 is a conceptual diagram explaining a drive wait compensation method according to a third embodiment; Fig. 18 is a conceptual diagram explaining whether or not drive wait compensation has been executed according to the third embodiment and a change of a sampling flag; Fig. 19 is a conceptual diagram explaining whether or not the drive wait compensation according to the third embodiment has been executed, a change of the sampling flag, and states according to various drive modes; Fig. 20 is a conceptual diagram explaining a change of a sampling flag according to a fourth embodiment; Fig. 21 is a conceptual diagram explaining whether or not drive wait compensation has been performed according to the fourth embodiment, a change of the sampling flag, and states according to various drive modes; Fig. 22 is a conceptual diagram explaining a modification of the fourth embodiment; and Fig. 23 to Fig. 26 are diagrams explaining contents involved in the drive waiting compensation according to the present disclosure. DETAILED DESCRIPTION

[0023] A display device according to the present disclosure may be embodied as, but not limited to, a television, an image display device, a personal computer (PC), a home theater, an electrical device for a car, a smartphone, etc. The display device according to the present disclosure may be embodied as a light-emitting display (LED) device, a quantum dot display (QDD) device, a liquid crystal display (LCD), etc. However, for convenience of description, the following description will be given in conjunction with an example in which the display device according to the present disclosure is a light-emitting display device configured to directly emit light based on an inorganic light-emitting diode or an organic light-emitting diode.

[0024] Fig. 1 is a block diagram schematically illustrating a light-emitting display device. Fig. 2 is a configuration diagram schematically showing a Fig. 1 represents the subpixel shown. Fig. Figure 3 is a diagram showing a pixel consisting of subpixels.

[0025] As in Fig. 1 to Fig. 3, the light-emitting display device may include an image feeder 110, a timing controller 120, a scan driver 130, a data driver 140, a display panel 150, a power supply 180, etc.

[0026] The image feeder 110 (a device or a host system) can output various drive signals, as well as an image data signal supplied from outside the device or an image data signal stored in an internal memory. The image feeder 110 can supply the data signal and the various drive signals to the timing controller 120.

[0027] Timing controller 120 may output a gate timing signal GDC for controlling the operating timing of scan driver 130, a data timing signal DDC for controlling the operating timing of data driver 140, various synchronization signals, etc. Timing controller 120 may supply a data signal DATA supplied from image feeder 110 to data driver 140 along with the data timing signal DDC. Timing controller 120 may take the form of an integrated circuit (IC) and, as such, may be mounted on a printed circuit board, but is not limited thereto.

[0028] The scan driver 130 may output a scan signal (or a scan voltage), etc., in response to the gate timing signal GDC supplied from the timing controller 120. The scan driver 130 may supply a scan signal to subpixels included in the display panel 150 via gate lines GL1 to GLm. The scan driver 130 may take the form of an integrated circuit (IC) or may be formed directly on the display panel 150 in the form of a gate-in-panel structure, but is not limited thereto.

[0029] The data driver 140 may, in response to the data timing control signal DDC, etc. supplied from the timing controller 120, sample and latch the data signal DATA, convert a data signal having a digital form into a data voltage having an analog form, and then output the resulting data voltage. The data driver 140 may supply the data voltage to the subpixels included in the display panel 150 via data lines DL1 to DLn. The data driver 140 may take the form of an integrated circuit (IC) and, as such, may be mounted on the display panel 150 or a printed circuit board, but is not limited thereto.

[0030] The power supply 180 can generate a first high-level voltage and a second low-level voltage based on an external input voltage supplied from the outside, can output the first voltage through a first power line EVDD, and can output the second voltage through a second power line EVSS. The power supply 180 can generate and output not only the first voltage and the second voltage, but also a voltage required to drive the scan driver 130 (for example, a scan high voltage and a scan low voltage) or a voltage required to drive the data driver 140 (a drain voltage and a half-drain voltage).

[0031] The display panel 150 can display an image corresponding to the drive signal including the scanning signal and the data voltage, the first voltage, the second voltage, etc. The subpixels of the display panel 150 can directly emit light. The display panel 150 can be fabricated based on a substrate with rigidity or stretchability, such as glass, silicon, polyimide, or the like. For example, a subpixel SP can include a pixel circuit connected to the first data line DL1, the first gate line GL1, the first power line EVDD, and the second power line EVSS, while being formed of a switching transistor, a drive transistor, a capacitor, an organic light-emitting diode, etc.

[0032] The subpixel SP used in the light-emitting display device directly emits light, and thus, the circuit configuration thereof is complex. Furthermore, a compensation circuit configured to compensate for deterioration not only of the organic light-emitting diode configured to emit light, but also of the driving transistor configured to supply the driving current required to drive the organic light-emitting diode, etc., is also diverse. Accordingly, it is noted that in Fig. 2 the subpixel SP is simply represented in the form of a block.

[0033] The subpixels may emit red light, green light, or blue light, or may emit red light, green light, blue light, or white light. Accordingly, a pixel P may have a red subpixel, a green subpixel, and a blue subpixel, or may have a red subpixel, a green subpixel, a blue subpixel, and a white subpixel. For example, a pixel P may have a red subpixel SPR connected to the first data line DL1, a white subpixel SPW connected to the second data line DL2, a green subpixel SPG connected to the third data line DL3, and a blue subpixel SPB connected to the fourth data line DL4. Furthermore, the red subpixel SPR, the white subpixel SPW, the green subpixel SPG, and the blue subpixel SPB may be commonly connected to a first reference line VREF1. The first reference line VREF1 may be used for sensing degradation, etc.of an element(s) contained in one of the red subpixel SPR, the white subpixel SPW, the green subpixel SPG, and the blue subpixel SPB. This will be described later.

[0034] Here, the timing controller 120, the scanning driver 130, the data driver 140, etc., have each been described as individual configurations. However, one or more of the timing controller 120, the scanning driver 130, and the data driver 140 may be integrated into an IC according to an implementation method of the light-emitting display device. The timing controller 120, the scanning driver 130, the data driver 140, and the display panel 150 may be defined as a display module.

[0035] Furthermore, an example of pixel P was shown in which the red subpixel SPR, the white subpixel SPW, the green subpixel SPG, and the blue subpixel SPB are arranged in this order. However, the arrangement order and direction of the subpixels may be varied in accordance with an implementation method of the light-emitting display device.

[0036] Fig. 4 and Fig. 5 are diagrams explaining a configuration of a gate-in-panel type scanning driver. Fig. 6 is a diagram showing an arrangement example of the gate-in-panel type scanning driver.

[0037] As in Fig. 4, the gate-in-panel type scanning driver may include a shift register 131 and a level shifter 135. The level shifter 135 may generate drive timing signals Clks and a start signal Vst based on signals and voltages output from a timing controller 120 and a power supply 180.

[0038] The shift register 131 can operate based on the signals Clks and Vst, etc., output from the level shifter 135, and can output scanning signals Scan[1] to Scan[m] for turning on or off transistors formed on a display panel. The shift register 131 can be formed on the display panel in the form of a thin film according to a gate-in-panel method.

[0039] As in Fig. 4 and Fig. 5, the level shifter 135, unlike the shift register 131, may be independently formed in the form of an IC or may be included in a power supply 180. Of course, these configurations are only illustrative, and the present disclosure is not limited thereto.

[0040] As in Fig. 6, in the gate-in-panel type scanning driver, shift registers 131a and 131b that output scanning signals may be arranged in a non-active area NA of a display panel 150. Although Fig. 6 illustrates an example in which the shift registers 131a and 131b are arranged in a left non-active area NA and a right non-active area NA of the display panel 150, respectively, the shift registers 131a and 131b may be arranged in an upper non-active area NA and a lower non-active area NA of the display panel 150, respectively, or may be arranged in an active area AA of the display panel 150.

[0041] Fig. 7 is a diagram illustrating a subpixel, a data driver, and a timing controller according to one embodiment. Fig. 8 is a diagram briefly explaining a method for sampling a threshold voltage of a drive transistor according to an embodiment.

[0042] As in Fig. As shown in Figure 7, a subpixel SP may include a switching transistor SW, a driving transistor DT, a sensing transistor ST, a capacitor CST, and an organic light-emitting diode OLED.

[0043] The driving transistor DT may be connected at a gate electrode thereof to a first electrode of the capacitor CST, while being connected at a first electrode thereof to a first power line EVDD, and at a second electrode thereof to an anode of the organic light-emitting diode OLED. The capacitor CST may be connected at a first electrode thereof to the gate electrode of the driving transistor DT, while being connected at a second electrode thereof to the anode of the organic light-emitting diode OLED. The organic light-emitting diode OLED may be connected at the anode thereof to the second electrode of the driving transistor DT, while being connected at a cathode thereof to a second power line EVSS.

[0044] The switching transistor SW may be connected at one gate electrode thereof to a first scan line Gate1 included in a first gate line GL1, while being connected at one first electrode thereof to a first data line DL1, and at one second electrode thereof to the gate electrode of the driving transistor DT. The scanning transistor ST may be connected at one gate electrode thereof to a second scan line Gate2 included in the first gate line GL1, while being connected at one first electrode thereof to a first reference line VREF1, and at one second electrode thereof to the anode of the organic light-emitting diode OLED.

[0045] The switching transistor SW may function to transmit a data voltage VData transmitted through the first data line DL1 to the capacitor CST. The sensing transistor ST may function to sense a sensing node defined between the driving transistor DT and the organic light-emitting diode OLED. The sensing transistor ST is a type of compensation circuit added to compensate for deterioration (of threshold voltage, mobility, etc.) of the driving transistor DT or the organic light-emitting diode OLED. Here, the first gate line GL1 may have a one-piece structure without being divided into the first sensing line Gate1 and the second sensing line Gate2. This means that the switching transistor SW and the sensing transistor ST may be commonly connected to the first gate line GL1 and thus may be turned on or off simultaneously.

[0046] The data driver, designated by reference numeral "140," may include a drive circuit part 141 configured to drive the subpixel SP and a sampling circuit part 145 configured to sample an element included in the subpixel SP. The drive circuit part 141 may output the data voltage VData, etc., through the first data line DL1 to drive the subpixel SP. The sampling circuit part 145 may receive a sampling voltage Vsen sampled from the subpixel SP through the first reference line VREF1.

[0047] The timing controller, denoted by reference numeral "120," may include a compensator 123, etc., configured to compensate a data signal DATA to be supplied to the subpixel SP based on the scanning voltage Vsen transmitted from the scanning circuit part 145, thereby supplying a compensated data signal CDATA. For example, the compensator 123 may obtain threshold voltage information (change values) from driving transistors DT associated with subpixels SP (in the entirety of a display panel), and may compensate data signals DATA to eliminate a problem caused by threshold voltage change (shift).The compensator 123 may update the threshold voltage information of the driving transistors DT stored in a memory 125 based on respective scanning voltages Vsen on a subpixel basis and may provide compensation values COMP for compensating respective data signals DATA based on the updated threshold voltage information.

[0048] As in Fig. 7 and Fig. As shown in Fig. 8, when scanning signals correspondingly applied to the first scanning line Gate1 and the second scanning line Gate2 transition from a low voltage (L) to a high voltage (H), a basic operating state required for scanning can be established.

[0049] The sensing transistor ST can enable physical sensing of a threshold voltage Vth based on a source-follower operation of the driving transistor DT. A source node voltage (source node [V]) of the driving transistor DT can increase along a predetermined curve with the passage of time.

[0050] However, the source node voltage (source node [V]) of the drive transistor DT may rise to the threshold voltage Vth of the drive transistor DT before reaching a target voltage. The sampling transistor ST may sample a time point at which the source node voltage (source node [V]) of the drive transistor DT rises to the threshold voltage Vth of the drive transistor DT. Consequently, the sampling transistor ST samples the threshold voltage Vth of the drive transistor DT by the sampling voltage Vsen.

[0051] Fig. 8 is an explanatory diagram that assists in understanding a voltage sensing method configured to obtain a voltage, among methods for sensing the threshold voltage Vth of the driving transistor DT using the sensing transistor ST. The method for sensing an element included in the subpixel SP using the sensing transistor ST, etc., can be performed based on various methods, for example, a current detection method configured to obtain current, and various circuits. Accordingly, the sensing method usable in the present disclosure is not limited to the circuit of the Fig. 7 and the waveform of the Fig. 8 limited.

[0052] Here, according to experimental results, it was found that a display panel included in a light-emitting display device may not only exhibit a change in characteristics caused by deterioration when the light-emitting display device is driven for a long period of time, but may also exhibit a change in characteristics even when the light-emitting display device is held (or left) without being driven for a long period of time. Here, the conditions for holding the display panel without being driven for a long period of time may vary according to a storage period (or transportation period) or a storage environment (temperature, humidity, etc.).

[0053] To this end, the present disclosure proposes a scheme for eliminating / reducing problems that may occur due to various causes when the light-emitting display device is held (or left) without being driven for a long period of time.

[0054] Fig. 9 is a conceptual diagram explaining a drive wait compensation method according to a first embodiment. Fig. 10 is a flowchart explaining the drive wait compensation method according to the first embodiment. Fig. 11 is a block diagram explaining generation of a sampling flag for drive wait compensation according to the first embodiment. Fig. 12 is an illustrative diagram explaining a scan line for drive wait compensation according to the first embodiment.

[0055] As in Fig. 9, a light-emitting display device according to the first embodiment can operate in an order of drive preparation CONFIG, drive wait compensation LT-VSC, and normal drive NOR-DRV.

[0056] The control preparation CONFIG is a step of operating a basic configuration (the timing control of the Fig. 1, etc.) required for the light-emitting display device to operate upon application of power (AC and DC). Drive wait compensation (LT-VSC) is a step of scanning subpixels arranged on the display panel, thereby compensating for a drive wait state according to conditions set internally in the light-emitting display device, such as whether the light-emitting display device has been held (or left) without being driven for a long period of time. Normal drive (NOR-DRV) is a step of displaying an image on the display panel while driving the light-emitting display device under normal (or general) conditions.

[0057] Here, the drive wait compensation LT-VSC may be executed in a state where the display panel displays black on one screen thereof, but is not limited thereto. For example, the drive wait compensation LT-VSC may be executed while text such as "drive wait compensation" or "drive preparation" is displayed on the display panel screen. Of course, an area where text is displayed may be excluded from the display panel lines to be scanned.

[0058] As in Fig. 9 to Fig. As shown in Figure 12, the light-emitting display device may determine whether the state of a scan flag SFLAG is high (1) (an active state) (SFLAG == 1) (S10) or not. For example, the scan flag SFLAG may be generated in an image feeder (device or host system) 110 or may be generated in a timing controller 120. The image feeder 110 and the timing controller 120 may share the state of the scan flag SFLAG for efficient device control and compensation. Furthermore, if necessary, the scan flag SFLAG may be generated in the image feeder 110 upon request of the timing controller 120 or may be generated in the timing controller 120 upon request of the image feeder 110.

[0059] When the state of the sampling flag SFLAG is not high (1) (a low (0) or inactive state) (N), normal NOR-DRV driving can be performed without executing the LT-VSC drive wait compensation (S60). On the other hand, when the state of the sampling flag SFLAG is high (1) (Y), the LT-VSC drive wait compensation can be executed. This will be described below.

[0060] When the drive wait compensation LT-VSC starts, the light-emitting display device may scan N gate lines (where N is an integer of 1 or greater) of the display panel (S20). In a first example, the light-emitting display device may define a gate line arranged at a specific position of the display panel 150 as a scan line, as shown in an upper part of the Fig. 12, and may then scan the gate line. In a second example, the light-emitting display device may define three gate lines arranged at a specific position of the display panel 150 as scan lines (first scan line, second scan line, and third scan line), as shown in a lower part of the Fig. 12, and can then scan these gate lines one after the other.

[0061] Scanning a gate line may mean scanning subpixels corresponding to different colors included in the display panel 150. For example, if the display panel 150 is implemented based on pixels P, each comprising a red subpixel SPR, a white subpixel SPW, a green subpixel SPG, and a blue subpixel SPB, as shown in Fig. 3, color-based sampling voltages can be obtained from the subpixels in an associated manner.

[0062] The number of scan lines adjustable in the drive wait compensation LT-VSC can be defined to be a minimum of 1 to a maximum of 8 (i.e., N = 1 to 8). This is because, although there is an advantage in terms of accuracy improvement as the number of scan lines increases, a time cost should be considered in this case. Of course, this is only illustrative, and the present disclosure is not limited to the conditions described above.

[0063] Next, a threshold voltage change value ΔVth can be calculated based on the sampling voltages obtained for the subpixels connected to the N gate lines, and a relationship f(Vth) between the threshold voltage change value ΔVth and an initial threshold voltage (ΔVth = f(Vth)) can be derived (S30). Here, the relationship f(Vth) between the threshold voltage change value ΔVth and the initial threshold voltage can be derived based on a linear function having a slope and an intercept. This will be described later.

[0064] Next, it may be determined whether an average threshold voltage change value ΔVth_avg deviates from an internally set reference threshold voltage value THRESHOLD (ΔVth_avg > THRESHOLD) (S40). Here, if the average threshold voltage change value ΔVth_avg is used instead of the threshold voltage change value ΔVth, it may be possible to minimize or remove sampling noise that may be generated during sampling. However, this is only an illustrative method for minimizing or removing sampling noise, and it may be determined whether the threshold voltage change value ΔVth deviates from the internally set reference threshold voltage value THRESHOLD.

[0065] Thereafter, if the average threshold voltage change value ΔVth_avg does not deviate from the reference threshold voltage value THRESHOLD(N), normal NOR-DRV driving may be performed without executing a subsequent step S50 (S60). On the other hand, if the average threshold voltage change value ΔVth_avg deviates from the reference threshold voltage value THRESHOLD(Y), a step of applying the threshold voltage change value ΔVth to each pixel-based threshold voltage compensation value may be performed (S50).

[0066] After that, normal NOR-DRV driving can be performed because the drive waiting compensation LT-VSC is completed by performing the step of applying the threshold voltage change value ΔVth to each pixel-based threshold voltage compensation value (S60). Although the scan flag SFLAG may be maintained in a low state (a 0 state or an inactive state) during normal NOR-DRV driving, the scan flag SFLAG may return to an active state if the scan flag SFLAG does not meet the internally set conditions. This will be described below.

[0067] Fig. 13 is a conceptual diagram explaining whether or not the drive wait compensation according to the first embodiment has been executed and change of the sampling flag. Fig. 14 is a conceptual diagram explaining a modification of the first embodiment.

[0068] As if from a Fig. As can be seen from the D-FLOW operating sequence shown in Figure 13, the sampling flag SFLAG can be maintained for a first period TP1 and a second period TP2 because the manufacturer sets a basic state of the sampling flag SFLAG to high (1) after a final inspection F-INSF has been performed for the light-emitting display device.

[0069] The first period TP1 can be defined as a delivery waiting period or a transportation period of the light-emitting display device for which the final inspection F-INSF has been completed. Typically, the first period TP1 can be a relatively long period, which can be defined in units of days, for example, approximately 10 to 100 days.

[0070] The second period TP2 may be defined as the receipt inspection period used by a company receiving the delivered light-emitting display device. A receipt inspection period may vary according to different companies receiving the light-emitting display device, and therefore, no description thereof is provided.

[0071] Fig. 13 is an illustrative diagram showing that the light-emitting display device was turned on / off at a first time 1T, a second time 2T, and a third time 3T in the second period TP2, and the drive wait compensation LT-VSC was executed at the third time 3T. Executing the drive wait compensation LT-VSC at the third time 3T means that the drive wait compensation LT-VSC was not normally executed at the first time 1T and the second time 2T because the light-emitting display device was forcibly turned off at the first time 1T and the second time 2T.Here, “forcibly turned off” may not correspond to the case where the light-emitting display device is turned off using a remote control, but may correspond to the case where a power plug of the light-emitting display device is pulled out from a power outlet.

[0072] Meanwhile, the drive wait compensation LT-VSC, as described above, may have conditions that allow its execution if the state of the sample flag SFLAG remains high (1). Accordingly, the sample flag SFLAG may only transition to low (0) when a final compensation, which will be described later with reference to Fig. 14, even if the display panel is turned on / off multiple times in the second period TP2. A description associated with the final compensation may refer to the following description.

[0073] As in Fig. 14, the light-emitting display device according to the modification of the first embodiment can operate in an order of drive preparation CONFIG, drive waiting compensation LT-VSC, normal drive NOR-DRV, and final compensation PE-CMP.

[0074] In the case where the execution time of the normal NOR-DRV drive is long (that is, in the case where an image is displayed for a long time), the subpixels included in the display panel may deteriorate with the passage of time. As described above, the display panel included in the light-emitting display device may not only exhibit a change in characteristics caused by deterioration when the light-emitting display device is driven for a long time, but may also exhibit a change in characteristics even when the light-emitting display device is held (or left) without being driven for a long time.

[0075] Even though the drive waiting compensation LT-VSC was performed taking into account the characteristics described above, the modification of the first embodiment can perform the final compensation PE-CMP to compensate for the change of characteristics caused by the deterioration when the normal drive NOR-DRV was performed for a long time.

[0076] The final compensation PE-CMP may use the same sampling method as the drive-wait compensation LT-VSC. However, the final compensation PE-CMP may be different from the drive-wait compensation LT-VSC because the final compensation PE-CMP is included in a substantial degradation compensation. For example, the light-emitting display device may sample all gate lines of the display panel, thereby obtaining color-based sampling voltages, and may correspondingly change and update pixel-based threshold voltage compensation values, etc., based on the color-based sampling voltages.

[0077] When the final compensation PE-CMP is executed for a long time after the normal drive NOR-DRV is executed as described above, an additional change value can be concretely reflected in the threshold change value ΔVth reflected in each pixel-based threshold voltage compensation value in the drive waiting compensation LT-VST, and thus each pixel-based threshold voltage compensation value can be updated again. This means that the threshold voltage compensation value in which deterioration conditions have been reflected up to a final deterioration condition before the end of drive of the display panel can be provided, and thus compensation accuracy can be improved when the display panel is driven again.

[0078] As is apparent from the above description, the first embodiment can eliminate a problem of brightness change (screen spots or line- or block-shaped spots) caused by distortion of threshold voltage information, which may occur when the light-emitting display device is held (or left) for a long time without being driven.

[0079] Fig. 15 is a conceptual diagram explaining a drive wait compensation method according to a second embodiment. Fig. 16 is a flowchart explaining the drive wait compensation method according to the second embodiment.

[0080] As in Fig. 15 and Fig. 16, a light-emitting display device according to the second embodiment can operate in an order of drive preparation CONFIG, drive wait compensation LT-VSC, start compensation PS-CMP, and normal drive NOR-DRV.

[0081] According to the second embodiment, when the state of a scan flag SFLAG is not high (1) (low or 0) (N), the start compensation PS-CMP can be executed without executing the drive wait compensation LT-VSC (S60), and then the normal drive NOR-DRV can be executed (S70). Furthermore, when an average threshold voltage change value ΔVth_avg does not deviate from a reference threshold voltage value THRESHOLD (N), the start compensation PS-CMP can be executed (S60) even if the drive wait compensation LT-VSC is executed, and then the normal drive NOR-DRV can be executed (S70). Remaining steps are similar to those of the first embodiment and thus can refer to the description given in connection with the first embodiment.

[0082] PS-CMP start compensation can use the same sampling method as PE-CMP end compensation. When PS-CMP start compensation is executed after LT-VSC drive hold compensation is executed, compensation can be performed per pixel based on a threshold voltage compensation value that is updated along with the drive of the display panel, even if the light-emitting display device is held (or left) without being driven for a long time.

[0083] The start compensation PS-CMP and the end compensation PE-CMP correspond to a step of scanning all gate lines of the display panel before the display panel displays an image by driving them (immediately after the display panel is turned on) or after the display panel displays an image (immediately before the display panel is turned off) and performing pixel-by-pixel compensation based on threshold voltage compensation values when the display module is turned on / off, and thus can be included in a drive preparation compensation.

[0084] As apparent from the above description, the second embodiment can improve compensation accuracy by performing compensation on a pixel basis based on a threshold voltage compensation value that is updated along with driving of the light-emitting display device, even if the light-emitting display device is held (or left) for a long time without being driven.

[0085] Fig. 17 is a conceptual diagram explaining a drive wait compensation method according to a third embodiment. Fig. 18 is a conceptual diagram explaining whether or not drive wait compensation has been executed according to the third embodiment and a change of a sampling flag. Fig. 19 is a conceptual diagram explaining whether or not the drive wait compensation according to the third embodiment has been executed, a change of the sampling flag, and states according to various drive modes.

[0086] As in Fig. As shown in Figure 17, according to the third embodiment, a light-emitting display device can operate in an order of drive preparation CONFIG, drive waiting compensation LT-VSC, start compensation PS-CMP, end compensation PE-CMP, and normal drive NOR-DRV. The third embodiment can be selected in the case where reception control is performed for a long period of time.

[0087] As if from a Fig. As can be seen from the D-FLOW operating sequence shown in Figure 18, a sampling flag SFLAG can be maintained for a first period TP1 and a second period TP2 because the manufacturer sets a default state of the sampling flag SFLAG to high (1) after performing a final inspection F-INSF for the light-emitting display device. A third period TP3 corresponds to the normal NOR-DRV drive, which is executed after the sampling flag SFLAG transitions to low (0).

[0088] According to the third embodiment, the light-emitting display device may be set such that the state of the scanning flag SFLAG transitions to low (0) only when the final compensation PE-CMP is finally executed, even if the drive waiting compensation LT-VSC is executed alone or together with the start compensation PS-CMP in the second period TP2. In other words, the start compensation PS-CMP may be Fig. 17 can be omitted, that is, the light-emitting display device can operate in a sequence of drive preparation CONFIG, drive waiting compensation LT-VSC, final compensation PE-CMP and normal drive NOR-DRV.

[0089] Fig. 18 is an illustrative diagram showing that the light-emitting display device was turned on / off at a first time 1T, a second time 2T, and a third time 3T in the second period TP2, the drive wait compensation LT-VSC was executed at the first time 1T, and the final compensation PE-CMP was executed at the third time 3T. Executing the final compensation PE-CMP at the third time 3T may mean that the final compensation PE-CMP was not normally executed at the first time 1T and the second time 2T because the light-emitting display device was forcibly turned off at the first time 1T and the second time 2T.

[0090] As in Fig. As shown in Figure 19, the light-emitting display device may execute the drive waiting compensation LT-VSC multiple times in the second period TP2. This is because the sampling flag SFLAG remains high (1) until the final compensation PE-CMP is executed.

[0091] Fig. 19 is similar to Fig. 18, however, is an illustrative diagram showing that the sampling flag SFLAG may continuously remain high (1) unless the final compensation PE-CMP is normally executed, and sampling for executing the drive wait compensation LT-VSC (LT-VSC sampling) may also be executed every time the light-emitting display device is turned on / off.

[0092] Referring to a control mode DRVM, which is described in Fig. As shown in FIG. 19, a compensation process of the light-emitting display device may be divided into a drive waiting compensation process LT-CMP and a normal control compensation process NOR-CMP according to a state of the scan flag SFLAG. The compensation process performed during a period in which the scan flag SFLAG remains high (1) may be included in the drive waiting compensation process LT-CMP.

[0093] Accordingly, the start compensation PS-CMP of the Fig. 17 and the final compensation PE-CMP of the Fig. 18 and Fig. 19, along with the drive wait compensation LT-VSC, may be temporarily included in the drive wait compensation method LT-CMP. Compensation performed in a remaining period in which the display panel is normally driven may be included in the normal drive compensation method NOR-CMP. For example, a method for sensing and compensating for mobility of drive transistors included in subpixels in real time may be included in the normal drive compensation method NOR-CMP.

[0094] As is apparent from the above description, the third embodiment can eliminate, within a relatively short time, a problem of brightness fluctuation (screen spots or line- or block-shaped spots) caused by distortion of the threshold voltage information by forcibly performing pixel-by-pixel compensation based on a threshold voltage compensation value updated along with driving of the light-emitting display device, even if the light-emitting display device is held (or left) without being driven for a long time.

[0095] Fig. 20 is a conceptual diagram explaining a change of a sampling flag according to a fourth embodiment. Fig. 21 is a conceptual diagram explaining whether or not the drive wait compensation according to the fourth embodiment has been executed, change of the sampling flag, and states corresponding to various drive modes. Fig. 22 is a conceptual diagram explaining a modification of the fourth embodiment.

[0096] As in Fig. 20, according to the fourth embodiment, when a sampling flag SFLAG deviates from an internally set condition after transitioning from a high-level state (1) to a low-level state (0) (I > I_th), the sampling flag SFLAG may transition back to the high-level state (1). In this case, the sampling flag SFLAG may transition to the low-level state (0) after performing at least one drive wait compensation. This will be described below in conjunction with an example.

[0097] As if from a Fig. As can be seen from the D-FLOW operation flow shown in FIG. 21, the light-emitting display device may have a period in which the light-emitting display device is substantially not used, such as a usage waiting period, in addition to a delivery waiting period, a transportation period, and a receipt control period. The light-emitting display device may regenerate the sampling flag SFLAG in accordance with whether the light-emitting display device deviates from a usage waiting state (in time units of hours, days, or days and hours). This will be described below.

[0098] When the light-emitting display device is operated before deviating from the usage standby state (for example, in terms of time) (T < T_th), the light-emitting display device may not generate the sampling flag SFLAG again. In this case, the light-emitting display device may be in a state where final compensation PE-CMP has been completed after normal execution, as can be seen from a first time 1T and a second time 2T. For reference purposes, the sampling flag SFLAG may be generated again by an image feeder 110 or a timing controller 120, as shown in Fig. 11 can be seen.

[0099] On the other hand, when the light-emitting display device is not operated after deviating from the usage wait state (for example, in terms of time) (T>T_th), the light-emitting display device may generate the sampling flag SFLAG again. In this case, the light-emitting display device may set the sampling flag SFLAG to low (0) after performing at least one of the compensation processes included in the drive wait compensation process LT-CMP, as seen from a third time 3T.

[0100] Fig. 21 illustrates an example in which the light-emitting display device sets the scan flag SFLAG to low (0) after performing the drive wait compensation LT-VSC and the final compensation PE-CMP included in the drive wait compensation method LT-CMP. For reference purposes, conditions for setting the scan flag SFLAG to low (0) may be selected differently, as described in the previous embodiments.

[0101] As if from a Fig. As can be seen from the D-FLOW operation flow shown in FIG. 22, the light-emitting display device may have a period in which final compensation PE-CMP is not continuously executed, in addition to a delivery waiting period, a transportation period, a reception check period, and a usage waiting period. The light-emitting display device may regenerate the sampling flag SFLAG in accordance with whether or not the light-emitting display device deviates from an internally set final compensation execution state. This will be described below.

[0102] When the final compensation PE-CMP is normally executed, for example, at the first time T1 and the second time 2T, the light-emitting display device cannot generate the scan flag SFLAG again. In this case, the light-emitting display device can execute a normal drive wait compensation process NOR-CMP that does not include the drive wait compensation LT-VSC.

[0103] On the other hand, if the final compensation PE-CMP is not executed at internally specified timings, for example, from the third timing 3T to an n-th timing nT (C > C_th), (Failure) ("Failure" means not executing the final compensation), the light-emitting display device may again generate a high-level (1) sampling flag SFLAG. In this case, the light-emitting display device may set the low-level (0) sampling flag SFLAG after executing at least one of the compensation processes included in the drive waiting compensation process LT-CMP, as seen from an n+1-th timing n+1T.

[0104] Fig. 22 illustrates an example in which the light-emitting display device sets the scanning flag SFLAG to low (0) after performing drive wait compensation LT-VSC and final compensation PE-CMP included in the drive wait compensation process LT-CMP at the n+1th time n+1T. For reference purposes, the conditions for switching the scanning flag SFLAG to a low level (0) may be selected differently, as described in the previous embodiments.

[0105] As apparent from the above description, the fourth embodiment can improve compensation reliability of the light-emitting display device by forcibly performing the drive waiting compensation when a situation in which the light-emitting display device is held (or left) without being driven for a long period of time is repeated or when the end compensation is not appropriately performed.

[0106] Fig. 23 to Fig. 26 are diagrams explaining the contents involved in drive wait compensation according to the present disclosure. However, in the following description, only items that may be considered to find a solution that can improve compensation accuracy while minimizing or eliminating sampling noise, errors, etc. in the compensation of a threshold voltage of a drive transistor will be described.

[0107] As in Fig. 23, threshold voltage (Vth) fluctuation modeling S100, parameter modeling S110, compensation based on derived parameters S120, etc. may be considered to facilitate execution of drive waiting compensation according to the present disclosure.

[0108] Threshold voltage (Vth) fluctuation modeling S100 is a step of modeling threshold voltage fluctuations of color-based driving transistors of subpixels in a non-driving state (storage / transportation or the like) in which the light-emitting display device is not driven. A threshold voltage (Vth) fluctuation of each driving transistor can be modeled based on a linear function with a threshold voltage value of the driving transistor as a variable.

[0109] As in Fig. 24 and Fig. As shown in FIG. 25, threshold voltage fluctuations of the color-based driving transistors of the subpixels in the non-driving state in which the light-emitting display device is not driven may change according to temporal conditions, environmental conditions, etc., such as an increase in the storage (transportation) period, a change in a storage (transportation) environment, or the like. Accordingly, when modeling threshold voltage (Vth) fluctuations, it is preferable to refer to the characteristics described above. In addition, the threshold voltage (Vth) fluctuation modeling S100 may further include a modeling check for determining adequacy, effectiveness, consistency, etc. of a modeled value.

[0110] Parameter modeling S110 is a step of modeling a relationship between values before and after threshold voltage compensation for a driving transistor based on at least two parameters. It may be possible to model a relationship between a pre-storage threshold voltage compensation value COMP and a post-storage threshold voltage compensation value ΔCOMP of each of the color-based driving transistors of the R / W / G / B subpixels, as long as there are two parameters in a diagram modeled based on a linear function, that is, an x-intercept COMP_max and a slope COMP_slope, as shown in Fig. 26. The pre-storage threshold voltage compensation value COMP may be a threshold voltage compensation value of each driving transistor specified at a final inspection (or upon delivery) of the light-emitting display device, and the post-storage threshold voltage compensation value ΔCOMP may be a threshold voltage compensation value varied according to a driving waiting time of the light-emitting display device.

[0111] Since the threshold voltage fluctuation of each of the color-based driving transistors of the subpixels in a non-driving state (storage / transportation, etc.) can be derived based on a linear function, the modeling described above can be obtained as long as there are two pieces of pixel data that can provide two parameters. Accordingly, by sampling only one gate line and obtaining two pieces of pixel data, it may be possible to model a relationship between pre-threshold voltage values and post-threshold voltage values for each driving transistor.

[0112] Furthermore, on a gate line, there is not only one subpixel configured to emit one color, but also subpixels configured to emit a plurality of colors. Accordingly, even if only one gate line is scanned, relationships between pre-threshold voltage compensation values and post-threshold voltage compensation values for driving transistors can be provided for different colors of the R / W / G / B subpixels.

[0113] In addition, Fig.26 shows a modeling graph obtained based on average vertical data (3840 data obtained by averaging data of subpixels R / W / G / B, each formed from 2160 data). When a modeling graph for compensating for a non-drive state (storage / transportation or the like) is configured using only a part of the data, its accuracy may be reduced due to sampling noise, errors, etc. Accordingly, when the modeling graph is formed based on average data obtained by averaging a plurality of pieces of data obtained based on different colors of the subpixels R / W / G / B, it may be possible to minimize or eliminate noise or errors.

[0114] The compensation based on derived parameters S120 is a step of performing the above-described drive waiting compensation and compensating threshold voltages of color-based drive transistors of the subpixels in a non-drive state (storage / transportation or the like) based on the parameters derived by the modeling graph.

[0115] As apparent from the above description, the present disclosure has an effect that can eliminate a problem of brightness fluctuation (screen spots or line- or block-shaped spots) caused by distortion of threshold voltage information that may occur when the display device is held (or left) without being driven for a long time. Furthermore, the present disclosure has an effect that can improve compensation accuracy by performing compensation per pixel based on a threshold voltage compensation value that is updated along with the driving of the light-emitting display device, even when the light-emitting display device is held (or left) without being driven for a long time.Furthermore, the present disclosure has an effect that can improve the compensation reliability of the light-emitting display device by forcibly performing end compensation when a situation in which the light-emitting display device is held (or left) without being driven for a long time is repeated or when the end compensation is not appropriately performed. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] KR 10 - 2023 - 0 197 064

[0001]

Claims

[1] A display device comprising: a display module comprising a display panel (150) configured to display an image, a driver (130, 140) configured to drive the display panel (150), and a timing controller (120) configured to control the driver (130, 140); and a power supply (180) configured to supply power to drive the display module, wherein the display module is configured to operate in an order of drive preparation comprising operating a basic configuration required for operation of a device, drive wait compensation comprising scanning at least one gate line (GL1, ..., GLm) to compensate for a drive wait state of the display panel (150), and normal driving comprising displaying an image on the display panel (150). [2] The display device according to claim 1, wherein the display module is further configured to perform the drive wait compensation when a sampling flag (SFLAG) defined in the timing controller (120) is in an active state. [3] The display device according to claim 2, wherein the display module is further configured to perform drive preparation compensation between the drive waiting compensation and the normal drive for scanning all the gate lines (GL1, ..., GLm) of the display panel (150). [4] The display device according to claim 2 or 3, further arranged such that the scan flag (SFLAG) enters an inactive state after the drive wait compensation is performed. [5] The display device according to claim 4, further arranged such that the scan flag (SFLAG) maintains the inactive state during execution of the normal driving. [6] The display device according to claim 3 or any one of claims 4 and 5 dependent on claim 3, further arranged such that the scan flag (SFLAG) enters an inactive state after performing the drive wait compensation and the drive preparation compensation. [7] The display device according to any one of claims 2 to 6, further configured to regenerate the scan flag (SFLAG) to have the active state when the display device deviates from a use waiting state of the display panel (150). [8] The display device according to any one of claims 2 to 7, further configured to regenerate the scan flag (SFLAG) to have the active state when the display device deviates from a final compensation execution state of the display panel (150). [9] The display device according to any one of claims 1 to 8, wherein the display module is further configured to perform final compensation after the normal driving in order to compensate for a change in characteristics caused by deterioration when the normal driving has been performed. [10] The display device according to claim 3 or any one of claims 4 to 9 dependent on claim 3, wherein the drive preparation compensation comprises at least one of a start compensation and an end compensation. [11] A driving method of a display device comprising a display module including a display panel (150) configured to display an image, a driver (130, 140) configured to drive the display panel (150), a timing controller (120) configured to control the driver (130, 140), and a power supply (180) configured to supply power to drive the display module, the driving method comprising: Control preparation, comprising operating a basic configuration required for operation of a device included in the display module; Drive wait compensation, comprising sampling at least one gate line (GL1, ..., GLm) to compensate for a drive wait state of the display panel (150); and normal control, comprising displaying an image on the display panel (150). [12] The driving method according to claim 11, further comprising: Performing a drive preparation compensation for scanning all gate lines (GL1, ..., GLm) of the display panel (150) between the drive waiting compensation and the normal driving. [13] The driving method according to claim 11 or 12, wherein: the drive wait compensation is executed when a sample flag (SFLAG) defined in the timing controller (120) is in an active state; and the sampling flag (SFLAG) changes to an inactive state after the drive wait compensation is executed. [14] The driving method according to claim 13, wherein the scanning flag (SFLAG) is generated again to have the active state when the display device deviates from a use waiting state of the display panel (150) or a final compensation execution state of the display panel (150). [15] The driving method according to any one of claims 11 to 14, further comprising final compensation after the normal driving, which is performed to compensate for a change in characteristics caused by deterioration when the normal driving has been performed. [16] The driving method according to claim 12 or any one of claims 13 to 15 dependent on claim 12, wherein the driving preparation compensation comprises at least one of a start compensation and an end compensation. [17] A display device comprising: a display module comprising a display panel (150) configured to display an image, a driver (130, 140) configured to drive the display panel (150), and a timing controller (120) configured to control the driver (130, 140); and a power supply (180) configured to supply power to drive the display module, wherein the display module is configured to operate according to a state of a scan flag (SFLAG) for compensating for a change in the characteristics of the display panel (150) according to a drive waiting compensation method and a normal drive compensation method, wherein the display module is configured to operate according to the drive wait compensation method when the scan flag (SFLAG) is in an active state, wherein in the drive waiting compensation process, at least one of the drive waiting compensation, the start compensation and the end compensation is performed, and wherein in the normal driving compensation method, the display module is configured to operate in a normal driving manner including displaying an image on the display panel (150). [18] The display device according to claim 17, further configured such that the scanning flag (SFLAG) is generated to have the active state when the display device deviates from a use waiting state of the display panel (150) or a final compensation execution state of the display panel (150).

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