Pixelmatrixsteuerung

Abstract

Pixel matrix control (10, 10', 10'', 10''') for controlling at least three pixel groups (22a, 22b, 22c), having the following features: an image memory (14) for storing image data associated with the at least three pixel groups (22a, 22b, 22c); and a controller (12, 12') which is designed to read the image data from the image memory (14) in groups and to control the at least three image groups accordingly in groups, wherein the controller (12, 12') is designed to control the at least three image groups in a first and a second sequence.

Description

Embodiments of the present invention relate to a pixel matrix controller and to a display, in particular a microdisplay, a communication element and a corresponding method. Preferred embodiments relate to a programmable scanning device, in particular for ultra-flexible high-speed scan control of a microdisplay. Further exemplary embodiments describe a specific control of a row decoder of a display matrix. In general, exemplary embodiments are in the field of controlling a display, in particular a row decoder of a display matrix or generally a pixel matrix, as is also used in communication applications.According to the prior art, it is usual that the lines of a display or microdisplay are programmed in a scanning method, i.e. from top to bottom or vice versa sequentially line by line.Microdisplays describe displays having a typical display diagonal of from 0.1" to typically 1.5", some selected ones also up to 2.5". Such microdisplays are generally constructed in a stacked manner, that is to say the drive circuit is located directly below (therefore also referred to below as a backplane) the elements to be driven (also referred to below collectively as a front plane). Depending on the application and optical use of the microdisplay, these elements to be controlled can be a layer system for realizing an organic LED, an inorganic LED or else an LC material. The term "OLED microdisplay", "micro LED microdisplay" (also known as μLED or μLED as common notation) or "liquid crystal on silicon" (LCOS) microdisplay" is used accordingly. The control circuit is adapted to particular properties of the element to be controlled. Examples which may be mentioned here are: precise electrical actuation in the typical voltage range 3 V or higher, good current injection into the layer and measures for aging compensation in the case of OLED microdisplays, high current densities of >1 A / cm 2 for uLED microdisplay or just no static current flow into the element to be actuated in the case of LCOS microdisplays. To implement an active matrix display, the backplane includes electrical circuit components such as transistors, capacitors, or resistors. These can be implemented in different technologies. Thin-film transistors (TFTs such as IGZO, a-Si or LTPS) or the realization in single-crystal silicon may be mentioned here as examples. In the following, the further explanation is carried out without restriction on the basis of the monocrystalline silicon using CMOS circuit technology (other conceivable). However, due to the continued progress of TFT miniaturization, a partial realization on TFTs is also conceivable in perspective. Microdisplays based on a silicon backplane are realized according to the prior art mainly in the technology nodes 0.25 μm...90 nm. The majority of the microdisplays are driven by a video stream with a constant frame rate, that is to say, for example, with a video stream with 30 Hz, 60 Hz, 90 Hz, 120 Hz or 240 Hz. Hereinafter, this type of architecture is referred to as "frame rate-based architecture". There are few driving schemes deviating from this-an example is the so-called "memory-based architecture", an architecture for partially updating pixels (always describes the smallest element that can be driven independently of the other). It has been common to all these architectures up to now that, in addition to the control circuit for the optical elements, they comprise, as further circuit blocks, a row and column decoder, optionally a DAC functionality for "translating" the digital pixel data into current and voltage values for the pixel, and a block for realizing a display data interface (parallel interface, LVDS, SPI, or the like) as a function of the above-mentioned. The invention also relates to driving principles. This dependency results from the required data bandwidth: for example, a "frame rate-based architecture" requires a much higher data rate, since all display pixels are continuously overwritten-even if this is not required, because for example the value of the pixel has not changed at all. Here, a parallel interface (i.e. parallel digital single-ended lines, which together transmit the data value of the pixel or of a plurality of pixels, and further control lines, also referred to as digital RGB) or serial transmissions (e.g. LVDS low-voltage differential signaling) are usually used. Examples of these are for LCOS and for an OLED microdisplay. In such systems, a very complicated, external video control electronics are required, which implement a conversion to the interfaces mentioned. As a rule, this is done by a separate integrated circuit or an FPGA. This increases the required power consumption and the installation space (and is thus disadvantageous for the ergonomy of a system) both factors which are of great importance in numerous mobile ("wearable") applications. For the "memory-based architecture", on the other hand, the transfer of the changing pixels is sufficient. Depending on the application, the required transmission bandwidth is thus reduced considerably, so that less complex interfaces, such as SPI, are possible. In each of these cases, an adapted drive circuit is required.Typical control of microdisplay realizations thereby resort to a scanning method during line programming, i.e. a sequential programming of the lines in upward or downward direction takes place. For such a control, it is necessary for all lines to be written again and, above all, transferred. The renewed activation and data transmission costs resources, such as energy and computing performance, which has a negative effect on the overall efficiency of the microdisplay or, above all, on the efficiency of the activation. Particularly in microdisplays, energy efficiency is a decisive issue. In further applications of a pixel matrix, the refresh rate plays a decisive role. Therefore, there is a need for an improved approach.It is an object of the present invention to provide a concept for driving a pixel matrix, for example a display, which offers an improved compromise between efficiency, flexibility and display possibility, in particular sufficient image repetition rate.The object is achieved by the subject matter of the independent claims.Embodiments of the present invention provide a pixel matrix controller for driving at least three pixel groups, e.g. lines, of a display, in particular a microdisplay, or generally a pixel matrix. The pixel matrix controller comprises an image memory for storing image data associated with the at least three pixel groups (lines) and a controller which is designed to read out the image data from the image memory in groups and to actuate the at least three pixel groups in groups accordingly. The controller is configured to read out and control the at least three pixel groups (lines) in a first and a second order (e.g. 123 and 132, i.e. in a jumped order) or is configured to selectively control the at least three image groups, i.e. in a freely programmable order. According to exemplary embodiments, it is also conceivable that at least three or more sequences, i.e. first, second and third sequences (e.g. group 123 or 132 or 231 or 321) are used by the controller.If one starts from three pixel groups, which are to be understood as including in particular rows (alternatively columns or free-form regions), the first sequence can comprise driving the second of the at least three pixel groups directly after the first pixel group, while the second sequence comprises driving the third pixel group directly after the first. For at least four or more pixel groups, there are considerably more variational variants for the order, e.g. 1243, 1324, 3214, etc. Also, one pixel group can be omitted in one pass or one pixel group can be repeated in one pass. According to exemplary embodiments, it would also be conceivable for the activation of the pixel groups to pass through repeatedly. This free programmableness can be used in combination with a shortening of the sequence cycle time, for example by interleaving the control. The advantage of this actuation with the flexible sequence, regardless of the absolute number of pixel groups, is that the free programability of the scanning sequence of all lines thus created enables a very high image repetition rate from the integrated image memory, whereby optical ripple of the pixels is reduced (in display applications). This increased refresh rate is particularly decisive in the case of (optical) modulators for, for example, telecommunication or LIDAR.The exemplary embodiments of the invention describe an architecture of a freely programmable row decoder control, wherein the sequence of the programming is determined by a sequence stored in a memory present in the system but preferably integrated directly on the backplane and can be individually adapted for the respective application. Embodiments of the present invention are thus based on the realization that by integrating a flexibly controllable program memory, e.g. in a backplane (or display), the flexibility, image reproduction quality and also energy efficiency or general efficiency can be significantly increased. Flexible controllable means that a flexible scanning sequence of the rows of the pixel matrix is made possible during reading out and control. The possibility of reading image data selectively from an image memory and thus controlling individual pixel groups, i.e. for example individual lines in groups, will achieve the flexible scanning sequence. The result of this flexible actuation is evident in the departure from a fixed sequence, that is to say in the provision of at least two or more different (actuation) sequences.According to embodiments, the image memory is integrated directly into the backplane, e.g. the microdisplay, which has the consequence that the display matrix can be linked with a high bandwidth. The almost arbitrary sequence during reading allows free programability of the scanning sequence for all lines, which leads to a very high image repetition rate from the integrated image memory, whereby the optical ripple of the pixels is reduced (in display, but also in (light) scanning sequences decisive for telecommunication or LIDAR, for example). If, for example, at least three pixel groups, i.e. at least three lines, are used as the basis, the sequence can be defined, for example, during a pass in such a way that, in the first sequence, the two of the at least three pixel groups are driven directly after the first of the at least three pixel groups, wherein the second sequence is defined in that the third of the at least three pixel groups is driven directly after the first of the at least three pixel groups. Of course, any other sequence is also conceivable; for example, one of the at least three pixel groups, e.g. the second one, could be driven directly one after the other, i.e. twice (e.g. line 1223), or one of the at least three pixel groups could not be driven in one pass. If more than three pixel groups, for example four pixel groups or the lines, are used as the starting point, the number of possible permutation (with and without repetition) for the sequence is increased arbitrarily. Four or more pixel groups provide an embodiment in which the scalability of the approach becomes clear, i.e. that a plurality of display lines are programmable or programmable independently of one another. The controller is then designed according to exemplary embodiments to select further possible sequences or all further possible sequences. According to exemplary embodiments, the controller is designed to actuate the pixel groups repeatedly, for example with the same order of the previous order or with a new order during the repetition. If, for example, in the simplest exemplary embodiment, three pixel groups are used as the starting point, the second sequence can be used for the first repetition and the first sequence can be used for the second repetition, so that the sequence thus varies from iteration to iteration. Also, each iteration or even over several iterations one or more of the pixel groups can be controlled twice or more. This advantageously allows previously unachieved frame rates in microdisplays in the kilohertz range.According to exemplary embodiments, the controller is configured to transmit individual bits or image data associated with individual pixels sequentially to the respective one of the at least three pixel groups in order to actuate the respective one of the at least three pixel groups. Additionally or alternatively, individual bits assigned to individual pixels of the respective one of at least three pixel groups can be transmitted individually to the respective one of the at least three pixel groups in order to actuate the respective one of the at least three pixel groups pixel by pixel (e.g. half row or only individual pixels). According to exemplary embodiments, the controller may also be configured to actuate at least two of the at least three pixel groups or at least two regions of the pixel matrix to which the at least three pixel groups belong, with different resolutions or different resolution of a pixel intensity or different update rates. The background is that pixels, e.g. in the edge region, can be clustered (combined) by the flexible control and can thus be controlled jointly (called "binning"). Consequently, the resolution is different, e.g. reduced, at these positions. Thus, for example, a lower local resolution can be achieved in the edge region than in the middle. Analogously, individual pixels with a different depth (4 bits vs. 10 bits, for example in the brightness or gray value) can be controlled. These two approaches have an advantageous effect on efficiency.Furthermore, the controller according to exemplary embodiments may be designed to dynamically adapt the sequence of the pixel groups to be controlled at runtime, i.e. dynamic adaptation of the control with regard to local resolution, frequency and / or grey level resolution.According to embodiments, the pixel array controller may also include a command memory. Even if it is assumed in the above embodiments that the image memory and / or command memory is integrated in the backplane, it can also be arranged externally, i.e. as locally as an external part of the pixel matrix controller.For driving according to the flexible modes explained above, the pixel matrix controller may be configured to receive one or more commands from a group of commands comprising:programming command with selection of the pixel group;programming command with selection of the pixel group and with selection of the image memory address;programming command selecting the pixel group while selecting the bit significance;programming command with selection of the pixel group and selection of the pixel subgroup;- wait command;program flow controlprogramming command for instruction-based driving and / or for programmable driving and / or for driving in any order of the at least three pixel groups and / or for addressing driving.On the basis of this, the pixel controller then executes the commands, that is to say processes them, in order to correspondingly control the image memory and / or the at least three pixel groups of the display.According to a further exemplary embodiment, the controller can also be designed to actuate at least two of the at least three pixel groups simultaneously. This increases its complexity, but also makes it possible to further increase the frame rates of the microdisplay, which offers a significant advantage. This feature also contributes to the free programmableness.In the above embodiments, it was primarily assumed that the pixel groups represent lines, since the scanning sequence is permanently predefined in the case of prior art applications. According to exemplary embodiments, therefore, exactly this scanning sequence is flexible for the lines. According to further exemplary embodiments, instead of a row-by-row control of the pixel matrix, a column-by-column control of the pixel matrix can also be carried out. In this embodiment, the pixel group would then be a column. Generally speaking, the at least three pixel groups may represent different regions.According to a further exemplary embodiment, the actuation mode can also vary. For example, depending on the selected mode or depending on the selected range, an amplitude-modulated conversion, a time-modulated or a combined conversion of the image data can take place.According to further embodiments, the pixel matrix controller comprises a frame controller configured to control all of the at least three pixel groups. According to embodiments, this frame controller may be configured to perform a global brightness adjustment for all of the at least three pixel groups and / or perform a blanking and / or a brightness blanking and / or insert black images and / or insert inverted images. This has the advantage that optical effects (for example motion thickness, motion bur) can be reduced in this way, wherein, contrary to classic scanning architecture, no intervention in the external data pipeline is required.According to exemplary embodiments, an integrated, programmable solution is provided, which enables a flexible adaptation of the architecture to the front plane and to the application. This represents a significant competitive advantage because this architecture typically requires a very small CMOS processor node associated with significant NRE. Architecture flexibility extends the market that can be achieved with these products.A further exemplary embodiment provides a method for controlling at least three pixel groups, for example at least three lines of a display, in particular of a microdisplay. The method comprises the steps of reading image data belonging to the at least three pixel groups from an image memory, wherein the reading is effected group by group; and driving the at least three pixel groups group by group in accordance with the image data, wherein the at least three pixel groups can be driven in a first and in a second sequence.According to further exemplary embodiments, the method may be computer-implemented. That is, a computer program for carrying out the method is provided when the program runs on a processor or a controller as has just been explained.Embodiments of the present invention will be explained with reference to the accompanying drawings. The following are shown: FIG. 1 a shows a schematic block diagram of a pixel matrix controller according to a basic embodiment; FIG. 1 b shows a schematic block diagram of a pixel matrix controller (basic architecture) according to a further embodiment; FIG. 1 cshows a schematic flow diagram of a method for controlling according to an exemplary embodiment; FIG. 2 is a schematic illustration of different commands for processing in a pixel matrix controller according to embodiments; FIG. 3 shows a schematic illustration of a pixel matrix controller according to extended exemplary embodiments (multiple simultaneous activation of lines or pixel groups); FIG. 4 ashows a schematic block diagram of a pixel matrix controller according to extended embodiments with a frame controller; and FIG. 4 bshows a schematic block diagram of a pixel matrix controller according to extended exemplary embodiments with a frame controller (multiple simultaneous driving of rows or pixel groups); and FIG. 5 shows a schematic table for contrasting different modulation types to explain advantages of exemplary embodiments.Before exemplary embodiments of the present invention are explained below with reference to the attached drawings, it should be noted that elements and structures having the same function are provided with the same reference numerals, so that the description of the elements and structures that can be used or interchanged with one another is applicable.FIG. 1 ashows a pixel matrix controller 10 comprising the two central components controller 12 and memory 14. the controller 12 is here a so-called row controller, which is configured to access the data memory or frame buffer 14. Both units 12 and 14 are connected to the display matrix 20. The display matrix here is, for example, an n column matrix and m row matrix with thus n x m pixels. It is assumed that at least three pixel groups are provided here, in this case in the form of at least three lines 22 a, 22 band 22 c, which are controlled via the controller 12. The controller 12 is configured to retrieve, i.e., read out, image data associated with the at least three pixel groups from the image memory, and to drive the three lines 22 a, 22 band 22 ccorresponding to the image data group by group. In the prior art, the activation typically takes place in accordance with a predefined sequence, namely in the descending direction, that is to say 22 abefore 22 bbefore 22 c, or in the ascending direction, that is to say 22 cbefore 22 bbefore 22 a. This means that the at least three pixel groups or pixel lines 22 a- 22 care displayed one after the other, i.e. successively, in order to then be displayed again in the next iteration, wherein an update is possible. In the event that display lines do not change, the same line is displayed once again or further, the data volume nevertheless increasing accordingly, since the same information is loaded once again.According to exemplary embodiments, it is now possible for the controller 12 to access the memory 14 selectively and thus select image data for the at least three image groups or one of the at least three image groups, read out and use these to actuate the associated one of the at least three image groups, for example 22 aor 22 bor 22 c. This selectivity changes the sequence in the driving of the pixel groups or 22a, 22b and 22c.In the case of the three rows illustrated here by way of example, this results in at least the possibility of activation with at least two sequences, that is to say with at least a first and a second which differ from one another. It should be noted here that the sequence is not to be considered as rigid, but may vary from iteration to iteration. Individual activations of pixel groups can also be omitted or repeated several times during an iteration. It is thus possible to individually control the individual ones of the at least 3 pixel groups and thus only update the pixel groups for which an update is necessary. This means, conversely, that non-changing lines do not necessarily have to be recharged and controlled, but can simply be further represented. For other rows or pixel groups 22a-22c, the free resource may be used to increase the refresh rate. The result is a flexible scanning sequence of the lines 22 a- 22 cof the microdisplay 20 illustrated here, with the advantage of high frame rates, for example in the kilohertz range. The high refresh rates allow optical ripple of the pixels to be reduced.FIG. 1 cshows the method 100 behind it. The method 100 comprises the two basic steps 110 and 120. In the first step 110, the one or more image data are read out from the memory 14 by the controller 12, for example, in order then to actuate the at least three pixel groups 22 a- 22 cin groups. As explained above, the driving takes place in a freely programmable manner, so that the controller is designed to drive at least two different sequences of the driving of the at least three image groups with the lines 22 a- 22 cin the result.In the following, an extended variant of the controller 10, namely the controller 10', is explained with reference to FIG. 1 b. Compared to the controller 10, this device also has a program memory 13 which is directly connected to the controller 12. Before the embodiment of the variant 10' shown here is explained in detail, the mode of operation of the individual elements 12, 13, 14 and 20 will be discussed. The frame buffer 14 may be implemented in the microdisplay integrated memory and includes the image data of all or a part of the pixels. The data are written into the memory by an external interface (for example, HDMI, DP, MIPI, USB, LVDS, or the like) or created on the backplane itself (for example, by rendering a GPU).An embodiment defines a display with a corresponding controller 10 (12+14), the display having the matrix 20 and being driven by the controller 12. A further embodiment concerns the transfer of this data from the image memory into the pixel matrix.The controller, here line controller 12, comprises a line controller program memory 13. The program memory 13 contains the instructions which describe the sequence of programming (or else display). The line controller 12 evaluates the instructions accordingly from the program memory and controls both the frame buffer (i.e. selection of the image data of a line or part of a line requested by the instruction) and the selection of the pixel line to be programmed. It also ensures consistency of the data from the frame buffer to the selected pixel line (for example, by offset request of the data from the frame buffer, reading should be possible only by a data pipeline).As can be seen here, the line controller 12 directly controls the display matrix 20, wherein the data from the frame buffer 14 are output directly to the display matrix 20. For this purpose, a control connection is provided between the line controller 12 and the frame buffer 14, which directly addresses the data stored in the memory 14 for transmission to the matrix 20. The frame buffer transmits the data to the display matrix on the basis thereof, wherein the display matrix writes the respective line into the corresponding line of the display matrix by selection of the respective line by means of the line controller 12.The pixel array is preferably the pixel array of a microdisplay. Typically realized pixel sizes are in the range 4.3 μm×4.3 μm 4 or. 6.3 μm×2.1 μm 5 or 6.3 μm×2.1 μm. 9.3 μm×3.1 μm 6, i.e. generally in the range 2 μm to 9.5 μm or 1 μm to 10 μm or 1 μm to 15 μm pixel dimension. The second pixel dimension may be identical or even slightly varying with respect thereto, i.e. square and rectangular.The aim of the arrangement is to program the pixels of the pixel matrix with a freely programmable drive and thus variable drive sequence. This includes both writing the pixels with the entire data word of the pixel values to be displayed and parts thereof. The latter in the most consistent case merely comprises the programming of an individual bit of the data word, wherein the individual bits are programmed into the pixel sequentially and possibly differently weighted in time (and the weighting is dynamically programmable), and the mapping of the value results as an average value over time. Mixing forms then comprise a plurality of bits, it then also being possible for these bits to be amplitude-modulated, with only the individual parts of the real data value being time-modulated.According to exemplary embodiments, all four of the aforementioned components 12, 13, 14 and 20 are integrated on the microdisplay backplane (for microdisplays this is generally a circuit realized in CMOS) and can thus be combined in an extremely compact and power-saving manner in a system.According to embodiments, the image memory and the controller may be implemented as a common backplane (backplane) of a pixel array and / or the image memory, the controller and the pixel array may be implemented as a connected component.According to exemplary embodiments, a free programability of the transfer of the image contents from the image memory 14 into the pixel matrix 20 is created. This is realized by a program memory 13 which can contain different instructions which are interpreted and executed by the line controller 12. The basic structure of such an instruction consists here of an instruction code and a data area which realizes different functions depending on the instruction. Some embodiments of these instructions and their function / effect according to the invention are carried out below (cf. also FIG. 2 ):Individual exemplary commands are explained below with reference to FIG. 2. FIG. 2 shows a collection of six instruction instructions (exemplary structure) as stored in the line control program memory; these are numbered with the reference numerals 31, 32, 33, 34, 35, 36. The general construction provides that the instruction begin with an instruction code which allows different instructions to be distinguished (examples of possible line instructions are given). The instructions may comprise multiple parts, as evidenced by the addition of the Bezugszeichenergänzungen...a,...b,...c.• Scan programming instruction of a row 32: Besides encoding instruction 32a itself, the instruction includes only row 32b of the pixel array to be programmed. The line controller 12 converts this instruction by requesting the corresponding data in the image data memory. As soon as these are present at the pixel matrix, the row decoder is likewise addressed with the corresponding address by the row controller 12, whereby the pixel row matching the data is selected and the data is transferred into the pixels. In this case, both the entire line can be programmed with a single programming operation or, in the case of a limited bandwidth of the output side of the image memory, also only parts of a line can be programmed. In the latter case, the programming of the entire row is realized by sequential programming of the individual subareas. In addition, the architecture allows a row-specific repetition rate via the programming, that is to say individual regions of the pixel matrix up to individual rows can be provided with an individual repetition rate.• Scan program instruction of a row selecting the frame memory address 33: In this embodiment, in addition to the matrix row of the instruction 33a, the row address 33b and the data address 33c are added to the corresponding data in the frame memory. This enables a location-dependent influencing of the image content such as a summary of pixels, i.e. a local resolution reduction or, quite generally, a local resolution influencing or a location-dependent influencing of the resolution of the intensity gradation (optionally in combination with the instruction described below specifying the bit significance of the data word) of the pixel value or else a combination of the two to be realized. These possibilities can be used advantageously for so-called "evolved rendering" (reduced rendering expenses by reducing the image quality in the area of the peripheral vision, since in this area the human eye is less sensitive to such effects).• Scan programming command of a row with selection of bit significance 34: In addition to programming the complete data of a picture row, it may also be necessary to transfer only individual data bits from the picture memory to the pixel matrix. In this embodiment, in addition to instruction 34a, row address 34b, and for the response of the frame buffer, the desired bit significance (bitplane) 34c is added to the instruction. This is advantageous in particular if the pixels in the pixel matrix can receive only a single bit or parts (for example when realizing particularly small pixels) and the total pixel value is realized in the pixel via the temporal weighting of the individual bits (also referred to as bit plans in the totality). In this case, the instruction is extended by specifying the bit-plane number, that is to say the respective bit-plane significance (for example for a data value of 8 bits, this means 8 bit-planes and therefore a bit-plane number of 1 to 8 or 0 to 7). In this embodiment too, the programming of the entire row or also parts of a row is conceivable. In addition, with this command, in combination with the possibility of the individual row-specific repetition rate implemented by the architecture according to the invention, different regions of the pixel matrix having different bit depths averaged over time can be realized.• Scan programming command of one row selecting pixel group 35: In some applications, different functions are assigned to different pixels. The simplest example of this is the embodiment of a red, green and blue pixel (further example YUV or CYM, generalized pixel groups). If these are to be transmitted sequentially and / or independently to the pixel matrix or the selected row, the selection of the desired pixel group is likewise part of the instruction 35 a, 35 b, 35 c.• Wait instruction 36: The program memory is executed, for example, by continuously incrementing the address. Depending on the desired programming of the pixel matrix, the requirement arises, especially in the case of a temporal weighting, that the time must first be allowed to wait until the desired temporal weighting is reached. This requires the instruction wait command 36 which contains the number of cycles to wait as a parameter. Non-continuous address processing would also be possible, namely by program sequence control.• Program Flow Control: Furthermore, in addition to a wait command, further complex instructions for program flow control are conceivable, such as, for example, program end, jump, loop, wait for external events, jump to external events or the like.It is obvious that the above-mentioned results are shown. Examples result in further complex instructions in an application-specific manner, such as, for example, the selection of the bit map of a specific color or the selection of a specific line for a specific time. Further embodiments of this architecture include a customized CPU-like implementation of the row controller or a reduced instruction set computer (RISC), CISC (complex instruction set computer) or a very large instruction word (VLIW) based architecture.According to further exemplary embodiments, it would be conceivable for the controller and the image memory to be designed to actuate two or more groups 22 a- 22 c, that is to say, for example, two lines, simultaneously. The background is that in small CMOS process nodes the above-described arrangement can be highly parallelized (i.e. output of a complete pixel line from the integrated frame buffer) and realized with high frequency. The refresh rate from the image memory into the pixels that can be realized with this can thus be increased by a multiple depending on the embodiment and can thus allow very high modulation frequencies (for example 240 Hz, 480 Hz, 1 kHz, 5 kHz, 10 kHz, 20 kHz, 50 kHz, 100 kHz and more) that are far above those of conventional video microdisplays (typically 60 Hz, 120 Hz or 240 Hz). This is made possible to a particular extent by the free programability of the sequence of the line scan and the connection of the pixel matrix to the frame buffer with a high bandwidth, since the updating of the individual lines is thus interleaved, the number of required wait cycles is minimized and the image repetition rate can thus be increased.According to further embodiments, the architecture allows further scaling. If the writing of a single pixel row requires too long a row time for the desired refresh rate, the architecture can be extended by the possibility of programming a plurality of rows simultaneously (implementation of parallelization, cf. FIG. 3 ).Figure 3 shows a scaled architecture controller 10'' for multiple (simultaneously) scanned lines. The controller 10'' is substantially comparable to the controller 10', i.e. it has the components 13, 14 and 20. In contrast to the controller 10', the controller 10'' however has the controller 12'' which is designed to select a plurality of the m lines and to drive the display matrix 20 simultaneously therewith. In this case, a plurality of lines are encoded in the instruction or a combination of a plurality of adjacent lines to form a common pixel group can be carried out, which is then programmed together. Moreover, different parallel programmed row groups at different positions of the pixel matrix are conceivable as a further expansion stage. Grouping together a plurality of rows into a pixel group shortens the instruction length (for example, whenever 4 consecutive rows are merged), since only the base address of the 4th group has to be encoded in the instruction and not the individual addresses of all 4 rows. These expansion stages can reduce the effective number of required line programming operations and thus further increase the refresh rate. According to the invention, this further expansion stage can be combined with the instruction types explained above.The prior art embodiments thus far only involve the cyclical execution of the instructions of the line controller program memory. If, on the other hand, global weighting of the line programming is to be realized, an implementation at the level of the line program memory is quite complicated. The arrangement according to exemplary embodiments can therefore be extended by a superordinate frame controller, which can be synchronized with the row drive via the "frame" synchronization signal. The sync signal is denoted by reference numeral 29.FIG. 4 ashows a developed architecture extended by an (optional) programmable frame controller 27, which enables the global modulation of the signals. The higher-order frame controller 27 is implemented as part of the controller 10'''. The controller 10 in turn has the individual controller 12, here the line controller 12, and the memory 14 for controlling the display matrix 20. In addition, in this exemplary embodiment, the line controller memory 13 and also a frame controller memory 28 are also provided. The frame controller 28 is arranged between the line controller 12 or memory 14 and the display matrix 20.The frame controller 28 modulates not individual lines 22a-22c but complete frames, contrary to the line controller 12. Thus, for example, a global brightness setting can be realized by blanking entire frames. In addition, blanking may also provide for the reduction of optically perceived effects, such as motion-bluing. In current displays, this blanking must be implemented by the external data provision, as a result of which a higher data rate is externally necessary, including the associated disadvantages of increased current consumption by charge reversal of higher line capacitances in the system electronics, increased circuit complexity in the electronics, lower maximum line length and interference sensitivity. By implementing as an embodiment of the architecture discussed, this disadvantage can be avoided since the frame controller uses the information about the blanking, for example (data is read once and kept constant; this allows for a lower energy consumption). In the most consistent embodiment, the reading of the data from the memory for further reducing the current consumption in the case of blanking can be replaced by constant data. The frame controller 28 can additionally perform further functions, such as image inversion or also light keying. The frame controller realizes a time-controlled modification of the line selection and / or of the pixel data of the frame buffer. If complex sequences of the functions of the frame controller 27 are to be realized, the frame controller, like the line controller 12, can be provided with a program memory 28. This enables instruction-based, application-specific programming in an analogous manner to the line controller program memory 13.FIG. 4 bshows a further embodiment of the architecture extended by an (optional) programmable frame controller 27, wherein this is designed for the simultaneous actuation of a plurality of lines (cf. actuation between controller 12 and controller 27 or between memory 14 and controller 27 and actuation between controller 27 and matrix 20). The exemplary embodiment from FIG. 4 b corresponds otherwise to the exemplary embodiment from FIG. 4 a.Another embodiment contemplates implementing both a separate row controller program memory 13 and a frame controller program memory 28 for individual groups of pixels so as to implement multiple individually programmable pixel groups.That is to say, that, according to exemplary embodiments, a pixel matrix can be divided into groups of pixels. For example, the pixel array may have 2, 3 or 4 or any number >1 group, each having its own controller 12 with optional program memory 13 and frame memory 14. Each of these groups can also have its own frame controller 27 with optional programming memory 28 or a frame controller 27 shared between the groups. In addition to the local structuring into pixel groups in the sense of rows or columns, the pixel matrix can also have a plurality of differently colored elements (e.g. RGB) per pixel. That is to say that the pixel matrix drive can therefore be designed multiple times for subareas and subgroups.It should be noted that embodiments may also include row and column swapping.This free programmableness can be used in combination with a shortening of the sequence cycle time, for example by interleaving the control. The background will be explained with reference to FIG. 5.FIG. 5 shows a table for contrasting different modulation schemes with different compromise between display accuracy and sequence sweep time or update rate for explaining the possible shortening of the sequence sweep time and associated increasing image repetition rates.The internal image update rate is defined primarily by the length of the scan sequence, i.e. the number of commands and wait states in the command program memory. To emphasize this effect, along with the backplane's capabilities to drive different schemes based on the flexible instruction memory architecture, three typical scan schemes for display applications are discussed:PWM: Pulse width modulation is a known approach to approximating an analog value by switching between two digital states. There are many different types of PWM, but the binary weighted bit plane scheme (each for each individual bit of the tone scale resolution, from MSB to LSB) is the most common in display applications. This is accompanied by a very good representation of the digital data value. However, the entire sequence must be relatively long to avoid pixel line programming conflicts in the LSB bit plane. In order to maintain correct values, many wait states must be introduced, especially in the MSB bit plane. This significantly reduces the achievable update rate. This is the motif for the two schemes / approaches that follow.Shortest Scan 1: This scan scheme aims at the shortest possible sequence using only successive programming commands. Wait states are implemented only to fill the pattern. In this sense, the optimum sampling approach follows the concept of the shortest possible pattern and thus a maximum internal update rate, although considerable errors must be accepted in the mapping of the values.Skip Sampling 2: This approach attempts to balance between the two previous schemes by accepting a slightly longer sequence, but also keeping errors within reasonable limits.Further details about the characteristic variables scan length and error can be gathered from the table from FIG. 5.An embodiment provides a display, e.g., microdisplay, with one of the (integrated) pixel array controls discussed above. Possible technical realization here is OLED.A further embodiment relates to a communication element for transmitting data using a pixel matrix and one of the above-explained (integrated) pixel matrix controllers. The communication element may comprise e.g. the pixel matrix as well as the pixel matrix controller. Possible examples of a communication element are satellite communication stations or satellite communication base stations, an optical multiplexer. A possible technical realization here is LCD or microLED.Another embodiment relates to a pixel array optical multiplexer or LIDAR element as well as the pixel array controller. The communication element or 1 Yuan Ji et al., "Optimum scan strategy for mega-pixels and kilo-gray-level OLED-on-silicon microdisplay". Applied Optics 51.17 (June 2012), page 3731. doi: 10.1364 / ao.51.003731. 2 Mutsumi Kimura et al. "Time-Ratio Grayscale and Hopping Scan with Current Uniformization for Thin-Film Transistor Driven Organic Light-Emitting Diode Displays". In: Japanese Journal of Applied Physics 45.5B (2006), pp. 4407-4412. doi: 10.1143 / JJAP.45.4407. the multiplexer and the LIDAR element benefit, among other things, from the high "image" repetition rate.Features or optional features discussed in connection with the microdisplay can also be used to discuss the applications just explained, namely communication element, multiplexer or LIDAR element, which likewise use pixel matrix.According to a further exemplary embodiment, a microdisplay, such as the display of a wearable, a microdisplay for use in augmented reality (AR), for use in virtual reality (VR), for use in mixed reality (MR), is used. According to a further exemplary embodiment, a spatial light modulator, i.e. a spatial light modulator, is provided for purposes of holography, telecommunication, optical data transmission, LIDAR technology or space technology, etc.According to exemplary embodiments, the microdisplay architecture is characterized in that the pixel data are read out from an integrated image memory, wherein the programming sequence and manner of the individual lines or pixel groups is determined by flexibly programmable instructions from a likewise integrated line controller program memory or pixel group controller program memory and is possible in any desired sequence.According to embodiments, individual bits of the pixel data of the individual pixels can be transmitted into the pixel matrix sequentially (in any programmable sequence of the lines).It should be noted that, according to embodiments, multiple bits (or all bits) of the pixel data may be simultaneously transferred into the corresponding pixel of the pixel matrix sequentially (in any programmable sequence of rows).According to embodiments, two, more or all pixels of all rows may be programmed with a single or all bits.According to one embodiment, the architecture is extended so that not only a single row but multiple rows can be programmed simultaneously and individual, multiple or all pixels of these selected rows are programmed.According to an embodiment, the programming is designed such that different regions of the pixel matrix are programmed with a different local resolution or / and a different resolution of the pixel intensity valueAccording to an embodiment, the programming is designed such that different regions of the pixel matrix are programmed with different repetition rates.According to embodiments, the programming of the different local resolutions and / or different resolutions of the pixel intensities can be adapted at runtime. According to exemplary embodiments, it would be conceivable for parts of the data to be amplitude-modulated and for parts of the data to be converted in the pixel in a time-modulated manner via the programmable line program memory.It should be noted here that, according to embodiments, the pixel array control is comparable in complexity of a CPU (computer processor unit), GPU (graphics processor unit) or DSP (digital signal processor unit). The complexity can be evaluated, for example, on the basis of the number of transistors, on the basis of the number of computing operations which can be carried out in parallel, on the basis of the scope of the instruction set. The pixel matrix controller explained here according to exemplary embodiments is more similar to a CPU, GPU or DSP, such as an ARM core, for example, than to a purely instruction-based control unit, as is otherwise typical for pixel matrix elements. According to embodiments, the pixel matrix controller may be configured to execute at least two or more processes simultaneously and / or process image data. The GPU can also be designed to decide which of the at least three pixel groups are driven at a high repetition rate (high refresh rate or update rate) and which are driven at a comparatively slower rate. This can occur as a function of information or states. Also, the control can be selected generally depending on this information or states. This means that it would be conceivable according to exemplary embodiments for the pixel matrix controller to determine which of the at least three pixel groups is actuated on the basis of further information or states, such as temperature states, for example. The setting takes place according to exemplary embodiments at runtime. Furthermore, it is also possible to determine at runtime by the pixel matrix controller which row is updated and which row is not.According to one exemplary embodiment, a frame controller may additionally be provided, which is designed to insert dark images, bright images or inverted images into the modulation. According to an embodiment, the modulation for individual pixel groups may be programmed differently by implementing individual cell controller program memories and / or image controller program memories in the architecture.Although some aspects have been described in connection with a device, it is understood that these aspects also represent a description of the corresponding method, so that a block or a component of a device is also to be understood as a corresponding method step or as a feature of a method step. Analogously, aspects described in connection with or as a method step also represent a description of a corresponding block or detail or feature of a corresponding device. Some or all of the method steps may be performed by a hardware apparatus (or using a hardware apparatus) such as a microprocessor, a programmable computer, or an electronic circuit. In some embodiments, some or more of the most important method steps may be carried out by such an apparatus.A signal encoded according to the invention, such as an audio signal or a video signal or a transport stream signal, can be stored on a digital storage medium or can be transmitted on a transmission medium, such as a wireless transmission medium or a wired transmission medium, e.g. the InternetDepending on certain implementation requirements, embodiments of the invention may be implemented in hardware or in software. The implementation can be carried out using a digital storage medium, for example a floppy disk, a DVD, a Blu-ray disk, a CD, a ROM, a PROM, an EPROM, an EEPROM or a FLASH memory, a hard disk or another magnetic or optical memory, on which electronically readable control signals are stored, which can cooperate or cooperate with a programmable computer system such that the respective method is carried out. Therefore, the digital storage medium may be computer readable.Some embodiments according to the invention thus comprise a data carrier having electronically readable control signals which are capable of interacting with a programmable computer system in such a way that one of the methods described herein is carried out.In general, embodiments of the present invention can be implemented as a computer program product having a program code, wherein the program code is operative to perform one of the methods when the computer program product runs on a computer.The program code can also be stored on a machine-readable carrier, for example.Other embodiments include the computer program for performing any of the methods described herein, wherein the computer program is stored on a machine readable carrier. In other words, an exemplary embodiment of the method according to the invention is thus a computer program which has a program code for carrying out one of the methods described herein when the computer program runs on a computer.A further embodiment of the methods according to the invention is thus a data carrier (or a digital storage medium or a computer-readable medium) on which the computer program for carrying out one of the methods described herein is recorded.A further exemplary embodiment of the method according to the invention is thus a data stream or a sequence of signals which represents or represent the computer program for carrying out one of the methods described herein. The data stream or sequence of signals may be configured, for example, to be transferred over a data communication link, for example, over the Internet.A further embodiment comprises a processing device, for example a computer or a programmable logic device, configured or adapted to perform one of the methods described herein.A further embodiment comprises a computer on which the computer program for carrying out one of the methods described herein is installed.A further embodiment according to the invention comprises an apparatus or a system which is designed to transmit a computer program for carrying out at least one of the methods described herein to a receiver. The transmission can be carried out electronically or optically, for example. The receiver may be, for example, a computer, a mobile device, a storage device, or similar device. The apparatus or system may, for example, comprise a file server for transmitting the computer program to the recipient.In some embodiments, a programmable logic device (e.g., a field programmable gate array, an FPGA) may be used to perform some or all of the functionalities of the methods described herein. In some embodiments, a field programmable gate array may cooperate with a microprocessor to perform any of the methods described herein. Generally, in some embodiments, the methods are performed by any hardware device. This can be universally usable hardware such as a computer processor (CPU) or hardware specific to the method, such as an ASIC.The above-described embodiments are merely illustrative of the principles of the present invention. It is to be understood that modifications and variations of the arrangements and details described herein will be apparent to others skilled in the art. Therefore, it is intended that the invention be limited only by the scope of the following claims and not by the specific details presented herein by way of description and explanation of the embodiments.References included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Cited Non-Patent LiteratureYuan Ji et al., "Optimal scan strategy for mega-pixels and kilo-gray-level OLED-on-silicon microdisplay". Applied Optics 51.17 (June 2012), pp. 3731. doi: 10.1364 / ao.51.003731

[0056] Mutsumi Kimura et al., "Time-Ratio Grayscale and Hopping Scan with Current Uniformization for Thin-Film Transistor Driven Organic Light-Emitting Diode Displays". In: Japanese Journal of Applied Physics 45.5B (2006), pp. 4407-4412. doi: 10.1143 / JJAP.45.4407

[0056]

Claims

Pixel matrix controller (10, 10', 10", 10"') for driving at least three pixel groups (22a, 22b, 22c) of a pixel matrix (20), in particular a pixel matrix (20) of a display or of a microdisplay, having the following features: an image memory (14) for storing image data associated with the at least three pixel groups (22a, 22b, 22c); and a controller (12, 12') which is designed to read out the image data from the image memory (14) in groups and to drive the at least three image groups in a corresponding group-by-group manner, wherein the controller (12, 12') is designed to drive the at least three image groups in a first and in a second order.The pixel array controller (10, 10', 10", 10"') of claim 1, wherein the controller (12, 12') is configured to drive the at least three image groups in a third order; and / or wherein the first order defines that the second of the at least three pixel groups (22a, 22b, 22c) is driven directly after the first of the at least three pixel groups (22a, 22b, 22c), wherein the second order defines that the third of the at least three pixel groups (22a, 22b, 22c) is driven directly after the first of the at least three pixel groups (22a, 22b, 22c).Pixel matrix controller (10, 10', 10", 10"') according to one of the preceding claims, wherein the pixel matrix controller (10, 10', 10", 10"') is designed to drive at least four pixel groups (22a, 22b, 22c).The pixel array controller (10, 10', 10", 10"') according to any one of the preceding claims, wherein the controller (12, 12') is configured to sequentially transmit individual bits of the image data associated with individual pixels to the respective one of the at least three pixel groups (22a, 22b, 22c) to drive the respective one of the at least three pixel groups (22a, 22b, 22c), or to individually transmit individual bits associated with individual pixels of the respective one of at least three pixel groups (22a, 22b, 22c) to the respective one of the at least three pixel groups (22a, 22b, 22c) to drive the respective one of the at least three pixel groups (22a, 22b, 22c) pixel by pixel.Pixel matrix controller (10, 10', 10", 10"') according to one of the preceding claims, wherein the controller (12, 12') is configured to drive at least two of the at least three pixel groups (22a, 22b, 22c) or at least two regions of the pixel matrix (20) with different local resolution and / or different resolution of a pixel intensity value and / or different update rate.Pixel matrix controller (10, 10', 10", 10"') according to one of the preceding claims, wherein the controller (12, 12') is designed to dynamically adapt the sequence of the pixel groups to be controlled at runtime.Pixel array controller (10, 10', 10", 10"') according to one of the preceding claims, wherein the pixel array controller (10, 10', 10", 10"') is configured to receive one or more commands from a group of commands and to process them in such a way as to drive the image memory (14) and / or the at least three pixel groups (22a, 22b, 22c) of the display accordingly, wherein the group of commands comprises the following: - programming command with selection of the pixel group (22a, 22b, 22c); - programming command with selection of the pixel group (22a, 22b, 22c) and with selection of the image memory address; - programming command with selection of the pixel group (22a, 22b, 22c) with selection of the bit significance; programming command with selection of the pixel group (22a, 22b, 22c) and selection of the pixel subgroup; wait command; program sequence control; programming command for instruction-based driving and / or for programmable driving and / or for driving in any order of the at least three pixel groups and / or for addressing driving.The pixel array controller (10, 10', 10", 10"') according to any of the preceding claims, wherein the pixel array controller (10, 10', 10", 10"') is configured to have a CPU / GPU / DSP comparable complexity or to have a number of transistors or functional elements or implemented instructions comparable to a GPU, CPU, DSP; and / or wherein the pixel matrix controller (10, 10', 10", 10"') is configured to perform a plurality of processes in parallel and / or process image data and / or is configured to update individual ones of the at least three pixel groups (22a, 22b, 22c) at a higher rate than other pixel groups and / or to perform the driving as a function of further information and / or as a function of further states and / or is configured to determine at runtime which of the at least three pixel groups (22a, 22b, 22c) is updated.Pixel array controller (10, 10', 10", 10"') according to one of the preceding claims, wherein the image memory (14) and the controller (12, 12') are realized as a common backplane of a pixel array or the image memory (14), the controller (12, 12') and the pixel array are realized as a connected component.Pixel matrix controller (10, 10', 10", 10"') according to one of the preceding claims, wherein the controller (12, 12') is designed to drive at least two of the at least three pixel groups (22a, 22b, 22c) simultaneously.The pixel array controller (10, 10', 10", 10"') according to any of the preceding claims, wherein the at least three pixel groups (22a, 22b, 22c) define regions of the pixel array (20); and / or wherein the at least three pixel groups (22a, 22b, 22c) comprise rows of the pixel array (20) or columns of the pixel array (20); wherein the at least three pixel groups (22a, 22b, 22c) comprise multiple regions, columns, rows or multiple consecutive regions, columns, rows.Pixel matrix controller (10, 10', 10", 10"') according to one of the preceding claims, wherein controller (12, 12') is designed to convert the image data amplitude-modulated and / or time-modulated depending on the selected mode and depending on the range.The pixel array controller (10, 10', 10", 10"') according to any one of the preceding claims, further comprising a frame controller (27) configured to control all of the at least three pixel groups (22a, 22b, 22c).The pixel array controller (10, 10', 10", 10"') according to claim 13, wherein the frame controller (27) is configured to perform global brightness adjustment for all of the at least three pixel groups (22a, 22b, 22c) and / or perform blanking and / or perform blanking and / or insert black images and / or insert inverted images.The pixel array controller (10, 10', 10", 10"') of claim 13 or 14, wherein the frame controller (27) is connected to a frame controller program memory (28) or comprises a frame controller program memory (28).Pixel matrix controller (10, 10', 10", 10"') according to one of the preceding claims, wherein the pixel matrix drive (10, 10', 10", 10"') is designed multiple times for subareas and subgroups.A communication element, optical multiplexer or lidar element with a pixel matrix controller (10, 10', 10", 10"') according to one of the preceding claims.Display, in particular microdisplay with a pixel matrix controller (10, 10', 10", 10"') according to one of Claims 1 - 16.Method for driving at least three pixel groups (22a, 22b, 22c) of a pixel matrix (20), in particular a pixel matrix (20) of a display or of a microdisplay, comprising the following steps; reading out image data belonging to the at least three pixel groups (22a, 22b, 22c) from an image memory (14), wherein the reading out takes place group by group; and driving the at least three pixel groups (22a, 22b, 22c) group by group in accordance with the image data, wherein the at least three pixel groups (22a, 22b, 22c) can be driven in a first and in a second sequence.Computer program for carrying out the method according to Claim 19, when the program runs on a processor and / or a controller (12, 12').

Images