Method for verifying a modulation of a phase-locked loop

Abstract

The invention relates to a method (100) for verifying a modulation of a phase-locked loop (1), comprising the following steps: - determining (101) a state of a divider module (2) of the phase-locked loop (1) at the start of the modulation, wherein the divider module (2) provides a clock frequency of the modulation based on an oscillation frequency of the phase-locked loop (1), - determining (102) a number of cycles of the phase-locked loop (1) completed at the end of the modulation, taking into account a number of output edges of the divider module (2) and the determined state of the divider module (2) of the phase-locked loop (1), - calculating (103) a number of cycles of the phase-locked loop (1) to be run through for the modulation, wherein the number is calculated on the basis of at least one modulation parameter of the modulation, - Verifying (104) the modulation on the basis of a comparison of the calculated number of cycles to be run through with the determined number of cycles run through the phase-locked loop (1). Furthermore, the invention relates to a computer program, a device and a storage medium for this purpose.

Description

[0001] The invention relates to a method for verifying a modulation of a phase-locked loop. Furthermore, the invention relates to a computer program, a device, and a storage medium for this purpose. State of the art

[0002] A phase-locked loop (PLL) is a control system that stabilizes an output frequency by synchronizing it to a reference frequency. This is achieved by continuously adjusting the phase of the oscillator to match the phase of the reference signal.

[0003] With a phase-locked loop, modulation can be performed in the sense of a targeted change in the frequency of the oscillator (VCO) controlled by a phase-locked loop (PLL), for example, using a frequency divider. For linear frequency modulation, for example, the frequency of the VCO is varied from a starting frequency to a final frequency, with a defined gradient of the frequency change over time.

[0004] During this modulation of the VCO frequency, various errors can occur that impair correct implementation. A "cycle slip", for example, can lead to a sudden and unexpected change in the phase difference between the input (reference) and the output (VCO) signal. This results in a momentary interruption of the phase synchronization between these signals. In simple terms, the PLL slips by one or more cycles of the input signal, which can lead to a temporary loss of synchronization. Cycle slips can be caused by various factors, such as sudden changes in the input frequency, signal interruptions, noise, non-ideal component properties or rapid changes in the control conditions. A cycle slip leads to a short-term misalignment in the phase of the output signal compared to the reference signal.This can be particularly problematic in communications systems, as it can lead to data errors or loss of signal integrity. Therefore, in many applications, it is important to detect and handle errors such as cycle slips.

[0005] DE 21 2017 000 244 U1 describes a system with phase-synchronized local oscillator paths.

[0006] DE 10 2020 123 010 A1 discloses a method and apparatus for fractional N frequency synthesis using a phase-locked loop.

[0007] A phase detector of the phase-locked loop determines a phase difference between a clock and a feedback clock. Disclosure of the invention

[0008] The subject matter of the invention is a method having the features of claim 1, a computer program having the features of claim 8, a device having the features of claim 9, and a computer-readable storage medium having the features of claim 10. Further features and details of the invention emerge from the respective subclaims, the description, and the drawings. Features and details described in connection with the method according to the invention naturally also apply in connection with the computer program according to the invention, the device according to the invention, and the computer-readable storage medium according to the invention, and vice versa, so that with regard to the disclosure of the individual aspects of the invention, reference is or can always be made to each other.

[0009] The invention particularly relates to a method for verifying a modulation of a phase-locked loop, comprising the following steps, wherein the steps can be carried out repeatedly and / or sequentially. In the context of the present invention, the modulation relates in particular to the targeted change of an output frequency of the oscillator (VCO) controlled by the phase-locked loop (PLL) by means of a divider module. Any frequency or phase modulations are conceivable. If, for example, linear frequency modulation is to be operated, the output frequency of the VCO is preferably varied from a start frequency to an end frequency, with a defined gradient of the frequency change over time. The gradient of the frequency change relates in particular to the rate at which the output frequency of the VCO is changed over time.Various modulation parameters can be specified for the modulation, such as the start frequency, the end frequency, the slope of the frequency change or a duration of the modulation.

[0010] In a first step, a state of a divider module of the phase-locked loop is preferably determined at the start of the modulation, wherein the divider module provides a clock frequency for the modulation based on an oscillation frequency of the phase-locked loop. The state of the divider module can also be referred to and understood as the internal state of the divider module. The divider module is, in particular, a frequency divider and can be arranged in a feedback path of the phase-locked loop. The output signal of the controlled oscillator (VCO) is, in particular, passed through the divider module. The divider module reduces the frequency of the VCO signal by a fixed or programmable factor. For example, a divider module configured to four could divide the frequency of the oscillator signal, i.e., the oscillation frequency, by four.The state of the divider module specifies in particular after how many subsequent cycles a next output edge is generated by the divider module.

[0011] In a further step, the number of cycles completed by the phase-locked loop at the end of the modulation is preferably determined, taking into account the number of output edges of the divider module and the specific state of the divider module of the phase-locked loop. It is also conceivable that an additional delay, i.e., an additional delay, is taken into account as an offset by additional components in the phase-locked loop. By taking into account the specific state of the divider module, a more precise determination of the number of cycles completed by the phase-locked loop can advantageously be achieved.

[0012] In a further step, a number of cycles of the phase-locked loop to be executed for the modulation is preferably calculated, wherein the number is calculated based on at least one modulation parameter. The at least one modulation parameter can be the oscillation frequency, a modulation slope, and / or a modulation duration. Furthermore, modulation parameters can be a start and / or end frequency of the oscillation frequency, which can be determined and taken into account accordingly. The start and end frequencies of the oscillation frequency are, in particular, the frequencies at the beginning and end of the modulation.

[0013] In a further step, the modulation is preferably verified based on a comparison of the calculated number of cycles to be completed with the determined number of cycles completed by the phase-locked loop. One result of the verification can thus be, for example, that the calculated number of cycles to be completed matches the determined number of cycles completed. This can indicate that the modulation was carried out without errors with a high probability. It is also conceivable to define a range for the match of the values, so that, for example, even one cycle too many or too few is still acceptable. The method can advantageously detect a so-called cycle slip.

[0014] Furthermore, within the scope of the invention, it is optionally possible for the state of the divider module to be determined at the beginning and end of the modulation in order to determine the number of cycles completed by the phase-locked loop, taking into account the state of the divider module determined at the beginning and end of the modulation. This advantageously allows for an even more precise determination of the number of cycles completed by the phase-locked loop.

[0015] In a further embodiment, the state of the divider module can be determined by sampling at least one counter of the phase-locked loop. It can also be provided that a sampling of the divider module is performed to determine the state of the divider module, wherein the sampling of the divider module is preferably performed within one clock cycle of the counter. A counter in an electronic circuit is, in particular, a digital sequential logic device that counts a specific number of pulses and can output these, for example, as a binary value. Counters can be or include special registers that store their count and increment their value by one with each input pulse.

[0016] Furthermore, it is conceivable that missing and / or erroneous values ​​during sampling are determined by extrapolation based on a modulation curve, wherein the curve is described by the at least one modulation parameter of the modulation. For example, a linear frequency ramp is described by the modulation parameters of a start frequency, an end frequency, a slope, and a duration of the modulation. This advantageously allows the number of cycles completed by the phase-locked loop to be determined more precisely, since no missing and / or erroneous values ​​distort the determined number.

[0017] It may be advantageous if, within the scope of the invention, the sampling is performed at least twice during one clock cycle of the counter. This advantageously allows erroneous values, which may be caused by metastability, to be ignored, thus making the determination of the number of cycles completed more precise.

[0018] Furthermore, it is conceivable that the determination and verification steps are additionally performed at least once during the modulation to verify an intermediate state of the modulation. This allows the modulation to be verified multiple times, which can be advantageous, for example, when the modulation lasts for a longer period.

[0019] The invention also relates to a computer program, in particular a computer program product, comprising instructions that, when executed by a computer, cause the computer to carry out the method according to the invention. Thus, the computer program according to the invention provides the same advantages as those described in detail with reference to a method according to the invention.

[0020] The invention also relates to a data processing device configured to carry out the method according to the invention. The device can be, for example, a computer that executes the computer program according to the invention. The computer can have at least one processor for executing the computer program. A non-volatile data memory can also be provided, in which the computer program is stored and from which the computer program can be read by the processor for execution.

[0021] The invention may also provide a computer-readable storage medium that contains the computer program according to the invention and / or includes instructions that, when executed by a computer, cause the computer to carry out the method according to the invention. The storage medium is designed, for example, as a data storage device such as a hard disk and / or a non-volatile memory and / or a memory card. The storage medium can, for example, be integrated into the computer.

[0022] Furthermore, the method according to the invention can also be implemented as a computer-implemented method.

[0023] Further advantages, features, and details of the invention will become apparent from the following description, which describes embodiments of the invention in detail with reference to the drawings. The features mentioned in the claims and in the description may be essential to the invention individually or in any combination. They show: Fig. 1 a schematic visualization of a method, a device, a storage medium and a computer program according to embodiments of the invention, Fig. 2 a schematic representation of a section of a phase-locked loop according to embodiments of the invention.

[0024] In Fig. 1, a method 100, a device 10, a storage medium 15 and a computer program 20 according to embodiments of the invention are schematically shown.

[0025] Fig. 1 shows, in particular, an exemplary embodiment of a method 100 for verifying a modulation of a phase-locked loop 1. In a first step 101, a state of a divider module 2 of the phase-locked loop 1 is determined at the start of the modulation, wherein the divider module 2 provides a clock frequency for the modulation based on an oscillation frequency of the phase-locked loop 1. In a second step 102, a number of cycles completed by the phase-locked loop 1 at the end of the modulation is determined, taking into account a number of output edges of the divider module 2 and the determined state of the divider module 2 of the phase-locked loop 1. In a third step 103, a number of cycles to be completed by the phase-locked loop 1 for the modulation is calculated, wherein the number is calculated based on at least one modulation parameter of the modulation.In a fourth step 104, the modulation is verified based on a comparison of the calculated number of cycles to be run through with the determined number of cycles run through the phase-locked loop 1.

[0026] Fig. 2 shows an exemplary embodiment of a section of a phase-locked loop 1. This has a first part 4 and a digital part 5. The first part 4 can be analog or digital and receives a measured oscillator clock 6 and a reference clock 7. These clocks 6, 7 are passed to a divider module 2 and a counter 3 of the first part 4. The divider module 2 can be partially or completely integrated into the counter 3, provided the desired division ratios can be realized with such a structure. For both the divider module 2 and the counter 3, a number of cycles completed is determined, on the one hand, by sampling elements in the divider module 2a, 2b and, on the other hand, by sampling elements in the counter 3a, 3b. The number determined in each case by the sampling elements in the divider module 2a, 2b is then checked for metastability in the digital part 5 according to step 201, and one of the determined numbers is selected.In step 202, erroneous values ​​can be handled by a measure such as extrapolation. In step 203, the number of cycles 8 that have been completed until the end of the modulation can be determined.

[0027] For safety-relevant applications, a modulation (e.g., frequency ramps in an FMCW radar system) can be monitored during runtime. The divider module 2 preferably counts exactly the number of oscillator cycles that occur during a modulation sequence and can thus advantageously provide an independent detection measure for potential digital modulation problems. This allows for exceedances of the clock range within the digital part 5 according to Fig. 2 can be avoided, whereby the accuracy of the test can remain at one oscillator clock cycle.

[0028] By sampling the state of divider module 2, the number of oscillator cycles in one modulation cycle can be precisely monitored. Subsequent counting of the divider clock edges ensures, in particular, the correct development of the oscillator clock cycles. Correct handling of divider samples at the modulation boundaries may be necessary, e.g., in a JS-FMCW. The correct alignment of the chirp start and end positions, or frequencies, can be performed using the neighboring divider samples. Errors due to invalid divider measurements, e.g., due to metastability, can be handled by extrapolating the next correct value using the modulation history or the known phase path of the closed control loop.

[0029] In a digital phase-locked loop 1, an analog or digital divider circuit with a divider module 2 can generate a modulation clock that can be used in the digital part 5 of the phase-locked loop 1. The method according to embodiments of the invention preferably uses the sampled state of this analog divider circuit or of the divider module 2. From this information, the oscillator phase can be reconstructed more precisely and, if necessary, further extrapolated. This value can be sampled at different times and compared with a pre-calculated value in order to check the correct number of oscillation cycles that have occurred. To avoid metastability during sampling, a double sampler can be used, i.e. in particular the two sampling elements in the counter 3a, 3b or the two sampling elements in the divider module 2a, 2b, which is clocked by sampling clocks that are aligned with the positive and negative oscillator phase.

[0030] In an architecture with a separate divider module 2 and counter 3, the counter samples alone may not provide the desired information, as they ignore the fact that the modulation circuitry itself is clocked by a divider module 2 and therefore cannot respond to cycles between transitions. Therefore, at least one separate sampling element in the divider module 2a, 2b may be required, which can be used in determining the state of the divider module 2. In architectures with a modulator clock derived from the counter 3, it may be sufficient to use the samples of the counter 3. In partially fused architectures with the counter 3 and the divider module 2, in which part of the counter 3 is used as a prescaler for the divider module 2, the oscillator phase can be reconstructed by evaluating the respective counter least significant bits (LSBs) and the state of the divider module 2.Therefore, a sampling element in the divider module 2a, 2b may be required for the state of the divider module 2.

[0031] Further delays in the modulator path (e.g., due to pipeline stages and other sources) can be incorporated into the method according to embodiments by adding them. Sampling and comparing intermediate points during modulation can make the method according to embodiments even more robust, as it can react more quickly to observed deviations.

[0032] The following describes an example with an independent counter 3 and divider module 2. The oscillation frequency before modulation is f0=500 MHz, with a divider ratio of DIV=8. The target modulation should be a linear frequency ramp starting at 1 µs with a duration of 10 µs and a slope of s=5 MHz / µs. At a starting time of 0 µs, the determined state of divider module 2 corresponds to the value 1 according to the example. This is sampled and serves as the origin for later comparison. At a time T1=, i.e., at the beginning of the modulation, the state of divider module 2 is sampled again and is: SDIV,1μs=(SDIV,0μs+1μs∗500MHz)%8=5.

[0033] This value is preferably stored in an unwrapper start register. Since the modulator clock does not provide an immediate transition, the modulator begins by generating the modulation ph lag ,1 = 8 - 5 = 3 cycles after the starting point of the modulation at T1' .

[0034] The modulation runs from 1µs to 11µs and ideally produces: phchirp=f0×t+s / 2×t2=5250 cycles.

[0035] During this phase, the modulation monitor counts the number of transitions or divider edges that have occurred: n sd = floor(ph chirp / DIV) = 656.

[0036] At a time T2=11µs the modulation stops and the divider module 2 is sampled again to determine the state: SSDM,11μs=(SDIV,1μs+phchirp)%8=7.

[0037] The modulator receives a next clock transition ph lag ,2= 8 - 7 = 1 cycle later to effectively ramp at T 2' to stop.

[0038] To obtain the number of cycles to be completed for this modulation, the proposed mechanism adds all available information as follows: countsupervision=nsd×DIV+phlag,1+phlag,2=656×8+3+1=5252

[0039] Since an initial state S DIV,0 (after switching on or at a specific time, e.g. T0, where this time may also coincide with the start of the modulation) is known, the state calculations at T1 and T2, S DIV,1µs and S DIV,11µs be carried out because the oscillator frequency is kept at the known target frequency by the phase-locked loop (PLL) 1. SDIV,1μs=SDIV,0+1μs*500MHz=501 SDIV,11μs=SDIV,1μs+phchirp=5751

[0040] This results in a number of cycles completed of: countprediction=phchirp+(8−SDIV,11us%8)−(8−SDIV,1us%8)=5252

[0041] Since the numbers count supervision and count prediction match, it can be concluded that the modulation was performed correctly.

[0042] The above explanation of the embodiments describes the present invention exclusively by way of examples. Of course, individual features of the embodiments can be freely combined with one another, provided they are technically feasible, without departing from the scope of the present invention. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] DE 21 2017 000 244 U1

[0005] DE 10 2020 123 010 A1

[0006]

Claims

[1] Method (100) for verifying a modulation of a phase-locked loop (1), comprising the following steps: - determining (101) a state of a divider module (2) of the phase-locked loop (1) at the start of the modulation, wherein the divider module (2) provides a clock frequency of the modulation based on an oscillation frequency of the phase-locked loop (1), - determining (102) a number of cycles of the phase-locked loop (1) completed at the end of the modulation, taking into account a number of output edges of the divider module (2) and the determined state of the divider module (2) of the phase-locked loop (1), - calculating (103) a number of cycles of the phase-locked loop (1) to be run through for the modulation, wherein the number is calculated on the basis of at least one modulation parameter of the modulation, - Verifying (104) the modulation on the basis of a comparison of the calculated number of cycles to be run through with the determined number of cycles run through the phase-locked loop (1). [2] Method (100) according to claim 1, characterized by that the state of the divider module (2) indicates after how many subsequent cycles a next output edge is generated by the divider module (2). [3] Method (100) according to one of the preceding claims, characterized by that the determination (101) of the state of the divider module (2) is carried out at the beginning and at the end of the modulation in order to determine the number of cycles of the phase-locked loop (1) carried out, taking into account the state of the divider module (2) determined at the beginning and at the end of the modulation. [4] Method (100) according to one of the preceding claims, characterized bythat the determination (101) of the state of the divider module (2) is carried out by sampling at least one counter (3) of the phase-locked loop (1). [5] Method (100) according to claim 4, characterized by that missing and / or erroneous values ​​during sampling are determined by an extrapolation on the basis of a modulation curve, wherein the curve is described by the at least one modulation parameter of the modulation. [6] Method (100) according to claim 4, characterized by that the sampling is carried out at least twice during one clock cycle of the counter (3). [7] Method (100) according to one of the preceding claims, characterized by that the determining (102) and the verifying (104) are additionally carried out at least once during the modulation in order to verify an intermediate state of the modulation. [8] Computer program (20) comprising instructions which, when the computer program (20) is executed by a computer (10), cause the computer (10) to carry out the method (100) according to one of the preceding claims. [9] Device (10) for data processing, which is arranged to carry out the method (100) according to one of claims 1 to 7. [10] A computer-readable storage medium (15) comprising instructions which, when executed by a computer (10), cause the computer (10) to carry out the steps of the method (100) according to any one of claims 1 to 7.

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