DISPLAY PANEL

Abstract

The present application provides a display panel comprising a display section having a plurality of sub-pixel rows and a driving section having a first driving circuit and a second driving circuit, wherein the first driving circuit comprises a plurality of first driving modules and the second driving circuit comprises a plurality of second driving modules, and wherein an output end of one of the first driving modules is electrically connected to the pixel circuit in the k adjacent sub-pixel rows and an output end of one of the second driving modules is electrically connected to the pixel circuit in the j adjacent sub-pixel rows, and wherein k is less than or equal to j and j is greater than or equal to 2;The present application reduces the number of second drive modules in the second driver circuit by causing the output end of one of the second drive modules in the drive section to output a control signal to the pixel circuits in at least two of the subpixel rows simultaneously, so that some of the transversely arranged drive elements in the drive section can be arranged in the longitudinal free space in an area where the second driver circuit is located, thereby reducing the space occupied by the drive section in the edge and realizing a narrow edge design.;

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of displays, in particular a display panel. STATE OF THE ART

[0002] With the development of display technology, the existing display devices have high requirements for narrow bezel, and therefore the existing display devices use GOA (Gate Driver On Array) technology instead of gate driver chip to reduce the bezel.

[0003] Meanwhile, each row of pixel circuits in existing display panels typically needs to receive at least two different scanning signals output from the gate driver circuit, and each scanning signal is typically output from a different driver circuit in the gate driver circuit, corresponding independently to each row of pixel circuits. This requires setting up a plurality of driver circuits in the gate driver circuits corresponding to each row of pixel circuits. This results in the gate driver circuit occupying a larger edge size of the display panel, and this is in contrast to the narrow edge design of the display panel. US 2015 / 0 348 472 A1 discloses a display panel driver. KR 10 2019 0 125 008 A discloses a display panel and an electroluminescent display including this display panel. DISCLOSURE OF THE INVENTION

[0004] The present application provides a display panel to solve the technical problem that the existing gate drive circuit occupies a larger edge size of the display panel, which is in contrast to the narrow edge design of the display panel.

[0005] The invention according to claim 1 of the present application provides a display panel comprising: a display section comprising a plurality of sub-pixel rows, each of the sub-pixel rows comprising a plurality of sub-pixel units, and a pixel circuit being arranged in each of the sub-pixel units; a driving section arranged with the display section along a first direction, wherein the driving section includes a first driving circuit and a second driving circuit arranged along the first direction, and wherein the second driving circuit is arranged between the first driving circuit and the display section, and wherein the first driving circuit includes a plurality of first driving modules arranged along a second direction, and wherein the second driving circuit includes a plurality of second driving modules arranged along the second direction; and wherein an output end of one of the first drive modules is electrically connected to the pixel circuit in the k adjacent sub-pixel rows and an output end of one of the second drive modules is electrically connected to the pixel circuit in the j adjacent sub-pixel rows, and wherein k is less than or equal to j, k is greater than or equal to 1, and j is greater than or equal to 2, and wherein both k and j are positive integers, wherein the pixel circuit comprises a switching transistor, a driver transistor, and a first reset transistor, wherein the switching transistor and the driver transistor are connected to a first reset node, and the first reset transistor and the driver transistor are connected to a second reset node; and wherein the first control module comprises a first signal output and the second control module comprises a second signal output; and wherein, when k is 1 and j is 2, the first signal output of an n-th stage is connected to the gate of the switching transistor in the pixel circuit of the n-th subpixel row, the n-th stage comprising the subpixels in the n-th subpixel row, the first signal output of the n+1-th stage is connected to the gate of the switching transistor in the pixel circuit of the n+1-th subpixel row, the n+1-th stage comprising the subpixels in the n+1-th subpixel row, and the second signal output of an a-th stage is connected to the gate of the first reset transistor in the pixel circuit of the n-th and n+1-th subpixel rows, and where a is (n+1) / 2, the a-th stage comprising the subpixels of the n-th and n+1-th subpixel rows; if k is 1 and j is 4, the first signal output of the nth stage is connected to the gate of the switching transistor in the pixel circuit of the nth subpixel row, wherein the nth stage comprises the subpixels in the nth subpixel row, the first signal output of the n+1th stage is connected to the gate of the switching transistor in the pixel circuit of the n+1th subpixel row, wherein the n+1th stage comprises the subpixels in the n+1th subpixel row, the first signal output of an n+2th stage is connected to the gate of the switching transistor in the pixel circuit of the n+2th subpixel row, wherein the n+2th stage comprises the subpixels in the n+2th subpixel row, the first signal output of an n+3th stage is connected to the gate of the switching transistor in the pixel circuit of the n+3th subpixel row, wherein the n+3th stage comprises the subpixels in the n+3-th subpixel row,and the second signal output of the a-th stage is connected to the gate of the first reset transistor in the pixel circuit of the n-th and n+3-th subpixel row, and wherein a is (n+3) / 4, wherein the a-th stage in this case comprises the subpixels of the n-th and n+3-th subpixel row, or wherein the first drive module further comprises a third signal output;, and wherein, when k is 2 and j is 2, the first signal output of a b-th stage is connected to the gate of the switching transistor in the pixel circuit of the n-th sub-pixel row, the third signal output of the b-th stage is connected to the gate of the switching transistor in the pixel circuit of the n+1-th sub-pixel row, and the second signal output of the a-th stage is connected to the gate of the first reset transistor in the pixel circuit of the n-th and n+1-th sub-pixel rows, and wherein a and b are equal and a is (n+1) / 2, the b-th and a-th stages in this case comprising the n-th and n+1-th sub-pixels, respectively; if k is 2 and j is 4, the first signal output of the b-th stage is connected to the gate of the switching transistor in the pixel circuit of the n-th subpixel row, the third signal output of the b-th stage is connected to the gate of the switching transistor in the pixel circuit of the n+1-th subpixel row, the b-th stage in this case comprising the subpixels of the n+1-th subpixel row, the first signal output of a b+1-th stage is connected to the gate of the switching transistor in the pixel circuit of the n+2-th subpixel row, the b+1-th stage in this case comprising the subpixels of the n+2-th subpixel row, the third signal output of the b+1-th stage is connected to the gate of the switching transistor in the pixel circuit of the n+3-th subpixel row, the b+1-th stage in this case comprising the subpixels of the n+3-th subpixel row,and the second signal output of the a-th stage is connected to the gate of the first reset transistor in the pixel circuit of the n-th and n+3-th subpixel rows, and where b is (n+1) / 2 and a is (n+3) / 4, the a-th stage in this case comprising the subpixels of the n-th and n+3-th subpixel rows.

[0006] Advantages: The present application provides a display panel comprising a display section having a plurality of sub-pixel rows and a driving section having a first driving circuit and a second driving circuit, wherein the first driving circuit comprises a plurality of first driving modules and the second driving circuit comprises a plurality of second driving modules, and wherein an output end of one of the first driving modules is electrically connected to the pixel circuit in the k adjacent sub-pixel rows and an output end of one of the second driving modules is electrically connected to the pixel circuit in the j adjacent sub-pixel rows, and wherein k is less than or equal to j and j is greater than or equal to 2;The present application reduces the number of second drive modules in the second driver circuit by causing the output end of one of the second drive modules in the drive section to output a control signal to the pixel circuits in at least two of the subpixel rows simultaneously, so that some of the transversely arranged drive elements in the drive section can be arranged in the longitudinal free space in an area where the second driver circuit is located, thereby reducing the space occupied by the drive section in the edge and realizing a narrow edge design.; PRESENTATION OF THE DRAWINGS

[0007] In conjunction with the accompanying drawings, the specific embodiment of the present application will be explained in more detail below in order to clarify the technical solution and other advantageous effects of the present application. Fig. 1 shows a structural diagram of a display panel of the present application. Fig. 2 shows a first structural diagram of a pixel circuit of the present application. Fig. 3 shows a first diagram of the connection between a driver circuit and a subpixel row in the driving section of the present application. Fig. Fig. 4 shows a second diagram of the connection between a driver circuit and a subpixel row in the driving section of the present application. Fig. 5 shows a second structural diagram of a pixel circuit of the present application. Fig. 6 shows a third diagram of the connection between a driver circuit and a subpixel row in the driving section of the present application. Fig. 7 shows a timing diagram of a pixel circuit according to Fig. 6. Fig. 8 shows a fourth diagram of the connection between a driver circuit and a subpixel row in the driving section of the present application. Fig. 9 shows a timing diagram of a pixel circuit according to Fig. 8. Fig. 10 shows a fifth diagram of the connection between a driver circuit and a subpixel row in the driving section of the present application. Fig. 11 shows a sixth diagram of the connection between a driver circuit and a subpixel row in the driving section of the present application. Fig. 12 shows a seventh diagram of the connection between a driver circuit and a subpixel row in the driving section of the present application. Fig. 13 shows an eighth diagram of the connection between a driver circuit and a subpixel row in the driving section of the present application. Fig. 14 shows a first circuit structure diagram of a first control module of the present application. Fig. 15 shows a circuit structure diagram of a second drive module of the present application. Fig. 16 shows a circuit structure diagram of a third drive module of the present application. Fig. 17 shows a second circuit structure diagram of a first drive module of the present application. Fig. 18 shows a structural diagram of a second pull-up transistor in the first drive module of the present application. Fig. 19 shows a structural diagram of a second pull-up transistor in the first drive module of the present application. CONCRETE EMBODIMENTS

[0008] In conjunction with the accompanying drawings in the embodiments of the present application, the technical solutions in the embodiments of the present application will be explained clearly and completely below. Obviously, the described embodiments do not represent all embodiments, but only a part of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments in the present application without creative work should be considered to be covered by the scope of the present application.

[0009] With reference to Fig. 1 to 19, an embodiment of the present application provides a display panel 100 that may include a display portion 200 and a driving portion 300 arranged on one side of the display portion 200, wherein the display portion 200 and the driving portion 300 are arranged along the first direction X.

[0010] In the present embodiment, the driving section 300 may be a one-sided driving or a two-sided driving, for example, the structure in Fig. 1 is a two-way control.

[0011] In the present embodiment, the display section 200 may include a plurality of sub-pixel rows 210, wherein each sub-pixel row 210 includes a plurality of sub-pixel units 211, and wherein a pixel circuit 211a is arranged in each sub-pixel unit 211; and wherein a plurality of sub-pixel units 211 are arranged along a first direction X and a plurality of sub-pixel rows 210 are arranged along a second direction Y.

[0012] With reference to Fig. 3, in the present embodiment, the driving section 300 includes a first driving circuit 310 and a second driving circuit 320 arranged along the first direction X, the second driving circuit 320 being arranged between the first driving circuit 310 and the display section 200, and the first driving circuit 310 includes a plurality of first driving modules 311 arranged along a second direction Y, and the second driving circuit 320 includes a plurality of second driving modules 321 arranged along the second direction Y.

[0013] It should be noted that a plurality of first drive modules 311 are cascaded first GOA units, a plurality of second drive modules 321 are cascaded second GOA units, and the first drive module 311 and the second drive module 321 have different structures; according to the differences in the structures of the first drive module 311 and the second drive module 321, the first drive module 311 can simultaneously output at least one first control signal and the second drive module 321 can simultaneously output at least one second control signal.

[0014] In the present embodiment, an output end of one of the first drive modules 311 is electrically connected to the pixel circuit 211a in the k adjacent sub-pixel rows 210, and an output end of one of the second drive modules 321 is electrically connected to the pixel circuit 211a in the j adjacent sub-pixel rows 210.

[0015] In the present embodiment, k can be taken as a positive integer greater than or equal to 1 and j as a positive integer greater than or equal to 2, but k must be less than or equal to j; in the following embodiment, the technical solution of the present application is illustrated by taking k as an example of 1 or 2 and j as an example of 2 or 4.

[0016] It should be noted that the angle between the first direction X and the second direction Y can be greater than 0 and less than or equal to 90 degrees, e.g. the first direction X is a horizontal direction, ie a transverse direction, and the second direction Y is a vertical direction, ie a longitudinal direction, and the angle between the first direction X and the second direction Y can be equal to 90 degrees.

[0017] In the present application, the output end of one of the second drive modules 321 in the drive section 300 is caused to output a control signal to the pixel circuits 211a in at least two of the sub-pixel rows 210 simultaneously. For example, one of the second drive modules 321 in the existing display panel 100 outputs only a control signal to the pixel circuit 211a of one sub-pixel row 210, while one of the second drive modules 321 of the present application simultaneously outputs a control signal to the pixel circuits 211a of two sub-pixel rows 210. This corresponds to halving the number of second drive modules 321, and reducing the number of second drive modules 321 allows the second drive circuit 320 to reserve a large amount of space in the second direction Y for the arrangement of other drive elements, for example,Devices arranged transversely in the second driving module 321 may be arranged in the longitudinal direction, or driving elements in the other driving circuits may be arranged in the area, thereby reducing the space occupied by the driving section 300 in the edge to realize a narrow edge design of the display panel 100.

[0018] It should be noted that the pixel circuit 211a of the present application may be of the type 3T1C, 4T1C, 5T2C, 6T1C, 7T1C, etc., and the technical solution of the present application will be described below using simple 3T1C and 4T1C as an example.

[0019] Referring to Fig. 2, shows Fig. 2 shows a first structural diagram of a pixel circuit 211a of the present application.

[0020] The pixel circuit 211a includes a fifth storage capacitor Cst, a switching transistor T1, a driver transistor T2, and a first reset transistor T3, wherein the gate of the switching transistor T1 is connected to a switching signal end WR, a first electrode of the switching transistor T1 is connected to a data signal line Data, and a second electrode of the switching transistor T1 is connected to a first reset node G; and wherein the gate of the driver transistor T2 is connected to the first reset node G, a first electrode of the driver transistor T2 is connected to a constant voltage high-level source VDD, and a second electrode of the driver transistor T2 is connected to a second reset node S; and wherein the gate of the first reset transistor T3 is connected to a first reset end INI, a first electrode of the first reset transistor T3 is connected to a first reference potential Vini, and a second electrode of the first reset transistor T3 is connected to the second reset node S;and wherein a first pole plate of the fifth storage capacitor Cst is connected to the first reset node G and a second pole plate of the fifth storage capacitor Cst is connected to the second reset node S;

[0021] In the structure according to Fig. 2, the potential of the second reset node S must be reset to a reference potential, and therefore a control signal for turning on the first reset transistor T3 must be input to the gate of the first reset transistor T3 before the switching transistor T1 is turned on.

[0022] In the present embodiment, the first control module 311 comprises a first signal output WR1(n) for outputting a first control signal, and the second control module 321 comprises a second signal output INI(n) for outputting a second control signal, wherein the first signal output WR1(n) can be connected to the switching signal end WR and the second signal output INI(n) can be connected to the first reset end INI.

[0023] For example, if k is 1 and j is 2, then with reference to Fig. 3, the first signal output WR1(n) of the nth stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the nth sub-pixel row 210 and outputs the first control signal of the nth stage, the first signal output WR1(n+1) of the n+1-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n+1-th sub-pixel row 210 and outputs the first control signal of the n+1-th stage, and the second signal output INI(a) of the a-th stage is connected to the gate of the first reset transistor T3 in the pixel circuit 211a of the n-th and n+1-th sub-pixel rows 210 and outputs the second control signal of the a-th stage, and a is (n+1) / 2.

[0024] For example, if k is 1 and j is 4, then with reference to Fig. 4 the first signal output WR1(n) of the n-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n-th subpixel row 210 and outputs the first control signal of the n-th stage, the first signal output WR1(n+1) of the n+1-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n+1-th subpixel row 210 and outputs the first control signal of the n+1-th stage, the first signal output WR1(n+2) of the n+2-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n+2-th subpixel row 210 and outputs the first control signal of the n+2-th stage, the first signal output WR1(n+3) of the n+3-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n+3-th subpixel row 210 and outputs the first control signal of the n+3-th stage,and the second signal output INI(a) of the a-th stage is connected to the gate of the first reset transistor T3 in the pixel circuit 211a of the n-th to n+3-th subpixel rows 210 and outputs the second control signal of the a-th stage, and a is (n+3) / 4.,

[0025] In the structure according to Fig. 3, the number of second control modules 321 of the present application can be reduced by almost half compared to the number of first control modules 311, and in the structure according to Fig. 4, the number of second drive modules 321 of the present application can be reduced by almost three-quarters compared to the number of first drive modules 311, and the reduction in the number of second drive modules 321 allows the second drive circuit 320 to reserve a large space in the second direction Y for arranging other drive elements, thereby reducing the space occupied by the drive section 300 in the edge to realize a narrow edge design.

[0026] Referring to Fig. 5, shows Fig. 5 is a first structural diagram of a pixel circuit 211a of the present application.

[0027] The pixel circuit 211a includes a fifth storage capacitor Cst, a switching transistor T1, a driver transistor T2, a first reset transistor T3, and a second reset transistor T4, wherein the gate of the switching transistor T1 is connected to a switching signal terminal WR, the first electrode of the switching transistor T1 is connected to a data signal line Data, and the second electrode of the switching transistor T1 is connected to a first reset node G; and wherein the gate of the driver transistor T2 is connected to the first reset node G, the first electrode of the driver transistor T2 is connected to a constant voltage high-level source VDD, and the second electrode of the driver transistor T2 is connected to a second reset node S;and wherein the gate of the first reset transistor T3 is connected to a first reset end INI, the first electrode of the first reset transistor T3 is connected to a first reference potential Vini, and the second electrode of the first reset transistor T3 is connected to the second reset node S; and wherein the gate of the second reset transistor T4 is connected to a second reset end REF, the first electrode of the second reset transistor T4 is connected to a second reference potential Vref, and the second electrode of the second reset transistor T4 is connected to the first reset node G; and wherein a first pole plate of the fifth storage capacitor Cst is connected to the first reset node G and a second pole plate of the fifth storage capacitor Cst is connected to the second reset node S.;

[0028] In the structure according to Fig. 5, the potential of the first reset node G and the second reset node S must be reset to a reference potential, and therefore, a control signal for turning on the first reset transistor T3 must be input to the gate of the first reset transistor T3 and a control signal for turning on the second reset transistor T4 must be input to the gate of the second reset transistor T4 before the switching transistor T1 is turned on.

[0029] In the pixel circuit 211a according to Fig. 5, may, with reference to Fig. 6 and Fig. 8, the drive section 300 may further comprise a third drive circuit 330, wherein the first drive circuit 310, the second drive circuit 320, and the third drive circuit 330 are arranged along the first direction X, wherein the third drive circuit 330 comprises a plurality of third drive modules 331 arranged along the second direction Y, and wherein each of the third drive modules 331 comprises a fourth signal output REF(n) for outputting a third control signal.

[0030] In the present embodiment, one of the fourth signal outputs REF(n) is connected to the gate of the second reset transistor T4 of a pixel circuit 211a in the adjacent j subpixel rows 210, wherein the fourth signal output REF(n) of the a-th stage is the same as the pixel circuit 211a of the subpixel row 210 to which the second signal output INI(n) of the a-th stage is connected.

[0031] For example, if k is 1 and j is 2, then with reference to Fig. 6 and Fig. 7 the first signal output WR1(n) of the n-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n-th subpixel row 210 and outputs the first control signal of the n-th stage, the first signal output WR1(n+1) of the n+1-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n+1-th subpixel row 210 and outputs the first control signal of the n+1-th stage, the second signal output INI(a) of the a-th stage is connected to the gate of the first reset transistor T3 in the pixel circuit 211a of the n-th and n+1-th subpixel rows 210 and outputs the second control signal of the a-th stage, and a is (n+1) / 2, the fourth signal output REF(a) of the a-th stage is connected to the gate of the second reset transistor T4 in the pixel circuit 211a of the n-th and n+1-th sub-pixel rows 210 is connected and outputs the third control signal of the a-th stage, and a is (n+1) / 2.

[0032] For example, if k is 1 and j is 4, then with reference to Fig. 8 and Fig. 9 the first signal output WR1(n) of the n-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n-th subpixel row 210 and outputs the first control signal of the n-th stage, the first signal output WR1(n+1) of the n+1-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n+1-th subpixel row 210 and outputs the first control signal of the n+1-th stage, the first signal output WR1(n+2) of the n+2-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n+2-th subpixel row 210 and outputs the first control signal of the n+2-th stage, the first signal output WR1(n+3) of the n+3-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n+3-th subpixel row 210 and outputs the first control signal of the n+3-th stage,and the second signal output INI(a) of the a-th stage is connected to the gate of the first reset transistor T3 in the pixel circuit 211a of the n-th to n+3-th subpixel rows 210 and outputs the second control signal of the a-th stage, the fourth signal output REF(a) of the a-th stage is connected to the gate of the second reset transistor T4 in the pixel circuit 211a of the n-th to n+3-th subpixel rows 210 and outputs the third control signal of the a-th stage, and a is (n+3) / 4.

[0033] In the structure according to Fig. 6, the number of the second control modules 321 and the third control modules 331 of the present application is reduced by almost half compared to the number of the first control modules 311, and in the structure according to Fig. 8, the number of the second drive modules 321 and the third drive modules 331 of the present application is each reduced by almost three-quarters compared to the number of the first drive modules 311, and the reduction in the number of the second drive modules 321 and the third drive modules 331 allows the second drive circuit 320 and the third drive circuit 330 to reserve a large space in the second direction Y for the arrangement of other drive elements, thereby reducing the space occupied by the drive section 300 in the edge to realize a narrow edge design.

[0034] With reference to Fig. 3 and Fig. 4, the number of first control modules 311 is greater than the number of second control modules 321; and due to the reduction in the number of second control modules 321, the width of the second control modules 321 in the first direction X is reduced, iein the first direction X, the width of the first drive modules 311 is greater than the width of the second drive modules 321, and in the second direction Y, the length of the first drive modules 311 is shorter than the length of the second drive modules 321, therefore, the lateral width of the second drive modules 321 of the present application is reduced, but the longitudinal length is increased, so that the longitudinal length of the first drive circuit 310 and the longitudinal length of the second drive circuit 320 can be the same, in this way, the lateral space occupied by the second drive module 321 in the edge of the display panel 100 is reduced and a narrow edge design is realized; analogously, with reference to . Fig. 6 and Fig. 8, the number of second drive modules 321 may be the same as the number of third drive modules 331, that is, in the first direction X, the width of the first drive modules 311 is greater than the width of the third drive modules 331, and in the second direction Y, the length of the first drive modules 311 is smaller than the length of the third drive modules 331, namely, the lateral width of the third drive modules 331 is reduced, but the longitudinal length is increased, so that the longitudinal length of the first drive circuit 310 and the longitudinal length of the third drive circuit 330 can be the same, in this way, the lateral space occupied by the third drive module 321 in the edge of the display panel 100 is reduced to further reduce the edge of the display panel 100.

[0035] In the present embodiment, the first control module 311 may comprise a first signal output WR1(n) for outputting a first control signal and a third signal output WR2(n+1) for outputting a first control signal, wherein the second control module 321 may comprise a second signal output INI(n) for outputting a second control signal, and wherein the first signal output WR1(n) and the third signal output WR2(n+1) may each be connected to the switching signal end WR, and wherein the second signal output INI(n) may be connected to the first reset end INI.

[0036] It should be noted that although the first signal output WR1(n) and the third signal output WR2(n+1) each output the first control signal for turning on the switching transistor T1, the first control signals output from the first signal output WR1(n) and the third signal output WR2(n+1) have a phase difference; For example, the first signal output WR1(n) of the n-th stage outputs the first control signal of the n-th stage, the third signal output WR2(n+1) of the n-th stage outputs the first control signal of the n+1-th stage, the switching transistor T1 of the n-th subpixel row 210 and the switching transistor T1 of the n+1-th subpixel row 210 are not turned on at the same time, while the first reset transistors T3 of the n-th and n+1-th subpixel rows 210 are turned on at the same time and the second reset transistors T4 of the n-th and n+1-th subpixel rows 210 are turned on at the same time.

[0037] For example, if the pixel circuit 211a has a structure according to Fig. 2 and k is 2 and j is 2, is with reference to Fig. 10, the first signal output WR1(b) of the b-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n-th subpixel row 210, namely, it outputs the first control signal to the n-th subpixel row 210, the third signal output WR2(b+1) of the b-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n+1-th subpixel row 210, namely, it outputs the first control signal to the n+1-th subpixel row 210, the second signal output INI(a) of the a-th stage is connected to the gate of the first reset transistor T3 in the pixel circuit 211a of the n-th and n+1-th subpixel rows 210, namely, it outputs a second control signal to the n-th and n+1-th subpixel rows 210, where a and b are equal and a is (n+1) / 2.

[0038] When the pixel circuit 211a has a structure according to Fig. 2 and k is 2 and j is 4, is with reference to Fig. 11 the first signal output WR1(b) of the b-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n-th subpixel row 210, namely it outputs the first control signal to the n-th subpixel row 210, the third signal output WR2(b+1) of the b-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n+1-th subpixel row 210, namely it outputs the first control signal to the n+1-th subpixel row 210, the first signal output WR1(b+1) of the b+1-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n+2-th subpixel row 210, namely it outputs the first control signal to the n+2-th subpixel row 210, the third signal output WR2(b+2) of the b+1-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n+3-th subpixel row 210, namely, it outputs the first control signal to the n+3-th subpixel row 210,the second signal output INI(a) of the a-th stage is connected to the gate of the first reset transistor T3 in the pixel circuit 211a of the n-th to n+3-th subpixel rows 210, namely, it outputs the second control signal to the n-th to n+3-th subpixel rows 210, where b is (n+1) / 2 and a is (n+3) / 4.

[0039] When the pixel circuit 211a has a structure according to Fig. 5 and k is 2 and j is 2, is with reference to Fig. 12, the first signal output WR1(b) of the b-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n-th subpixel row 210, namely, it outputs the first control signal to the n-th subpixel row 210, the third signal output WR2(b+1) of the b-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n+1-th subpixel row 210, namely, it outputs the first control signal to the n+1-th subpixel row 210, the second signal output INI(a) of the a-th stage is connected to the gate of the first reset transistor T3 in the pixel circuit 211a of the n-th and n+1-th subpixel rows 210, namely, it outputs a second control signal to the n-th and n+1-th subpixel rows 210, the fourth Signal output REF(a) of the a-th stage is connected to the gate of the second reset transistor T4 in the pixel circuit 211a of the n-th and n+1-th subpixel rows 210, namely, it outputs a third control signal to the n-th and n+1-th subpixel rows 210,where a and b are equal and a is (n+1) / 2.

[0040] When the pixel circuit 211a has a structure according to Fig. 5 and k is 2 and j is 4, is with reference to Fig. 13 the first signal output WR1(b) of the b-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n-th subpixel row 210, namely it outputs the first control signal to the n-th subpixel row 210, the third signal output WR2(b+1) of the b-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n+1-th subpixel row 210, namely it outputs the first control signal to the n+1-th subpixel row 210, the first signal output WR1(b+1) of the b+1-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n+2-th subpixel row 210, namely it outputs the first control signal to the n+2-th subpixel row 210, the third signal output WR2(b+2) of the b+1-th stage is connected to the gate of the switching transistor T1 in the pixel circuit 211a of the n+3-th subpixel row 210, namely, it outputs the first control signal to the n+3-th subpixel row 210,The second signal output INI(a) of the a-th stage is connected to the gate of the first reset transistor T3 in the pixel circuit 211a of the nth to n+3th subpixel rows 210, namely, it outputs the second control signal to the nth to n+3th subpixel rows 210. The fourth signal output REF(a) of the a-th stage is connected to the gate of the second reset transistor T4 in the pixel circuit 211a of the nth to n+3th subpixel rows 210, namely, it outputs a third control signal to the nth to n+3th subpixel rows 210, where b is (n+1) / 2 and a is (n+3) / 4.

[0041] With reference to Fig. 10 and Fig. 12, the number of first control modules 311 is equal to the number of second control modules 321; and due to the reduction in the number of second control modules 321, the width of the second control modules 321 in the first direction X is reduced, ieIn the first direction X, the width of the first drive modules 311 is greater than the width of the second drive modules 321, and in the second direction Y, the length of the first drive modules 311 is equal to the length of the second drive modules 321. Therefore, the lateral width of the second drive modules 321 of the present application is reduced, but the longitudinal length is increased, so that the longitudinal length of the first drive circuit 310 and the longitudinal length of the second drive circuit 320 can be the same. In this way, the lateral space occupied by the second drive module 321 in the edge of the display panel 100 is reduced, and a narrow edge design is realized. Similarly, the number of the first drive modules 311 can be increased with reference to FIG. Fig. 11 and Fig. 13 may be smaller than the number of second drive modules 321, the number of second drive modules 321 is further reduced to further reduce the edge of the display panel 100; similarly, the relevant limitations of the third drive module 331 and the first drive module 311 are the same as the relevant limitations of the second drive module 321 and the first drive module 311.

[0042] In the structures according to Fig. 3, 4, and 6 to 13, the structure of the first drive module 311, the second drive module 321, and the third drive module 331 is not specifically limited by the present application. However, the structures of the first drive module 311, the second drive module 321, and the third drive module 331 may all include a pull-up control unit, a pull-up unit, a pull-down unit, and a pull-down sustain unit electrically connected to the same control node, and the present application does not impose any specific restrictions. The structure of the first drive module 311, the second drive module 321, and the third drive module 331 of the present application will be limited by specific circuit structures below.

[0043] For example, the first control module 311 can be Fig. 3, Fig. 4, Fig. 6 and Fig. 8 may comprise a first pull-up control unit 311a, a first pull-up unit 311b, a first pull-down unit 311c and a first pull-down maintenance unit 311d, as shown in Fig. 14 shown.

[0044] In the structure according to Fig. 14, the first pull-up control unit 311a includes a first pull-up control transistor T11, wherein a gate of the first pull-up control transistor T11 is connected to a first stage transmission signal line Cout1, and wherein a first electrode of the first pull-up control transistor T11 is connected to a first high-potential line Vgh1, and wherein a second electrode of the first pull-up control transistor T11 is connected to a first control node Q1.

[0045] In the structure according to Fig. 14, the first pull-up unit 311b comprises a first pull-up transistor T21, a second pull-up transistor T22 and a first storage capacitor C1, wherein a first electrode of the first pull-up transistor T21 is connected to a first clock signal line CK1, and wherein a second electrode of the first pull-up transistor T21 is connected to a stage transmission signal end Cout(n), and wherein a first electrode of the second pull-up transistor T22 is connected to a second clock signal line CK2, and wherein a second electrode of the second pull-up transistor T22 is connected to the first signal output WR1(n), and wherein the gate of the first pull-up transistor T21, the gate of the second pull-up transistor T22 and a first pole plate of the first storage capacitor C1 are connected to the first control node Q1, and wherein a second pole plate of the first storage capacitor C1 is connected to the stage transmission signal end Cout(n); in the structure according to Fig. 14, the first pull-down unit 311c comprises a first pull-down transistor T41 and a second pull-down transistor T42, wherein the gate of the first pull-down transistor T41 and the gate of the second pull-down transistor T42 are connected to a second stage transmission signal line Cout2, and wherein a first electrode of the first pull-down transistor T41 is connected to the first control node Q1, and wherein a second electrode of the first pull-down transistor T41 is connected to a first electrode of the second pull-down transistor T42, and wherein a second electrode of the second pull-down transistor T42 is connected to a first low-potential line Vgl1; in the structure according to Fig. 14, the first pull-down sustain unit 311d comprises a first pull-down sustain transistor T31, a second pull-down sustain transistor T32, a third pull-down sustain transistor T33, and a first inverter 311e, and wherein the gate of the first pull-down sustain transistor T31, the gate of the second pull-down sustain transistor T32, the gate of the third pull-down sustain transistor T33, and the first inverter 311e are connected to a second control node P1, and wherein a first electrode of the first pull-down sustain transistor T31 is connected to a second electrode of the first pull-up transistor T21, and wherein a second electrode of the first pull-down sustain transistor T31 is connected to the first low-potential line Vgl1, and wherein a first electrode of the second pull-down sustain transistor T32 is connected to a second electrode of the second pull-up transistor T22,and wherein a second electrode of the second pull-down sustain transistor T32 is connected to a second low-potential line Vgl2, and wherein a first electrode of the third pull-down sustain transistor T33 is connected to the first control node Q1, and wherein a second electrode of the third pull-down sustain transistor T33 is connected to the first low-potential line Vgl1; and wherein the first inverter 311e is used to invert the potentials of the first control node Q1 and the second control node P1.

[0046] In the structure according to Fig. 14, the first inverter 311e comprises a first inverting transistor T51, a second inverting transistor T52, a third inverting transistor T53, a fourth inverting transistor T54, a fifth inverting transistor T55, and a sixth inverting transistor T56, wherein a first electrode of the first inverting transistor T51, the gate of the first inverting transistor T51, the gate of the second inverting transistor T52, and a first electrode of the fourth inverting transistor T54 are connected to a low-frequency clock signal line LC, and wherein a second electrode of the first inverting transistor T51 is connected to a first electrode of the second inverting transistor T52, and wherein a second electrode of the second inverting transistor T52 is connected to a first electrode of a third inverting transistor T53 and the gate of the fourth inverting transistor T54,and wherein a second electrode of the third inverting transistor T53 is connected to the first low-potential line Vgl1; and wherein a second electrode of the fourth inverting transistor T54, a first electrode of the fifth inverting transistor T55, and a first electrode of the sixth inverting transistor T56 are connected to the second control node P1, and wherein a second electrode of the fifth inverting transistor T55 and a second electrode of the sixth inverting transistor T56 are connected to the first low-potential line Vgl1, and wherein the gate of the third inverting transistor T53 and the gate of the fifth inverting transistor T55 are connected to the first control node Q1, and wherein the gate of the sixth inverting transistor T56 is connected to the first stage transmission signal line Cout1.

[0047] In the structure according to Fig. 14, the first control module 311 further comprises a first leakage protection unit 311f connected to the first control node Q1. The first leakage protection unit 311f comprises a first leakage protection transistor T71 and a second leakage protection transistor T72, wherein a first electrode of the first leakage protection transistor T71 is connected to a fifth high-potential line Vgh5, and wherein a second electrode of the first leakage protection transistor T71 is connected to the second leakage protection transistor T72, and wherein a second electrode of the second leakage protection transistor T72 is connected to an output N(n) of the first leakage protection unit 311f, and wherein the gate of the first leakage protection transistor T71 and the gate of the second leakage protection transistor T72 are connected to the first control node Q1.

[0048] In the structure according to Fig. 14, the first drive module 311 further comprises a first global reset unit 311g, wherein the first global reset unit 311g comprises a first reference transistor T81 and a second reference transistor T82, wherein a first electrode of the first reference transistor T81 is connected to the first control node Q1, and wherein a second electrode of the first reference transistor T81 and a first electrode of the second reference transistor T82 are connected to an output N(n) of the leakage protection unit 150, and wherein a second electrode of the second reference transistor T82 is connected to the first low-potential line Vgl1, and wherein the gates of the first reference transistor T81 and the second reference transistor T82 are connected to a control signal line VST. Normally, when the first drive module 311 stops its operation or starts its operation, the first global reset unit 311g resets the potential of the first control node Q1.

[0049] In the present embodiment, the second electrode of the first pull-down transistor T41 and the first electrode of the second pull-down transistor T42 may each be connected to the output N(n) of the first leakage protection unit 311f to reduce the leakage current; at the same time, the third pull-down sustain transistor T33 may be provided with two transistors connected in series, and the output N(n) of the first leakage protection unit 311f is connected between the two transistors to further reduce the leakage current.

[0050] It should be noted that it is feasible to arrange only one of the two series-connected transistors of the present application. For example, it is feasible to arrange only one of the first inverting transistor T51 and the second inverting transistor T52. With the arrangement of the first inverting transistor T51 and the second inverting transistor T52, the leakage current can be reduced. The sixth inverting transistor T56 mainly serves as a feedback function, and it is possible not to use the sixth inverting transistor as a part of the inverter.

[0051] It should be noted that the first stage transmission signal line Cout1 may be a cascade transmission signal output from the stage transmission signal end Cout(n) of a previous stage, e.g., a cascade transmission signal output from the stage transmission signal end Cout(n) of the first drive module 311 of the nx-th stage, where x may be 2; and the second stage transmission signal line Cout2 may be a cascade transmission signal output from the stage transmission signal end Cout(n) of a subsequent stage, e.g., a cascade transmission signal output from the stage transmission signal end Cout(n) of the first drive module 311 of the n+y-th stage, where y may be 2.

[0052] For example, the second control module 321 comprises Fig. 3, 4, 6 to 13, a second pull-up control unit 321a, a second pull-up unit 321b, a second pull-down unit 321c and a second pull-down maintenance unit 321d, as in Fig. 15 shown.

[0053] In the structure according to Fig. 15, the second pull-up control unit 321a includes a second pull-up control transistor T12, wherein a gate of the second pull-up control transistor T12 is connected to a first signal transmission line INI-1, and wherein a first electrode of the second pull-up control transistor T12 is connected to a second high-potential line Vgh2, and wherein a second electrode of the second pull-up control transistor T12 is connected to a third control node Q2.

[0054] In the structure according to Fig. 15, the second pull-up unit 321b comprises a fourth pull-up transistor T24 and a second storage capacitor C2, wherein a first electrode of the fourth pull-up transistor T24 is connected to a fourth clock signal line CK4, and wherein a second electrode of the fourth pull-up transistor T24 is connected to the second signal output INI(n), and wherein the gate of the fourth pull-up transistor T24 and a first pole plate of the second storage capacitor C2 are connected to the third control node Q2, and wherein a second pole plate of the second storage capacitor C2 is connected to the second signal output INI(n).

[0055] In the structure according to Fig. 15, the second pull-down unit 321c includes a third pull-down transistor T43 and a fourth pull-down transistor T44, wherein the gate of the third pull-down transistor T43 and the gate of the fourth pull-down transistor T44 are connected to a second signal transmission line INI-2, and wherein a first electrode of the third pull-down transistor T43 is connected to the third control node Q2, and wherein a second electrode of the third pull-down transistor T43 is connected to a first electrode of the fourth pull-down transistor T44, and wherein a second electrode of the fourth pull-down transistor T44 is connected to a first low-potential line Vgl1.

[0056] In the structure according to Fig. 15, the second pull-down sustain unit 321d comprises a fifth pull-down sustain transistor T35, a sixth pull-down sustain transistor T36, a seventh pull-down sustain transistor T37, and a second inverter 321e, wherein the gate of the fifth pull-down sustain transistor T35, the gate of the sixth pull-down sustain transistor T36, the gate of the seventh pull-down sustain transistor T37, and the second inverter 321e are connected to a fourth control node P2, and wherein a first electrode of the fifth pull-down sustain transistor T35 is connected to a second electrode of the fourth pull-up transistor T24, and wherein a second electrode of the fifth pull-down sustain transistor T35 is connected to the first low-potential line Vgl1, and wherein a first electrode of the sixth pull-down maintenance transistor T36 is connected to the third control node Q2,and wherein a second electrode of the sixth pull-down sustain transistor T36 is connected to a first electrode of the seventh pull-down sustain transistor T37, and wherein a second electrode of the seventh pull-down sustain transistor T37 is connected to the first low-potential line Vgl1, and wherein the second inverter 321e is used to invert the potentials of the third control node Q2 and the fourth control node P2.,

[0057] In the structure according to Fig. 15, the second inverter 321e comprises a seventh inverting transistor T57, an eighth inverting transistor T58, a ninth inverting transistor T59, a tenth inverting transistor T51a, an eleventh inverting transistor T51b, and a twelfth inverting transistor T51c, wherein a first electrode of the seventh inverting transistor T57, the gate of the seventh inverting transistor T57, the gate of the eighth inverting transistor T58, and a first electrode of the tenth inverting transistor T51a are connected to a low-frequency clock signal line LC, and wherein a second electrode of the seventh inverting transistor T57 is connected to a first electrode of the eighth inverting transistor T58, and wherein a second electrode of the eighth inverting transistor T58 is connected to a first electrode of the ninth inverting transistor T59 and to the gate of the tenth inverting transistor T51a. is,and wherein a second electrode of the ninth inverting transistor T59 is connected to the first low-potential line Vgl1; and wherein a second electrode of the tenth inverting transistor T51a, a first electrode of the eleventh inverting transistor T51b, and a first electrode of the twelfth inverting transistor T51c are connected to the fourth control node P2, and wherein a second electrode of the eleventh inverting transistor T51b and a second electrode of the twelfth inverting transistor T51c are connected to the first low-potential line Vgl1, and wherein the gate of the ninth inverting transistor T59 and the gate of the eleventh inverting transistor T51b are connected to the third control node Q2, and wherein the gate of the twelfth inverting transistor T51c is connected to the first signal transmission line INI-1.

[0058] In the structure according to Fig. 15, the second drive module 321 further comprises a second leakage protection unit 321f connected to the third control node Q2. The second leakage protection unit 321f comprises a third leakage protection transistor T73 and a fourth leakage protection transistor T74, wherein a first electrode of the third leakage protection transistor T73 is connected to a sixth high-potential line Vgh6, and wherein a second electrode of the third leakage protection transistor T73 is connected to a first electrode of the fourth leakage protection transistor T74, and wherein a second electrode of the fourth leakage protection transistor T74 is connected to an output N(n) of the second leakage protection unit 321f, and wherein the gate of the third leakage protection transistor T73 and the gate of the fourth leakage protection transistor T74 are connected to the third control node Q2.

[0059] In the structure according to Fig. 15, the second drive module 321 further comprises a second global reset unit 321g, wherein the second global reset unit 321g comprises a third reference transistor T83 and a fourth reference transistor T84, and wherein a first electrode of the third reference transistor T83 is connected to the third control node Q2, and wherein a second electrode of the third reference transistor T83 and a first electrode of the fourth reference transistor T84 are connected to an output N(n) of the second leakage protection unit 321f, and wherein a second electrode of the fourth reference transistor T84 is connected to the first low-potential line Vgl1, and wherein the gates of the third reference transistor T83 and the fourth reference transistor T84 are connected to the control signal line VST. Normally, the second global reset unit 321g resets when the second drive module 321 stops its operation or starts its operation,the potential of the third control node Q2.

[0060] In the present embodiment, the second electrode of the sixth pull-down sustain transistor T36, the first electrode of the seventh pull-down sustain transistor T37, the second electrode of the third pull-down transistor T43, and the first electrode of the fourth pull-down transistor T44 may each be connected to the output N(n) of the second leakage protection unit 321f to reduce the leakage current.

[0061] It should be noted that it is feasible to arrange only one of the two series-connected transistors of the present application, for example, it is feasible to arrange only one of the seventh inverting transistor T57 and the eighth inverting transistor T58, with the arrangement of the first inverting transistor T57 and the second inverting transistor T58, the leakage current can be reduced, the twelfth inverting transistor T51c mainly serves as a feedback function, and it is possible not to use the twelfth inverting transistor as a part of the inverter 160.

[0062] It should be noted that the first signal transmission line INI-1 may be a second control signal output from the second signal output INI(n) of a previous stage, e.g., a second control signal output from the second signal output INI(n) of the second drive module 321 of the nx-th stage, where x may be 2; and the second signal transmission line INI-2 may be a second control signal output from the second signal output INI(n) of a subsequent stage, e.g., a second control signal output from the second signal output INI(n) of the second drive module 321 of the n+y-th stage, where y may be 2.

[0063] For example, the third control module 331 comprises Fig. 3, 4, 6 to 13, a third pull-up control unit 331a, a third pull-up unit 331b, a third pull-down unit 331c and a third pull-down maintenance unit 331d, as in Fig. 16 shown.

[0064] In the structure according to Fig. 16, the third pull-up control unit 331a comprises a third pull-up control transistor T13 and a fourth pull-up control transistor T14, wherein the gate of the third pull-up control transistor T13 and the gate of the fourth pull-up control transistor T14 are each connected to the second signal output INI(n), and wherein a first electrode of the third pull-up control transistor T13 is connected to a third high-potential line Vgh3, and wherein a second electrode of the third pull-up control transistor T13 is connected to a first electrode of the fourth pull-up control transistor T14, and wherein a second electrode of the fourth pull-up control transistor T14 is connected to a fifth control node Q3.

[0065] In the structure according to Fig. 16, the third pull-up unit 331b comprises a fifth pull-up transistor T25 and a third storage capacitor C3, wherein a first electrode of the fifth pull-up transistor T25 is connected to a fourth high-potential line Vgh4, and wherein a second electrode of the fifth pull-up transistor T25 is connected to the fourth signal output REF(n), and wherein the gate of the fourth pull-up transistor T24 and a first pole plate of the third storage capacitor C3 are connected to the fifth control node Q3, and wherein a second pole plate of the third storage capacitor C3 is connected to the fourth signal output REF(n).

[0066] In the structure according to Fig. 16, the third pull-down unit 331c comprises a fifth pull-down transistor T45 and a sixth pull-down transistor T46, wherein the gate of the fifth pull-down transistor T45 and the gate of the sixth pull-down transistor T46 are connected to the first signal output WR1(n), and wherein a first electrode of the fifth pull-down transistor T45 is connected to the fifth control node Q3, and wherein a second electrode of the fifth pull-down transistor T45 is connected to a first electrode of the sixth pull-down transistor T46, and wherein a second electrode of the sixth pull-down transistor T46 is connected to the second low-potential line Vgl2.

[0067] In the structure according to Fig. 16, the third pull-down sustaining unit 331d comprises an eighth pull-down sustaining transistor T38, a ninth pull-down sustaining transistor T39, a tenth pull-down sustaining transistor T31a, an eleventh pull-down sustaining transistor T31b, a twelfth pull-down sustaining transistor T31c, and a potential increasing unit 331e, wherein the gate of the eighth pull-down sustaining transistor T38, the gate of the ninth pull-down sustaining transistor T39, the gate of the tenth pull-down sustaining transistor T31a, and the potential increasing unit 331e are connected to the sixth control node P3, and wherein a first electrode of the eighth pull-down sustaining transistor T38 is connected to a second electrode of the fifth pull-up transistor T25, and wherein a second electrode of the eighth Pull-down maintenance transistor T38 is connected to a third low-potential line Vgl3,and wherein a first electrode of the ninth pull-down sustain transistor T39 is connected to the fifth control node Q3, and wherein a second electrode of the ninth pull-down sustain transistor T39 is connected to a first electrode of the tenth pull-down sustain transistor T31a, and wherein a second electrode of the tenth pull-down sustain transistor T31a is connected to the second low-potential line Vgl2, and wherein the gate of the eleventh pull-down sustain transistor T31b is connected to the fifth control node Q3, and wherein a first electrode of the eleventh pull-down sustain transistor T31b is connected to the sixth control node P3, and wherein a second electrode of the eleventh pull-down sustain transistor T31b is connected to the second low-potential line Vgl2, and wherein the gate of the twelfth pull-down sustain transistor T31c is connected to the second signal output INI(n) is connected,and wherein a first electrode of the twelfth pull-down sustain transistor T31c is connected to the sixth control node P3, and wherein a second electrode of the eleventh pull-down sustain transistor T31b is connected to the second low-potential line Vgl2, and wherein the potential increasing unit 331e is used to invert the potentials of the fifth control node Q3 and the sixth control node P3.,

[0068] In the present embodiment, the potential boosting unit 331e comprises a first boosting transistor T91, a second boosting transistor T92, a third boosting transistor T93, a fourth boosting transistor T94, and a fourth storage capacitor C4, wherein the gate of the first boosting transistor T91 and the gate of the second boosting transistor T92 are connected to the stage transfer signal end Cout(n), and wherein a first electrode of the first boosting transistor T91 is connected to the first signal output WR1(n), and wherein a second electrode of the first boosting transistor T91 is connected to a first electrode of the second boosting transistor T92 and a first electrode of the third boosting transistor T93, and wherein a second electrode of the second boosting transistor T92 is connected to the gate of the third boosting transistor T93,a first pole plate of the fourth storage capacitor C4 and the gate of the fourth boost transistor T94, and wherein a second electrode of the third boost transistor T93, a second pole plate of the fourth storage capacitor C4, and a first electrode of the fourth boost transistor T94 are each connected to a seventh high-potential line Vgh7, and wherein a second electrode of the fourth boost transistor T94 is connected to the sixth control node P3.

[0069] In the structure according to Fig. 16, the third control module 331 further comprises a third leakage protection unit 331f connected to the fifth control node Q3. The third leakage protection unit 331f comprises a fifth leakage protection transistor T75, wherein a first electrode of the fifth leakage protection transistor T75 is connected to the fourth high-potential line Vgh4, and wherein a second electrode of the fifth leakage protection transistor T75 is connected to the output N(n) of the third leakage protection unit 331f, and wherein the gate of the fifth leakage protection transistor T75 is connected to the fifth control node Q3.

[0070] In the present embodiment, the second electrode of the ninth pull-down sustain transistor T39, the first electrode of the tenth pull-down sustain transistor T31a, the second electrode of the fifth pull-down transistor T45, and the first electrode of the sixth pull-down transistor T46 may each be connected to the output N(n) of the third leakage protection unit 331f to reduce the leakage current.

[0071] It should be noted that the first signal output WR1(n) and the stage transfer signal end Cout(n) are Fig. 16 the first signal output WR1(n) and the stage transmission signal end Cout(n) according to Fig. 14, the received first control signal and cascade transmission signal according to Fig. 16 are each a control signal of the present stage, the second signal output INI(n) according to Fig. 16 the second signal output INI(n) according to Fig. 15 and the received second control signal according to Fig. 16 is the control signal of the present stage.

[0072] For example, for the first control module 311 according to Fig. 10 to 13 will refer to Fig. 17 taken, Fig. 17 is equal to or similar to Fig. 14 and the difference lies in that the first pull-up unit 311b further comprises a third pull-up transistor T23, wherein a first electrode of the third pull-up transistor T23 is connected to a third clock signal line CK3, and wherein a second electrode of the third pull-up transistor T23 is connected to the third signal output WR2(n+1), and wherein the gate of the third pull-up transistor T23 is connected to the first control node Q1.

[0073] The first pull-down sustain unit 311d further comprises a fourth pull-down sustain transistor T34, wherein a first electrode of the fourth pull-down sustain transistor T34 is connected to a second electrode of the third pull-up transistor T23, and wherein a second electrode of the fourth pull-down sustain transistor T34 is connected to the second low-potential line Vgl2, and wherein the gate of the fourth pull-down sustain transistor T34 is connected to the second control node P1.

[0074] In the structure according to Fig. 14, one of the first control modules 311 outputs only a first control signal; in the structure according to Fig. 17, one of the second control modules 321 can output two first control signals, wherein the two first control signals have a phase difference.

[0075] From the structures according to Fig. 7, 9 and 14 to 17 it can be seen that the timing diagram of the pulse signal output from the fourth signal output REF(n) is controlled by a first control signal output from the first signal output WR1(n) and a second control signal output from the second signal output INI(n).

[0076] It should be noted that in the structure according to Fig. 14 to 17, the potentials of the third low-potential line Vgl3 and the second low-potential line Vgl2 may be equal, and the potential of the second low-potential line Vgl2 may be greater than the potential of the first low-potential line Vgl1; the potential of the second low-potential line Vgl2 may be, for example, -8V, and the potential of the first low-potential line Vgl1 may be -10V, namely, the potential of the first control node will be pulled down to -8V, and in the structure according to Fig. 14, the potential of the first signal output WR1(n) is pulled down to -10V, the first control node is the gate of the second pull-up transistor T22, and the first signal output WR1(n) is the source end of the second pull-up transistor T22, then the difference value of the potential between the gate and the source of the second pull-up transistor T22 is -2V, which is much smaller than the threshold voltage of the second pull-up transistor T22, the second pull-up transistor T22 is completely turned off, thereby avoiding the second pull-up transistor T22 from being turned on and outputting a control signal when a row is not selected.

[0077] It should be noted that in the structure of FIGS. 14 to 17, the voltages of the first low-potential line Vgl1, the second low-potential line Vgl2, and the third low-potential line Vgl3 may be the same, that is, the first low-potential line Vgl1, the second low-potential line Vgl2, and the third low-potential line Vgl3 may be the same signal line to simplify the arrangement of the signal lines.

[0078] It should be noted that in the structure of FIGS. 14 to 17, the voltages of the first high potential line Vgh1, the second high potential line Vgh2, the third high potential line Vgh3, the fourth high potential line Vgh4, the fifth high potential line Vgh5, the sixth high potential line Vgh6, and the seventh high potential line Vgh7 may be the same in the present application, that is, the first high potential line Vgh1, the second high potential line Vgh2, the third high potential line Vgh3, the fourth high potential line Vgh4, the fifth high potential line Vgh5, the sixth high potential line Vgh6, and the seventh high potential line Vgh7 may be the same signal line to simplify the arrangement of the signal lines.

[0079] It should be noted that the first electrode and the second electrode of the present application are each one of the source and drain electrodes, which are different from each other.

[0080] Since the pull-up transistor is mainly used to output a control signal, the device performance of the pull-up transistor has a great influence on the stability of the output control signal. Since the number of the second drive modules 321 and the third drive modules 331 is reduced, a large space can be reserved for the second driver circuit 320 and the third driver circuit 330 in the second direction Y, and the present application can arrange some of the transversely arranged components in the second pull-up unit 321b and the third pull-up unit 331b longitudinally.

[0081] In the present embodiment, in the first direction X, the width of any pull-up transistor in the first pull-up unit 311b is larger than the width of any pull-up transistor in the second pull-up unit 321b, and in the second direction Y, the length of any pull-up transistor in the first pull-up unit 311b is smaller than the length of any pull-up transistor in the second pull-up unit 321b.

[0082] In the structure according to Fig. 6 and Fig. 8, the number of first control modules 311 is smaller than the number of second control modules 321, namely, the length in the longitudinal direction of 2 or 4 first control modules 311 is the same as the length in the longitudinal direction of a second control module 321;At the same time, the pull-up transistor in the first pull-up unit 311b is the second pull-up transistor T22, and the pull-up transistor in the second pull-up unit 321b is the fourth pull-up transistor T24. The fourth pull-up transistor T24 in the second pull-up unit 321b can arrange some transversely arranged devices longitudinally. Namely, the width in the transverse direction of the fourth pull-up transistor T24 is reduced and the length in the longitudinal direction is increased. Therefore, the width in the transverse direction of the second pull-up transistor T22 is larger than the width in the transverse direction of the fourth pull-up transistor T24, and the length in the longitudinal direction of the second pull-up transistor T22 is smaller than the length in the longitudinal direction of the fourth pull-up transistor T24.

[0083] In the structure according to Fig. 10, the number of first drive modules 311 is the same as the number of second drive modules 321, namely, the length in the longitudinal direction of a first drive module 311 is the same as the length in the longitudinal direction of a second drive module 321. However, with the same length in the longitudinal direction of the first drive module 311, the second pull-up transistor T22 and the third pull-up transistor T23 should be arranged at the same time. In the present application, the second pull-up transistor T22 and the third pull-up transistor T23 are normally arranged in the longitudinal direction;therefore, the width in the transverse direction of the second pull-up transistor T22 and the third pull-up transistor T23 is each larger than the width in the transverse direction of the fourth pull-up transistor T24, and the length in the longitudinal direction of the second pull-up transistor T22 and the third pull-up transistor T23 is each smaller than the length in the longitudinal direction of the fourth pull-up transistor T24.;

[0084] In the structure according to Fig. 11, the width in the transverse direction of the fourth pull-up transistor T24 can be calculated based on Fig. 10 is further reduced and the length in the longitudinal direction is further increased, therefore the width in the transverse direction of the second pull-up transistor T22 is greater than the width in the transverse direction of the fourth pull-up transistor T24, and the length in the longitudinal direction of the second pull-up transistor T22 is smaller than the length in the longitudinal direction of the fourth pull-up transistor T24. Similarly, in the third pull-up unit 331b, the width in the transverse direction of the second pull-up transistor T22 is greater than the width in the transverse direction of the fifth pull-up transistor T25, and the length in the longitudinal direction of the second pull-up transistor T22 is smaller than the length in the longitudinal direction of the fifth pull-up transistor T25.

[0085] The structure of the second pull-up transistor T22 in Fig. 12 and the fourth pull-up transistor T24 in Fig. 13 are described below as examples.

[0086] With reference to Fig. 18, the second pull-up transistor T22 comprises a first gate T22G, a first source T22S, a first drain T22D and a first active section T22A, wherein the first gate T22G is arranged between the first source T22S and the first drain T22D, and wherein the first active section T22A overlaps with each of the first gate T22G, the first source T22S and the first drain T22D, and wherein the overlapping section of the first active section T22A and the first gate T22G is the channel of the first active section T22A.

[0087] With reference to Fig. 18, the first source T22S comprises a first trunk source T22Sa and a plurality of first branch sources T22Sb connected to the first trunk source T22Sa, the first drain T22D comprises a first trunk drain T22Da and a plurality of first branch drains T22Db connected to the first trunk drain T22Da, the first trunk source T22Sa and the first trunk drain T22Db extend along the second direction Y, the first branch source T22Sa and the second branch source T22Sb extend along the first direction X, the plurality of first branch sources T22Sb and the plurality of first branch drains T22Db being sequentially arranged at intervals along the second direction Y;and wherein the first active section T22A comprises a plurality of first active subsections T22Aa arranged along the first direction X, and wherein each of the first active subsections T22Aa overlaps with the first gate T22G, the first branch source T22Sb, and the first branch drain T22Db.;

[0088] With reference to Fig. 18, the first source T22S comprises a first trunk source T22Sa and two first branch sources T22Sb, the first drain T22D comprises a first trunk drain T22Da and two first branch drains T22Db, and the first gate T22G is S-shaped, and the first gate T22G is located between two first branch sources T22Sb and two first branch drains T22Db arranged at intervals;at the same time, the first active section T22A comprises five first active subsections T22Aa, each of the first active subsections T22Aa overlapping with two first branch sources T22Sb, two first branch drains T22Db and a first gate T22G located between the first branch source T22Sb and the first branch drain T22Db, and wherein one of the first active subsections T22Aa and the first gate T22G have three overlapping segments, and wherein the overlapping segment is a first channel subsection T22Ab, namely, each of the first active subsections T22Aa has three first channel subsections T22Ab, and wherein one of the first channel subsections T22Ab with the branch sources and branch drains located on its two sides can form a first transistor unit T22AC, and wherein the second pull-up transistor T22 according to ; Fig. 18 can consist of 15 first transistor units T22AC.

[0089] With reference to Fig. 19, the fourth pull-up transistor T24 comprises a second gate T24G, a second source T24S, a second drain T24D, and a second active portion T24A; wherein the second gate T24G is arranged between the second source T24S and the second drain T24D, and wherein the second active portion T24A overlaps with each of the second gate T24G, the second source T24S, and the second drain T24D, and wherein the overlapping portion of the second gate T24G and the second active portion T24A is the channel of the second active portion T24A.

[0090] With reference to Fig. 19, the second source T24S comprises a second trunk source T24Sa and a plurality of second branch sources T24Sb connected to the second trunk source T24Sa, the second drain T24D comprises a second trunk drain T24Da and a plurality of second branch drains T24Db connected to the second trunk drain T24Da, the second trunk source T24Sa and the second trunk drain T24Db extend along the second direction Y, the second branch source T24Sa and the second branch source T24Sb extend along the first direction X, the plurality of second branch sources T24Sb and the plurality of second branch drains T24Db being sequentially arranged at intervals along the second direction Y;and wherein the second active section T24A comprises a plurality of second active subsections T24Aa arranged along the first direction X, and wherein each of the second active subsections T24Aa overlaps with the second gate T24G, the second branch source T24Sb, and the second branch drain T24Db.;

[0091] With reference to Fig. 19, the second source T24S comprises a second trunk source T24Sa and four first branch sources T24Sb, the second drain T24D comprises a second trunk drain T24Da and four second branch drains T24Db, and the second gate T24G is S-shaped, and the second gate T24G is located between four second branch sources T24Sb and four second branch drains T24Db arranged at intervals;at the same time, the second active section T24A comprises three second active subsections T24Aa, each of the second active subsections T24Aa overlapping with four second branch sources T24Sb, four second branch drains T24Db and a second gate T24G located between the second branch source T24Sb and the second branch drain T24Db, and wherein one of the second active subsections T24Aa and the second gate T24G have 7 overlapping segments, and wherein the overlapping segment is a second channel subsection T24Ab, namely, each of the second active subsections T24Aa has 7 second channel subsections T24Ab, and wherein one of the second channel subsections T24Ab with the branch sources and branch drains located on its two sides can form a second transistor unit T24AC, and wherein the fourth pull-up transistor T24 according to ; Fig. 19 can consist of 21 second transistor units T24AC.

[0092] It should be noted that in the first direction X, a width of the first active subsections T22Aa and a width of the second active subsections T24Aa are equal, in the second direction Y, a length of the first active subsections T22Aa is smaller than a length of the second active subsections T24Aa, and the number of the first active subsections T22Aa is greater than the number of the second active subsections T24Aa.

[0093] In the structure according to Fig. 18, the second pull-up transistor T22 consists of 3X5 first transistor units T22AC arranged in an array, in the structure according to Fig. 19, the fourth pull-up transistor T24 consists of 7×3 second transistor units T24AC arranged in an array, namely, the channel of the first active section T22A may consist of 15 first channel subsections T22Ab and the channel of the second active section T24A may consist of 21 second channel subsections T24Ab, furthermore, the length and the width of the first transistor unit T22AC are according to Fig. 18 are each equal to the length and width of the second transistor unit T24AC according to Fig. 19, namely, the lengths and widths of the first channel sub-portion T22Ab and the second channel sub-portion T24Ab are the same, therefore, a channel length of the first active portion T22A in the present application is smaller than a channel length of the second active portion T24A.

[0094] It should be noted that for the structure of the fourth pull-up transistor T24 in the prior art, reference is made to the structure of the second pull-up transistor T22 according to Fig.18, which is equivalent to changing the 3×5 arranged second transistor units T24AC in the prior art to the 7×3 arranged second transistor units T24AC in the present application. Namely, in the present application, some of the transversely arranged second transistor units T24AC are arranged longitudinally to reduce the width of the fourth pull-up transistor T24 in the horizontal direction; at the same time, the original 15 second transistor units T24AC are changed to 21 second transistor units T24AC in the present application, which is equivalent to increasing the sizes of the second gate T24G, the second source T24S, the second drain T24D, and the second active portion T24A in the fourth pull-up transistor T24, thereby increasing the load of the fourth pull-up transistor T24, thus ensuring the stability of the fourth pull-up transistor T24 when outputting the control signal.

[0095] The present application further provides a display device comprising a terminal main body and a display panel 100, wherein the terminal main body and the display panel 100 are integrally combined with each other. The terminal main body may be a device such as a circuit board bonded to the display panel 100 and a cover plate or the like covering the display panel 100. The display device may be an electronic device such as a mobile phone, a television, a laptop, and the like.

[0096] In the above embodiments, there is a focus for the explanation of the respective embodiments; for the parts not explained in more detail in one embodiment, reference can be made to relevant explanations in other embodiments.

Claims

[1] Display panel (100), characterized by that it includes: a display section (200) comprising a plurality of sub-pixel rows (210), each of the sub-pixel rows (210) comprising a plurality of sub-pixel units (211), and a pixel circuit (211a) being arranged in each of the sub-pixel units (211); a drive section (300) arranged with the display section (200) along a first direction (X), wherein the drive section (300) comprises a first driver circuit (310) and a second driver circuit (320) arranged along the first direction (X), and wherein the second driver circuit (320) is arranged between the first driver circuit (310) and the display section (200), and wherein the first driver circuit (310) comprises a plurality of first driver modules (311) arranged along a second direction (Y), and wherein the second driver circuit (320) comprises a plurality of second driver modules (321) arranged along the second direction (Y); and wherein an output end of one of the first drive modules (311) is electrically connected to the pixel circuit (211a) in the k adjacent sub-pixel rows (210) and an output end of one of the second drive modules (321) is electrically connected to the pixel circuit (211a) in the j adjacent sub-pixel rows (210), and wherein k is less than or equal to j, k is greater than or equal to 1, and j is greater than or equal to 2, and wherein both k and j are positive integers, wherein the pixel circuit (211a) comprises a switching transistor (T1), a driver transistor (T2), and a first reset transistor (T3), wherein the switching transistor (T1) and the driver transistor (T2) are connected to a first reset node (G), and the first reset transistor (T3) and the driver transistor (T2) are connected to a second reset node (S); and wherein the first control module (311) comprises a first signal output and the second control module (321) comprises a second signal output; and wherein, when k is 1 and j is 2, the first signal output of an n-th stage is connected to the gate of the switching transistor in the pixel circuit (211a) of the n-th subpixel row (210), the n-th stage comprising the subpixels in the n-th subpixel row (210), the first signal output of an n+1-th stage is connected to the gate of the switching transistor (T1) in the pixel circuit (211a) of the n+1-th subpixel row (210), the n+1-th stage comprising the subpixels in the n+1-th subpixel row (210), and the second signal output of an a-th stage is connected to the gate of the first reset transistor (T3) in the pixel circuit (211a) of the n-th and n+1-th subpixel row (210), and wherein a is (n+1) / 2, the a-th stage being the subpixels of the nth and n+1th subpixel row (210); if k is 1 and j is 4, the first signal output of the n-th stage is connected to the gate of the switching transistor (T1) in the pixel circuit (211a) of the n-th subpixel row (210), wherein the n-th stage comprises the subpixels in the n-th subpixel row (210), the first signal output of the n+1-th stage is connected to the gate of the switching transistor (T1) in the pixel circuit (211a) of the n+1-th subpixel row (210), wherein the n+1-th stage comprises the subpixels (210) in the n+1-th subpixel row (210), the first signal output of an n+2-th stage is connected to the gate of the switching transistor (T1) in the pixel circuit (211a) of the n+2-th subpixel row (210), wherein the n+2-th stage comprises the subpixels in the n+2-th subpixel row (210), the first signal output of an n+3-th stage is connected to the gate of the switching transistor (T1) in the pixel circuit (211a) of the n+3-th subpixel row (210), the n+3-th stage comprising the subpixels in the n+3-th subpixel row (210),and the second signal output of the a-th stage is connected to the gate of the first reset transistor (T3) in the pixel circuit (211a) of the n-th and n+3-th subpixel row (210), and where a is (n+3) / 4, the a-th stage in this case comprising the subpixels of the n-th and n+3-th subpixel row (210), or wherein the first control module (311) further comprises a third signal output; and wherein, when k is 2 and j is 2, the first signal output of a b-th stage is connected to the gate of the switching transistor (T1) in the pixel circuit (211a) of the n-th subpixel row (210), the third signal output of the b-th stage is connected to the gate of the switching transistor (T1) in the pixel circuit (211a) of the n+1-th subpixel row (210), and the second signal output of the a-th stage is connected to the gate of the first reset transistor (T3) in the pixel circuit (211a) of the n-th and n+1-th subpixel row (210), and wherein a and b are equal and a is (n+1) / 2, the b-th and a-th stages in this case comprising the n-th and n+1-th subpixels, respectively; if k is 2 and j is 4, the first signal output of the b-th stage is connected to the gate of the switching transistor (T1) in the pixel circuit (211a) of the n-th subpixel row (210), the third signal output of the b-th stage is connected to the gate of the switching transistor (T1) in the pixel circuit (211a) of the n+1-th subpixel row (210), wherein the b-th stage in this case comprises the subpixels of the n+1-th subpixel row (210), the first signal output of a b+1-th stage is connected to the gate of the switching transistor (T1) in the pixel circuit (211a) of the n+2-th subpixel row (210), wherein the b+1-th stage in this case comprises the subpixels of the n+2-th subpixel row (210), the third signal output of the b+1-th stage is connected to the gate of the switching transistor (T1) in the pixel circuit (211a) of the n+3th subpixel row (210), wherein the b+1th stage in this case comprises the subpixels of the n+3th subpixel row (210),and the second signal output of the a-th stage is connected to the gate of the first reset transistor (T3) in the pixel circuit (211a) of the n-th and n+3-th subpixel row (210), and where b is (n+1) / 2 and a is (n+3) / 4, the a-th stage in this case comprising the subpixels of the n-th and n+3-th subpixel row (210). [2] Display panel (100) according to claim 1, characterized bythat, when the first control module (311) comprises only the first signal output, the number of first control modules (311) is greater than the number of second control modules (321), wherein in the first direction (X) the width of the first control module (311) is greater than the width of the second control module (311), and wherein in the second direction (Y) the length of the first control module is less than the length of the second control module (311);and wherein, when the first control module (311) comprises the first signal output and the third signal output, the number of first control modules (311) is the same as the number of second control modules (321), wherein in the first direction (X) the width of the first control module (311) is greater than the width of the second control module (311), and wherein in the second direction (Y) the length of the first control module (311) is less than or equal to the length of the second control module (311); [3] Display panel (100) according to claim 2, characterized bythat the first control module (311) comprises a first pull-up control unit (311a), a first pull-up unit (311b), a first pull-down unit (311c) and a first pull-down maintenance unit (311d), wherein the second control module (321) comprises a second pull-up control unit (321a), a second pull-up unit (321b), a second pull-down unit (321c) and a second pull-down maintenance unit (321d); and wherein in the first direction (X) the width of any pull-up transistor in the first pull-up unit (311b) is greater than the width of any pull-up transistor (T22, T23, T24, T25) in the second pull-up unit (321b), and wherein in the second direction (Y) the length of any pull-up transistor (T22, T23, T24, T25) in the first pull-up unit (311b) is less than the length of any pull-up transistor (T22, T23, T24, T25) in the second pull-up unit (321b). [4] Display panel (100) according to claim 3, characterized bythat a first pull-up control unit (311a) comprises a first pull-up control transistor (T11), wherein a gate of the first pull-up control transistor (T11) is connected to a first stage transmission signal line (Cout1), and wherein a first electrode of the first pull-up control transistor (T11) is connected to a first high-potential line (Vgh1), and wherein a second electrode of the first pull-up control transistor (T11) is connected to a first control node (Q1); and wherein the first pull-up unit (311b) comprises a first pull-up transistor (T21), a second pull-up transistor (T22), and a first storage capacitor (C1), wherein a first electrode of the first pull-up transistor (T21) is connected to a first clock signal line (CK1), and wherein a second electrode of the first pull-up transistor (T21) is connected to a stage transmission signal end (Cout(n)), and wherein a first electrode of the second pull-up transistor (T22) is connected to a second clock signal line (CK2), and wherein a second electrode of the second pull-up transistor (T22) is connected to the first signal output, and wherein the gate of the first pull-up transistor (T21), the gate of the second pull-up transistor (T22), and a first pole plate of the first storage capacitor (C1) are connected to the first control node (Q1) are connected,and wherein a second pole plate of the first storage capacitor (C1) is connected to the stage transmission signal end (Cout(n));, and wherein the first pull-down unit (311c) comprises a first pull-down transistor (T41) and a second pull-down transistor (T42), and wherein the gate of the first pull-down transistor (T41) and the gate of the second pull-down transistor (T42) are connected to a second stage transfer signal line (Cout2), and wherein a first electrode of the first pull-down transistor (T41) is connected to the first control node, and wherein the second electrode of the first pull-down transistor (T41) is connected to the first electrode of the second pull-down transistor (T42), and wherein the second electrode of the second pull-down transistor (T42) is connected to a first low-potential line (Vgl1); and wherein the first pull-down sustain unit (311d) comprises a first pull-down sustain transistor (T31), a second pull-down sustain transistor (T32), a third pull-down sustain transistor (T33), and a first inverter (311e), and wherein the gate of the first pull-down sustain transistor (T31), the gate of the second pull-down sustain transistor (T32), the gate of the third pull-down sustain transistor (T33), and the first inverter (311e) are connected to a second control node (P1), and wherein a first electrode of the first pull-down sustain transistor (T31) is connected to a second electrode of the first pull-up transistor (T21), and wherein a second electrode of the first pull-down sustain transistor (T31) is connected to the first low-potential line (Vgl1), and wherein a first electrode of the second pull-down maintenance transistor (T32) is connected to a second electrode of the second pull-up transistor (T22),and wherein a second electrode of the second pull-down maintenance transistor (T32) is connected to a second low-potential line (Vgl2), and wherein a first electrode of the third pull-down maintenance transistor (T33) is connected to the first control node (Q1), and wherein a second electrode of the third pull-down maintenance transistor (T32) is connected to the first low-potential line (Vgl1);, and wherein the first inverter (311e) is used to invert the potentials of the first control node (Q1) and the second control node (P1). [5] Display panel (100) according to claim 4, characterized bythat the first pull-up unit (311b) further comprises a third pull-up transistor (T23), wherein a first electrode of the third pull-up transistor (T23) is connected to a third clock signal line (CK3), and wherein a second electrode of the third pull-up transistor (T23) is connected to the third signal output, and wherein the gate of the third pull-up transistor (T23) is connected to the first control node (Q1); and wherein the first pull-down sustain unit (311d) comprises a fourth pull-down sustain transistor (T34), and wherein a first electrode of the fourth pull-down sustain transistor (T34) is connected to a second electrode of the third pull-up transistor (T23), and wherein a second electrode of the fourth pull-down sustain transistor (T34) is connected to the second low-potential line (Vgl2), and wherein the gate of the fourth pull-down sustain transistor (T34) is connected to the second control node (P1). [6] Display panel (100) according to claim 4 or 5, characterized by that the second pull-up control unit (321a) comprises a second pull-up control transistor (T12), wherein a gate of the second pull-up control transistor (T12) is connected to a first signal transmission line (INI-1), and wherein a first electrode of the second pull-up control transistor (T12) is connected to a second high-potential line (Vgh2), and wherein a second electrode of the second pull-up control transistor (T12) is connected to a third control node (Q2); and wherein the second pull-up unit (321b) comprises a fourth pull-up transistor (T24) and a second storage capacitor (C2), and wherein a first electrode of the fourth pull-up transistor (T24) is connected to a fourth clock signal line (CK4), and wherein a second electrode of the fourth pull-up transistor (T24) is connected to the second signal output (INI(n)), and wherein the gate of the fourth pull-up transistor (T24) and a first pole plate of the second storage capacitor (C2) are connected to the third control node (Q2), and wherein a second pole plate of the second storage capacitor (C2) is connected to the second signal output (INI(n)); and wherein the second pull-down unit (321c) comprises a third pull-down transistor (T43) and a fourth pull-down transistor (T44), and wherein the gate of the third pull-down transistor (T43) and the gate of the fourth pull-down transistor (T44) are connected to a second signal transmission line (INI-2), and wherein a first electrode of the third pull-down transistor (T43) is connected to the third control node (Q2), and wherein the second electrode of the third pull-down transistor (T43) is connected to the first electrode of the fourth pull-down transistor, and wherein the second electrode of the fourth pull-down transistor (T44) is connected to a first low-potential line (Vgl1); and wherein the second pull-down sustain unit (321d) comprises a fifth pull-down sustain transistor (T35), a sixth pull-down sustain transistor (T36), a seventh pull-down sustain transistor (T37), and a second inverter (321e), and wherein the gate of the fifth pull-down sustain transistor (T35), the gate of the sixth pull-down sustain transistor (T36), the gate of the seventh pull-down sustain transistor (T37), and the second inverter (321e) are connected to a fourth control node (P2), and wherein a first electrode of the fifth pull-down sustain transistor (T35) is connected to a second electrode of the fourth pull-up transistor (T34), and wherein a second electrode of the fifth pull-down sustain transistor (T35) is connected to the first low-potential line (Vgl1), and wherein a first electrode of the sixth pull-down maintenance transistor (T36) is connected to the third control node (Q2),and wherein a second electrode of the sixth pull-down sustain transistor (T36) is connected to a first electrode of the seventh pull-down sustain transistor (T37), and wherein a second electrode of the seventh pull-down sustain transistor (T37) is connected to the first low-potential line (Vgl1);, and wherein the second inverter (321e) is used to invert the potentials of the third control node (Q29) and the fourth control node (P2). [7] Display panel (100) according to claim 6, characterized bythat the second pull-up transistor (T22) or the third pull-up transistor (T23) comprises a first gate (T22G), a first source (T22S), a first drain (T22D) and a first active section (T22A), wherein the first gate (T22G) is provided between the first source (T22S) and the first drain (T22D), and wherein the first active section (T22A) overlaps the first gate (T22G), the first source (T22S) and the first drain (T22D), respectively; and wherein the fourth pull-up transistor (T24) comprises a second gate (T24G), a second source (T24S), a second drain (T24D), and a second active section (T24A); wherein the second gate (T24G) is arranged between the second source (T24S) and the second drain (T24D), and wherein the second active section (T24A) overlaps the second gate (T24G), the second source (T24S), and the second drain (T24D), respectively; and wherein a channel length of the first active section (T22A) is smaller than a channel length of the second active section (T24A). [8] Display panel (100) according to claim 7, characterized by in that the first source (T22S) comprises a first trunk source (T22Sa) and a plurality of first branch sources (T22Sb) connected to the first trunk source (T22Sa), wherein the first drain (T22D) comprises a first trunk drain (T22Da) and a plurality of first branch drains (T22Db) connected to the first trunk drain (T22Da), and wherein the first trunk source (T22Sa) and the first trunk drain (T22Db) extend along the second direction (Y), and wherein the first branch source (T22Sa) and the second branch source (T22Sb) extend along the first direction (X), and wherein the plurality of first branch sources (T22Sb) and the plurality of first branch drains (T22Db) are arranged one after the other at intervals along the second direction (Y); and wherein the second source (T24S) comprises a second root source (T24Sa) and a plurality of second branch sources (T24Sb) connected to the second root source (T24Sa), and wherein the second drain (T24D) comprises a second root drain (T24Da) and a plurality of second branch drains (T24Da) connected to the second root drain (T24Da), and wherein the second root source (T24Sa) and the second root drain (T24Db) extend along the second direction (Y), and wherein the second branch source (T24Sa) and the second branch source (T24S) extend along the first direction (X), and wherein the plurality of second branch sources (T24Sb) and the plurality of second branch drains (T24Db) are arranged sequentially along the second direction (Y) at intervals; and wherein the first active section (T24A) comprises a plurality of first active subsections (T22Aa) arranged along the first direction (X), each of the first active subsections (T22Aa) overlapping the first gate (T22G), the first branch source (T22Sb), and the first branch drain (T22Db), and wherein the second active section (T24A) comprises a plurality of second active subsections (T24Aa) arranged along the first direction (X), each of the second active subsections (T24Aa) overlapping the second gate (T24G), the second branch source (T22Sb), and the second branch drain (T24Db). [9] Display panel (100) according to claim 8, characterized bythat in the first direction (X) a width of the first active subsections (T22Aa) and a width of the second active subsections (T24Aa) are the same, in the second direction (Y) a length of the first active subsections (T22Aa) is less than a length of the second active subsections (T24Aa) and the number of first active subsections (T22Aa) is greater than the number of second active subsections (T24Aa). [10] Display panel (100) according to claim 6, characterized bythat the drive section (300) further comprises a third driver circuit (330), wherein the first driver circuit (310), the second driver circuit (320) and the third driver circuit (330) are arranged along the first direction (X), wherein the third driver circuit (330) comprises a plurality of third drive modules (331) arranged along the second direction (Y), and wherein each of the third drive modules (331) comprises a fourth signal output (Ref(n)); and wherein the pixel circuit (211a) further comprises a second reset transistor (T4), wherein the second reset transistor (T4) and the switching transistor (T1) are connected to the first reset node (G); and wherein one of the fourth signal outputs (Ref(n)) is connected to the gate of the second reset transistor (T4) of a pixel circuit (211a) in the adjacent j subpixel rows (210), and wherein the fourth signal output (Ref(n)) of the a-th stage is the same as the pixel circuit (211a) of the subpixel row (210) to which the second signal output of the a-th stage is connected. [11] Display panel (100) according to claim 10, characterized by that the third driver circuit (330) comprises: a third pull-up control unit (331a) comprising a third pull-up control transistor (T13) and a fourth pull-up control transistor (T14), wherein the gate of the third pull-up control transistor (T13) and the gate of the fourth pull-up control transistor (T14) are each connected to the second signal output (INI(n)), and wherein the first electrode of the third pull-up control transistor (T13) is connected to a third high-potential line (Vgh3), and wherein a second electrode of the third pull-up control transistor (T13) is connected to a first electrode of the fourth pull-up control transistor (T14), and wherein a second electrode of the fourth pull-up control transistor (T14) is connected to a fifth control node (Q3); a third pull-up unit (331b) comprising a fifth pull-up transistor (T25) and a third storage capacitor (C3), wherein a first electrode of the fifth pull-up transistor (T25) is connected to a fourth high-potential line (Vgh4), and wherein a second electrode of the fifth pull-up transistor (T25) is connected to the fourth signal output (Ref(n)), and wherein the gate of the fourth pull-up transistor (T24) and a first pole plate of the third storage capacitor (C3) are connected to the fifth control node (Q3), and wherein a second pole plate of the third storage capacitor (C3) is connected to the fourth signal output (Ref(n)); a third pull-down unit (331c) comprising a fifth pull-down transistor (T45) and a sixth pull-down transistor (T46), wherein the gate of the fifth pull-down transistor (T45) and the gate of the sixth pull-down transistor (T46) are connected to the first signal output, and wherein a first electrode of the fifth pull-down transistor (T45) is connected to the fifth control node (Q3), and wherein a second electrode of the fifth pull-down transistor (T45) is connected to a first electrode of the sixth pull-down transistor (T46), and wherein a second electrode of the sixth pull-down transistor (T46) is connected to the second low-potential line (Vgl2); a third pull-down sustain unit (331d) comprising an eighth pull-down sustain transistor (T38), a ninth pull-down sustain transistor (T39), a tenth pull-down sustain transistor (T31a), an eleventh pull-down sustain transistor (T31b), a twelfth pull-down sustain transistor (T31c), and a potential-increasing unit (331e), wherein the gate of the eighth pull-down sustain transistor (T38), the gate of the ninth pull-down sustain transistor (T39), the gate of the tenth pull-down sustain transistor (T31a), and the potential-increasing unit (331e) are connected to a sixth control node (P3), and wherein a first electrode of the eighth pull-down sustain transistor (T38) is connected to a second electrode of the fifth pull-up transistor (T25), and wherein a second electrode of the eighth pull-down maintenance transistor (T38) is connected to a third low-potential line (Vgl3),and wherein a first electrode of the ninth pull-down sustain transistor (T39) is connected to the fifth control node (Q3), and wherein a second electrode of the ninth pull-down sustain transistor (T39) is connected to a first electrode of the tenth pull-down sustain transistor (T31a), and wherein a second electrode of the tenth pull-down sustain transistor (T31a) is connected to the second low-potential line (Vgl2), and wherein the gate of the eleventh pull-down sustain transistor (T31b) is connected to the fifth control node (Q3), and wherein a first electrode of the eleventh pull-down sustain transistor (T31b) is connected to the sixth control node (Q3), and wherein a second electrode of the eleventh pull-down sustain transistor (T31b) is connected to the second low-potential line (Vgl2), and wherein the gate of the twelfth pull-down maintenance transistor (T31c) is connected to the second signal output,and wherein a first electrode of the twelfth pull-down maintenance transistor (T31c) is connected to the sixth control node (P3), and wherein a second electrode of the eleventh pull-down maintenance transistor (T31b) is connected to the second low-potential line (Vgl2);, and wherein the potential increasing unit (331e) is used to invert the potentials of the fifth control node (Q3) and the sixth control node (P3).

Images