Power field-effect transistor featuring a fin

Abstract

The invention relates to a power field-effect transistor having a fin (FinFET) (100), wherein the power FinFET (100) comprises: a drain contact (1), a substrate region (2) of a first doping type oriented towards the drain contact (1), a drift region (3) of the first doping type having a base (31) with a side surface (32) and a mesa region forming the fin (33), a first passivation layer (5) partially oriented towards the fin (33) and extending partially parallel to the side surface (32), a gate contact (7) at least partially oriented towards the first passivation layer (5), a second passivation layer (8) separating the gate contact (7) and a source contact (6) oriented towards a top surface of the fin (33), wherein a material of the substrate region (2) and the drift region (3) is an ultra-wide bandgap semiconductor material.

Description

Technical field

[0001] The invention relates to a power field-effect transistor having a fin. background

[0002] Junctionless field-effect transistors (FETs) are increasingly preferred for applications requiring comparatively high power transmission, particularly in the medium-voltage range of 1200 V to 3300 V, intended for automotive and industrial applications. FETs are vertical unipolar devices that incorporate one or more conductive layers of a doped type that exhibits low activation energy and numerous free charge carriers without compromising blocking capability or the dynamic response associated with deep layers. The conductive layer features a mesa region that forms a fin. This type of FET is called FinFET. Compared to planar FETs, the fin enables significantly faster switching times and higher current density.

[0003] In addition to the conductivity layer, power FinFETs incorporate a passivation layer, preferably an oxide layer, for the gate. This passivation layer introduces energy barriers, preferably against both conduction and valence bands, and enables gate control within the fin. To ensure effective gate control, this passivation layer must exhibit only minimal interfacial traps at the semiconductor interface. To reduce leakage currents, it is known to use a material with a different doping type.

[0004] Due to their remarkable material properties, such as low intrinsic carrier concentration and high electric field strength, ultra-wide bandgap semiconductor materials have emerged as a compelling option for conduction layers in power electronics. The exceptional impact ionization coefficients exhibited by these materials facilitate the reduction of the conduction layer size, for example, the drift region. Consequently, this miniaturization contributes to improved on-resistance compared to silicon and other wide bandgap semiconductors, such as 4H silicon carbide (4H-SiC) and gallium nitride (GaN), while maintaining equivalent blocking capabilities.

[0005] Nevertheless, challenges related to inadequate doping control and premature breakdown failure have limited the potential improvement in electrical performance in device structures. Furthermore, power FinFETs fabricated from ultra-wide bandgap materials face various challenges and reliability issues, such as…premature breakdowns due to high gate leakage currents or oxide defects, the effectiveness of the gate control which depends on the quality of the interface, affecting the on / off performance and mobility, which is particularly influenced by the interface between the passivation layer and the conductivity layer, inadequate operation in quadrant III due to the lack of an intrinsic body diode, and limited short-circuit performance if the conductivity layer is made of a material with poor thermal conductivity.

[0006] Alternative approaches to addressing premature breakdowns introduce a second-type layer that shifts the maximum electric field away from the passivation layer interface. However, this technique may not be as effective for ultra-wide-bandgap power FinFETs due to poor controllability of the second-type doping and high activation energy.

[0007] To address the inadequate operation in quadrant III, an alternative layout was introduced, featuring a Schottky diode with a trench metal-oxide-semiconductor barrier and a depletion-free FET. However, the disadvantage of this approach lies in the limited availability of active device area. Furthermore, techniques employing p-shielding typically stipulate that the potential of this layer must be coupled to the source terminal and thus grounded throughout the device's operation. This approach has certain limitations, as the presence of a significant depletion region can limit the forward current.

[0008] Therefore, there is a great need for a power FinFET that uses an ultra-wide bandgap semiconductor material for conductivity layers in order to exploit its advantages while simultaneously overcoming the aforementioned disadvantages. This invention aims to overcome these problems. Disclosure of the invention

[0009] This task is solved in a surprisingly simple but effective manner by a power field-effect transistor having a fin (FinFET), wherein the power FinFET comprises: a drain contact, a substrate region of a first doping type oriented towards the drain contact, a drift region of the first doping type having a base with a side face and a mesa region forming the fin, a first passivation layer partially oriented towards the fin and extending partially parallel to the side face, a gate contact at least partially oriented towards the first passivation layer, a second passivation layer separating the gate contact and a source contact oriented towards a top face of the fin, wherein a material of the substrate region and the drift region is an ultra-large bandgap semiconductor material.The power FinFET is characterized in that the power FinFET has a barrier layer that is oriented towards the side surface, wherein the barrier layer has a second doping type.

[0010] The core idea of ​​the invention is to reduce the electric field at the junction between the base and the fin when the power FinFET is switched on. This reduces premature breakdowns of the power FinFET. In particular, this protective mechanism plays an important role in mitigating problems such as time-dependent dielectric breakdown (TDDB) and hot carrier injection.

[0011] The power FinFET according to the invention has a drain contact formed by a suitable material that ensures a low-resistance path which can be connected to a control circuit that operates the power FinFET.

[0012] A substrate region of first doping type is oriented towards the drain contact. Thus, electric current can be transferred between the substrate region and the drain contact. The first doping type can be either n-doped or p-doped. The substrate region material is an ultra-wide bandgap semiconductor material. An ultra-wide bandgap semiconductor material is one with a bandgap significantly larger than that of standard bandgap semiconductor materials. A semiconductor material with a bandgap greater than 3.4 eV is generally considered to have an ultra-wide bandgap semiconductor material. Examples of ultra-wide bandgap semiconductors include...

[0013] A drift region of the first doping type is oriented towards the substrate region. The first doping type of the drift region can be either n-doped or p-doped, as long as the doping type is identical to that of the substrate region. The substrate region material is an ultra-wide bandgap semiconductor material, preferably the same material as the substrate region. The drift region preferably has a lower doping concentration than the substrate region. The purpose of the drift region is to provide intrinsic charge carriers in a switched-on state of the power FinFET and to suppress intrinsic charge carriers in a switched-off state of the power FinFET. The drift region and the substrate region are conductive layers.

[0014] The ultra-wide bandgap semiconductor material can be monoclinic gallium(III) oxide (β-Ga₂O₃), aluminum nitride (AlN), or diamond. In β-Ga₂O₃, n-type doping can be achieved by silicon implantation or tin incorporation during epitaxial growth. Both dopants create shallow donor levels within the bandgap. P-type doping can be achieved using nickel oxide or iridium gallium oxide (α-(IrGa)₂O₃) in combination with corundum gallium oxide (α-Ga₂O₃). Nickel oxide exhibits p-type conductivity, which is associated with defects, such as lithium vacancies, that can be adjusted by high-frequency sputtering of argon or oxygen flow control. Similarly, α-(IrGa)₂O₃, in combination with the α-Ga₂O₃ polymorph, has proven effective in providing p-type conductivity. In AlN, n-type doping can also be achieved with silicon. p-type doping appears to be possible with beryllium.In diamond, n-type doping can be achieved using phosphorus or nitrogen, and p-type doping using boron. When AlN or diamond is used, a first, second, and / or third passivation layer is preferably produced from aluminum oxide (Al₂O₃) or silicon dioxide (SiO₂).

[0015] The drift region comprises a base with a lateral surface and a mesa region forming the fin. The lateral surface extends along the upper surface of the base from the fin to the base's edge. The fin preferably exhibits a region of high doping concentration on its upper surface.

[0016] A first passivation layer is partially aligned with the fin and extends partially parallel to the side surface. The passivation layer preferably has an L-shaped cross-section, with one leg of the L oriented towards the fin and the other leg oriented towards the side surface. Preferably, the passivation layer material is an oxide. The passivation layer provides galvanic isolation between the drift region and a gate contact. The gate contact is at least partially aligned with the first passivation layer. The passivation layer can extend further than the gate contact. The potential difference between the gate contact and a source contact controls the on / off state of the power FinFET via the electric field that builds up between the gate contact and the source contact in the fin.The gate contact ensures a low-resistance path that can be connected to the control circuit that operates the power FinFET.

[0017] A second passivation layer separates the gate contact from the source contact, which is aligned with one side of the fin. The potential difference between the source and drain contacts causes a flow of charge carriers, if present. The source contact provides a low-resistance path that can be connected to the control circuitry that operates the power FinFET. Thus, electrical current can flow between the drift region and the source contact.

[0018] Preferably, the source contact, the drain contact and / or the gate contact are metal contacts that have an ohmic characteristic.

[0019] Preferably, the power FinFET has a third passivation layer located between the side face and the first passivation layer. The first and third passivation layers can be made of identical or different materials, depending on the preferred process and the desired quality or type of interface between the third passivation layer and the side face. The third passivation layer can extend alongside the barrier layer or at least partially onto a top surface of the barrier layer. If the third passivation layer is located alongside the barrier layer, the lengths of the third passivation layer and the barrier layer can be varied to fine-tune state power and state conductivity.

[0020] A barrier layer is oriented towards the side face, and this barrier layer has a second doping type. The second doping type is different from the first. The second doping type can be n-doped if the first doping type is p-doped, or p-doped if the first doping type is n-doped. Therefore, a power FinFET with long-term reliability is obtained.

[0021] Advantageous embodiments of the invention, which can be implemented individually or in combination, are described in the dependent claims.

[0022] In an advantageous embodiment of the invention, it is conceivable that the barrier layer is at least partially made of a first material, wherein the first material is identical to the material of the substrate region. This enables effective protection of the first passivation layer. The disadvantage of a low switching speed, caused by the dynamics of incomplete ionization, can be compensated for by the poor thermal conductivity of most ultra-large bandgap materials, in particular β-Ga₂O₃. The continuous operation of the power FinFET raises the temperature at the base-fin junction to a level sufficient to enable good activation of dopant species in the barrier layer.

[0023] In an advantageous embodiment of the invention, it is conceivable that the barrier layer is at least partially made of a second material, wherein the second material differs from the material of the substrate region. This ensures correct operation of the power FinFET at low temperatures with fast switching speeds. The barrier layer provides a high number of charge carriers and enables more robust operation in the third quadrant. Preferably, the material is an oxide, in particular NiO. The barrier layer can be made partially of the first material and partially of the second material, with the materials arranged one above the other or side by side.

[0024] In an advantageous embodiment of the invention, it is conceivable that the barrier layer extends from an edge of the base to the fin. This provides the best protection for the first passivation layer. However, to improve state performance and state conductivity, it is conceivable to shorten the barrier layer on the fin side and / or on the edge side.

[0025] In an advantageous embodiment of the invention, the barrier layer can be multi-part. A multi-part layer refers to a discontinuous layer. Preferably, all parts of the multi-part layer are arranged on the same plane. The barrier layer, as well as the first passivation layer, the gate contact, the second passivation, the third passivation layer, a conductive layer, and / or a metal layer, are preferably at least two-part, and the two parts are arranged on opposite sides of the fin. Alternatively, the barrier layer, the first passivation layer, the gate contact, the second passivation, the third passivation layer, the conductive layer, and / or the metal layer form a loop that surrounds the fin. Furthermore, the barrier layer can be multi-part and arranged in a regular or irregular structure along the lateral surface.The barrier layer can have 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20 or more parts. This allows for the adjustment of desired performance characteristics, such as the degree of transparency.

[0026] In an advantageous embodiment of the invention, the power FinFET may have a metal layer and / or a conductive layer oriented towards the second passivation layer and extending from the base and / or the barrier layer. The metal layer reduces leakage current by forming a Schottky barrier between the metal layer and the drift region. The conductive layer is connected to the barrier layer, thus enabling a connection between the barrier layer and the control circuit. This leads to a further attenuation of the electric field present in the first passivation layer. Preferably, the metal layer and / or the conductive layer can extend to the same height as the fin. More preferably, the metal layer and / or the conductive layer is grounded, floating, or connected to the control circuit that operates the power FinFET.When grounded or connected to the control circuit, the metal layer and / or the conductive layer can serve as an additional current path in quadrant III operation, thereby reducing the intensity of the electric field at the base-fin junction. Connection to the control circuit allows for additional control and thus reduces the disadvantages of incorporating the metal layer and / or the conductive layer. A floating metal layer and / or the conductive layer are readily available.

[0027] In an advantageous embodiment of the invention, it is conceivable that the metal layer and / or the conductive layer between the lateral surface and the first passivation layer extends towards the fin. This layout reduces the intensity of the electric field at the junction between the base and the fin, thereby improving the lifetime of the power FinFET. Preferably, the metal layer and / or the conductive layer extends towards the fin.

[0028] In an advantageous embodiment of the invention, it is conceivable that the metal layer and / or the conductive layer extends alongside the barrier layer. This layout reduces the intensity of the electric field at the junction between the base and the fin, thereby improving the lifetime of the power FinFET.

[0029] In an advantageous embodiment of the invention, the power FinFET may have a circuit comprising a first junction, a first resistor, a second junction, a second resistor, and a third junction connected in series, wherein the first junction is connected to the gate contact, the second junction is connected to the metal layer and / or the conductive layer, and the third junction is grounded. The barrier layer has the disadvantage of potentially reducing the breakdown voltage of the power FinFET, increasing the electric field in the off-state, and increasing the gate-drain capacitance of the power FinFET. A circuit as described above mitigates the risk of parasitic diode turn-on.The first resistor and / or the second resistor are preferably ten times larger than a gate resistor connected to the gate contact. More preferably, the first resistor and / or the second resistor are larger than 1 kΩ. More preferably, the second resistor is 20% of the first resistor. Most preferably, the first resistor has a positive temperature coefficient and / or the second resistor has a negative temperature coefficient.

[0030] In an advantageous embodiment of the invention, the circuit may include a diode connected in parallel to the first resistor, with the diode forward-biased from the second junction to the first junction, and / or a capacitor connected in parallel to the second resistor. This allows for negative biasing of the metal layer and / or the conductive layer, thereby providing complete protection of the first passivation layer and / or the third passivation layer and improving the lifetime and reliability of the power FinFET. The capacitance of the capacitor is preferably in the range of 0.1 pF to 20 pF, more preferably in the range of 1 pF to 10 pF, and most preferably 5 pF. Brief description of the drawings Fig. Figure 1 shows a cross-sectional side view of a first embodiment of a power FinFET according to the invention; Fig. Figure 2 shows a cross-sectional side view of a second embodiment of a power FinFET according to the invention; Fig. Figure 3 shows a top view of a third embodiment of a power FinFET according to the invention; Fig. Figure 4 shows a cross-sectional side view of a fourth embodiment of a power FinFET according to the invention; Fig. Figure 5 shows a cross-sectional side view of a fifth embodiment of a power FinFET according to the invention; Fig. Figure 6 shows a cross-sectional side view of a sixth embodiment of a power FinFET according to the invention; Fig. Figure 7 shows a circuit diagram of a first embodiment of a circuit connected to a power FinFET arrangement according to the invention, and Fig. Figure 8 shows a circuit diagram of a second embodiment of a circuit connected to a power FinFET arrangement according to the invention. Detailed description of the drawings

[0031] Further details, features, and advantages of the invention are evident from the following description of preferred embodiments in conjunction with the dependent claims. The respective features can be implemented individually or as a combination of several features. The invention is not limited to the described embodiments. The embodiments are shown schematically in the figures. Identical reference numerals in the individual figures refer to identical or functionally equivalent elements, or elements that correspond to each other with respect to their function.

[0032] Fig. Figure 1 shows a cross-sectional side view of a first embodiment of a power FinFET 100 according to the invention. The power FinFET 100 has a drain contact 1 formed by a metal plate that is in direct contact with a substrate region 2. A drift region 3 adjoins the substrate region 2. The substrate region 2 and the drift region 3 are made of an ultra-wide bandgap semiconductor material that is n-doped. The drift region 3 is divided into a base 31 with a side surface 32 and a fin 33. A two-part L-shaped first passivation layer 5 is arranged next to the fin 33, with one leg of the L oriented towards the fin 33 and the second leg parallel to the side surface 32. A two-part L-shaped gate contact 7 is arranged next to the first passivation layer 5.A two-part second passivation layer 8 is located on the top surface of the gate contact 7, encapsulating the gate contact 7. A two-part conductive layer 13 is arranged on the side surface 32 adjacent to the first passivation layer 5 and the second passivation layer 8. The conductive layer 13 is preferably made of metal. A region 4 of high doping concentration is located on the top surface of the fin 33. A source contact 6 is oriented towards the top surface of the fin 33. A two-part third passivation layer 9 is arranged between the side surface 32, the first passivation layer 5, the metal layer 13, and the fin 33. A barrier layer 10 is arranged on the top surface of the base 31, starting from the edge of the base 31 and extending towards the fin 33. The barrier layer 10 is shortened by the distance d on the fin side to improve state performance and state conductivity.The barrier layer 10 is made of the same ultra-large bandgap semiconductor material as the substrate region 2 and the drift region 3, but is p-doped.

[0033] Fig. Figure 2 shows a cross-sectional side view of a second embodiment of a power FinFET 100 according to the invention. The second embodiment is similar to the first embodiment, but the barrier layer 12 and the third passivation layer 9 are arranged side by side. The third passivation layer 9 has a length of a distance d2 by which the barrier layer 10 is shortened. The length of the distance d2 can be varied to tune the state power and state conductance. A metal layer 11 extends from the barrier layer 12. The barrier layer 12 is made of a p-doped oxide.

[0034] Fig. Figure 3 shows a top view of a third embodiment of a power FinFET 100 according to the invention. The third embodiment is similar to the first and second embodiments, but the conductive layer 13 and the barrier layer (not shown) are more segmented. A multi-part metal layer 11, which forms a Schottky barrier with the base (not shown), is arranged between the parts of the metal layer 11 in a regular alternating structure on both sides of the fin 33. The parts of the metal layer 11 have length a1, and the parts of the conductive layer 13 have length a2. The lengths a1 and a2 can be matched to achieve desired performance characteristics. The parts of the barrier layer are arranged below the parts of the conductive layer 13.

[0035] Fig. Figure 4 shows a cross-sectional side view of a fourth embodiment of a power FinFET 100 according to the invention. The fourth embodiment is similar to the first embodiment, but the conductive layer is replaced by an L-shaped metal layer 11, the first leg of which extends parallel to the fin 33 and the second leg of which extends from the edge of the base 31 to the fin 33. The second leg of the metal layer 11 is arranged between the barrier layer 10 and the first passivation layer 5, and replaces the third passivation layer 9 of the first embodiment. The barrier layer 10 is shortened by the distance d on the side of the fin 33 to improve state power and state conductivity.

[0036] Fig. Figure 5 shows a cross-sectional side view of a fifth embodiment of a power FinFET 100 according to the invention. The fifth embodiment is similar to the second embodiment, but the metal layer 11 is L-shaped, with the first leg extending upwards parallel to the fin 33 and the second leg extending from the edge of the base 31 to the fin 33. The second leg of the metal layer 11 is arranged between the barrier layer 12 and the first passivation layer 5, and replaces the third passivation layer 9 of the second embodiment. At the end of the second leg, the metal layer 11 extends downwards to the lateral surface 32 adjacent to the barrier layer 12.

[0037] Fig. Figure 6 shows a cross-sectional side view of a sixth embodiment of a power FinFET 100 according to the invention. The sixth embodiment is similar to the fourth embodiment, but the barrier layer 10 is multi-part, with the parts arranged on both sides of the fin 33 on the lateral surface 32 of the fin 33 and at the edge of the base 31. The parts of the barrier layer 10 on each side of the fin 33 have a length d1 and are spaced apart by a distance d2. Varying d1 and d2 affects the degree of transparency.

[0038] Fig. Figure 7 shows a circuit diagram of a first embodiment of a circuit 14 connected to a power FinFET array according to the invention. The circuit 14 has a first connection point connected to the gate contact 7, a second connection point connected to the conductive layer 13, and a third connection point that is grounded. A first resistor 15 is connected to the first and second connection points. A second resistor 16 is connected to the second and third connection points. The first resistor has a value of 10 kΩ, and the second resistor has a value of 2 kΩ. A gate resistor 19 is connected to the first connection point.

[0039] Fig.Figure 8 shows a circuit diagram of a second embodiment of a circuit 14 connected to a power FinFET array according to the invention. The second embodiment is similar to the first, but a diode 17 is connected in parallel to the first resistor 15, and a capacitor 18 is connected in parallel to the second resistor 16.

Claims

[1] Power field-effect transistor having a fin (FinFET) (100), wherein the power FinFET (100) has: a drain contact (1), a substrate region (2) of a first doping type oriented towards the drain contact (1), a drift region (3) of the first doping type having a base (31) with a side surface (32) and a mesa region forming the fin (33), a first passivation layer (5) oriented partly towards the fin (33) and extending partly parallel to the side surface (32), a gate contact (7) oriented at least partly towards the first passivation layer (5), a second passivation layer (8) separating the gate contact (7) and a source contact (6) oriented towards a top surface of the fin (33), wherein a material of the substrate region (2) and the drift region (3) is an ultra-wide bandgap semiconductor material, characterized by, that the power FinFET (100) has a barrier layer (10, 12) oriented towards the side surface (32), wherein the barrier layer (10, 12) has a second doping type. [2] Power FinFET (100) according to claim 1, characterized by , that the barrier layer (10, 12) is at least partially made of a first material, wherein the first material is the same as the material of the substrate region (2). [3] Power FinFET (100) according to claim 1 or 2, characterized by , that the barrier layer (10, 12) is at least partially made of a second material, wherein the second material is different from the material of the substrate area. [4] Power FinFET (100) according to any one of the preceding claims, characterized by , that the barrier layer (10, 12) extends from an edge of the base (31) to the fin (33). [5] Power FinFET (100) according to any one of the preceding claims, characterized by, that the barrier layer (10, 12) is multi-part. [6] Power FinFET (100) according to any one of the preceding claims, characterized by , that the FinFET (100) has a metal layer (11) and / or a conductive layer (13) that are aligned with the second passivation layer (8) and extend from the base (31) and / or the barrier layer (10, 12). [7] Power FinFET (100) according to claim 6, characterized by , that the metal layer (11) and / or the conductive layer (13) extend / extends between the lateral surface (32) and the first passivation layer (5) towards the fin (33). [8] Power FinFET (100) according to claim 6 or 7, characterized by , that the metal layer (11) and / or the conductive layer (13) extend / extend alongside the barrier layer (10, 12). [9] Power FinFET (100) according to any one of claims 6 to 8, characterized by, that the FinFET (100) has a circuit (14) comprising a first junction point, a first resistor (15), a second junction point, a second resistor (16) and a third junction point connected in series, wherein the first junction point is connected to the gate contact (7), the second junction point is connected to the metal layer (11) and / or the conductive layer (13), and the third junction point is grounded. [10] Power FinFET (100) according to claim 9, characterized by , that the circuit (14) has a diode (17) connected in parallel to the first resistor (15), wherein a forward direction of the diode (17) leads from the second connection point to the first connection point, and / or the circuit (14) has a capacitor (18) connected in parallel to the second resistor (16).

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