Circuit arrangement for controlling a half-bridge circuit
The integrated circuit with edge detection and adjustable time delays provides reliable sequential control of gate drivers, addressing reliability issues in half-bridge circuits by ensuring synchronized shutdown and enablement, even under voltage fluctuations.
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- SCHAEFFLER TECHNOLOGIES AG & CO KG
- Filing Date
- 2024-11-12
- Publication Date
- 2026-05-21
AI Technical Summary
Existing half-bridge circuits in power electronics face reliability issues due to unreliable shutdown/release mechanisms for high-side and low-side gate drivers, particularly under voltage fluctuations, which can lead to asynchronous interventions and potential damage.
A circuit arrangement with an integrated monitoring device and signal processing unit generates sequential shutdown/enable signals for high-side and low-side gate drivers, using edge detection and adjustable time delays to ensure reliable and synchronized control, even under voltage fluctuations.
Enhances operational reliability by ensuring sequential and synchronized shutdown/enabling of gate drivers, reducing the risk of damage and maintaining control integrity during fault conditions.
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Abstract
Description
[0001] The present invention relates to a circuit arrangement for controlling a half-bridge circuit and to the use of such a circuit arrangement.
[0002] In the field of power electronics, for example in power converters (e.g. DC / DC converters or DC / AC converters), controllable half-bridge circuits with one or more half-bridges are often used, each consisting of a series connection of two controllable semiconductor switches (high-side FET switch and low-side FET switch) supplied with a supply voltage, in order to provide a respective output voltage at an output node between the two semiconductor switches.
[0003] DE 198 51 186 A1 discloses an integrated circuit with interface functions between a controller and a potential isolation of a converter, suitable for controlling semiconductor switches with an internal structure including the functions selector, turn-on delay, operating voltage monitoring, clock generation, error processing and storage, DC / DC converter control and driver for several IGBT or MOSFET switches.
[0004] Such a half-bridge can be operated, for example, using PWM control (or another modulation method) to switch the two FET switches on and off in a complementary manner. When the half-bridge is supplied with a DC voltage applied to the series connection of the FET switches, an AC voltage is provided at the output node according to the control method (e.g., PWM control). With several half-bridges operated in parallel, the individual phase voltages and resulting phase currents required for a multi-phase (e.g., three-phase) AC machine can thus be generated, for example, in an inverter.
[0005] The complementary switching on and off of the two FET switches of a half-bridge, high-side FET switch and low-side FET switch, caused by the control, means that switching on one FET switch (e.g. high-side FET switch) is accompanied by switching off the other FET switch (e.g. low-side FET switch), and vice versa.
[0006] In order to achieve the steepest possible edges of the output voltages during switching operations in the half-bridge circuit and thus reduce electrical losses, the high-side and low-side control signals are nowadays usually generated by a microcontroller, especially in the automotive sector, and output to the high-side and low-side gate drivers, which generate sufficiently powerful gate control signals that are applied to the gates (control terminals) of the FET switches.
[0007] However, if the operating range of the microcontroller or the control unit containing the microcontroller is exceeded, e.g. due to over- or undervoltage in the electrical supply of this unit, error-free control of the half-bridge circuit is no longer guaranteed and therefore, in such a fault case, an asynchronous intervention is carried out by the specially provided monitoring device, e.g., a so-called safety computer or "monitoring unit".
[0008] The monitoring device monitors the functionality of the control device used to operate the half-bridge circuit and is designed to generate a digital shutdown / enable control signal for controlling the shutdown / enablement of the gate drivers, depending on the result of this monitoring and, if necessary, other input variables, e.g., from a power supply or other monitoring devices. Thus, if, for example, a fault event detected by the monitoring device occurs during operation of the half-bridge circuit, safety can be maintained by outputting a shutdown / enable control signal to shut down the gate drivers.
[0009] Upon detection of an error event, the gate drivers can be advantageously switched off by means of an appropriate shutdown / enable control signal (for shutdown), in order to switch off, for example, all the high-side FET switches and the low-side FET switches.
[0010] It is an object of the present invention to provide a circuit arrangement that enables reliable shutdown / release of high-side and low-side gate drivers, particularly in power electronics applications.
[0011] The problem is solved by the features of the independent patent claims. Advantageous embodiments are characterized in the dependent claims.
[0012] According to a first aspect, the problem is solved by a circuit arrangement comprising a monitoring device for monitoring the functionality of a control device intended for controlling a half-bridge circuit, wherein the control device is configured to generate a high-side control signal for controlling a high-side gate driver for controlling at least one high-side FET switch of the half-bridge circuit and a low-side control signal for controlling a low-side gate driver for controlling at least one low-side FET switch of the half-bridge circuit. The monitoring device is configured to generate a digital turn-off / enable control signal, depending on a result of the monitoring, for controlling the turn-off / enablement of the two gate drivers.The circuit arrangement further comprises a signal processing device configured to generate a digital high-side shutdown / enable signal for the high-side gate driver and a digital low-side shutdown / enable signal for the low-side gate driver based on the shutdown / enable control signal, such that when the shutdown / enable control signal changes to shut down the gate drivers, the high-side shutdown / enable signal changes immediately and the low-side shutdown / enable signal changes only after a time delay, whereas when the shutdown / enable control signal changes to enable the gate drivers, the low-side shutdown / enable signal changes immediately and the high-side shutdown / enable signal changes only after a time delay.
[0013] When controlling a three-phase machine, it may be desirable, for example, to switch off all high-side FET switches and switch on all low-side FET switches (to short-circuit the motor windings of the three-phase machine) in the event of a fault. To prevent, under all circumstances, a short circuit in the current path of a half-bridge during the gate driver switch-off process, which could be destructive, the circuit arrangement according to the invention allows the gate drivers to be switched off sequentially (one after the other) upon detection of a fault event, thus sequentially bringing the high-side FET switches and the low-side FET switches into their respective designated switching states. Accordingly, in the aforementioned example of controlling a three-phase machine, in the event of a fault, for example...First, all high-side FET switches are switched off, and after a short delay, all low-side FET switches are switched on. Based on this consideration for increasing operational reliability, the gate drivers can also be enabled sequentially (one after the other) to enable the controllability of the high-side and low-side FET switches sequentially.
[0014] In at least one advantageous embodiment according to the first aspect, the circuit arrangement is designed as an integrated circuit. To implement the sequential shutdown / enabling of the high-side and low-side gate drivers, a discretely implemented delay circuit can be used to generate time-delayed signals for the shutdown / enabling of the high-side gate driver and the low-side gate driver, respectively, when the state of the shutdown / enabling control signal changes.
[0015] A disadvantage of this approach, however, is that, for example, due to the failure rate of externally interconnected individual components of the discretely implemented delay circuit, as well as due to unavoidable component tolerances, the delay circuit must be considered potentially unreliable. Furthermore, it is a disadvantage that monitoring or testing the functionality of the delay circuit to rule out latent faults would be relatively costly. The integration, as provided for in the invention, of a shutdown / enabling mechanism, implemented particularly via edge detection, into the integrated circuit (e.g., safety computer or "monitoring unit") which also includes the monitoring device, with two separate shutdown / enabling control signals for high-side and low-side gate drivers, makes it possible to eliminate or at least significantly mitigate the problems described above.
[0016] In at least one advantageous embodiment according to the first aspect, the integrated circuit is designed as a microcontroller component. In another embodiment of the invention, the integrated circuit is designed as an ASIC (application-specific integrated circuit) component.
[0017] Advantageously, the signal processing unit integrated into the circuit according to the invention, and thus the elimination of a complex discrete delay circuit, can significantly increase the reliability during the sequential shutdown / enabling of the gate drivers. Furthermore, the invention enables continuous monitoring and / or periodic or on-demand testing of the signal processing unit's functionality without significant additional effort.
[0018] In at least one advantageous embodiment according to the first aspect, the signal processing device includes an edge detection device for detecting rising edges and / or falling edges of the shutdown / enabling control signal. Regarding the specific implementation of the edge detection device, it is advantageous, for example, to draw upon designs known in digital technology and, in particular, digital signal processing technology.
[0019] In a further embodiment of this device, the edge detection unit comprises a first edge detector for detecting rising edges and a second edge detector for detecting falling edges of the shutdown / enabling control signal. Designs for such selectively rising or falling edge-responsive detectors are well known in digital technology and can be advantageously employed in the invention.
[0020] In a further development, it is provided that the signal processing unit of the edge detection unit includes a signal delay unit downstream. This allows the time delays required by the invention to be achieved in a simple manner.
[0021] If the integrated circuit includes the aforementioned edge detection device with first and second edge detectors, then, for example, first and second signal delay elements can be provided downstream of these to generate the individual time delays. Designs for such signal delay elements are also known in digital technology and can be advantageously used in the invention. In this context, it should be noted that this also enables a very precise and reproducible specification of the time delays. Furthermore, it is possible to provide the two delays with different values and / or adjustability.
[0022] Given that the "delay functionality" of the signal processing device must function reliably regardless of supply voltage fluctuations (which can also affect the integrated circuit), one embodiment of the invention advantageously provides for implementing this functionality and / or the specification of the delays ("dead time" between the edges of the control signals) via an analog function in the signal processing device. This refers, for example, to the use of at least one RC circuit to implement at least one of the delays, circuit-wise similar to the known discrete delay circuit, but with circuit components (resistor R and capacitor C) integrated into the integrated circuit. In particular, this advantageously enables or simplifies an embodiment in which, for example,Even internal resets of an integrated circuit designed as an ASIC or microcontroller have no effect on the functionality of the sequential shutdown. Furthermore, using such an analog function as part of the signal processing unit is advantageously even more robust against supply voltage faults.
[0023] In one embodiment of a system that includes not only the integrated circuit with the monitoring device but also the (monitored) control device, the following functionality can be provided: During startup of the control unit (e.g., a microcontroller's control unit), the two enable / disable lines remain in the disabled state (for disabling the gate drivers) until the computer or the control unit's microcontroller is fully initialized. After the monitoring function of the monitoring unit is activated, the integrated circuit, serving as an external "safety IC (monitoring unit)," first enables the low-side driver's shutdown signal, followed by the high-side driver's shutdown signal. This prevents, for example, (PWM) errors, such as pin toggling, from energizing the output drivers during microcontroller startup and port initialization by the control unit.
[0024] When the safety function in the safety IC shuts down (by outputting a corresponding shutdown / enable control signal), the sequence is reversed. This means that first the shutdown / enable line for the high-side driver is activated (switching off the high-side driver), and only after a delay is the shutdown of the low-side driver initiated. This disconnects the high-side FET switches from the DC link first, and only then, for example when controlling three-phase motors, does the low-side FET switches create an active short circuit of the motor windings. In the application of controlling a half-bridge circuit of a DC / DC converter, the low-side FET switches can alternatively be switched to their off (high-impedance) state by switching off the low-side driver in the aforementioned last step.
[0025] In at least one advantageous embodiment according to the first aspect, the integrated circuit further comprises a self-test device for monitoring the functionality of the signal processing device. The self-test device can, for example, be configured to evaluate the shutdown / enable control signal supplied to the signal processing device, as well as the high-side and low-side shutdown / enable signals generated by the signal processing device. If the evaluation reveals a discrepancy between the evaluated signals, an error signal indicating this error can, for example, be generated.
[0026] According to a further aspect of the invention, the use of an integrated circuit of the type described herein for monitoring the functionality of a control device designed as a microcontroller for controlling a half-bridge circuit is proposed. Alternatively, the integrated circuit could be used to monitor a control device designed as an ASIC.
[0027] According to a further aspect of the invention, the use of an integrated circuit of the type described herein for monitoring the functionality of a control device provided for controlling a half-bridge circuit implemented in a power converter is proposed. The power converter can, for example, be an inverter or at least be operable as an inverter. Alternatively or additionally, the power converter can, for example, be a rectifier or at least be operable as a rectifier.
[0028] As mentioned at the outset, the half-bridge circuit relevant to the use of the invention can comprise one or more (e.g., three) half-bridges (e.g., a so-called B6 bridge), each consisting of two controllable semiconductor switches, a high-side FET switch and a low-side FET switch, connected in series and supplied with a half-bridge supply voltage to provide a respective output voltage at an output node between the two semiconductor switches. Particularly in the automotive sector, the half-bridge supply voltage can be a high voltage from the high-voltage electrical system of the vehicle in question, which here refers to voltages of more than 100 V or even more than 400 V, as is typical for electric vehicles, e.g., approximately 800 V to 1000 V.The control of the half-bridge circuit can be provided, for example, by means of a PWM control or by means of another modulation method, in order to effect a complementary switching on and off of the two FET switches in each half-bridge during operation of the half-bridge circuit.
[0029] In particular, the invention may advantageously be used on board a vehicle, for example in connection with the control of an inverter by means of which a three-phase motor intended for driving the vehicle (e.g., electric vehicle or hybrid vehicle) is operated. The three-phase motor may, in particular, be a three-phase motor.
[0030] The invention is further described below with reference to exemplary embodiments and the accompanying drawings. These depict: Fig. 1 a block diagram of a system with a half-bridge circuit and associated high-side and low-side gate drivers, a control device and a monitoring device according to an embodiment according to the invention. Fig. 2. A representation of the time courses of different signals in the system of Fig. 1, and Fig. 3 a block diagram of a system with a half-bridge circuit and associated high-side and low-side gate drivers, a control device and a monitoring device according to an embodiment according to the invention.
[0031] Fig. Figure 1 illustrates a system with a half-bridge circuit 3 and associated high-side and low-side gate drivers HSGD, LSGD, a control device 1 for controlling the gate drivers and an integrated circuit 11 including a monitoring device 20 for monitoring the functionality of the control device 1.
[0032] In the example, half-bridge circuit 3 forms a circuit with, for example, three half-bridges that are located in the Fig. The inverter of the type shown is implemented for generating three phase voltages and the resulting phase currents to power a three-phase AC machine (e.g., the drive motor of an electric or hybrid vehicle). Each half-bridge is as shown in Fig. 1 shown as a series circuit of two controllable semiconductor switches, a high-side FET switch HST and a low-side FET switch LST, supplied with a supply voltage (e.g. 800 V from a vehicle electrical system), formed to provide the respective output voltage (phase voltage) at a respective output node between the two switches HST, LST.
[0033] In the operation of the half-bridge circuit 3, the high-side FET switch HST and the low-side FET switch LST of each half-bridge are switched on and off in a complementary manner via the high-side gate driver HSGD and the low-side gate driver LSGD.
[0034] The control device 1 (e.g., "engine control unit" in a vehicle) can be designed, for example, as an ASIC or microcontroller component and serves to generate a high-side control signal HSpwm for controlling the high-side gate driver HSGD for controlling the high-side FET switches HST of the half-bridge circuit 3 and a low-side control signal LSpwm for controlling the low-side gate driver LSGD for controlling the low-side FET switches LST of the half-bridge circuit 3.
[0035] In this example, the control device 1 is configured for PWM control and includes a modulator 2 for generating the control signals. If the control device 1 is implemented by a microcontroller, the modulator 2 can represent a functional component of the control device (e.g., part of a control application running on the microcontroller).
[0036] The integrated circuit 11 can also be designed, for example, as an ASIC or microcontroller component and includes the monitoring device 20, which is configured to monitor the functionality of the control device 1 intended for controlling the half-bridge circuit 3. The specific method of this monitoring is described below. Fig. 1, symbolized by a dashed line, can draw on numerous concepts known from the state of the art (e.g., "watchdog", etc.).
[0037] The monitoring device 20 is further configured to generate a digital shutdown / enable control signal DISset, depending on the result of the monitoring performed, to control the shutdown / enablement of the two gate drivers HSGD and LSGD. In this example, it is assumed that a high voltage in the digital signal DISset defines a logic high level (or logic 1) and is intended to "enable," whereas a low voltage defines a low level (or logic 0) and is intended to "shut down," for example, with a high voltage of more than 2.0 V and a low voltage of less than 0.8 V.
[0038] If the monitoring device 20 detects a fault event based on the monitoring, the high-side gate driver LSGD and the low-side gate driver LSGD are sequentially switched off in order to bring the high-side FET switches HST and the low-side FET switches LST of the half-bridge circuit 3 into a controlled, sequential switching state intended for the fault case.
[0039] Conversely, for example after a proper completion of a start procedure of the control device 1 and the monitoring device 2 during commissioning of the system, the high-side gate driver LSGD and the low-side gate driver LSGD are sequentially enabled to allow the controlled sequential activation of the high-side FET switches HST and the low-side FET switches LST (using the high-side and low-side control signals HSpwm, LSpwm).
[0040] The gate drivers LSGD and HSGD are switched off / enabled by means of the control signals supplied for this purpose: a high-side switch-off / enable signal HSdis for the high-side gate driver HSGD and a low-side switch-off / enable signal LSdis for the low-side gate driver LSGD. In this example, it is assumed that for the digital signals HSdis and LSdis, a high voltage defines a logic high level (or logic 1) and enables the respective gate driver, whereas a low voltage defines a low level (or logic 0) and disables the respective gate driver.
[0041] To implement the sequential shutdown / enabling of the high-side and low-side gate drivers HSGD and LSGD, the following is done as described in Fig. As can be seen, a signal processing device 30, which has a discretely implemented delay circuit, is used, to which the shutdown / enabling control signal DISset issued by the monitoring device 20 is input and which appropriately generates the signals HSdis (for the high-side gate driver HSGD) and LSdis (for the low-side gate driver LSGD).
[0042] Fig. Figure 2 shows an example of the time course of the shutdown / release control signal DISset and the resulting time courses of the signals HSdis and LSdis.
[0043] When the DISset signal changes from "0" to "1" (in Fig. 2 links), to enable the gate drivers, then the signal LSdis changes immediately from “0” to “1” (enabling LSGD), whereas the signal HSdis only changes from “0” to “1” (enabling HSGD) after a time delay “Δten”.
[0044] When the DISset signal changes from "1" to "0" (in Fig. 2 right), to switch off the gate drivers (i.e. to prevent PWM control and to bring HST, LST into defined switching states), then the signal HSdis immediately changes from “1” to “0” (switching off HSGD), whereas the signal LSdis only changes from “1” to “0” (switching off LSGD) after a time delay “Δtdis”.
[0045] Returning to Fig. 1 The delay circuit in the exemplary embodiment as shown comprises an RC element formed from a series connection of a resistor R and a capacitor C, a Schmitt trigger, an AND gate, and an OR gate. These components, as shown in Fig. The interconnected components shown in 1 are described in the following text. Fig. 2. The “delay functionality” shown is achieved during the shutdown and release of the gate drivers HSGD and LSGD.
[0046] Unfortunately, reliability and accuracy (e.g., regarding the specified time delays “Δten” and “Δtdis”) cannot be guaranteed, especially over longer operating times.
[0047] The following refers to Fig. 3 An embodiment of an improved system with a configuration according to the invention is described. The same reference numerals are used for components that act identically. Essentially, only the differences from the system already described above with reference to the Fig. 1 and Fig. The embodiment described in section 2 is addressed here, and reference is expressly made to the description of the preceding embodiment.
[0048] Fig. Figure 3 shows a system with a half-bridge circuit 3 and associated high-side and low-side gate drivers HSGD, LSGD and a control unit 1 for controlling the gate drivers HSGD, LSGD by means of high-side and low-side control signals HSpwm, LSpwm output by a modulator 2 of the control unit 1. These components of the system of Fig. Three, for example, are trained as in the example of Fig. 1.
[0049] Furthermore, the system includes Fig. 3 as in the example of Fig. 1 an integrated circuit 10 including a monitoring device 20 for monitoring the functionality of the control device 1 and for generating a digital shutdown / enable control signal DISset for controlling a shutdown / enable of the two gate drivers HSGD, LSGD.
[0050] Unlike, for example, Fig. 1 includes the integrated circuit 10 in Fig. 3. However, a signal processing device 30 is configured to generate, based on the shutdown / enabling control signal DISset generated by the monitoring device 20, a digital high-side shutdown / enabling signal HSdis for the high-side gate driver HSGD and a digital low-side shutdown / enabling signal LSdis for the low-side gate driver LSGD within the integrated circuit. In this case, the integrated circuit 10 forms or comprises the circuit arrangement 5.
[0051] The signal processing unit 30 is used here again to process the information already provided with reference to Fig. 2. The described “delay functionality” is achieved during the shutdown and activation of the gate drivers HSGD, LSGD, i.e., when the shutdown / activation control signal DISset changes to shut down the gate drivers HSGD, LSGD, the high-side shutdown / activation signal HSdis changes immediately and the low-side shutdown / activation signal LSdis only after a time delay “Δtdis”, whereas when the shutdown / activation control signal DISset changes to activate the gate drivers HSGD, LSGD, the low-side shutdown / activation signal LSdis changes immediately and the high-side shutdown / activation signal HSdis only changes after a time delay “Δten”.
[0052] The signal processing device 30 comprises an edge detection device 31, 32, comprising a first edge detector 31 for detecting rising edges of the signal DISset and a second edge detector 32 for detecting falling edges of the signal DISset. The two edge detectors 31, 32, connected in parallel in this example, are each followed by a first and second signal delay element 33, 34 (by means of which the individual time delays “Δten” and “Δtdis” are defined or generated), and as shown in Fig. 3 signal paths are provided in parallel to each of the delay elements 33, 34 in order to output a total of four signals to a driver control 35, which mark, in a sense, the times at which the corresponding changes of the signals LSdis and HSdis are to take place when the signal DISset changes from "0" to "1" (to enable the gate drivers) and when the signal DISset changes from "1" to "0" (to disable the gate drivers).
[0053] With the method of defining the aforementioned time points (or generating the aforementioned four signals) provided here, by means of, for example, a digitally implemented combination of edge detection and signal delay, the required time delays "Δten" and "Δtdis" or the resulting time profiles of the signals LSdis and HSdis can be provided very reliably, precisely, and reproducibly even over extended operating times. In contrast to the illustrated embodiment, it is possible to make the two delays adjustable (e.g., depending on at least one operating parameter detected within the system). In a more advantageous embodiment, the delay functionality of the signal processing unit 30 or the aforementioned delay elements 33, 34 can be implemented via an analog function, e.g.,using at least one RC element formed in the integrated circuit.
[0054] The driver control 35 is configured to control two downstream control signal drivers 36 based on the input signals (four in the example), one (in Fig. 3 upper) control signal driver 36 for generating the HSdis signal and a (in Fig. 3 lower) control signal driver 36 for generating the signal LSdis.
[0055] The control signal drivers 36 are each formed as shown from a series connection of two controllable semiconductor switches, here FETs, supplied with a supply voltage VIO (e.g. 3.3 V), in order to generate at a respective output node between the two switches as a respective output signal of the signal HSdis or LSdis and output to the respective gate driver HSGD or LSGD.
[0056] An advantageous feature of the control signal drivers 36 is that the respective “highside” semiconductor switches are each formed by a so-called “back-to-back” arrangement of two simultaneously controlled FETs, in order to prevent damage to the integrated circuit 10 (in the example an ASIC component, alternatively e.g. a microcontroller) in the event of a fault in which, for any reason, an impermissibly high voltage is present on one of the line paths carrying the signals HSdis and LSdis.
[0057] Another advantageous feature of the integrated circuit 10 or the signal processing device 30 formed therein is that controllable “pull-down” devices 37, here FETs, are provided on the line paths carrying the signals HSdis and LSdis, by means of which, through appropriate control (e.g. in the event of a fault), the voltages or logic levels prevailing on these line paths can be actively pulled to “0” in order to switch off the gate drivers HSGD, LSGD.
[0058] Furthermore, in the integrated circuit 10, a status detection device 41 is provided on each of the line paths (switch-off / enable lines) carrying the HSdis and LSdis signals, as shown, for detecting the logic levels on these line paths. Each of these status detection devices 41 comprises a voltage divider formed from a series connection of resistors for dividing the voltage tapped on the respective path and a Schmitt trigger for generating the respective logic status signals LSstat or HSstat, which are output to a self-test device 40 within the integrated circuit 10. It should be noted that, due to this design of the status detection devices 41, their voltage dividers have an additional "passive pull-down" function, by which (e.g.,In the event of a failure of the aforementioned “active” (controlled) pull-down semiconductor switches and / or failure of their control, the voltages or logic levels prevailing on the line paths are also pulled to “0” (fail-safe behavior).
[0059] The self-test device 40 serves for internal monitoring of the functionality of the signal processing device 30 within the integrated circuit 10 and is designed in the example to evaluate the shutdown / enable control signal DISset supplied to the signal processing device 30 as well as the high-side and low-side shutdown / enable signals HSdis, LSdis generated by the signal processing device 30.
[0060] The example provides that, at least in certain operating situations, such as the commissioning and / or decommissioning of the monitoring device 20 (e.g., due to the commissioning and / or decommissioning of the control device 1 and thus half-bridge circuit 3), a self-test of the signal processing device 30 is performed by means of the self-test device 40. In particular, during a self-test, it may be provided that (e.g., with the power supply to the gate drivers switched off) the self-test device 40 generates a predefined test sequence of the signal DISset (e.g., with several transitions between "0" and "1") and outputs it to the signal processing device 30, and the self-test device 40 then evaluates the resulting status signals LSstat and HSstat to verify the correct function of the signal processing device 30.
[0061] In summary, the invention and the described embodiment offer a significantly enhanced benefit for an integrated circuit implementing the monitoring device of the type of interest here. Integrating a sequential control into an integrated circuit offers several advantages, such as increased robustness against voltage fluctuations and overvoltage. Active structures ensure that the off state (gate driver shutdown) is maintained even at very low supply voltages. Failure rates of an integrated analog function in the signal processing unit are significantly lower than in discrete circuit arrangements. Testing the function of the signal processing unit can be advantageously integrated into a standard automatic self-test (SIST), which is typically already implemented. This allows, for example, the verification of faulty components.Latent errors can be detected, and no additional test is necessary during control unit startup. If an analog function, for example with at least one RC circuit, is provided for implementing the delays provided for in the invention, it should be considered that tolerances in a manufacturing process (e.g. silicon process) are then advantageously much lower than with external discrete circuits. Reference symbol list 1 Control unit 2 Modulator 3 half-bridge circuit HST Highside FET Switch LST Lowside FET Switch HSpwm Highside Control Signal HSGD Highside-Gate Driver LSpwm Lowside Control Signal LSGD Lowside Gate Driver 5 Circuit arrangement 10 integrated circuit VIO supply voltage 20 Monitoring device DISset shutdown / release control signal 30 Signal processing unit HSdis Highside shutdown / enabling signal LSdis Lowside shutdown / enable signal 31. Edge detector (for rising edge) 32. Edge detector (for falling edge) 33 Signal Delay Stage 34 Signal delay stage Δtdis delay (on shutdown) Δth delay (upon release) 35 Driver control 36 Control signal drivers 37 Pull-down device 40 Self-test kit 41 Status recording device HSstat Highside Status Signal LSstat Lowside status signal 100 delay circuit
Claims
Circuit arrangement (5) comprising a monitoring device (20) for monitoring the functionality of a control device (1) provided for controlling a half-bridge circuit (3), wherein the control device (1) is configured to generate a high-side control signal (HSpwm) for controlling a high-side gate driver (HSGD) for controlling at least one high-side FET switch (HST) of the half-bridge circuit (3) and a low-side control signal (LSpwm) for controlling a low-side gate driver (LSGD) for controlling at least one low-side FET switch (LST) of the half-bridge circuit (3), and wherein the monitoring device (20) is configured to generate, depending on a result of the monitoring, a digital turn-off / enable control signal (DISset) for controlling a turn-off / enable of the two gate drivers (HSGD, LSGD), wherein the circuit arrangement (5) further comprises a signal processing device (30) includes,which is designed to generate, based on the shutdown / enable control signal (DISset), a digital high-side shutdown / enable signal (HSdis) for the high-side gate driver (HSGD) and a digital low-side shutdown / enable signal (LSdis) for the low-side gate driver (LSGD), such that when the shutdown / enable control signal (DISset) changes to disable the gate drivers (HSGD, LSGD), the high-side shutdown / enable signal (HSdis) changes immediately and the low-side shutdown / enable signal (LSdis) changes only after a time delay (Δtdis), whereas when the shutdown / enable control signal (DISset) changes to enable the gate drivers (HSGD, LSGD), the low-side shutdown / enable signal (LSdis) changes immediately and the high-side shutdown / enable signal (HSdis) changes only after a time delay (Δten) changes. Circuit arrangement (5) according to claim 1, wherein the circuit arrangement (5) is designed as an integrated circuit (10). Circuit arrangement (5) according to claim 2, wherein the integrated circuit (10) is designed as an ASIC or microcontroller component. Circuit arrangement (5) according to claim 2 or 3, wherein the signal processing device (30) has an edge detection device (31, 32) for detecting rising edges and / or falling edges of the disable / enable control signal (DISset). Circuit arrangement (5) according to claim 4, wherein the edge detection device (31, 32) comprises a first edge detector (31) for detecting rising edges and a second edge detector (32) for detecting falling edges of the shutdown / enabling control signal (DISset). Circuit arrangement (5) according to claim 4 or 5, wherein the signal processing device (30) of the edge detection device (31, 32) has a signal delay device (33, 34) downstream. Circuit arrangement (5) according to one of the preceding claims 2 to 6, further comprising a self-test device (40) for monitoring the functionality of the signal processing device (30), wherein the self-test device (40) is configured to evaluate the shutdown / enable control signal (DISset) supplied to the signal processing device (30) and the high-side and low-side shutdown / enable signals (HSdis, LSdis) generated by the signal processing device (30). Use of a circuit arrangement (5) according to one of the preceding claims 2 to 7 for monitoring the functionality of a control device (1) designed as a microcontroller for controlling a half-bridge circuit (3). Use according to claim 8 on board a vehicle.