Semiconductor device and manufacturing process

Abstract

A pre-cleaning operation is performed using a metal precursor to remove a metal oxide layer from the top surface of a semiconductor device's contact structure before a conductive semiconductor device structure is fabricated on the contact structure. By using the metal precursor as a pre-cleaning agent, system-inherent oxides (and not just components like oxygen) can be completely removed without creating pores on the top surface of the contact structure, thus achieving low contact resistance between the contact structure and the conductive structure.

Description

Cross-reference to related registration

[0001] The present application claims priority over the preliminary US patent application filed on September 4, 2024, with file number 63 / 690.553 and entitled “SEMICONDUCTOR DEVICE AND METHODS OF FORMATION” (“semiconductor device and manufacturing method”), which is incorporated by reference into the present application. background

[0002] An interconnect layer, sometimes referred to as a back-end region or back-end-of-line (BEOL) region, is a region of a semiconductor device containing multiple layers of conductive structures configured to transmit signals and / or provide power distribution throughout the semiconductor device. These multiple layers of conductive structures may include various vertically arranged layers of interconnect structures (e.g., vias) and layers of metallization structures (e.g., trenches, conductive traces, conductor tracks). Brief description of the drawings

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. The Fig. 1A and Fig. Figure 1B shows a part of an exemplary semiconductor device described here. The Fig. Figures 2A to 2F are representations of an exemplary implementation for manufacturing the semiconductor device described here. The Fig. Figures 3A to 3H are representations of an exemplary implementation for creating a source / drain interconnect structure described here. The Fig. Figures 4A to 4D are representations of exemplary implementations of source / drain contact structures and source / drain interconnect structures for the semiconductor device described here. The Fig. Figures 5A to 5E are representations of exemplary implementations of source / drain contact structures and source / drain interconnect structures for the semiconductor device described here. Fig. Figure 6 is a flowchart of an exemplary procedure associated with the fabrication of a semiconductor device described herein. Fig. Figure 7 is a flowchart of an exemplary procedure associated with the fabrication of a semiconductor device described herein. Detailed description

[0004] The disclosure below provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the description below may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of one element or structural element to one or more other elements or structural elements depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90° or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0006] An interconnect layer of a semiconductor device can be fabricated above a device layer of the semiconductor device. The device layer can include a substrate layer of the semiconductor device and integrated circuit devices (e.g., transistors, capacitors, diodes, memory cells) embedded in and / or on the semiconductor substrate. A layer of contact structures (referred to as source / drain contacts) can be used between the integrated circuit devices and the interconnect layer. These contacts electrically connect the integrated circuit devices to a bottom layer of conductive structures (referred to as source / drain interconnects and gate interconnects) within the interconnect layer.

[0007] To create a conductive interconnect layer on a contact structure, a recess can be formed through a dielectric layer to expose the top surface of the contact structure. The conductive material can then be deposited onto this top surface, thus electrically connecting the conductive structure to the contact structure.

[0008] In some cases, a pre-cleaning operation can be performed on the top surface of the contact structure after creating the recess and before depositing the contact structure material. After recess creation, exposure to atmospheric oxygen and / or oxygen used in semiconductor processes for the semiconductor device can cause a thin layer of a metal oxide material (referred to as a "native oxide") to form on the top surface of the contact structure. If this metal oxide layer is not removed, it can increase the contact resistance between the contact structure and the conductive structure. However, the pre-cleaning operation can only remove the oxygen from the metal oxide layer, leaving pores or other types of cavities on the surface of the top of the contact structure.This porosity can increase the contact resistance between the contact structure and the conductive structure.

[0009] In some implementations described here, a pre-cleaning operation is performed using a metal precursor to remove a metal oxide layer from the top surface of a semiconductor device's contact structure before a conductive structure of the semiconductor device is fabricated on the contact structure. The metal precursor may be a metal precursor of a metal material of the contact structure, a metal precursor of a metal material of the conductive structure, and / or another metal precursor.The metal precursor can be a halogen-based metal precursor that etches and removes both the oxygen and metal components of the metal oxide layer on the top surface of the contact structure, rather than removing only the oxygen component of the metal oxides (which could otherwise lead to the formation of pores on the top surface of the contact structure, increasing the contact resistance between the contact structure and the conductive structure). The resulting top surface of the contact structure after the pre-cleaning operation is smooth and essentially free of pores and other cavities.

[0010] In this way, by using the metal precursor as a pre-cleaning agent, system-inherent oxides (and not just components like oxygen) can be completely removed without creating pores on the top surface of the contact structure, thus achieving low contact resistance between the contact structure and the conductive structure. Furthermore, the metal precursor can also etch a portion of the metal material on the top surface of the contact structure, slightly bareging it and providing a larger surface area for the conductive structure to contact the contact structure. This increased surface area further reduces the contact resistance between the conductive structure and the contact structure.

[0011] The Fig. 1A and Fig. Figure 1B shows a portion of an exemplary semiconductor device 100 described herein. The semiconductor device 100 may include: a system-on-chip (SoC) device, a logic device such as a main processor (CPU) or a graphics processing unit (GPU), a storage device such as a high-bandwidth memory (HBM) device, a panel driver device, an integrated circuit (IC) driver, an RF power amplifier, a display driver IC (DDIC), and / or other types of semiconductor devices.

[0012] As in Fig. As shown in Figure 1A, the semiconductor device 100 can have a device layer 102 and an interconnect layer 104 above the device layer 102 in a z-direction within the semiconductor device 100. The device layer 102 has a substrate layer 106. The substrate layer 106 can correspond to a portion of a semiconductor wafer on which the semiconductor device 100 is fabricated. The substrate layer 106 comprises: a silicon substrate (Si substrate); a substrate made of a material containing silicon; a substrate made of a III-V compound semiconductor material such as gallium arsenide (GaAs); a silicon-on-insulator substrate (SOI substrate); or another type of semiconductor substrate. The substrate layer 106 can extend in an x-direction and / or a y-direction within the semiconductor device 100.

[0013] A dielectric layer 108 is arranged above the substrate layer 106. The dielectric layer 108 comprises an interlayer dielectric layer (ILD layer; e.g., an ILDo layer), an etch-stop layer (ESL), and / or another type of dielectric layer. The dielectric layer 108 contains one or more dielectric materials that enable different parts of the substrate layer 106 to be selectively etched or protected against etching and / or electrically insulated integrated circuit devices 110 in the device layer 102. The dielectric layer 108 contains a silicon nitride (Si x N y ), an oxide [e.g., a silicon oxide (SiO₂) x ) and / or another oxide material] and / or another type of dielectric material. The dielectric layer 108 can extend in the semiconductor device 100 in the x-direction and / or the y-direction.

[0014] The integrated circuit devices 110 can be arranged in and / or on the substrate layer 106 and / or in the dielectric layer 108 in the device layer 102 of the semiconductor device 100. The integrated circuit devices 110 comprise transistors [e.g., planar transistors, fin field-effect transistors (FinFETs), gate-all-around transistors (GAA transistors)], pixel sensors, capacitors, resistors, inductors, photodetectors, transceivers, transmitters, receivers, optical circuits, and / or other types of semiconductor devices.

[0015] An integrated circuit device 110 can have a plurality of source / drain regions 112 that are grown on portions of the substrate layer 106 and / or around these portions and / or are generated in some other way. “Source / drain regions” can, depending on the context, refer individually or collectively to a source or a drain. The source / drain regions 112 can be generated by epitaxial growth of doped semiconductor regions and / or by another semiconductor process. In some implementations, the source / drain regions 112 are generated in recessed areas in the substrate layer 106. The recessed areas can be produced by strained source / drain etching (SDD etching) of the substrate layer 106 and / or by another type of etching operation. In some implementations, the source / drain regions 112 are generated in recesses created in a stack of alternating channel layers and sacrificial layers, e.g.,Silicon germanium layers (SiGe layers) are produced.

[0016] The integrated circuit device 110 can also include a dielectric gate layer 114 between a gate structure 116 and channel layers 118 of the integrated circuit device 110. The channel layers 118 can extend between the source / drain regions 112 of the integrated circuit device 110, and the dielectric gate layer 114 and the gate structure 116 can enclose two or more sides of the channel layers 118. In some implementations, the dielectric gate layer 114 and the gate structure 116 enclose all four sides of the channel layers 118. In these implementations, the integrated circuit device 110 can be described as a nanostructured transistor, such as a GAA transistor.

[0017] The channel layers 118 can comprise nanoscale layers of a semiconductor material, including silicon (Si), silicon germanium (SiGe), and / or doped silicon. The channel layers 118 can be fabricated from silicon nanosheets that are part of a nanosheet stack above the substrate layer 106.

[0018] In some implementations, the dielectric gate layer 114 contains a dielectric material with a low dielectric constant (low-k material), such as silicon oxide (SiO₂). x In some implementations, the dielectric gate layer 114 contains a dielectric material with a high dielectric constant (high-k material), such as hafnium oxide (HfO₂). x ).

[0019] The gate structure 116 can be arranged laterally between the source / drain regions 112. In some implementations, the gate structure 116 is made of a polysilicon material. In these implementations, the polysilicon material can be doped with one or more types of dopants (e.g., p- or n-dopeds) to adjust the work function of the gate structure 116.

[0020] In some implementations, the gate structure 116 is fabricated from one or more metallic materials, e.g., tungsten (W), titanium (Ti), cobalt (Co), and / or another metal. In these implementations, the gate structure 116 may include one or more work function metal layers (e.g., p- or n-metal layers) for adjusting the work function of the gate structure 116. The one or more work function metal layers may be positioned between the dielectric gate layer 114 and the gate structure 116.

[0021] A p-work function metal layer can contain one or more p-metals, such as tungsten (W), cobalt (Co), titanium nitride (TiN), or tungsten nitride (WN), and / or another metal with a work function greater than approximately 4.7 eV. A p-work function metal layer can be used to adjust the work function of the gate structure 116 to be close to the valence band of the channel layer material 118.

[0022] An n-workflow metal layer can contain one or more metal materials that match or adjust the work function of the gate structure 116 near the valence band of the channel layer material 118 of the semiconductor device 100. In some implementations, the n-workflow metal layer can contain titanium-aluminum (TiAl). In some implementations, the n-workflow metal layer contains titanium-aluminum-carbon (TiAlC). In some implementations, the n-workflow metal layer contains another aluminum-containing metal. In some implementations, another n-metal is included in an n-workflow metal layer.

[0023] Various spacers can be used in the integrated circuit devices 110. For example, sidewall spacers 120a can be arranged on sidewalls of the gate structure 116 to provide, among other things, electrical isolation for the gate structure 116. In some implementations, the sidewall spacers 120a are in contact with the dielectric gate layer 114. In other implementations, the sidewall spacers 120a are in contact with the exit-work metal layer. The sidewall spacers 120a can be made of silicon oxide (SiO₂). x ), a silicon nitride (Si x N y ), silicon dioxide carbide (SiOC), silicon dioxide carbonitride (SiOCN) and / or another suitable material.

[0024] As another example, internal spacers 120b can be arranged laterally between the gate structure 116 and the source / drain regions 112 of the integrated circuit device 110. The internal spacers 120b can be used to reduce the parasitic capacitance in the integrated circuit device 110 and to protect the source / drain regions 112 against etching in a nanosheet delamination operation for removing sacrificial layers between the channel layers 118. The internal spacers 120b can be made of silicon nitride (Si₂O₆). x N y ), a silicon oxide (SiO₂) x ), silicon oxide nitride (SiON), silicon oxide carbide (SiOC), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN) and / or another dielectric material.

[0025] The source / drain regions 112 are electrically and / or physically connected to source / drain contact structures 122. The source / drain contact structures 122 may include vias, contact pins, and / or other types of contact structures that electrically connect the source / drain regions 112 of the integrated circuit devices 110 to the interconnect layer 104 of the semiconductor device 100. The source / drain contact structures 122 contain cobalt (Co), ruthenium (Ru), tungsten (W), molybdenum (Mo), copper (Cu), and / or another electrically conductive or metallic material. One or more coating layers 124 may be arranged on the sidewalls of the source / drain contact structures 122.The coating layers 124 may comprise: a barrier layer designed to prevent or minimize the diffusion of materials from the source / drain contact structures 122 into surrounding dielectric layers; an adhesive or bonding layer designed to promote adhesion between the source / drain contact structures 122 and the surrounding dielectric layers; and / or another type of coating. Examples of materials for the coating layers 124 include titanium nitride (TiN), tantalum nitride (TaN), and / or other suitable coating materials.

[0026] The interconnect layer 104 of the semiconductor device 100 is arranged above the device layer 102 and the integrated circuit devices 110 in the z-direction within the semiconductor device 100. The interconnect layer 104 contains a plurality of dielectric layers arranged in a direction (e.g., the z-direction) that is approximately perpendicular to the substrate layer 106. The dielectric layers can include ILD layers 126 and ESLs 128, which are arranged alternately in the z-direction. The ILD layers 126 and the ESLs 128 can extend in the x-direction and / or the y-direction within the semiconductor device 100.

[0027] The ILD layers 126 can each contain an oxide [e.g. a silicon oxide (SiO₂)]. x) and / or another oxide material], undoped silicate glass (USG), borosilicate glass (BSG), fluorosilicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrogen silsesquioxane (HSQ), and / or another suitable dielectric material. In some implementations, the ILD layer 126 contains a dielectric material with an extremely low dielectric constant (dielectric ELK material) of less than about 2.5. Examples of dielectric ELK materials include carbon-doped silicon dioxide (C-SiO₂). x ), amorphous fluorocarbon (aC x F y ), parylene, bis-benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), SiOC polymer, porous hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyaryl ether (PAE) and / or porous silicon dioxide (SiO₂) x ).

[0028] The ESLs 128 can each contain a silicon nitride (Si x N y), silicon carbide (SiC), silicon nitride (SiON), and / or another suitable dielectric material. In some implementations, the ILD layer 126 and the ESL 128 contain different dielectric materials to provide etch selectivity, allowing different structures to be fabricated in the interconnect layer 104.

[0029] Metallization structures 130 and interconnect structures 132 can each contain one or more electrically conductive materials such as tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), or gold (Au), and / or a combination thereof, or other electrically conductive materials. In some implementations, one or more coating layers are arranged between the metallization structures 130 and / or the interconnect structures 132 and the surrounding dielectric layers in the interconnect layer 104. The one or more coating layers can include barrier layers, adhesive layers, and / or other types of coatings. Examples of materials for the one or more coatings include tantalum nitride (TaN) and / or titanium nitride (TiN).

[0030] In some implementations, the metallization structures 130 and the interconnect structures 132 of the interconnect layer 104 can be arranged vertically (e.g., in the z-direction). In other words, a plurality of stacked metallization structures 130 and interconnect structures 132 can extend between the device layer 102 and a top layer of the interconnect layer 104 to allow the routing of electrical signals and / or power between the device layer 102 and interconnect structures (not shown) of the semiconductor device 100. The plurality of stacked metallization structures 130 can be arranged in layers that can be referred to as M-layers, and the plurality of stacked interconnect structures 132 can be arranged in layers that can be referred to as V-layers.

[0031] A bottom layer of the interconnect structures in interconnect layer 104 contains a plurality of conductive structures. The conductive structures are electrically and / or physically connected to one or more of the integrated circuit devices 110 in device layer 102 and / or the interconnect layer 104. Signals and / or power can be supplied to and / or from the integrated circuit devices 110 via the conductive structures.

[0032] The conductive structures comprise a combination of metallization structures 130 and interconnect structures 132. The metallization structures 130 can include trenches, conductor tracks, and / or other types of conductive structures that extend mainly in the x-direction and / or the y-direction within the interconnect layer 104. The interconnect structures 132 can include vias, pins, conductive pillars, and / or other types of conductive structures that extend mainly in the z-direction within the semiconductor device. In some implementations, a conductive structure in the interconnect layer 104 comprises a dual damascene structure that contains a combination of a metallization structure 130 and an interconnect structure 132.

[0033] The interconnect structures 132 in the interconnect layer 104 are electrically connected to the gate structures 116 and the source / drain contact structures 122 of the integrated circuit devices 110. The lowest layer of interconnect structures 132 contains source / drain interconnect structures 134, which are electrically and / or physically connected to the source / drain contact structures 122, and gate interconnect structures 136, which are electrically and / or physically connected to the gate structures 116. In some implementations, gate contacts (not shown) are arranged between the gate structures 116 and the gate interconnect structures 136.In some implementations, the lowest layer of interconnect structures 132 is referred to as a via-o layer (Vo layer), the source / drain interconnect structures 134 are referred to as source / drain vias (VDs), and the gate interconnect structures 136 are referred to as gate vias (VGs).

[0034] A metal layer (Mo layer) can be arranged above the source / drain interconnect structures 134 and the gate interconnect structures 136. The metallization structures 130 in the Mo layer can be connected to the source / drain interconnect structures 134 and the gate interconnect structures 136. A via-1 layer (V1 layer) containing one or more interconnect structures 132 can be arranged above the Mo layer. A metal layer (M1 layer) can be arranged above the V1 layer in the interconnect layer 104, a via-2 layer (V2 layer) can be arranged above the M1 layer, a metal layer (M2 layer) can be arranged above the V2 layer, and so on.

[0035] Fig. Figure 1B shows a detailed view of a connection between a source / drain contact structure 122 and a source / drain interconnect structure 134 of the semiconductor device 100. As shown in Fig. As shown in Figure 1B, the source / drain contact structure 122 can be contained within the dielectric layer 108. An ESL 128 of the interconnect layer 104 can be arranged above the source / drain contact structure 122. An ILD layer 126 (e.g., an ILD1 layer) of the interconnect layer 104 can be arranged above the ESL 128.

[0036] As also in Fig. As shown in Figure 1B, the source / drain interconnect structure 134 is located above and / or on top of the source / drain contact structure 122, such that the source / drain contact structure 122 and the source / drain interconnect structure 134 are arranged vertically (e.g., in the z-direction) in the semiconductor device 100. The top surface of the source / drain contact structure 122 is located below the ESL 128 and has a recess 138 that is filled by the bottom surface of the source / drain interconnect structure 134. Thus, the top surface of the source / drain contact structure 122 is recessed below the ESL 128, and the bottom surface of the source / drain interconnect structure 134 is recessed in the top surface of the source / drain contact structure 122.

[0037] The recess 138 in the top surface of the source / drain contact structure 122 is the result of a pre-cleaning process performed on the top surface of the source / drain contact structure 122 to remove a metal oxide layer (e.g., system-inherent oxides) from the top surface of the source / drain contact structure 122 before the source / drain interconnect structure 134 is fabricated on the top surface of the source / drain contact structure 122. An exemplary pre-cleaning process is described with reference to the Fig. 3A to 3H described.

[0038] The recess 138 provides an increased surface contact area between the top surface of the source / drain contact structure 122 and the bottom surface of the source / drain interconnect structure 134. The source / drain contact structure 122 and the source / drain interconnect structure 134 can contain different types of metals. For example, the source / drain contact structure 122 may contain tungsten (W), and the source / drain interconnect structure 134 may contain copper (Cu). The heterometallic interface between the source / drain contact structure 122 and the source / drain interconnect structure 134 can result in a higher contact resistance between the two structures. Thus, the recess 138 can reduce some of this higher contact resistance and / or enable a lower overall contact resistance to be achieved.

[0039] As also in Fig. As shown in Figure 1B, due to the recess 138, the underside of the source / drain interconnect structure 134 is located beneath the underside of the ESL 128. The underside of the source / drain interconnect structure can have a rounded cross-sectional profile that corresponds to the cross-sectional profile of the top side of the source / drain contact structure 122.

[0040] As also in Fig. As shown in Figure 1B, the source / drain contact structure 122 and / or the source / drain interconnect structure 134 can have one or more exemplary dimensions. One exemplary dimension D1 corresponds to an upper lateral width (e.g., a top width) of the source / drain interconnect structure 134, and another exemplary dimension D2 corresponds to a lower lateral width (e.g., a bottom width) of the source / drain interconnect structure 134. Dimension D1 and dimension D2 can each be approximately 3 nm to approximately 50 nm. However, other values ​​and ranges are also within the scope of protection of this disclosure. In some implementations, dimension D1 is larger than dimension D2, so that the sidewalls of the source / drain interconnect structure are angled outward from a center point of the source / drain interconnect structure, and the lateral width of the source / drain interconnect structure decreases from dimension D1 to dimension D2.

[0041] In some implementations, dimension D2 also corresponds to an upper lateral width of the top surface of the source / drain contact structure 122. In some implementations, the upper lateral width of the top surface of the source / drain contact structure 122 is larger than dimension D2, so that the top surface of the source / drain contact structure 122 extends laterally outward from the bottom surface of the source / drain interconnect structure 134, as shown in various examples in the Fig. 5A to 5E is shown.

[0042] Another exemplary dimension D3 corresponds to a z-direction height (or vertical thickness) of the source / drain interconnect structure 134. In some implementations, the dimension D3 is approximately 15 nm to approximately 45 nm. However, other values ​​and ranges are also within the scope of protection of this disclosure.

[0043] Another exemplary dimension D4 corresponds to a z-direction height (or vertical thickness) of the source / drain contact structure 122. In some implementations, the dimension D4 is approximately 15 nm to approximately 45 nm. However, other values ​​and ranges are also within the scope of protection of this disclosure.

[0044] In some implementations, the ratio of dimension D3 to dimension D4 is approximately 1:4 to approximately 45:1. However, other values ​​and ranges are also within the scope of protection of this disclosure.

[0045] Another exemplary dimension D5 is the z-direction depth of the recess 138. The z-direction depth of the recess 138 corresponds to a vertical distance (e.g., in the z-direction) between the bottom part of the recess 138 and the underside of the ESL 128. In some implementations, dimension D5 is approximately 0.5 nm to approximately 5 nm. If dimension D5 is outside this range, the metal oxide layer that forms on the top surface of the source / drain contact structure 122 may not be completely removed, resulting in a higher contact resistance between the source / drain contact structure 122 and the source / drain interconnect structure 134. However, other values ​​and ranges are also within the scope of protection of this disclosure.

[0046] Another exemplary dimension D6 is a vertical distance (e.g., in the z-direction) between the lower part of the recess 138 and the upper surface of the ESL 128. In some implementations, dimension D6 is approximately 3 nm to approximately 12 nm. However, other values ​​and ranges are also within the scope of protection of this disclosure.

[0047] As explained above, the Fig. 1A and Fig. 1B as an example. Other examples may differ from what is given with reference to the Fig. 1A and Fig. 1B has been explained.

[0048] The Fig. Figures 2A to 2F are representations of an exemplary implementation 200 for fabricating the semiconductor device 100 described here. In some implementations, one or more of the semiconductor processing operations described with reference to the Fig. 2A to 2E are described, are carried out using one or more semiconductor processing systems, such as a deposition system, an exposure system, a developing system, an etching system, a planarization system, an ion implantation system, a wafer / die transport system and / or another type of semiconductor processing system.

[0049] Let's move on to... Fig. 2A, in which the substrate layer 106 is provided. The substrate layer 106 can be provided in the form of a semiconductor wafer, such as a silicon wafer (Si wafer), a silicon-on-insulator wafer (SOI wafer), and / or another type of semiconductor workpiece. The semiconductor device 100 can be fabricated on the semiconductor wafer along with other semiconductor devices.

[0050] A layer stack can be fabricated on substrate layer 106. The layer stack can be described as a superlattice. The layer stack can contain a plurality of alternating layers arranged in a direction (e.g., the z-direction) that is approximately perpendicular to substrate layer 106. For example, the layer stack can have vertically alternating layers of sacrificial layers 202 and nanostructure channel layers 204 above substrate layer 106. The number of sacrificial layers 202 and the number of nanostructure channel layers 204 that are in Fig. Figure 2A shows only examples, and other numbers of sacrificial layers 202 and nanostructure channel layers 204 are also within the scope of protection of the present disclosure.

[0051] The sacrificial layers 202 enable the definition of a vertical distance between adjacent nanostructure channels, which are made from the nanostructure channel layers 204, and they serve as placeholder layers for subsequently manufactured gate structures of the integrated circuit devices 110 of the semiconductor device 100, which are made around the nanostructure channels.

[0052] The sacrificial layers 202 have a first material composition, and the nanostructure channel layers 204 have a second material composition. In some implementations, the first and second material compositions are the same. In other implementations, the first and second material compositions are different. For example, the sacrificial layers 202 may contain silicon germanium (SiGe), and the nanostructure channel layers 204 may contain silicon (Si). This allows, depending on the type of etchant used, selective etching of the sacrificial layers 202 and / or the nanostructure channel layers 204 (e.g., the sacrificial layers 202 can be etched, but not the nanostructure channel layers 204, or the nanostructure channel layers 204 can be etched, but not the sacrificial layers 202).

[0053] One or more types of deposition equipment can be used to deposit and / or grow the alternating layers of the layer stack, which is to contain nanostructures (e.g., nanosheets), onto the substrate layer 106. For example, a deposition equipment can be used to grow the sacrificial layers 202 and / or the nanostructure channel layers 204 by epitaxial growth, which can be achieved using epitaxial techniques such as molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or another suitable epitaxial technique. Additionally and / or alternatively, the sacrificial layers 202 and / or the nanostructure channel layers 204 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or another suitable deposition technique.

[0054] The layer stack and the substrate layer 106 can be seen in the y-direction, which is shown in the representation of Fig. 2A, which is not visible, can be etched to create fin structures extending in the x-direction. A fin structure can include a portion of the layer stack and a portion of the substrate layer 106 beneath the layer stack. The fin structures can be created by structuring one or more masking layers and etching based on a structure generated in one or more of the masking layers. The one or more masking layers can be structured using photolithography techniques, including double or multiple structuring methods. An etching system can be used to etch the layer stack and the substrate layer 106 based on the generated structure using a dry etching technique (e.g., reactive ion etching), a wet etching technique, and / or a combination thereof.In some implementations, STI areas (STI: shallow trench isolation; not shown) can be created between adjacent fin structures in the y-direction.

[0055] As in Fig. As shown in Figure 2B, dummy gate structures 206 (which can also be called dummy gate stacks or temporary gate structures) can be fabricated over portions of the layer stack of sacrificial layers 202 and nanostructure channel layers 204. The dummy gate structures 206 can extend in the y-direction and can be arranged in the x-direction so that they are approximately perpendicular to the fin structures. The dummy gate structures 206 are sacrificial structures that must be replaced by substitute gate structures or substitute gate stacks at a later processing stage for the integrated circuit devices 110 of the semiconductor device 100. The dummy gate structures 206 can also be used to define source / drain recesses (S / D recesses) in which source / drain regions of the nanostructure transistors are created in the layer stack of sacrificial layers 202 and nanostructure channel layers 204.

[0056] The dummy gate structures 206 can contain polycrystalline silicon (polysilicon or PO) or another material. The layers of the dummy gate structures 206 can be fabricated using various semiconductor processing techniques, such as deposition of the layers of the dummy gate structures 206, structuring of the layers of the dummy gate structures 206 to define the dummy gate structures 206, and / or other semiconductor processing techniques. The sidewall spacers 120a can be fabricated on the sidewalls of the dummy gate structures 206.

[0057] As in Fig. As shown in Figure 2C, the source / drain regions 112 of the integrated circuit devices 110 are created in the layer stack of sacrificial layers 202 and nanostructure channel layers 204. To create the source / drain regions 112, source / drain recesses can be produced through the layer stack of sacrificial layers 202 and nanostructure channel layers 204 in an etching operation. The source / drain recesses can be created on opposite sides of the dummy gate structure 206 in the x-direction. The etching operation can be performed using the etching system and can be referred to as an SSD etching operation (SSD: strained source / drain). In some implementations, the etching operation involves the use of a plasma etching process, a wet chemical etching process, and / or another type of etching process.

[0058] The channel layers 118 can be defined by creating the source / drain recesses. The channel layers 118 can contain silicon-based nanostructures (e.g., nanosheets or nanowires, among others) that function as the semiconducting channels of the integrated circuit devices 110 of the semiconductor device 100. The channel layers 118 are arranged in a direction (e.g., the z-direction) that is approximately perpendicular to the substrate layer 106. In other words, the channel layers 118 are arranged vertically or stacked above the substrate layer 106.

[0059] Prior to the creation of the source / drain regions 112 in the source / drain recesses, the ends of the sacrificial layers 202, which are exposed in the source / drain recesses, can be laterally etched away, creating cavities in the ends of the sacrificial layers 202. The internal spacers 120b can be produced in these cavities. A deposition system can be used to produce the internal spacers 120b by depositing a layer of dielectric material in the cavities and along the sidewalls and bottom surfaces of the source / drain recesses. A CVD, PVD, or ALD process and / or another deposition method can be used to deposit the layer of dielectric material.To subsequently remove excess material of the dielectric material layer from the source / drain recesses, an etching system is used so that remaining parts correspond to the internal spacers 120b in the cavities.

[0060] After fabricating the internal spacers 120b, the source / drain recesses can be filled with one or more layers of epitaxial material to create the source / drain regions 112 within the source / drain recesses. For example, one deposition unit can be used to deposit a buffer region on the bottom of the source / drain recess, and another deposition unit can deposit a source / drain region 112 on top of the buffer region within the source / drain recess. In some implementations, one deposition unit is used to deposit a capping layer on top of the source / drain region 112 within the source / drain recess.As another example, a deposition system can epitaxially grow a first layer of a source / drain region 112 (designated L1) over an associated buffer region (which can be designated L0), and it can epitaxially grow a second layer of the source / drain region 112 (designated L2, L2-1, and / or L2-2) over the first layer. The first layer can contain lightly doped silicon, doped, for example, with boron (B), phosphorus (P), and / or another dopant, and it can be used as a shielding layer to reduce short-channel effects in the semiconductor device 100 and to reduce dopant extrusion or migration into the channel layers 118. The second layer can contain heavily doped silicon or heavily doped silicon germanium. The second layer can be used to provide compressive stress in the source / drain regions 112 to reduce boron loss.

[0061] As also in Fig. As shown in Figure 2C, the dielectric layer 108 can be fabricated over the source / drain regions 112 and around the dummy gate structures 206. The dielectric layer 108 can fill regions between the dummy gate structures 206. In some implementations, a contact etch stop layer (CESL) (e.g., using a deposition system) is conformally deposited over the source / drain regions 112 before the dielectric layer 108 is fabricated. The dielectric layer 108 is then fabricated on the CESL. The CESL can provide a mechanism for terminating an etching process when fabricating source / drain contacts 122 for the source / drain regions 112. The CESL can be fabricated from a dielectric material that has a different etch selectivity than adjacent layers or components. The CESL can contain or be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material.Furthermore, CESL can, among other things, silicon nitride (Si. x N y ), silicon carbon nitride (SiCN), carbon nitride (CN), silicon oxide nitride (SiON), silicon carbon oxide (SiCO), or a combination thereof. The CESL can be deposited using a deposition process such as ALD, CVD, or another deposition method.

[0062] As in Fig. As shown in Figure 2D, a replacement gate process can be performed to replace the dummy gate structures 206 with the gate structures 116 of the integrated circuit devices 110. A dummy gate removal operation can be performed to remove the dummy gate structures 206 from the semiconductor device 100. Removing the dummy gate structures 206 creates openings (or recesses) in the dielectric layer 108 and provides access to the underlying sacrificial layers 202. The dummy gate structures 206 can be removed by one or more etching operations. These etching operations can be performed using a plasma etching process, a wet chemical etching process, and / or another type of etching process.

[0063] The replacement gate process can include a nanostructure detachment operation (e.g., a SiGe detachment operation). The nanostructure detachment operation is performed to remove the sacrificial layers 202 (e.g., the silicon germanium layers). This creates openings between the channel layers 118 (e.g., the areas surrounding the channel layers 118). The sacrificial layers 202 can be removed through the spaces previously occupied by the dummy gate structures 206. An etching system can be used for the nanostructure detachment operation to remove the sacrificial layers 202 based on the difference in etch selectivity between the material of the sacrificial layers 202 and the material of the channel layers 118, as well as between the material of the sacrificial layers 202 and the material of the internal spacers 120b.The internal spacers 120b can function as etch stop layers in the etching operation to protect the source / drain areas 112 against etching.

[0064] The substitute gate operation involves fabricating dielectric gate layers 114 and gate structures (e.g., substitute gate structures) 116 of the integrated circuit devices 110 in the openings between the source / drain regions 112 and between the internal spacers 120b. Specifically, the dielectric gate layers 114 and the gate structures 116 fill the areas between and around the channel layers 118 that were previously occupied by the sacrificial layers 202, so that the gate structures 116 completely enclose the channel layers 118. This enhances, among other things, the control of the channel layers 118, increases the drive current for the integrated circuit devices 110, and / or reduces short-channel effects (SCEs) for the integrated circuit devices 110. The gate structures 116 can also fill the spaces previously occupied by the dummy gate structures 206.Between pairs of channel layers 118 in a vertical alternating arrangement, parts of a gate structure 116 are formed. In other words, the semiconductor device 100 has one or more vertical stacks of alternating channel layers 118 and parts of a gate structure 116.

[0065] As also in Fig. As shown in 2D, the source / drain contact structures 122 of the integrated circuit devices 110 can be fabricated through the dielectric layer 108. The source / drain contact structures 122 can be fabricated in recesses in the dielectric layer 108. In some implementations, a structure in a photoresist layer is used to etch the dielectric layer 108 to create the recesses. In these implementations, a deposition unit can be used to fabricate the photoresist layer on the dielectric layer 108. An exposure unit can be used to expose the photoresist layer with a radiation source to pattern the photoresist layer. A developing unit can be used to develop and remove portions of the photoresist layer to expose the structure.An etching unit can be used to etch the dielectric layer based on the structure to create the recesses. In some implementations, the etching operation includes a dry etching operation (e.g., a plasma-based or gas-based etching operation), a wet chemical etching operation, and / or another type of etching operation. In some implementations, a photoresist removal unit can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical remover, plasma removal, and / or another method). In some implementations, a hard mask layer is used as an alternative method for etching the dielectric layer 108 based on a structure to create the recesses.

[0066] The source / drain contact structures 122 can be fabricated in the recesses so that they rest on the source / drain regions 112. A deposition system can be used to deposit the material of the source / drain contact structures 122 in the recesses using a CVD process, a PVD process, an ALD process, an electroplating process, and / or another suitable deposition method. The material of the source / drain contact structures 122 can be deposited in one or more deposition operations. In some implementations, a seed layer is deposited first, and then the material of the source / drain contact structures 122 is deposited on the seed layer. In some implementations, one or more coating layers 124 are deposited in the recesses, and the source / drain contact structures 122 are then deposited on the coating layers 124.In some implementations, a planarization unit is used to perform a planarization operation (e.g., a CMP operation) to planarize the source / drain contact structures 122 after their deposition, so that the top surfaces of the source / drain contact structures 122 are approximately coplanar with the top surface of the dielectric layer 108.

[0067] As in Fig. As shown in Figure 2E, the interconnect layer 104 of the semiconductor device 100 is fabricated over the dielectric layer 108. One or more deposition units are used to deposit alternating layers of ILD layers 126 and ESLs 128 in the interconnect layer 104 of the semiconductor device 100. In this way, the ILD layers 126 and the ESLs 128 can be arranged in the z-direction of the semiconductor device 100. One or more deposition units can be used to deposit each of the ILD layers 126 and each of the ESLs 128 using a PVD process, an ALD process, a CVD process, an oxidation process, and / or another suitable deposition method. In some implementations, a planarization unit can be used to planarize the ILD layers 126 and / or the ESLs 128 after their deposition.

[0068] As also in Fig. As shown in Figure 2E, a deposition unit, an exposure unit, a developing unit, an etching unit, a planarizing unit, a plating unit, and / or another semiconductor processing unit can be used to perform various operations to fabricate the source / drain interconnect structures 134 and / or the gate interconnect structures 136 on the underside of the interconnect layer 104. One or more source / drain interconnect structures 134 can be fabricated on one or more source / drain contact structures 122 of one or more integrated circuit devices 110. One or more gate interconnect structures 136 can be fabricated on one or more gate structures 116 of one or more integrated circuit devices 110.

[0069] A deposition unit, an exposure unit, a developing unit, an etching unit, a planarizing unit, a plating unit, and / or other semiconductor processing equipment can be used to perform various operations to fabricate the metallization structures 130 and the interconnect structures 132 in the interconnect layer 104 of the semiconductor device 100. In some implementations, the interconnect layer 104 can be fabricated in a plurality of layers. For example, an ILD layer 126 and an ESL 128 can be fabricated (e.g., using one or more deposition units and / or one or more planarizing units); recesses can be created in and / or by the ILD layer 126 and the ESL 128 (e.g., using an exposure unit, a developing unit, and / or an etching unit); and a layer of metallization structures 130 (e.g.,The Mo layer can be produced in the ILD layer 126 and the ESL 128 (e.g., using one or more deposition units and / or one or more planarization units). Another ILD layer 126 and another ESL 128 can be produced, and a layer of interconnect structures 132 (e.g., a V1 layer) can be produced in the ILD layer 126 and the ESL 128. Further layers of metallization structures 130 and further layers of interconnect structures 132 can be produced in a similar manner.

[0070] One or more deposition units can be used to deposit the source / drain interconnect structures 134, the gate interconnect structures 136, the metallization structures 130, and / or the interconnect structures 132 using a PVD process, an ALD process, a CVD process, an electroplating process (e.g., an electrochemical plating process), and / or another suitable deposition method. In some implementations, a planarization unit can be used to planarize the source / drain interconnect structures 134, the gate interconnect structures 136, the metallization structures 130, and / or the interconnect structures 132 after their deposition.

[0071] As explained above, the Fig. 2A to 2E are merely examples. Other examples may differ from what is given with reference to the Fig. 2A to 2E has been explained.

[0072] The Fig. Figures 3A to 3H are representations of an exemplary implementation 300 for fabricating a source / drain interconnect structure described here 134. In some implementations, one or more semiconductor processing operations, which refer to the Fig. 3A to 3H are described and performed using one or more semiconductor processing units, such as a deposition unit, an exposure unit, a developing unit, an etching unit, a planarization unit, an ion implantation unit, a wafer / die transport unit, and / or another type of semiconductor processing unit. In some implementations, one or more semiconductor processing operations, described with reference to the Fig. 3A to 3H are described as being carried out as part of the process for manufacturing the semiconductor device 100, which is described in the Fig. 2A to 2E is shown and has been described with reference to them.

[0073] As in Fig. As shown in Figure 3A, a source / drain contact structure 122 of the semiconductor device 100 can be fabricated in the dielectric layer 108. The ESL 128 can be fabricated above and / or on the dielectric layer 108 and above and / or on the source / drain contact structure 122, such that the ESL 128 covers the top surface of the source / drain contact structure 122.

[0074] As in Fig. As shown in Figure 3B, a recess 302 is created by the ILD layer 126 and the ESL 128. The recess 302 extends to the source / drain contact structure 122, so that the top surface of the source / drain contact structure 122 is exposed in the recess 302.

[0075] In some implementations, a structure in a photoresist layer is used to etch the ILD layer 126 and / or the ESL 128 to create the recess 302. In these implementations, a deposition unit can be used to fabricate the photoresist layer on the ILD layer 126 (e.g., using a spin coating process and / or another suitable deposition process). An exposure unit can be used to expose the photoresist layer with a radiation source to structure the photoresist layer. A developing unit can be used to develop and remove portions of the photoresist layer to expose the structure. An etching unit can be used to etch the ILD layer 126 and / or the ESL 128 based on the structure using an etchant 304 to create the recess 302. In some implementations, the etching operation includes a dry etching operation (e.g.,an etching operation using a plasma-based etchant 304 or an etching operation using a gas-based etchant 304), a wet chemical etching operation (e.g., an etching operation using a wet chemical etchant 304), and / or another type of etching operation. In some implementations, a photoresist removal unit may be used to remove the remaining portions of the photoresist layer (e.g., using a chemical remover, plasma removal, and / or another method). In some implementations, a hard mask layer is used as an alternative method for generating the recess 302 based on a structure.

[0076] As in Fig. As shown in Figure 3C, a metal oxide layer 306 can be formed on the top surface of the source / drain contact structure 122 in the recess 302. The metal oxide layer 306 can be described as a "natural oxide" insofar as it forms naturally through oxidation of the top surface of the source / drain contact structure 122. Exposure to oxygen from various sources, such as oxygen in the air in the processing chamber of the etching system, oxygen in the air in a semiconductor manufacturing system where the semiconductor device 100 is manufactured, and / or oxygen from another oxygen source, can oxidize the top surface of the source / drain contact structure 122. In some implementations, the top surface of the source / drain contact structure 122 can oxidize through exposure to oxygen while waiting for the next processing step for the semiconductor device 100.

[0077] The metal oxide layer 306 can correspond to a portion of the top surface of the source / drain contact structure 122 with which atmospheric oxygen has bonded. Thus, the metal oxide layer 306 contains a metal from the source / drain contact structure 122 and extends beneath the ESL 128. For example, if the source / drain contact structure 122 contains tungsten (W), then the metal oxide layer 306 can be oxidized tungsten or tungsten oxide (WO₄). x , such as WO3). As another example, if the source / drain contact structure contains molybdenum (Mo) 122, the metal oxide layer 306 can be oxidized molybdenum or a molybdenum oxide (MoO₂). x , such as MoO3).

[0078] As in the Fig. 3D and Fig. As shown in Figure 3E, a pre-cleaning operation can be performed to remove the metal oxide layer 306 from the top surface of the source / drain contact structure 122. The metal oxide layer 306 can be removed from the top surface of the source / drain contact structure 122 to provide a bare-metal substrate on which a source / drain interconnect structure 134 is to be fabricated on the source / drain contact structure 122 in the recess 302.

[0079] In some implementations, the pre-cleaning operation is performed in a processing chamber of a deposition system, such as a CVD or PVD system. This allows the pre-cleaning operation to be carried out in the processing chamber that will be used to deposit the material of the source / drain interconnect structure 134. In other words, the pre-cleaning operation and the deposition of the material of the source / drain interconnect structure 134 can be performed in the same processing chamber of the deposition system. This allows the pre-cleaning operation and the deposition of the material of the source / drain interconnect structure 134 to take place in the same vacuum (e.g.,(while maintaining the vacuum in the processing chamber), thereby reducing the likelihood that the metal oxide layer 306 will re-grow on the top of the source / drain contact structure 122 in the recess 302 before the source / drain interconnect structure 134 is produced.

[0080] As in Fig. As shown in the 3D figure, the pre-cleaning operation involves the use of a pre-cleaning agent 308. The pre-cleaning agent 308 can be a wet-chemical pre-cleaning agent, a dry-gas pre-cleaning agent, and / or another type of pre-cleaning agent. The pre-cleaning agent 308 is introduced into the recess 302 (e.g., using the separation unit or a dedicated pre-cleaning unit) so that the metal oxide layer 306 is impregnated with the pre-cleaning agent 308 for a period of time.

[0081] The pre-cleaning agent 308 contains a metal precursor that etches or removes material from the metal oxide layer 306. The pre-cleaning agent 308 may, for example, contain a halogen-based metal precursor, such as a transition metal halide. Examples of transition metal halides for the pre-cleaning agent 308 may include, but are not limited to, tungsten fluoride (e.g., WF6), tungsten chloride (e.g., WCl6, WCl3), molybdenum chloride (e.g., MoCl6, MoCl5), tantalum chloride (e.g., TaCl5), and / or titanium chloride (e.g., TiCl4). In some implementations, the pre-cleaning agent 308 contains a metal precursor of the material of the source / drain contact structure 122. In some implementations, the pre-cleaning agent 308 contains a metal precursor of the material of the source / drain interconnect structure 134.In these implementations, the pre-cleaning operation can be performed as part of the deposition of the source / drain interconnect structure 134, which reduces the process complexity of the fabrication of the semiconductor device 100.

[0082] The metal precursor of the pre-cleaning agent 308 selectively etches the metal oxide layer 306, leaving minimal or no etching of the ILD layer 126 and / or the ESL 128. In this way, the pre-cleaning agent 308 removes the metal oxide layer 306, with minimal or no widening of the recess 302. Therefore, the use of the metal precursor for the pre-cleaning agent 308 allows the recess 302 to retain its aspect ratio (e.g., height-to-width ratio).

[0083] In some implementations, the metal precursor of the pre-cleaning agent 308 is a tungsten precursor. The tungsten precursor can, for example, be a tungsten fluoride (WF₆). x) (e.g., a tungsten fluoride gas), such as tungsten hexafluoride (WF6). In these implementations, the pre-cleaning operation can be carried out at a temperature in the processing chamber of approximately 200 °C to approximately 450 °C to promote a reaction between the tungsten fluoride of the pre-cleaning agent 308 and the metal oxide layer 306. However, other values ​​and ranges are also within the scope of protection of this disclosure. Additionally and / or alternatively, the pre-cleaning operation can be carried out at a pressure in the processing chamber of approximately 0.1 Torr to approximately 50 Torr to promote the reaction between the tungsten fluoride of the pre-cleaning agent 308 and the metal oxide layer 306. However, other values ​​and ranges are also within the scope of protection of this disclosure.

[0084] As another example, the tungsten precursor can be a tungsten chloride (WCl). x) (e.g., a tungsten chloride gas or a tungsten chloride liquid), such as tungsten hexachloride (WCl6). In these implementations, the pre-cleaning operation can be carried out at a temperature in the processing chamber of approximately 200 °C to approximately 450 °C to promote a reaction between the tungsten chloride of the pre-cleaning agent 308 and the metal oxide layer 306. However, other values ​​and ranges are also within the scope of protection of this disclosure. Additionally and / or alternatively, the pre-cleaning operation can be carried out at a pressure in the processing chamber of approximately 0.1 Torr to approximately 50 Torr to promote the reaction between the tungsten chloride of the pre-cleaning agent 308 and the metal oxide layer 306. However, other values ​​and ranges are also within the scope of protection of this disclosure.

[0085] In some implementations, the metal precursor of the pre-cleaning agent 308 is a molybdenum precursor. The molybdenum precursor can, for example, be a molybdenum fluoride (MoF₂). x) (e.g., a molybdenum fluoride gas), such as molybdenum hexafluoride (MoF6). In these implementations, the pre-cleaning operation can be carried out at a temperature in the processing chamber of approximately 200 °C to approximately 450 °C to promote a reaction between the molybdenum fluoride of the pre-cleaning agent 308 and the metal oxide layer 306. However, other values ​​and ranges are also within the scope of protection of this disclosure. Additionally and / or alternatively, the pre-cleaning operation can be carried out at a pressure in the processing chamber of approximately 0.1 Torr to approximately 260 Torr to promote the reaction between the molybdenum fluoride of the pre-cleaning agent 308 and the metal oxide layer 306. However, other values ​​and ranges are also within the scope of protection of this disclosure.

[0086] As another example, the molybdenum precursor can be molybdenum chloride (MoCl₂). x) (e.g., a molybdenum chloride gas or a molybdenum chloride liquid), such as molybdenum pentachloride (MoCl5). In these implementations, the pre-cleaning operation can be carried out at a temperature in the processing chamber of approximately 200 °C to approximately 450 °C to promote a reaction between the molybdenum chloride of the pre-cleaning agent 308 and the metal oxide layer 306. However, other values ​​and ranges are also within the scope of protection of this disclosure. Additionally and / or alternatively, the pre-cleaning operation can be carried out at a pressure in the processing chamber of approximately 0.1 Torr to approximately 260 Torr to promote the reaction between the molybdenum chloride of the pre-cleaning agent 308 and the metal oxide layer 306. However, other values ​​and ranges are also within the scope of protection of this disclosure.

[0087] As in Fig. As shown in Figure 3E, the pre-cleaning operation results in the top surface of the source / drain contact structure 122 being spared. The pre-cleaning agent 308 removes metal and oxygen components from the metal oxide layer 306, the metal component corresponding to the metal of the source / drain contact structure 122. Therefore, removing the metal oxide layer 306 using the pre-cleaning agent 308 results in the removal of metal from the top surface of the source / drain contact structure 122.

[0088] Fig. Figure 3F shows an alternative implementation in which a residual layer 310 remains on the top surface of the source / drain contact structure 122 after the pre-cleaning operation. The residual layer 310 can be a metallic element from the pre-cleaning agent 308. For example, if molybdenum chloride (MoCl₂) xIf ) is used as the pre-cleaning agent, the residual layer 310 can comprise a layer of molybdenum on the top surface of the source / drain contact structure 122. Thus, if the source / drain contact structure 122 is made of tungsten (W), the top surface of the source / drain contact structure 122 can have a thin layer of molybdenum.

[0089] As in Fig. As shown in Figure 3G, the material of a source / drain interconnect structure 134 is produced on the top side of the source / drain contact structure 122 in the recess 302. The material of the source / drain interconnect structure 134 fills the recess 302. A deposition system (e.g., the same deposition system using the same processing chamber that was used to perform the pre-cleaning operation) can be used to deposit the material of the source / drain interconnect structure 134 using a CVD process, an ALD process, a PVD process, an electroplating process, and / or another suitable deposition process.

[0090] A metal precursor can be used to deposit the material of the source / drain interconnect structure 134. The metal precursor can be the same metal precursor that was used as the pre-cleaning agent 308 for the pre-cleaning operation, or it can be a different metal precursor. The metal precursor used to deposit the material of the source / drain interconnect structure 134 can be selectively deposited on metals, such as on the top surface of the source / drain contact structure 122. This allows the material of the source / drain interconnect structure 134 to be deposited by bottom-up growth, with the material of the source / drain interconnect structure 134 forming on the top surface of the source / drain contact structure 122 and not on the side walls of the recess 302, which correspond to the ILD layer 126 and the ESL 128.The bottom-up growth of the material for the source / drain interconnect structure 134 reduces the probability of the formation of voids in the source / drain interconnect structure.

[0091] In some implementations, the source / drain interconnect structure 134 is fabricated from tungsten (W) and a tungsten precursor used to deposit the material of the source / drain interconnect structure 134. The tungsten precursor can, for example, be a tungsten fluoride (WF). x ) (e.g., a tungsten fluoride gas), such as tungsten hexafluoride (WF6). Another example of a tungsten precursor is tungsten chloride (WCl). xThe material used for the source / drain interconnect structure 134 (e.g., a tungsten chloride gas or liquid), such as tungsten hexachloride (WCl6), can be deposited. Deposition of the material using the tungsten precursor can be carried out at a processing chamber temperature of approximately 200 °C to approximately 450 °C. However, other values ​​and ranges are also within the scope of this disclosure. Additionally and / or alternatively, deposition of the material using the tungsten precursor can be carried out at a processing chamber pressure of approximately 0.1 Torr to approximately 50 Torr. However, other values ​​and ranges are also within the scope of this disclosure. In some implementations, the tungsten precursor can be used with or without a treatment gas, such as hydrogen gas (H2 gas) and / or ammonia gas (NH3 gas).

[0092] In some implementations, the source / drain interconnect structure 134 is fabricated from molybdenum (Mo) and a molybdenum precursor, which is used to deposit the material of the source / drain interconnect structure 134. The molybdenum precursor can, for example, be a molybdenum fluoride (MoF₂). x) (e.g., a molybdenum fluoride gas), such as molybdenum hexafluoride (MoF6). The deposition of the material of the source / drain interconnect structure 134 using molybdenum fluoride as a precursor can be carried out at a temperature in the processing chamber of the deposition system of approximately 200 °C to approximately 450 °C. However, other values ​​and ranges are also within the scope of protection of this disclosure. In some implementations, the deposition of the material of the source / drain interconnect structure 134 using molybdenum fluoride as a precursor can be carried out at a pressure in the processing chamber of approximately 0.1 Torr to approximately 260 Torr. However, other values ​​and ranges are also within the scope of protection of this disclosure. In some implementations, the molybdenum fluoride can be used with or without a treatment gas, such as hydrogen gas (H2 gas).

[0093] As another example, the molybdenum precursor can be molybdenum chloride (MoCl₂). x) (e.g., a molybdenum chloride gas or a molybdenum chloride liquid), such as molybdenum pentachloride (MoCl3). The deposition of the material of the source / drain interconnect structure 134 using molybdenum chloride as a precursor can be carried out at a temperature in the processing chamber of the deposition system of approximately 300 °C to approximately 450 °C. However, other values ​​and ranges are also within the scope of protection of this disclosure. In some implementations, the deposition of the material of the source / drain interconnect structure 134 using molybdenum chloride as a precursor can be carried out at a pressure in the processing chamber of approximately 0.1 Torr to approximately 300 Torr. However, other values ​​and ranges are also within the scope of protection of this disclosure. In some implementations, the molybdenum chloride can be used with or without a treatment gas, such as hydrogen gas (H2 gas).

[0094] In some implementations, the source / drain interconnect structure 134 is fabricated from ruthenium (Ru) and a ruthenium precursor, which is used to deposit the material of the source / drain interconnect structure 134. The ruthenium precursor can, for example, be a ruthenium oxide (RuO₄). x, such as RuO2). The deposition of the material of the source / drain interconnect structure 134 using ruthenium oxide as a precursor can be carried out at a temperature in the processing chamber of the deposition system of approximately 200 °C to approximately 450 °C. However, other values ​​and ranges are also within the scope of protection of this disclosure. In some implementations, the deposition of the material of the source / drain interconnect structure 134 using ruthenium oxide as a precursor can be carried out at a pressure in the processing chamber of approximately 0.1 Torr to approximately 260 Torr. However, other values ​​and ranges are also within the scope of protection of this disclosure. In some implementations, the ruthenium precursor can be used with or without a treatment gas, such as hydrogen gas (H2 gas).

[0095] In some implementations, the source / drain interconnect structure 134 is fabricated from cobalt (Co) and a cobalt precursor, which is used to deposit the material of the source / drain interconnect structure 134. The cobalt precursor can, for example, be cobalt chloride (CoCl₂). x , such as CoCl2), a combination of a cobalt sulfate (CoS x ) and a cobalt oxide (CoO y ) and / or another cobalt precursor. In some implementations, the cobalt precursor may be with or without treatment with, for example, dimethylamine borane (DMAB), ammonium chloride (NH4Cl), and / or boron hydroxide (BO3). x H y ) can be used. In some implementations, the pH of the treatment chemical can be approximately 6 to approximately 9. However, other values ​​and ranges are also within the scope of protection of this disclosure.

[0096] In some implementations, the source / drain interconnect structure 134 is fabricated from copper (Cu) and a copper precursor used to deposit the material of the source / drain interconnect structure 134. The copper precursor can, for example, be a copper chloride (CuCl₂). x , such as CuCl2), a combination of a copper sulfate (CuS) x ) and a copper oxide (CuO y ) and / or another copper precursor. In some implementations, the copper precursor can be with or without treatment, e.g., with a compound of cobalt, carbon, hydrogen, and nitrogen (CoC). x H y N z ) and / or a carbon hydroxide (CH₄) x O y ) can be used. In some implementations, the pH of the treatment chemical can be approximately 7 to approximately 10. However, other values ​​and ranges are also within the scope of protection of this disclosure.

[0097] As in Fig. As shown in Figure 3H, a planarization facility can be used to perform a planarization operation (e.g., a CMP operation) to planarize the source / drain interconnect structure 134. In this way, the top surface of the source / drain interconnect structure 134 can be essentially coplanar with the top surface of the ILD layer 126.

[0098] As explained above, the Fig. 3A to 3H are merely examples. Other examples may differ from what is given with reference to the Fig. 3A to 3H have been explained.

[0099] The Fig. Figures 4A to 4D are representations of exemplary implementations of the source / drain contact structures 122 and the source / drain interconnect structures 134 for the semiconductor device 100 described here. Fig. Figure 4A shows an exemplary implementation 400 of a source / drain contact structure 122 and a source / drain interconnect structure 134. As in Fig. As shown in Figure 4A, the source / drain contact structure 122 and the source / drain interconnect structure 134 are in the exemplary implementation 400 of the source / drain contact structure 122 and the source / drain interconnect structure 134, respectively, in the Fig. The exemplary implementation shown in 1B is similar.

[0100] In exemplary implementation 400, however, a lower part of the source / drain interconnect structure 134 in the recess 138 of the source / drain contact structure 122 exhibits an enlarged area 402 that extends laterally outwards beyond the side walls of the source / drain interconnect structure 134. The area 402 can be created by lateral etching in the top surface of the source / drain contact structure 122 during the pre-cleaning operation, which is described in the Fig. 3D and Fig. 3E has been described. In some implementations, the lateral width (dimension D7) of an enlarged area 402 can be greater than 0 nm and up to approximately 5 nm. However, other values ​​and ranges also fall within the scope of protection of this disclosure.

[0101] As also seen in the close-up view of Fig. As shown in Figure 4A, the lower part of the source / drain interconnect structure can have 134 rounded corners. The angle of a rounded corner (dimension D8) can range from approximately 10° to approximately 80°. However, other values ​​and ranges are also within the scope of protection of this disclosure.

[0102] As also seen in the close-up view of Fig. As shown in Figure 4A, the highest parts of the top surface of the source / drain contact structure 122 (e.g., an outer circumference of the source / drain contact structure 122) can be spaced from the bottom surface of the ESL 128 in the z-direction by a distance corresponding to dimension D9. In some implementations, dimension D9 is approximately 0 nm to approximately 7 nm. However, other values ​​and ranges are also within the scope of protection of this disclosure.

[0103] Fig. Figure 4B shows an exemplary implementation 404 of a source / drain contact structure 122 and a source / drain interconnect structure 134. As in Fig. As shown in Figure 4B, the source / drain contact structure 122 and the source / drain interconnect structure 134 are in the exemplary implementation 404 of the source / drain contact structure 122 and the source / drain interconnect structure 134, respectively, in the Fig. The exemplary implementation shown in 1B is similar.

[0104] In the exemplary implementation 404, however, the source / drain interconnect structure 134 and the source / drain contact structure 122 in the semiconductor device 100 can be partially offset from each other in the x-direction and / or the y-direction. This partial offset can arise from a faulty superposition during the creation of the recess 302. As a result, the underside of the source / drain interconnect structure 134, which is produced in the recess 302, can be laterally offset with respect to the top side of the source / drain contact structure 122.

[0105] This can result in part 406 of the underside of the source / drain interconnect structure 134 being in contact with the dielectric layer 108 and / or part 408 of the top side of the source / drain contact structure 122 being in contact with the ESL 128. In some implementations, a lateral size (dimension D10) of part 408 can be approximately 0 nm to approximately 3 nm. However, other values ​​and ranges are also within the scope of protection of this disclosure. In some implementations, a lateral size (dimension D11) of part 406 can also be approximately 0 nm to approximately 3 nm. However, other values ​​and ranges are also within the scope of protection of this disclosure.

[0106] Fig. Figure 4C shows an exemplary implementation 410 of a source / drain contact structure 122 and a source / drain interconnect structure 134. As in Fig. As shown in Figure 4C, the source / drain contact structure 122 and the source / drain interconnect structure 134 are in the exemplary implementation 410 of the source / drain contact structure 122 and the source / drain interconnect structure 134, respectively, in the Fig. The exemplary implementation shown in 1B is similar.

[0107] In the exemplary implementation 410, however, the interface between the underside of the source / drain interconnect structure 134 and the topside of the source / drain contact structure 122 may be uneven and / or non-uniform, and it may have a non-uniform depth. This can result in various high and low spots in the interface between the underside of the source / drain interconnect structure 134 and the topside of the source / drain contact structure 122. A low spot 412 may be the lowest point in the interface between the underside of the source / drain interconnect structure 134 and the topside of the source / drain contact structure 122, and a high spot 414 may be the highest point in the interface between the underside of the source / drain interconnect structure 134 and the topside of the source / drain contact structure 122.The interface between the underside of the source / drain interconnect structure 134 and the top side of the source / drain contact structure 122 can have various intermediate points 416 which can correspond to local high spots and / or local low spots.

[0108] In some implementations, the z-direction distance (dimension D12) between the lowest point 412 and the underside of the ESL 128 can be approximately 0 nm to approximately 5 nm. However, other values ​​and ranges are also within the scope of protection of this disclosure. In some implementations, the z-direction distance (dimension D13) between the highest point 414 and the underside of the ESL 128 can be approximately 0 nm to approximately 3 nm. However, other values ​​and ranges are also within the scope of protection of this disclosure. In some implementations, the z-direction difference (dimension D14) between dimension D12 and dimension D13 can be approximately 0 nm to approximately 2 nm.

[0109] In some implementations, the z-direction distance (dimension D15) between an intermediate point 416 and the underside of the ESL 128 can be smaller than dimension D12 and larger than dimension D13. In some implementations, the z-direction difference (dimension D16) between dimension D13 and dimension D14 can be... (Translator's note: sentence is incomplete).

[0110] Fig. Figure 4D shows an exemplary implementation 418 of a source / drain contact structure 122 and a source / drain interconnect structure 134. As in Fig. As shown in Figure 4D, the source / drain contact structure 122 and the source / drain interconnect structure 134 are in the exemplary implementation 418 of the source / drain contact structure 122 and the source / drain interconnect structure 134, respectively, in the Fig. The exemplary implementation 410 shown in Figure 4C is similar. However, in the exemplary implementation 418, the lowest point 412 and the highest point 414 are located in the interface between the bottom of the source / drain interconnect structure 134 and the top of the source / drain contact structure 122, on opposite sides of the source / drain contact structure 122 and on opposite sides of the source / drain interconnect structure 134. The interface can transition from the lowest point 412 on a first side of the source / drain contact structure 122 and on a first side of the source / drain interconnect structure 134 to the highest point 414 on a second (opposite) side of the source / drain contact structure 122 and on a second (opposite) side of the source / drain interconnect structure 134.

[0111] As explained above, the Fig. 4A to 4D are intended merely as examples. Other examples may differ from what is described in the following. Fig. 4A to 4D have been explained.

[0112] The Fig. Figures 5A to 5E are representations of exemplary implementations of the source / drain contact structures 122 and the source / drain interconnect structures 134 for the semiconductor device 100 described here. Fig. Figure 5A shows an exemplary implementation 500 of a source / drain contact structure 122 and a source / drain interconnect structure 134. Fig. Figure 5B shows an exemplary implementation 502 of a source / drain contact structure 122 and a source / drain interconnect structure 134. Fig. 5C shows an exemplary implementation 504 of a source / drain contact structure 122 and a source / drain interconnect structure 134. Fig. Figure 5D shows an exemplary implementation 506 of a source / drain contact structure 122 and a source / drain interconnect structure 134. Fig. Figure 5E shows an exemplary implementation 508 of a source / drain contact structure 122 and a source / drain interconnect structure 134.

[0113] The exemplary implementations 500 to 508 in the Fig. 5A to 5E are the exemplary implementations 100, 400, 404, 410 and 418 respectively of the source / drain contact structures 122 and the source / drain interconnect structures 134 in the Fig. 1B, Fig. 4A, Fig. 4B, Fig. 4C and 4D are similar. Example implementations 500 to 508 in the Fig. However, in 5A to 5E, the top surfaces of the source / drain contact structures 122 are wider than the bottom surfaces of the source / drain interconnect structures 134. Thus, in the exemplary implementations 500 to 508, the Fig. 5A to 5E extend the upper surfaces of the source / drain contact structures 122 laterally outwards beyond one or more sides of the lower surfaces of the source / drain interconnect structures 134. This reduces the probability and / or the magnitude of a lateral offset between the source / drain contact structures 122 and the source / drain interconnect structures 134.

[0114] As explained above, the Fig. 5A to 5E are merely examples. Other examples may differ from what is stated in the reference to the Fig. has been explained in sections 5A to 5E.

[0115] Fig. Figure 6 is a flowchart of an exemplary process 600 associated with the fabrication of the semiconductor device described here. In some implementations, one or more process blocks of Fig. 6. performed using one or more semiconductor processing facilities, such as a deposition facility, an exposure facility, a developing facility, an etching facility, a planarization facility, an ion implantation facility, a tempering facility, a wafer / die transport facility and / or another type of semiconductor processing facility.

[0116] As in Fig. As specified in Section 6, Method 600 may include creating a recess in a dielectric layer of an interconnect layer of a semiconductor device (Block 610). For example, one or more semiconductor processing units may be used to create a recess (e.g., a recess 302) in a dielectric layer (e.g., an ILD layer 126 or an ESL 128) in an interconnect layer (e.g., an interconnect layer 104) of a semiconductor device (e.g., a semiconductor device 100), as described here. In some implementations, the recess exposes the top surface of a contact structure (e.g., a source / drain contact structure 122) of the semiconductor device.

[0117] As also in Fig. As specified in section 6, process 600 may include performing a pre-cleaning operation on the top surface of the contact structure using a metal precursor pre-cleaning agent (block 620). For example, one or more semiconductor processing units may be used to perform a pre-cleaning operation on the top surface of the contact structure using a metal precursor pre-cleaning agent (e.g., a pre-cleaning agent 308), as described herein.

[0118] As also in Fig. As specified in section 6, method 600 may include fabricating a conductive interconnect layer structure on the top side of the contact structure in the recess (block 630). For example, one or more semiconductor processing units may be used to fabricate a conductive structure (e.g., a source / drain interconnect structure 134) of the interconnect layer on the top side of the contact structure in the recess, as described here.

[0119] Procedure 600 may include further implementations, such as a single implementation or a combination of implementations described below and / or in conjunction with one or more other processes described elsewhere herein.

[0120] In an initial implementation, performing the pre-cleaning operation involves conducting a chemical impregnation process in which the metal precursor pre-cleaning agent remains on the top surface of the contact structure for a period of time.

[0121] In a second implementation, alone or in combination with the first implementation, the metal precursor pre-cleaning agent contains a halogenated metal precursor.

[0122] In a third implementation, alone or in combination with the first and / or the second implementation, the metal precursor pre-cleaning agent contains a fluorine-containing metal precursor.

[0123] In a fourth implementation, alone or in combination with one or more of the first to third implementations, the metal precursor pre-purification agent contains a chlorine-containing metal precursor.

[0124] In a fifth implementation, alone or in combination with one or more of the first to fourth implementations, the metal precursor pre-cleaning agent contains a metal precursor with a contact structure material.

[0125] In a sixth implementation, alone or in combination with one or more of the first to fifth implementations, the metal precursor pre-cleaning agent contains a metal precursor with a material of the conductive structure.

[0126] Fig. Figure 6 shows example blocks of Procedure 600, but in some implementations, Procedure 600 includes additional blocks, fewer blocks, different blocks, or differently arranged blocks than those shown in Figure 600. Fig. 6 are listed. Additionally or alternatively, two or more of the blocks of procedure 600 can be carried out in parallel.

[0127] Fig. Figure 7 is a flowchart of an exemplary process 700 associated with the fabrication of the semiconductor device described here. In some implementations, one or more process blocks of Fig. 7. performed using one or more semiconductor processing facilities, such as a deposition facility, an exposure facility, a developing facility, an etching facility, a planarization facility, an ion implantation facility, a tempering facility, a wafer / die transport facility and / or another type of semiconductor processing facility.

[0128] As in Fig. As specified in Figure 7, Method 700 may include creating a recess in a dielectric layer of an interconnect layer of a semiconductor device (Block 710). For example, one or more semiconductor processing units may be used to create a recess (e.g., a recess 302) in a dielectric layer (e.g., an ILD layer 126 or an ESL 128) in an interconnect layer (e.g., an interconnect layer 104) of a semiconductor device (e.g., a semiconductor device 100), as described herein. In some implementations, the interconnect layer is located above a device layer (e.g., a device layer 102) of the semiconductor device. In some implementations, the recess exposes the top surface of a contact structure (e.g., a source / drain contact structure 122) of the semiconductor device.

[0129] As also in Fig. As specified in section 7, method 700 may include performing a pre-cleaning operation on the top surface of the contact structure using a metal precursor pre-cleaning agent to remove metal and oxygen from the top surface of the contact structure (block 720). For example, one or more semiconductor processing units may be used to perform a pre-cleaning operation on the top surface of the contact structure using a metal precursor pre-cleaning agent to remove metal and oxygen from the top surface of the contact structure, as described herein.

[0130] As also in Fig. As specified in Figure 7, Method 700 may include fabricating a conductive interconnect layer structure on the top side of the contact structure in the recess (Block 730). For example, one or more semiconductor processing units may be used to fabricate a conductive structure (e.g., a source / drain interconnect structure 134) of the interconnect layer on the top side of the contact structure in the recess, as described here. In some implementations, the pre-cleaning operation and the fabrication of the conductive structure are performed in the same processing chamber, with a vacuum maintained in that processing chamber between the pre-cleaning operation and the fabrication of the conductive structure.

[0131] Procedure 700 may include further implementations, such as a single implementation or a combination of implementations, as described below and / or in conjunction with one or more other processes mentioned elsewhere herein.

[0132] In a first implementation, the metal precursor pre-cleaning agent contains a first metal precursor, and the fabrication of the conductive structure includes fabricating the conductive structure using a second metal precursor, wherein the first and second metal precursors comprise the same metal precursor.

[0133] In a second implementation, alone or in combination with the first implementation, the metal precursor pre-cleaning agent contains a first metal precursor, and the fabrication of the conductive structure includes fabricating the conductive structure using a second metal precursor, wherein the first and second metal precursors comprise different metal precursors.

[0134] In a third implementation, alone or in combination with the first and / or second implementation, the contact structure contains tungsten (W), and the metal precursor pre-cleaning agent contains tungsten fluoride (WF). x ) and / or tungsten chloride (WCl x ).

[0135] In a fourth implementation, alone or in combination with one or more of the first to third implementations, the contact structure contains molybdenum (Mo), and the metal precursor pre-cleaning agent contains molybdenum fluoride (MoF). x) and / or molybdenum chloride (MoCl₂) x ).

[0136] In a fifth implementation, alone or in combination with one or more of the first to fourth implementations, performing the pre-cleaning operation involves performing the pre-cleaning operation at a temperature of approximately 200 °C to approximately 450 °C.

[0137] Fig. Figure 7 shows example blocks of Procedure 700, but in some implementations, Procedure 700 includes additional blocks, fewer blocks, different blocks, or differently arranged blocks than those shown in Figure 700. Fig. 7 are listed. Additionally or alternatively, two or more of the blocks of procedure 700 can be carried out in parallel.

[0138] In this way, a pre-cleaning operation is performed using a metal precursor to remove a metal oxide layer from the top surface of a semiconductor device's contact structure before a conductive semiconductor device structure is fabricated on the contact structure. By using the metal precursor as a pre-cleaning agent, system-inherent oxides (and not just components like oxygen) can be completely removed without creating pores in the top surface of the contact structure, thus achieving a low contact resistance between the contact structure and the conductive structure.

[0139] As detailed above, some of the implementations described here provide a method. This method comprises creating a recess in a dielectric layer within an interconnect layer of a semiconductor device, exposing the top surface of the semiconductor device's contact structure through the recess. The method further comprises performing a pre-cleaning operation on the top surface of the contact structure using a metal precursor pre-cleaning agent. Finally, the method includes creating a conductive interconnect layer structure on the top surface of the contact structure within the recess.

[0140] As detailed above, a method is provided for some of the implementations described here. The method comprises creating a recess in a dielectric layer within an interconnect layer of a semiconductor device, wherein the interconnect layer is located above a device layer of the semiconductor device, and the recess exposes the top surface of a contact structure of the semiconductor device. The method further comprises performing a pre-cleaning operation on the top surface of the contact structure using a metal precursor pre-cleaning agent.The process further comprises fabricating a conductive structure of the interconnect layer on the top of the contact structure in the recess, wherein the pre-cleaning operation and the fabrication of the conductive structure are carried out in the same processing chamber, maintaining a vacuum in this processing chamber between the pre-cleaning operation and the fabrication of the conductive structure.

[0141] As explained in more detail above, some of the implementations described here provide a semiconductor device. The semiconductor device includes a substrate layer. The semiconductor device further includes an integrated circuit device in and / or on the substrate layer. The semiconductor device further includes a contact structure arranged in a first dielectric layer above the substrate layer and electrically connected to the integrated circuit device, the contact structure containing a first metallic material. The semiconductor device further includes a conductive structure arranged in a second dielectric layer above the first dielectric layer and in contact with the contact structure, with a bottom surface of the conductive structure recessed in a top surface of the contact structure.

[0142] The terms "approximately" and "essentially" can indicate a value of a given quantity that varies within 5% of its value (e.g., by +1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. It is understood that the terms "approximately" and "essentially" can refer to a percentage of the values ​​of a given quantity within the scope of this disclosure.

[0143] Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present disclosure. It should be clear to those skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other methods and structures to achieve the same objectives and / or to obtain the same advantages as in the embodiments presented here. Those skilled in the art should also recognize that such equivalent interpretations do not deviate from the fundamental concept and scope of protection of the present disclosure and that they can make various changes, substitutions, and modifications without deviating from the fundamental concept and scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 690.553

[0001]

Claims

[1] Procedure, encompassing: Creating a recess in a dielectric layer in an interconnect layer of a semiconductor device, wherein a top side of the contact structure of the semiconductor device is exposed through the recess; Performing a pre-cleaning operation on the top side of a contact structure using a metal precursor pre-cleaning agent; and Creating a conductive structure of the interconnect layer on the top side of the contact structure in the recess. [2] The method of claim 1, wherein performing the pre-cleaning operation comprises: Performing a chemical impregnation, whereby the metal precursor pre-cleaning agent remains on the top of the contact structure for a period of time. [3] Method according to claim 1 or 2, wherein the metal precursor pre-cleaning agent contains a halogenated metal precursor. [4] Method according to any of the preceding claims, wherein the metal precursor pre-purification agent contains a fluorine-containing metal precursor. [5] Method according to any of the preceding claims, wherein the metal precursor pre-purification agent contains a chlorine-containing metal precursor. [6] Method according to any of the preceding claims, wherein the metal precursor pre-cleaning agent contains a metal precursor with a contact structure material. [7] Method according to any of the preceding claims, wherein the metal precursor pre-cleaning agent contains a metal precursor having a material of the conductive structure. [8] Procedures, comprehensive: Creating a recess in a dielectric layer in an interconnect layer of a semiconductor device, wherein the interconnect layer is located above a device layer of the semiconductor device and a top surface of a contact structure of the semiconductor device is exposed through the recess; Performing a pre-cleaning operation on the top surface of the contact structure using a metal precursor pre-cleaning agent to remove metal and oxygen from the top surface of the contact structure; and Creating a conductive structure of the interconnect layer on the top side of the contact structure in the recess, wherein The pre-cleaning operation and the fabrication of the conductive structure are carried out in the same processing chamber, with a vacuum being maintained in this processing chamber between the pre-cleaning operation and the fabrication of the conductive structure. [9] Method according to claim 8, wherein the metal precursor pre-cleaning agent contains a first metal precursor, The fabrication of the conductive structure includes fabricating the conductive structure using a second metal precursor, and the first and second metallic precursors comprise the same metallic precursor. [10] Method according to claim 8, wherein the metal precursor pre-cleaning agent contains a first metal precursor, The fabrication of the conductive structure includes fabricating the conductive structure using a second metal precursor, and The first and second metal precursors comprise different metal precursors. [11] Method according to any one of claims 8 to 10, wherein the contact structure contains tungsten (W), and the metal precursor pre-purification agent tungsten fluoride (WF x ) and / or tungsten chloride (WClx ) contains. [12] Method according to any one of claims 8 to 11, wherein the contact structure contains molybdenum (Mo), and the metal precursor pre-cleaning agent molybdenum fluoride (MoF x ) and / or molybdenum chloride (MoCl₂) x ) contains. [13] Method according to any one of claims 8 to 12, wherein performing the pre-cleaning operation comprises performing the pre-cleaning operation at a temperature of about 200 °C to about 450 °C. [14] Semiconductor device with: a substrate layer; an integrated circuit device in and / or on the substrate layer; a contact structure arranged in a first dielectric layer above the substrate layer and electrically connected to the integrated circuit device, wherein the contact structure contains a first metallic material; and a conductive structure arranged in a second dielectric layer above the first dielectric layer and in contact with the contact structure, wherein a bottom side of the conductive structure is recessed in a top side of the contact structure. [15] Semiconductor device according to claim 14, wherein the depth of a recess in the top surface of the contact structure, with which the conductive structure is recessed, is about 0.5 nm to about 5 nm. [16] Semiconductor device according to claim 14 or 15, wherein the conductive structure is offset laterally from the contact structure, such that part of the underside of the conductive structure is in contact with the first dielectric layer. [17] Semiconductor device according to one of claims 14 to 16 wherein a part of the top surface of the contact structure is in contact with a third dielectric layer vertically between the first and the second dielectric layer. [18] Semiconductor device according to any one of claims 14 to 17, wherein a lateral width of the top of the contact structure is greater than a lateral width of the bottom of the conductive structure, and a recess in the top surface of the contact structure, in which the conductive structure is recessed, only enclosing a part of the top surface of the contact structure. [19] Semiconductor device according to any one of claims 14 to 18, wherein a lateral width of a first part of the conductive structure, which is recessed in the top of the contact structure, is greater than a lateral width of a second part of the conductive structure above the top of the contact structure. [20] Semiconductor device according to one of claims 14 to 19, wherein the underside of the conductive structure is recessed with a non-uniform depth over the top side of the contact structure.

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