DISPLAY DEVICE WITH PIXEL AREAS

Abstract

A display device is provided that includes pixel regions. The pixel regions may be arranged between first / second gate lines. Each of the pixel regions may include a first sub-pixel controlled by the first gate line and a second sub-pixel controlled by the second gate line. The second sub-pixel may display a different color than the first sub-pixel of the corresponding pixel region. The first / second sub-pixel of each pixel region may include a first / second driver circuit arranged close to the first / second gate line. The second driver circuit of each pixel region may share a data line with the first driver circuit of an adjacent pixel region. The second driver circuit of each pixel region may have a symmetrical arrangement with the first driver circuit of an adjacent pixel region.Consequently, the deviation in the coupling capacitance that occurs between each driver circuit and the gate line coupled to the corresponding driver circuit can be reduced.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0028797, filed on February 28, 2024. BACKGROUNDTechnical field

[0002] The disclosure relates to a display device in which each of the pixel regions is electrically connected to a pad region through one of the connecting wirings. Description of the state of the art

[0003] In general, a display device provides an image to a user. The display device may, for example, contain multiple pixel regions. Each of the pixel regions may realize different colors. Each of the pixel regions may, for example, contain multiple sub-pixels. The sub-pixels in each pixel region may display different colors. Each of the pixel regions may, for example, contain a first sub-pixel and a second sub-pixel that displays a different color than the first sub-pixel.

[0004] The second subpixel of each pixel region can be controlled independently of the first subpixel of the corresponding pixel region. For example, the first subpixel of each pixel region can include a first driver circuit, while the second subpixel of each pixel region can include a second driver circuit. The first subpixel and the second subpixel of each pixel region can be controlled by different gate signals. For example, the first driver circuit of each pixel region can be electrically connected to a first gate line, while the second driver circuit of each pixel region can be electrically connected to a second gate line.

[0005] The pixel regions may be arranged between the first gate line and the second gate line. Consequently, the second driver circuit of each pixel region may have a different arrangement than the first driver circuit of the corresponding pixel region. For example, each of the first driver circuit and the second driver circuit in each pixel region may include a driver thin-film transistor, wherein a distance between the driver thin-film transistor of the second driver circuit and the second gate line may differ from a distance between the driver thin-film transistor of the first driver circuit and the first gate line. SHORT SUMMARY

[0006] In a display device, a coupling capacitance may occur between each driver circuit and the gate line electrically connected to the corresponding driver circuit. The coupling capacitance may be proportional to the distance between the driver thin-film transistor of each driver circuit and the gate line electrically connected to the corresponding driver circuit. Consequently, in the display device, the second sub-pixel of each pixel region may have a different coupling capacitance than the first sub-pixel of the corresponding pixel region. That is, in the display device, the light emitted by the second sub-pixel of each pixel region may have a different luminance than the light emitted by the first sub-pixel of the corresponding pixel region.

[0007] Therefore, according to the prior art display device, the quality of the image may decrease due to the deviation of the luminance of the light emitted from the sub-pixels in each pixel region.

[0008] Accordingly, the disclosure is directed to a display device that substantially obviates one or more problems due to the limitations and disadvantages of the prior art.

[0009] Various embodiments of the disclosure provide a display device that can reduce the deviation of the luminance of the light emitted from the sub-pixels of each pixel region.

[0010] Various embodiments of the disclosure provide a display device that can reduce the variation in the coupling capacitance of the sub-pixels in each pixel region.

[0011] Additional advantages, technical advantages, and features of the disclosure will be set forth in part in the description that follows, and in part will become apparent to those of ordinary skill in the art upon examination of the following or may be learned from practice of the disclosure. Other advantages of the disclosure may be realized and attained by the structure particularly pointed out in both the written description and its claims, as well as in the accompanying drawings.

[0012] The object is achieved by the features of the independent claims. Preferred embodiments are specified in the dependent claims.

[0013] To achieve these advantages, as embodied and generally described herein, a display device is provided that includes a first gate line, a first data line, and a second gate line. The first gate line and the second gate line extend in a first direction. The second gate line is arranged parallel to the first gate line. The data line extends in a second direction. The second direction is perpendicular to the first direction. The data line crosses the first gate line and the second gate line. A first driver circuit of a first sub-pixel is electrically connected to the first gate line and the first data line. A second driver circuit of a second sub-pixel is electrically connected to the first data line and the second gate line. The first data line crosses between the first sub-pixel and the second sub-pixel.A first emission region of the first sub-pixel is arranged between the first driver circuit and the second gate line. A second emission region of the second sub-pixel is arranged between the first gate line and the second driver circuit. The second emission region displays a different color than the first emission region. The second driver circuit has a symmetrical arrangement to the first driver circuit.

[0014] The second emission region may be arranged in a first direction near the first emission region.

[0015] Both the first driver circuit and the second driver circuit may include a driver thin film transistor.

[0016] A gate electrode of the driver thin film transistor may be arranged in parallel to the first gate line and the second gate line.

[0017] A semiconductor pattern of the driver thin film transistor may be arranged in parallel to the first data line.

[0018] A second data line may be arranged parallel to the first data line.

[0019] A third driver circuit of a third sub-pixel may be electrically connected to the first gate line and the second data line.

[0020] A fourth driver circuit of a fourth sub-pixel may be electrically connected to the second data line and the second gate line.

[0021] The first subpixel may be arranged between the second data line and the third subpixel.

[0022] The fourth sub-pixel may be arranged between the second sub-pixel and the first data line.

[0023] The fourth driver circuit may be arranged in a first direction near the second driver circuit.

[0024] The third driver circuit may be arranged in the first direction at the first driver circuit.

[0025] The fourth driver circuit may have an arrangement symmetrical to the third driver circuit.

[0026] The third driver circuit may have an arrangement symmetrical to the first driver circuit, wherein the fourth driver circuit has an arrangement symmetrical to the second driver circuit.

[0027] A third emission region of the third sub-pixel may be arranged between the third driver circuit and the second gate line.

[0028] The third emission area may display a different color than the first emission area and the second emission area.

[0029] A fourth emission region of the fourth sub-pixel may be arranged between the first gate line and the fourth driver circuit.

[0030] The fourth emission area may display a different color than the first emission area, the second emission area, and the third emission area.

[0031] Reference voltage supply lines may be arranged in parallel to the first data line and the second data line.

[0032] The first sub-pixel and the third sub-pixel may be arranged between one of the reference voltage supply lines and the second data line.

[0033] The second sub-pixel and the fourth sub-pixel may be arranged between one of the reference voltage supply lines and the first data line.

[0034] According to another embodiment, a display device is provided that includes first data lines crossing a first gate line. Second data lines are arranged between the first data lines. The second data lines cross the first gate line. A second gate line, extending parallel to the first gate line, crosses the first data lines and the second data lines. The pixel regions are arranged between the first data lines and the second data lines. Each of the pixel regions includes a first sub-pixel and a second sub-pixel arranged along the first gate line and the second gate line. A first emission region of the first sub-pixel is arranged between a first driver circuit of the first sub-pixel and the second gate line.A second emission region of the second sub-pixel is arranged between the first gate line and a second driver circuit of the second sub-pixel. The first driver circuit is electrically connected to one of the first data lines and the first gate line. The second driver circuit is electrically connected to one of the second data lines and the second gate line. The second driver circuit has a symmetrical arrangement with respect to the first driver circuit.

[0035] The second subpixel of each pixel area may display a different color than the first subpixel of the corresponding pixel area.

[0036] The first subpixel of each pixel area may display the same or substantially the same color as the first subpixel of an adjacent pixel area.

[0037] The second subpixel of each pixel region may display the same or substantially the same color as the second subpixel of an adjacent pixel region.

[0038] Each of the first sub-pixel and the second sub-pixel in each pixel region may include a first switching thin-film transistor and a second switching thin-film transistor.

[0039] A semiconductor pattern of the first switching thin film transistor may cross the first gate line or the second gate line.

[0040] The first emission region and the second emission region of each pixel region may be arranged between the first gate line and the second gate line.

[0041] A gate electrode of the second switching thin film transistor may have a shape protruding from the first gate line or the second gate line.

[0042] A semiconductor pattern of the second switching thin film transistor may be arranged in parallel to the first gate line and the second gate line.

[0043] Reference voltage supply lines may be arranged between the first data lines and the second data lines.

[0044] The reference voltage supply lines may cross the first gate line and the second gate line.

[0045] Each of the reference voltage supply lines may cross between the first sub-pixel and the second sub-pixel in one of the pixel regions.

[0046] Each of the reference voltage supply lines may include a main wiring, an auxiliary wiring, and a connecting wiring.

[0047] The auxiliary wiring can be arranged parallel to the main wiring.

[0048] The connecting wiring can be arranged between the main wiring and the auxiliary wiring.

[0049] The auxiliary wiring may be electrically connected to the main wiring via the connecting wiring. Both the first sub-pixel and the second sub-pixel may include a light-emitting device that overlaps the corresponding emission region.

[0050] A first electrode of each light-emitting device may include a portion that overlaps the auxiliary wiring. BRIEF DESCRIPTION OF THE MULTIPLE VIEWS OF THE DRAWINGS

[0051] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate one or more embodiments of the disclosure and, together with the description, serve to explain the principle of the disclosure; in the drawings: Fig. 1 is a view schematically showing a display device of an embodiment of the disclosure; Fig. 2 is a view showing a circuit of a pixel region in the display device of the embodiment; Fig. 3 an enlarged view of the R-area in Fig. 1; Fig. 4 an enlarged view of the area K1 in Fig. 3; Fig. 5 an enlarged view of area K2 in Fig. 3; Fig. 6 one along II' to Fig. 4 taken view; and Fig. 7 and Fig. 8 views showing the display device of another embodiment of the disclosure. DETAILED DESCRIPTION

[0052] In the following, details regarding the above objects, technical configurations, and operational effects of the embodiments of the disclosure will be clearly understood through the following detailed description with reference to the drawings illustrating some embodiments of the disclosure. The embodiments of the disclosure are provided here to enable the technical inventive concept of the disclosure to be satisfactorily conveyed to those skilled in the art; accordingly, the disclosure may be embodied in other forms and is not limited to the embodiments described below.

[0053] In addition, the same or very similar elements may be designated by the same reference numerals throughout the application text and the drawings.

[0054] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, number of elements, and the like illustrated in the accompanying drawings for describing the embodiments of the disclosure are merely examples, and the disclosure is not limited thereto.

[0055] A dimension including the size and a thickness of each component illustrated in the drawings are illustrated for convenience of description, and the disclosure is not limited to the size and thickness of the illustrated component, but it should be noted that the relative dimensions including the relative size, location, and thickness of the components illustrated in various drawings presented herewith are part of the disclosure.

[0056] It will be appreciated that when a first element is referred to as being "on" a second element, a third element may be interposed between the first and second elements, although the first element may be arranged on the second element so as to contact the second element.

[0057] Here, terms such as "first" and "second" may be used to distinguish any element from another element. However, the first element and the second element may be named arbitrarily according to the convenience of those skilled in the art without departing from the technical inventive spirit of the disclosure.

[0058] The terms used in the application text of the disclosure are used only to describe specific embodiments and are not intended to limit the scope of the disclosure. For example, an element described in the singular form is intended to include multiple elements unless the context clearly indicates otherwise. In addition, it is further recognized that in the application text of the disclosure, the terms "comprises" and "includes" specify the presence of stated features, integers, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations.

[0059] And, unless "directly" is used, the terms "connected" and "coupled" may imply that two components are "connected" or "coupled" by one or more other components that are located between the two components.

[0060] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. It is further recognized that terms, such as those defined in commonly used dictionaries, should be interpreted to have a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein. Embodiments

[0061] Fig. 1 is a view schematically showing a display device according to an embodiment of the present disclosure. Fig. 2 is a view showing a circuit of a pixel region in the display device according to the embodiment of the disclosure.

[0062] In the Fig. 1 and Fig. 2, the display device according to the embodiment of the disclosure may include a display panel DP. The display device DP may generate an image provided to a user. For example, the pixel regions PA and the signal wirings GL1, GL2, DL1, DL2, PL, and RL may be arranged in the display device DP. In each pixel region PA, various signals may be provided via the signal wirings GL1, GL2, DL1, DL2, PL, and RL. The signal wirings GL1, GL2, DL1, DL2, PL, and RL may include, for example, the gate lines GL1 and GL2 that apply a gate signal, the data lines DL1 and DL2 that apply a data signal, the power voltage supply lines PL that supply a power voltage, and the reference voltage supply lines RL that supply a reference voltage. The data lines DL1 and DL2 may extend in a direction that crosses the gate lines GL1 and GL2.The power voltage supply lines PL and the reference voltage supply lines RL can extend parallel to the data lines DL1 and DL2.

[0063] The gate lines GL1 and GL2 can be electrically connected to a gate driver GD. The data lines DL1 and DL2 can be electrically connected to a data driver DD. The gate driver GD and the data driver DD can be electrically connected to a timing control unit TC. The gate driver GD and the data driver DD can be controlled by the timing control unit TC. The gate driver GD can receive, for example, clock signals, reset signals, and a start signal from the timing control unit TC, while the data driver DD can receive digital video data and a source timing signal from the timing control unit TC. The power voltage supply lines PL and the reference voltage supply lines RL can be electrically connected to a power unit PU.

[0064] The display panel DP may include an active area AA in which the pixel areas PA are arranged, and a bezel area BZ arranged outside the active area AA. The bezel area BZ may be arranged outside the pixel areas PA. The active area AA may, for example, be surrounded by the bezel area BZ. The gate driver GD, the data driver DD, the timing control unit TC, and the power unit PU may be arranged outside the active area AA. Each of the signal wirings GL1, GL2, DL1, DL2, PL, and RL may, for example, include a region arranged in the bezel area BZ. At least one of the gate driver GD, the data driver DD, the timing control unit TC, and the power unit PU may be arranged in the bezel area BZ. The display device according to the embodiment of the disclosure may, for example,a GIP (Gate in Panel Type Display) in which the gate driver GD is formed in the bezel region BZ.

[0065] The pixel regions PA can be arranged adjacent to one another in a first direction and a second direction. The second direction can be a direction perpendicular to the first direction. Each of the pixel regions PA can realize different colors. Each of the pixel regions PA can contain, for example, a plurality of sub-pixels R-SP, G-SP, W-SP, and B-SP. The sub-pixels R-SP, G-SP, W-SP, and B-SP in each pixel region PA can display different colors. Each of the pixel regions PA can contain, for example, a red sub-pixel R-SP displaying a red color, a green sub-pixel G-SP displaying a green color, a white sub-pixel W-SP displaying a white color, and a blue sub-pixel B-SP displaying a blue color.

[0066] The subpixels R-SP, G-SP, W-SP, and B-SP of each pixel area PA can be controlled by the signals applied via the signal wirings GL1, GL2, DL1, DL2, PL, and RL. A driver circuit R-DC, G-DC, W-DC, and B-DC, electrically connected to a light-emitting device 300R, 300G, 300W, and 300B, can be arranged, for example, in each subpixel R-SP, G-SP, W-SP, and B-SP of each pixel area PA.

[0067] The driver circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP can control the light-emitting devices 300R, 300G, 300W, and 300B of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP by a signal applied via the signal wirings GL1, GL2, DL1, DL2, PL, and RL. The driver circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be electrically connected to one of the gate lines GL1 and GL2, one of the data lines DL1 and DL2, one of the power supply lines PL, and one of the reference supply lines RL. For example, the driving circuit R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP can supply a driving current corresponding to the data signal to the light-emitting device 300R, 300G, 300W, and 300B of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP according to the gate signal.The drive current supplied by the drive circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be maintained for one frame. The drive circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP can have the same or substantially the same structure. The drive circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP can include, for example, a first thin-film transistor TR1, a second thin-film transistor TR2, a third thin-film transistor TR3, and a storage capacitor Cst.

[0068] Fig. 3 is an enlarged view of the R-area in Fig. 1. Fig. 4 is an enlarged view of the K1 area in Fig. 3. Fig. 5 is an enlarged view of the K2 area in Fig. 3. Fig. 6 is a line along II' to Fig. 4 taken view.

[0069] In the Fig. 2 to 6, the first thin-film transistor TR1 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can transmit the data signal to the second thin-film transistor TR2 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP according to the gate signal. The first thin-film transistor TR1 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can function, for example, as a switching thin-film transistor. The first thin-film transistor TR1 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can include a first semiconductor pattern 211 and a first gate electrode 213. The first semiconductor pattern 211 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can include a first drain region, a first channel region, and a first source region. The first channel region can be arranged between the first drain region and the first source region. The first drain region and the first source region may have a lower resistance than the first channel region.The first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be disposed on the first channel region of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be electrically connected to the corresponding gate line GL1 and GL2, while the first drain region of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be electrically connected to the corresponding data line DL1 and DL2.

[0070] The second thin-film transistor TR2 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can generate the drive current corresponding to the data signal. The second thin-film transistor TR2 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can function, for example, as a driver thin-film transistor. The second thin-film transistor TR2 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can have the same or substantially the same structure as the first thin-film transistor TR1 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The second thin-film transistor TR2 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can include, for example, a second semiconductor pattern 221 and a second gate electrode 223.

[0071] The second semiconductor pattern 221 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a semiconductor material. The second semiconductor pattern 221 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include, for example, low-temperature poly-Si (LPTS) or an oxide semiconductor such as IGZO. The second semiconductor pattern 221 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a second drain region 221d, a second channel region 221c, and a second source region 221s. The second channel region 221c may be disposed between the second drain region 221d and the second source region 221s. The second drain region 221d and the second source region 221s may have a resistance lower than that of the second channel region 221c. The second drain region 221d and the second source region 221s may include, for example, a conductive region made of an oxide semiconductor.The second channel region 221c may be a region of an oxide semiconductor that is not conductive.

[0072] The first semiconductor pattern 211 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may contain the same or substantially the same material as the second semiconductor pattern 221 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The first semiconductor pattern 211 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be disposed on the same or substantially the same layer as the second semiconductor pattern 221 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The first semiconductor pattern 211 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be formed by the same process as the second semiconductor pattern 221 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The first semiconductor pattern 211 of each sub-pixel R-SP, G-SP, W-SP and B-SP may be formed simultaneously with the second semiconductor pattern 221 of the corresponding sub-pixel R-SP, G-SP, W-SP and B-SP.The second drain region 221d of each sub-pixel R-SP, G-SP, W-SP and B-SP may be electrically connected to one of the power voltage supply lines PL.

[0073] The second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be disposed on the second semiconductor pattern 221 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may, for example, overlap the second channel region 221c of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The second drain region 221d and the second source region 221s of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be disposed outside the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a conductive material. The second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP and B-SP may contain, for example, a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti) and tungsten (W).The second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be spaced apart from the second semiconductor pattern 221 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be insulated from the second semiconductor pattern 221 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The second channel region 221c of each sub-pixel R-SP, G-SP, W-SP, and B-SP may, for example, have an electrical conductivity corresponding to a voltage applied to the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP and B-SP may be electrically connected to the first source region of the corresponding sub-pixel R-SP, G-SP, W-SP and B-SP.

[0074] The first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include the same or substantially the same material as the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The first gate electrode 213 and the second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be disposed on the same layer. The first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be formed by the same or substantially the same process as the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the first gate electrode 213 and the second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be formed simultaneously.

[0075] The storage capacitor Cst of each sub-pixel R-SP, G-SP, W-SP, and B-SP can maintain a voltage applied to the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP for one frame. The storage capacitor Cst of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be electrically connected, for example, to the second source region 221s and the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The storage capacitor Cst of each sub-pixel R-SP, G-SP, W-SP, and B-SP can have a stacked structure of capacitor electrodes. The storage capacitor Cst of each sub-pixel R-SP, G-SP, W-SP, and B-SP includes, for example,a first capacitor electrode electrically connected to the second source region 221s of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP; and a second capacitor electrode electrically connected to the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. At least one of the first capacitor electrode and the second capacitor electrode in each sub-pixel R-SP, G-SP, W-SP, and B-SP can be formed using a process for forming the second thin-film transistor TR2 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. Consequently, in the display device according to the embodiment of the disclosure, a process for forming the drive circuit R-DC, G-DC, W-ED, and B-DC in each sub-pixel R-SP, G-SP, W-SP, and B-SP can be simplified.

[0076] The third thin-film transistor TR3 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can initialize the storage capacitor Cst of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP according to the gate signal. For example, the reference voltage can be applied to the storage capacitor Cst of each sub-pixel R-SP, G-SP, W-SP, and B-SP by the third thin-film transistor TR3 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP according to the gate signal. The third thin-film transistor TR3 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can function as a switching thin-film transistor. The third thin-film transistor TR3 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may have the same or substantially the same structure as the first thin-film transistor TR1 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The third thin-film transistor TR3 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include, for example, a third semiconductor pattern 231 and a third gate electrode 233.The third gate electrode 233 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a third drain region, a third channel region, and a third source region. The third gate electrode 233 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be electrically connected to the corresponding gate line GL1 and GL2, and the third drain region of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be electrically connected to the corresponding reference voltage supply line RL. The gate line GL1 and GL2 electrically connected to the third gate electrode 233 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be the same or substantially the same as the gate line GL1 and GL2 electrically connected to the first gate electrode 213 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The first thin film transistor TR1 and the third thin film transistor TR3 of each sub-pixel R-SP, G-SP, W-SP and B-SP can be, for example,be switched on / off simultaneously.

[0077] The light-emitting device 300R, 300G, 300W, and 300B of each sub-pixel R-SP, G-SP, W-SP, and B-SP can emit light displaying a specific color according to the drive current applied by the drive circuit R-DC, G-DC, W-DC, and B-DC of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The light-emitting device 300R, 300G, 300W, and 300B of each sub-pixel R-SP, G-SP, W-SP, and B-SP can have the same or substantially the same structure. The light-emitting device 300R, 300G, 300W, and 300B of each sub-pixel R-SP, G-SP, W-SP, and B-SP can, for example, B. include a first electrode 310, a light-emitting layer 320 and a second electrode 330 which are stacked one after the other.

[0078] The first electrode 310 may contain a conductive material. The first electrode 310 may contain a material with a high degree of transmittance. For example, the first electrode 310 may be a transparent electrode made of a transparent conductive material, such as ITO and IZO.

[0079] The light-emitting layer 320 can generate light with a luminance corresponding to a voltage difference between the first electrode 310 and the second electrode 330. The light-emitting layer 320 can include, for example, at least one emissive material (EML) layer. The emissive material layer can include an organic emissive material, an inorganic emissive material, or a hybrid emissive material. The display device according to the embodiment of the disclosure can be, for example, an organic light-emitting display device including an organic emissive material. The light-emitting layer 320 can have a multilayer structure. The light-emitting layer 320 can include, for example, at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).Consequently, in the display device according to the embodiment of the disclosure, the efficiency of the light-emitting layer 320 can be improved.

[0080] The second electrode 330 may contain a conductive material. The second electrode 330 may contain a different material than the first electrode 310. A reflection of the second electrode 330 may be greater than a reflection of the first electrode 310. The second electrode 330 may contain, for example, a metal such as aluminum (Al) and silver (Ag). Consequently, in the display device according to the embodiment of the disclosure, the light generated by the light-emitting layer 320 may be emitted outward through the first electrode 310. The second electrode 330 may have a lower work function than the first electrode 310. For example, the first electrode 310 may function as an anode, while the second electrode 330 may function as a cathode.

[0081] The light-emitting devices 300R, 300G, 300W, and 300B and the driver circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be arranged on a device substrate 100. The device substrate 100 may include an insulating material. The device substrate 100 may include, for example, glass or plastic.

[0082] A plurality of insulating layers 110, 120, 130, 140, and 150 may be disposed on the device substrate 100 to reduce or prevent unnecessary electrical connection. For example, a buffer insulating layer 110, a gate insulating layer 120, a device passivation layer 130, a planarization layer 140, and a bank insulating layer 150 may be disposed on the device substrate 100.

[0083] The buffer insulating layer 110 may be disposed on the device substrate 100. The buffer insulating layer 110 may reduce or prevent contamination from the device substrate 100 in a process of forming the driving circuit R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP. A top surface of the device substrate 100 toward the driving circuit R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be completely covered by the buffer insulating layer 110, for example. The driving circuit R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be disposed on the buffer insulating layer 110. The buffer insulating layer 110 may include an insulating material. The buffer insulating layer 110 may, for example, be made of a silicon dioxide (SiO2) oxide film. B. contain an inorganic insulating material, such as silicon oxide (SiOx) and silicon nitride (SiNx). The buffer insulating layer 110 may have a multilayer structure. The buffer insulating layer 110 may, for example,B. have a structure in which an inorganic insulating layer made of silicon oxide (SiOx) and an inorganic insulating layer made of silicon nitride (SiNx) are stacked.

[0084] A light-blocking pattern 105 may be disposed between the device substrate 100 and the buffer insulating layer 110 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. The light-blocking pattern 105 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a material capable of blocking light. The light-blocking pattern 105 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include, for example, a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The light-blocking pattern 105 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may overlap the second semiconductor pattern 221 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP.Consequently, in the display device according to the embodiment of the disclosure, the light traveling toward the second semiconductor pattern 221 of each sub-pixel R-SP, G-SP, W-SP, and B-SP and passing through the device substrate 100 can be blocked by the light-blocking pattern 105 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. Therefore, in the display device according to the embodiment of the disclosure, the change in the characteristics of the second thin-film transistor TR2 in each sub-pixel R-SP, G-SP, W-SP, and B-SP due to external light can be reduced or prevented.

[0085] A specific voltage can be applied to the light-blocking pattern 105 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. In the sub-pixel R-SP, G-SP, W-SP, and B-SP, for example, a source connection electrode 240 for electrically connecting the light-blocking pattern 105 to the second source region 221s can be arranged. The source connection electrode 240 of the sub-pixel R-SP, G-SP, W-SP, and B-SP can include a conductive material. The source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can include a material that has a relatively low resistance. The source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP can include, for example, a metal, such as a silicon dioxide (SiO2). B. aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti) and tungsten (W).The source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be disposed on the same layer as the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The second gate electrode 223 and the source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may contain the same or substantially the same material. The source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be formed by the same or substantially the same process as the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the second gate electrode 223 and the source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be formed simultaneously.Consequently, in the display device according to the embodiment of the disclosure, the change in the characteristics of the second thin film transistor TR2 in each sub-pixel R-SP, G-SP, W-SP and B-SP can be effectively reduced or prevented.

[0086] The gate insulating layer 120 may be disposed on the buffer insulating layer 110. The first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be insulated from the first semiconductor pattern 211 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP by the gate insulating layer 120. The second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be insulated from the second semiconductor pattern 221 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP by the gate insulating layer 120. The third gate electrode 233 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be insulated from the third semiconductor pattern 231 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP by the gate insulating layer 120. For example, the gate insulating layer 120 may cover the first semiconductor pattern 211, the second semiconductor pattern 221, and the third semiconductor pattern 231 of each sub-pixel R-SP, G-SP, W-SP, and B-SP.The first gate electrode 213, the second gate electrode 223, and the third gate electrode 233 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be disposed on the gate insulating layer 120. The source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be disposed on the gate insulating layer 120. The gate insulating layer 120 may include an insulating material. The gate insulating layer 120 may include, for example, an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0087] The device passivation layer 130 may be disposed on the gate insulating layer 120. The device passivation layer 130 may reduce or prevent damage to the driver circuits R-DC, G-DC, W-DC, and B-DC in each subpixel R-SP, G-SP, W-SP, and B-SP due to external influences and moisture. For example, the first gate electrode 213, the second gate electrode 223, and the third gate electrode 233 of each subpixel R-SP, G-SP, W-SP, and B-SP may be covered by the device passivation layer 130. The device passivation layer 130 may include an insulating material. The device passivation layer 130 may be, for example, a linear insulating layer made of an inorganic insulating material.

[0088] The planarization layer 140 may be disposed on the device passivation layer 130. The planarization layer 140 may eliminate a thickness difference due to the driver circuitry R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP. A top surface of the planarization layer 140 relative to the device substrate 100 may be flat, for example. The top surface of the planarization layer 140 may be parallel to the top surface of the device substrate 100. The planarization layer 140 may include an insulating material. The planarization layer 140 may include a different material than the device passivation layer 130. The planarization layer 140 may include a material having relatively high flowability. The planarization layer 140 may include, for example, an organic insulating material.

[0089] The bank insulation layer 150 may be disposed on the planarization layer 140. The bank insulation layer 150 may contain an insulating material. For example, the bank insulation layer 150 may contain an organic insulating material. The bank insulation layer 150 may contain a different material than the planarization layer 140.

[0090] The light-emitting device 300R, 300G, 300W, and 300B of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be arranged on the planarization layer 140. The first electrode 310 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be insulated from the first electrode 310 of the adjacent sub-pixel R-SP, G-SP, W-SP, and B-SP by the bank insulating layer 150. An edge of the first electrode 310 in each sub-pixel R-SP, G-SP, W-SP, and B-SP may be covered, for example, by the bank insulating layer 150. The first electrode 310 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be partially exposed by the bank insulating layer 150. The bank insulating layer 150 may, for example, B. define an emission region R-EA, G-EA, W-EA and B-EA in each subpixel R-SP, G-SP, W-SP and B-SP.The light-emitting layer 320 and the second electrode 330 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be stacked on a portion of the first electrode 310 that overlaps the emission region R-EA, G-EA, W-EA, and B-EA of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the light-emitting layer 320 may be in direct contact with the first electrode 310 and the second electrode 330 in the emission region R-EA, G-EA, W-EA, and B-EA of each sub-pixel R-SP, G-SP, W-SP, and B-SP.

[0091] The first electrode 310 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be electrically connected to the driver circuit R-DC, G-DC, W-DC, and B-DC of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the first electrode 310 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be in direct contact with the source connection electrode of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP by penetrating the device passivation layer 130 and the planarization layer 140. The device passivation layer 130 and the planarization layer 140 may include pixel contact holes that expose a portion of the source connection electrode 240 in each sub-pixel R-SP, G-SP, W-SP, and B-SP. The first electrode 310 of each sub-pixel R-SP, G-SP, W-SP and B-SP may be electrically connected to the source connection electrode 240 of the corresponding sub-pixel R-SP, G-SP, W-SP and B-SP via one of the pixel contact holes.The pixel contact holes may be arranged outside the emission region R-EA, G-EA, W-EA, and B-EA defined in each sub-pixel R-SP, G-SP, W-SP, and B-SP. The pixel contact holes may, for example, overlap the bank insulation layer 150. Consequently, in the display device according to the embodiment of the disclosure, the change in the location of the first electrode 310 within the emission region R-EA, G-EA, W-EA, and B-EA of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be reduced or minimized. A portion of the first electrode 310 that overlaps the emission region R-EA, G-EA, W-EA, and B-EA of each sub-pixel R-SP, G-SP, W-SP, and B-SP may, for example, be in direct contact with the top surface of the planarization layer 140.Therefore, in the display device according to the embodiment of the disclosure, the luminance deviation can be reduced or prevented according to the generation location of the light emitted from the emission region R-EA, G-EA, W-EA and B-EA of each sub-pixel R-SP, G-SP, W-SP and B-SP.

[0092] The light emitted by the light-emitting device 300R, 300G, 300W, and 300B of each sub-pixel R-SP, G-SP, W-SP, and B-SP may display a different color than the light emitted by the light-emitting device 300R, 300G, 300W, and 300B of an adjacent sub-pixel R-SP, G-SP, W-SP, and B-SP. The light-emitting layer 320 of the light-emitting device 300R, 300G, 300W, and 300B in each sub-pixel R-SP, G-SP, W-SP, and B-SP may be spaced apart from the light-emitting layer 320 of the light-emitting device 300R, 300G, 300W, and 300B in an adjacent sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the light-emitting layer 320 of the light-emitting device 300R, 300G, 300W, and 300B in each subpixel R-SP, G-SP, W-SP, and B-SP may contain different materials.The light-emitting layer 320 of the light-emitting device 300R, 300G, 300W, and 300B in each subpixel R-SP, G-SP, W-SP, and B-SP may have a stacked structure that is different from the light-emitting layer 320 of the light-emitting device 300R, 300G, 300W, and 300B in an adjacent subpixel R-SP, G-SP, W-SP, and B-SP. The light-emitting layer 320 of the light-emitting device 300R, 300G, 300W, and 300B in each subpixel R-SP, G-SP, W-SP, and B-SP may include one end disposed on the bank insulating layer 150.

[0093] A voltage applied to the second electrode 330 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be the same or substantially the same as a voltage applied to the second electrode 330 of an adjacent sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the second electrode 330 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be electrically connected to the second electrode 330 of an adjacent sub-pixel R-SP, G-SP, W-SP, and B-SP. The second electrode 330 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include the same or substantially the same material as the second electrode 330 of the adjacent sub-pixel R-SP, G-SP, W-SP, and B-SP. The second electrode 330 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be formed by the same or substantially the same process as the second electrode of an adjacent sub-pixel R-SP, G-SP, W-SP, and B-SP. The second electrode 330 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may, for example,simultaneously with the second electrode 330 of an adjacent sub-pixel R-SP, G-SP, W-SP, and B-SP. The second electrode 330 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be in direct contact with the second electrode 330 of an adjacent sub-pixel R-SP, G-SP, W-SP, and B-SP. Consequently, in the display device according to the embodiment of the disclosure, a process for forming the second electrode 330 in each sub-pixel R-SP, G-SP, W-SP, and B-SP can be simplified.

[0094] A color filter 400 may be disposed in a path of the light emitted by the light-emitting device 300R, 300G, 300W, and 300B in each sub-pixel R-SP, G-SP, W-SP, and B-SP. The color filter 400 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be disposed, for example, between the device passivation layer 130 and the planarization layer 140. A thickness difference due to the color filter 400 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be removed by the planarization layer 140. The light passing through the color filter 400 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may display the same or substantially the same color as the light generated by the light-emitting device 300R, 300G, 300W, and 300B of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP.Consequently, in the display device according to the embodiment of the disclosure, the color reproduction of the light emitted from each sub-pixel R-SP, G-SP, W-SP and B-SP can be improved.

[0095] A cover layer 160 may be disposed on the light-emitting device 300R, 300G, 300W, and 300B of each sub-pixel R-SP, G-SP, W-SP, and B-SP. The cover layer 160 may reduce or prevent damage to the light-emitting device 300R, 300G, 300W, and 300B in each sub-pixel R-SP, G-SP, W-SP, and B-SP. The light-emitting device 300R, 300G, 300W, and 300B of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be covered, for example, by the cover layer 160. The cover layer 160 may include an insulating material. The cover layer 160 may include, for example, an inorganic insulating material and / or an organic insulating material. The cap layer 160 may have a multi-layer structure. For example, the cap layer 160 may have a structure in which an inorganic insulating layer made of an inorganic insulating material and an organic insulating layer made of an organic insulating material are stacked.Consequently, in the display device according to the embodiment of the disclosure, the damage to the light-emitting device 300R, 300G, 300W, and 300B in each sub-pixel R-SP, G-SP, W-SP, and B-SP can be effectively reduced or prevented by the cap layer 160.

[0096] An encapsulation layer 500 and an encapsulation substrate 600 may be stacked on the cap layer 160. The encapsulation substrate 600 may include a different material than the device substrate 100. The encapsulation substrate 600 may include a material that has relatively high heat dissipation properties. For example, the encapsulation substrate 600 may include a metal such as aluminum (Al) and nickel (Ni).

[0097] The encapsulation layer 500 may contain an insulating material. The encapsulation layer 500 may contain an adhesive material. The encapsulation substrate 600 may, for example, be coupled to the device substrate 100, with the cover layer 160 covered by the encapsulation layer 500. The encapsulation layer 500 may block or retard the movement of external moisture. The encapsulation layer 500 may contain absorbent particles. The encapsulation layer 500 may have a multi-layer structure. The encapsulation layer 500 may, for example, include a lower encapsulation layer 510 and an upper encapsulation layer 520 disposed on the lower encapsulation layer 510. The lower encapsulation layer 510 may be disposed between the cover layer 160 and the upper encapsulation layer 520. The absorbent particles may be dispersed in the upper encapsulation layer 520.Consequently, in the display device according to the embodiment of the disclosure, the stress exerted in one direction of the device substrate 100 due to the expansion of the absorbing particles can be alleviated by the lower encapsulation layer 510. The upper encapsulation layer 520 may include a different material than the lower encapsulation layer 510. Therefore, in the display device according to the embodiment of the disclosure, damage to the light-emitting devices 300R, 300G, 300W, and 300B in each sub-pixel R-SP, G-SP, W-SP, and B-SP due to the intrusion of external moisture and external impact can be effectively reduced or prevented.

[0098] The subpixels R-SP, G-SP, W-SP, and B-SP of each pixel region PA may be arranged adjacent to each other in a first direction. The red subpixel R-SP, the green subpixel G-SP, the white subpixel W-SP, and the blue subpixel B-SP of each pixel region PA may, for example, be arranged adjacent to each other in the first direction X. The light-emitting device 300R, 300G, 300W, and 300B of each subpixel R-SP, G-SP, W-SP, and B-SP may be independently controlled. The gate lines GL1 and GL2 may, for example, include first gate lines GL1 extending in the first direction X and second gate lines GL2 extending parallel to the first gate lines GL1. The second gate lines GL2 may be arranged between the first gate lines GL1. The emission region R-EA, G-EA, W-EA and B-EA of each sub-pixel R-SP, G-SP, W-SP and B-SP may be arranged, for example, between one of the first gate lines GL1 and one of the second gate lines GL2.The data lines DL1 and DL2 may include first data lines DL1 extending in the second direction Y and second data lines DL2 extending parallel to the first data lines DL1. One of the first data lines DL1 and one of the second data lines DL2 may be arranged between the pixel regions PA. The power supply lines PL and the reference supply lines RL may extend in the second direction Y. Each of the data lines DL1 and DL2, the power supply lines PL, and the reference supply lines RL may cross, for example, the first gate lines GL1 and the second gate lines GL2.

[0099] Each of the sub-pixels R-SP, G-SP, W-SP, and B-SP in each pixel region PA may share the data lines DL1 and DL2 with one of the sub-pixels R-SP, G-SP, W-SP, and B-SP in an adjacent pixel region PA. For example, one of the first data lines DL1 and one of the second data lines DL2 may cross between the pixel regions PA, wherein a red driver circuit R-DC of the red sub-pixel R-SP in each pixel region PA may be electrically connected to the first data line DL1 located on one side of the corresponding pixel region PA, and a green driver circuit G-DC of the green sub-pixel G-SP in each pixel region PA may be electrically connected to the first data line DL1 located on an opposite side of the corresponding pixel region PA.A white driver circuit W-DC of the white sub-pixel W-SP in each pixel region PA may be electrically connected to the second data line DL2 located on one side of the corresponding pixel region PA, while a blue driver circuit B-DC of the blue sub-pixel B-SP in each pixel region PA may be electrically connected to the second data line DL2 located on an opposite side of the corresponding pixel region PA. That is, in the display device according to the embodiment of the disclosure, the red sub-pixel R-SP of each pixel region PA may share one of the first data lines DL1 with the green sub-pixel G-SP of an adjacent pixel region PA, while the white sub-pixel W-SP of each pixel region PA may share one of the second data lines DL2 with the blue sub-pixel B-SP of an adjacent pixel region PA.Consequently, in the display device according to the embodiment of the disclosure, the number of data lines DL1 and DL2 can be reduced. Therefore, in the display device according to the embodiment of the disclosure, an area of ​​each sub-pixel R-SP, G-SP, W-SP, and B-SP can be increased. For example, in the display device according to the embodiment of the disclosure, a size of the emission region R-EA, G-EA, W-EA, and B-EA defined in each sub-pixel R-SP, G-SP, W-SP, and B-SP can be increased.

[0100] Each of the sub-pixels R-SP, G-SP, W-SP, and B-SP may be electrically connected to the gate lines GL1 and GL2, unlike the sub-pixels R-SP, G-SP, W-SP, and B-SP that share the data lines DL1 and DL2 with the corresponding sub-pixels R-SP, G-SP, W-SP, and B-SP. For example, the red sub-pixel R-SP and the white sub-pixel W-SP of each pixel region PA may be electrically connected to one of the first gate lines GL1, while the green sub-pixel G-SP and the blue sub-pixel B-SP of each pixel region PA may be electrically connected to one of the second gate lines GL2. Consequently, in the display device according to the embodiment of the disclosure, the data signal can be applied to the sub-pixels R-SP, G-SP, W-SP, and B-SP of each pixel region PA simultaneously via the data lines DL1 and DL2.That is, in the display device according to the embodiment of the disclosure, the sub-pixels R-SP, G-SP, W-SP, and B-SP of each pixel region PA can be driven simultaneously. Therefore, in the display device according to the embodiment of the disclosure, the decrease in the driving speed due to the operation delay of each pixel region PA can be reduced or prevented.

[0101] The driver circuits R-DC, G-DC, W-DC, and B-DC and the emission region R-EA, G-EA, W-EA, and B-EA of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be arranged adjacent to each other in the second direction Y. The driver circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be arranged close to the corresponding gate line GL1 and GL2. For example, the red driver circuit R-DC and the white driver circuit W-DC of each pixel region PA may be arranged close to the corresponding first gate line GL1, while the green driver circuit G-DC and the blue driver circuit B-DC of each pixel region PA may be arranged close to the corresponding second gate line GL2.A red emission region R-EA defined in the red sub-pixel R-SP of each pixel region PA may be arranged between the red driving circuit R-DC of the corresponding pixel region PA and the corresponding second gate line GL2, while a white emission region W-EA defined in the white sub-pixel W-SP of each pixel region PA may be arranged between the white driving circuit W-DC of the corresponding pixel region PA and the corresponding second gate line GL2.A green emission region G-EA defined in the green sub-pixel G-SP of each pixel region PA may be arranged between the corresponding first gate line GL1 and the green driver circuit G-DC of the corresponding pixel region PA, while a blue emission region B-EA defined in the blue sub-pixel B-SP of each pixel region PA may be arranged between the corresponding first gate line GL1 and the blue driver circuit B-DC of the corresponding pixel region PA.

[0102] The sub-pixels R-SP, G-SP, W-SP, and B-SP electrically connected to the first gate lines GL1, and the sub-pixels R-SP, G-SP, W-SP, and B-SP electrically connected to the second gate lines GL2 may be alternately arranged in each pixel region PA. For example, the green sub-pixel G-SP of each pixel region PA may be arranged between the red sub-pixel R-SP and the white sub-pixel W-SP of the corresponding pixel region PA, while the white sub-pixel W-SP of each pixel region PA may be arranged between the green sub-pixel G-SP and the blue sub-pixel B-SP of the corresponding pixel region PA. Consequently, in the display device according to the embodiment of the disclosure, a space for the driving circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be sufficiently secured.Therefore, in the display device according to the embodiment of the disclosure, the reduction in the area of ​​the emission regions R-EA, G-EA, W-EA and B-EA defined in each pixel region PA due to the driving circuits R-DC, G-DC, W-DC and B-DC of the corresponding pixel region PA can be reduced or minimized.

[0103] The driver circuits R-DC, G-DC, W-DC, and B-DC of each pixel region PA can be arranged to be symmetrical to each other. For example, the green driver circuit G-DC of each pixel region PA can be arranged to be symmetrical to the red driver circuit R-DC of the corresponding pixel region PA with respect to the first direction X, while the white driver circuit W-DC of each pixel region PA can be arranged to be symmetrical to the blue driver circuit B-DC of the corresponding pixel region PA with respect to the first direction X.Consequently, in the display device according to the embodiment of the disclosure, the coupling capacitance of the green sub-pixel G-SP in each pixel region PA may be substantially the same as the coupling capacitance of the red sub-pixel R-SP in the corresponding pixel region PA, while the coupling capacitance of the blue sub-pixel B-SP in each pixel region PA may be substantially the same as the coupling capacitance of the white sub-pixel W-SP in the corresponding pixel region PA. The white driving circuit W-DC of each pixel region PA may be arranged to be symmetrical to the red driving circuit R-DC of the corresponding pixel region PA with respect to the second direction Y, while the blue driving circuit B-DC of each pixel region PA may be arranged to be symmetrical to the green driving circuit G-DC of the corresponding pixel region PA with respect to the second direction Y.That is, in the display device according to the embodiment of the disclosure, the coupling capacitance of the white sub-pixel W-SP in each pixel region PA may be substantially the same as the coupling capacitance of the red sub-pixel R-SP in the corresponding pixel region PA, while the coupling capacitance of the blue sub-pixel B-SP in each pixel region PA may be substantially the same as the coupling capacitance of the green sub-pixel G-SP in the corresponding pixel region PA. Therefore, in the display device according to the embodiment of the disclosure, the deviation in the luminance of the light emitted by each sub-pixel R-SP, G-SP, W-SP, and B-SP due to the difference in the coupling capacitance can be reduced or prevented.

[0104] The second thin-film transistor TR2 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be arranged remotely from the emission region R-EA, G-EA, W-EA, and B-EA of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the first gate lines GL1 and the second gate lines GL2 may be arranged between the emission region R-EA, G-EA, W-EA, and B-EA and the second thin-film transistor TR2 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. Consequently, in the display device according to the embodiment of the disclosure, the coupling capacitance of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be reduced or minimized.

[0105] The first semiconductor pattern 211 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may have a shape extending in the second direction Y. The first semiconductor pattern 211 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may, for example, cross one of the first gate lines GL1 and the second gate lines GL2. The first gate lines GL1 and the second gate lines GL2 may be arranged on the same layer as the first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. The first gate lines GL1 and the second gate lines GL2 may, for example, be arranged between the gate insulating layer 120 and the device passivation layer 130. The first gate lines GL1 and the second gate lines GL2 may include the same or substantially the same material as the first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP and B-SP.The first gate lines GL1 and the second gate lines GL2 may be formed by the same or substantially the same process as the first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. The first gate lines GL1 and the second gate lines GL2 may, for example, be formed simultaneously with the first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. The first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be in direct contact with one of the first gate lines GL1 and the second gate lines GL2. The first gate electrode 213 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may, for example, be a portion of the corresponding gate line GL1 and GL2. Consequently, in the display device according to the embodiment of the disclosure, a process for forming the first gate electrode 213 in each sub-pixel R-SP, G-SP, W-SP, and B-SP can be simplified.

[0106] The second gate electrode 223 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be arranged parallel to the first gate lines GL1 and the second gate lines GL2. The second semiconductor pattern 221 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may have a shape extending in the second direction Y. For example, the second semiconductor pattern 221 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be arranged parallel to the data lines DL1 and DL2. The power connection lines 250 extending in the first direction X may be electrically connected to at least one of the power voltage supply lines PL, wherein the second semiconductor pattern 221 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be electrically connected to one of the power connection lines 250.Consequently, in the display device according to the embodiment of the disclosure, the configuration of the driving circuits R-DC, G-DC, W-DC, and B-DC in each sub-pixel R-SP, G-SP, W-SP, and B-SP can be simplified. That is, in the display device according to the embodiment of the disclosure, an area occupied by the driving circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be reduced or minimized. Therefore, in the display device according to the embodiment of the disclosure, a size of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be reduced. And in the display device according to the embodiment of the disclosure, an area of ​​the emission region R-EA, G-EA, W-EA, and B-EA defined in each sub-pixel R-SP, G-SP, W-SP, and B-SP can be enlarged or maximized.

[0107] The power connection lines 250 may be arranged on a different layer than the power voltage supply lines PL. The power connection lines 250 may be arranged on the same layer as the source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. The power connection lines 250 may be arranged, for example, between the gate insulating layer 120 and the device passivation layer 130. The power connection lines 250 may contain the same or substantially the same material as the source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. The power connection lines 250 may be formed by the same or substantially the same process as the source connection electrode 240 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. The power connection lines 250 may, for example,simultaneously with the source connection electrode 240 of each R-SP, G-SP, W-SP, and B-SP subpixel. Consequently, in the display device according to the embodiment of the disclosure, the decrease in process efficiency due to the formation of the power connection lines 250 can be reduced or prevented.

[0108] The power supply lines PL may be arranged closer to the device substrate 100 than the power connection lines 250. The power supply lines PL may, for example, be arranged on the same layer as the light-emitting pattern 105 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. The power supply lines PL may contain the same or substantially the same material as the light-emitting pattern 105 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. The power supply lines PL may be formed by the same or substantially the same process as the light-emitting pattern 105 of each sub-pixel R-SP, G-SP, W-SP, and B-SP. The power supply lines PL may, for example, be formed simultaneously with the light-emitting pattern 105 of each sub-pixel R-SP, G-SP, W-SP, and B-SP.Consequently, in the display device according to the embodiment of the disclosure, a process for forming the power voltage supply lines PL can be simplified.

[0109] The data lines DL1 and DL2 may be arranged on the same layer as the power voltage supply lines PL. The data lines DL1 and DL2 may be arranged, for example, between the device substrate 100 and the buffer insulation layer 110. The data lines DL1 and DL2 may include the same or substantially the same material as the power voltage supply lines PL. The data lines DL1 and DL2 may be formed by the same or substantially the same process as the power voltage supply lines PL. For example, the data lines DL1 and DL2 may be formed simultaneously with the power voltage supply lines PL. Consequently, in the display device according to the embodiment of the disclosure, a process for forming the data lines DL1 and DL2 can be simplified.

[0110] The third thin-film transistor TR3 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be spaced apart from the first thin-film transistor TR1 and the second thin-film transistor TR2 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. The third semiconductor pattern 231 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may have a shape extending in a different direction than the first semiconductor pattern 211 and the second semiconductor pattern 221 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the third semiconductor pattern 231 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may have a shape extending in the first direction X. The third semiconductor pattern 231 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be arranged parallel to the first gate lines GL1 and the second gate lines GL2. The third gate electrode 233 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may extend in the second direction Y.The third gate electrode 233 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may extend in a direction perpendicular to the first gate lines GL1 and the second gate lines GL2. The third gate electrode 233 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may, for example, have a shape that protrudes from one of the first gate lines GL1 and the second gate lines GL2. Therefore, in the display device according to the embodiment of the disclosure, a width of each first gate line GL1 and a width of each second gate line GL2 can be increased. For example, in the display device according to the embodiment of the disclosure, a resistance of each first gate line GL1 and a resistance of each second gate line GL2 can be reduced. Therefore, in the display device according to the embodiment of the disclosure, the delay of the signal applied through the first gate lines GL1 and the second gate lines GL2 can be reduced or prevented.

[0111] The reference voltage supply lines RL may be arranged parallel to the power voltage supply lines PL. The reference voltage supply lines RL may extend, for example, in the second direction Y. Each of the reference voltage supply lines RL may cross one of the pixel regions PA. The red sub-pixel R-SP and the green sub-pixel G-SP of each pixel region PA may be arranged, for example, between one of the second data lines DL2 and one of the reference voltage supply lines RL, while the white sub-pixel W-SP and the blue sub-pixel B-SP of each pixel region PA may be arranged between one of the reference voltage supply lines RL and one of the first data lines DL1.Consequently, in the display device according to the embodiment of the disclosure, a process of connecting the third drain region of the third thin film transistor TR3 in each sub-pixel R-SP, G-SP, W-SP, and B-SP to the corresponding reference voltage supply line RL can be simplified.

[0112] The reference voltage supply lines RL may be arranged on the same layer as the power voltage supply lines PL. The reference voltage supply lines RL may be arranged, for example, between the device substrate 100 and the buffer insulation layer 110. The reference voltage supply lines RL may include the same or substantially the same material as the power voltage supply lines PL. The reference voltage supply lines RL may be formed by the same or substantially the same process as the power voltage supply lines PL. For example, the reference voltage supply lines RL may be formed simultaneously with the power voltage supply lines PL. Consequently, in the display device according to the embodiment of the disclosure, a process for forming the reference voltage supply lines RL can be simplified.

[0113] The third drain region of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be electrically connected to the corresponding reference voltage supply line RL via one of the reference connection lines 260 extending in the first direction X. Each of the reference connection lines 260 may, for example, be electrically connected to one of the reference voltage supply lines RL. The reference connection lines 260 may be arranged on a different layer than the reference voltage supply lines RL. The reference connection lines 260 may be arranged on the same layer as the power connection lines 250. The reference connection lines 260 may, for example, be arranged between the gate insulation layer 120 and the device passivation layer 130. The reference connection lines 260 may include the same or substantially the same material as the power connection lines 250.The reference connection lines 260 may be formed by the same or substantially the same process as the power connection lines 250. For example, the reference connection lines 260 may be formed simultaneously with the power connection lines 250. Consequently, in the display device according to the embodiment of the present disclosure, the deterioration of process efficiency due to the formation of the reference connection lines 260 may be reduced or prevented.

[0114] Accordingly, the display device according to the embodiment of the disclosure may include the pixel regions PA arranged between the gate lines GL1 and GL2, the data lines DL1 and DL2, and the power voltage supply lines PL, wherein each of the pixel regions PA may include the sub-pixels R-SP, G-SP, W-SP, and B-SP arranged adjacent to each other along the gate lines GL1 and GL2, wherein the sub-pixels R-SP and W-SP of each pixel region PA, which are electrically connected to the first gate lines GL1 of the gate lines GL1 and GL2, may share the data lines DL1 and DL2 with the sub-pixels G-SP and B-SP of an adjacent pixel region PA, which are electrically connected to the second gate lines GL2 of the gate lines GL1 and GL2, and wherein the driving circuit R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP has an arrangement which can be connected to the driver circuit R-DC, G-DC,W-DC and B-DC of the sub-pixels R-SP, G-SP, W-SP, and B-SP adjacent in the first direction X or the second direction Y are symmetrical. Consequently, in the display device according to the embodiment of the disclosure, the sub-pixels R-SP, G-SP, W-SP, and B-SP of each pixel region PA can have substantially the same coupling capacitance. Therefore, in the display device according to the embodiment of the disclosure, the deterioration of the quality of the image due to the deviation in the luminance of the light emitted by each sub-pixel R-SP, G-SP, W-SP, and B-SP can be reduced or prevented.

[0115] And in the display device according to the embodiment of the disclosure, the coupling capacitance of each sub-pixel R-SP, G-SP, W-SP, and B-SP can be substantially the same without degrading the process efficiency. Consequently, in the display device according to the embodiment of the disclosure, production energy can be reduced through process optimization.

[0116] The display device according to the embodiment of the disclosure is described such that the driving circuit R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP may consist of the first thin-film transistor TR1, the second thin-film transistor TR2, the third thin-film transistor TR3, and the storage capacitor Cst. However, in the display device according to another embodiment of the disclosure, the driving circuit R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a driving thin-film transistor and at least one switching thin-film transistor. In the display device according to another embodiment of the disclosure, for example,The driver circuits R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP consist only of the first thin-film transistor TR1 functioning as a switching thin-film transistor, the second thin-film transistor TR2 functioning as a driver thin-film transistor, and the storage capacitor Cst. Consequently, in the display device according to another embodiment of the disclosure, the degree of freedom in configuring the driver circuits R-DC, G-DC, W-DC, and B-DC in each sub-pixel R-SP, G-SP, W-SP, and B-SP can be improved.

[0117] In the display device according to the embodiment of the disclosure, the location and electrical connection of the first drain region, the first source region, the second drain region 221d, the second source region 221s, the third drain region, and the third source region in each driver circuit R-DC, G-DC, W-DC, and B-DC may vary depending on the configuration of the corresponding driver circuit R-DC, G-DC, W-DC, and B-DC and / or the type of the corresponding thin-film transistors TR1, TR2, and TR3. For example, in the display device according to another embodiment of the disclosure, the second gate electrode 223 of each driver circuit R-DC, G-DC, W-DC, and B-DC may be electrically connected to the first drain region of the corresponding driver circuit R-DC, G-DC, W-DC, and B-DC.Consequently, in the display device according to another embodiment of the disclosure, the degree of freedom in the configuration of each drive circuit R-DC, G-DC, W-DC and B-DC and the type of each thin film transistor TR1, TR2 and TR3 can be improved.

[0118] The display device according to the embodiment of the disclosure is described such that the first drain region, the first source region, the second drain region 221d, the second source region 221s, the third drain region, and the third source region of each pixel region PA can be used as one wiring. However, in the display device according to another embodiment of the disclosure, the first thin-film transistor TR1, the second thin-film transistor TR2, and the third thin-film transistor TR3 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may have different structures. For example, in the display device according to the embodiment of the disclosure, the driving circuit R-DC, G-DC, W-DC, and B-DC of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a second drain electrode electrically connected to the second drain region 221d and a second source electrode electrically connected to the second source region 221s.The second drain electrode and the second source electrode of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be disposed on a different layer than the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP. For example, the second drain electrode and the second source electrode of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be disposed between an interlayer insulating film covering the second gate electrode 223 of the corresponding sub-pixel R-SP, G-SP, W-SP, and B-SP and the device passivation layer 130. Consequently, in the display device according to another embodiment of the disclosure, the degree of freedom for configuring the drive circuit R-DC, G-DC, W-DC, and B-DC in each sub-pixel R-SP, G-SP, W-SP, and B-SP can be improved.

[0119] The display device according to the embodiment of the disclosure is described such that each of the reference voltage supply lines RL may be a signal wiring. However, in the display device according to another embodiment of the disclosure, each of the reference voltage supply lines RL may be formed of multiple wirings. For example, in the display device according to another embodiment of the disclosure, each of the reference voltage supply lines RL may include a main wiring R1, an auxiliary wiring R2, and a connection wiring Rc, as shown in FIGS. Fig. 7 and Fig.8. The auxiliary wiring R2 may extend parallel to the main wiring R1. The auxiliary wiring R2 may be spaced from the main wiring R1. The connecting wiring Rc may be arranged between the main wiring R1 and the auxiliary wiring R2. The connecting wiring Rc may be in direct contact with a portion of the main wiring R1 and a portion of the auxiliary wiring R2. The auxiliary wiring R2 may be in direct contact with the main wiring R1, for example, through the connecting wiring Rc. The auxiliary wiring R2 and the connecting wiring Rc may contain the same or substantially the same material as the main wiring R1. The auxiliary wiring R2 and the connecting wiring Rc may be arranged, for example, on the same layer as the main wiring R1.The auxiliary wiring R2 and the connecting wiring Rc can be formed by the same or substantially the same process as the main wiring R1. For example, the auxiliary wiring R2 and the connecting wiring Rc can be formed simultaneously with the main wiring R1.

[0120] The third drain region of each sub-pixel R-SP, G-SP, W-SP, and B-SP may be electrically connected to the main wiring R1 of the corresponding reference voltage supply line RL. The first electrode 310 of each sub-pixel R-SP, G-SP, W-SP, and B-SP may include a portion that intersects with the auxiliary wiring R2 of the corresponding reference voltage supply line RL. The auxiliary wiring R2 of each reference voltage supply line RL may be used, for example, in a repair process. The repair process may include a process for disconnecting the auxiliary wiring R2 and the connecting wiring Rc of some of the reference voltage supply lines RL. The red driver circuit R-DC of each pixel region PA may, for example,be electrically connected to the red light-emitting device 300R arranged in the red sub-pixel R-SP of an adjacent pixel region PA via the auxiliary wiring R2 of the corresponding reference voltage supply line RL, which is disconnected by the repair process. Consequently, in the display device according to another embodiment of the disclosure, the repair process can be simplified. Therefore, in the display device according to another embodiment of the disclosure, production energy can be effectively reduced through process optimization.

[0121] As a result, the display device according to the embodiments of the disclosure may include the pixel regions arranged between the first gate line and the second gate line, wherein each of the pixel regions may include the first sub-pixel and the second sub-pixel, wherein the data line overlapping the first gate line and the second gate line may cross the second sub-pixel of each pixel region and the first sub-pixel of an adjacent pixel region, and wherein the second driving circuit of the second sub-pixel arranged close to the second gate line may have an arrangement symmetrical to the first driving circuit of the first sub-pixel arranged close to the first gate line.Consequently, in the display device according to the embodiments of the disclosure, the difference between the coupling capacitance of the first sub-pixel in each pixel region and the coupling capacitance of the second sub-pixel in each pixel region can be reduced. Therefore, in the display device according to the embodiments of the disclosure, the light emitted by the second sub-pixel of each pixel region can have substantially the same luminance as the light emitted by the first sub-pixel of each pixel region. That is, in the display device according to the embodiments of the disclosure, the deterioration of image quality due to the difference in luminance between the first sub-pixel and the second sub-pixel of each pixel region can be reduced or prevented. Furthermore, in the display device according to the embodiments of the disclosure, production energy can be reduced through process optimization.

[0122] The various embodiments described above may be combined to create further embodiments. Aspects of the embodiments may be modified, if necessary, to utilize concepts from the various patents, applications, and publications to create still further embodiments. These and other changes may be made to the embodiments in light of the detailed description described above. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the application text and claims, but should be construed to include all possible embodiments, along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] KR 10-2024-0028797

[0001]

Claims

[1] Display device comprising: a first gate line (GL12) extending in a first direction (X); a first data line (DL1) extending in a second direction (Y), the first data line (DL1) crossing the first gate line (GL1); a second gate line (GL2) extending parallel to the first gate line (GL1) and crossing the first data line (DL1); a first sub-pixel (R-SP) including a first driver circuit (R-DC), the first driver circuit (R-DC) being electrically connected to the first gate line (GL1) and the first data line (DL1); and a second sub-pixel (G-SP) including a second driver circuit (G-DC), the second driver circuit (G-DC) being electrically connected to the first data line (DL1) and the second gate line (GL2), wherein the first data line (DL1) crosses between the first sub-pixel (R-SP) and the second sub-pixel (G-SP), wherein a second emission region (G-EA) of the second sub-pixel (G-SP) arranged between the first gate line (GL1) and the second driver circuit (G-DC) displays a different color than a first emission region (R-EA) of the first sub-pixel (R-SP) arranged between the first driver circuit (R-DC) and the second gate line (GL2), and wherein the second driver circuit (G-DC) has a symmetrical arrangement with the first driver circuit (R-DC). [2] A display device according to claim 1, wherein the second emission region (G-EA) is arranged in the first direction (X) at the first emission region (R-EA). [3] A display device according to claim 1 or 2, wherein each of the first driving circuit (R-DC) and the second driving circuit (G-DC) includes a driving thin film transistor (TR2), and wherein a gate electrode (223) of the driving thin film transistor (TR2) is arranged in parallel to the first and second gate lines (GL1, 2). [4] A display device according to claim 3, wherein a semiconductor pattern (221) of the driver thin film transistor (TR2) is arranged in parallel to the first data line (DL1). [5] Display device according to one of the preceding claims, further comprising: a second data line (DL2) arranged in parallel to the first data line (DL1); a third sub-pixel (W-SP) including a third driver circuit (W-DC), the third driver circuit (W-DC) being electrically connected to the first gate line (GL1) and the second data line (DL2); and a fourth sub-pixel (B-SP) including a fourth driver circuit (B-DC), the fourth driver circuit (B-DC) being electrically connected to the second data line (DL2) and the second gate line (GL2), wherein the first sub-pixel (R-SP) is preferably arranged between the second data line (DL2) and the third sub-pixel (W-SP) and / or the fourth sub-pixel (B-SP) is arranged between the second sub-pixel (G-SP) and the first data line (DL1). [6] The display device according to claim 5, wherein the fourth driver circuit (B-DC) arranged in a first direction (X) at the second driver circuit (G-DC) has a symmetrical arrangement with the third driver circuit (W-DC) arranged in the first direction (X) at the first driver circuit (R-DC), and / or the third driver circuit (W-DC) has a symmetrical arrangement with the first driver circuit (R-DC) and the fourth driver circuit (B-DC) has a symmetrical arrangement with the second driver circuit (G-DC). [7] The display device according to claim 5 or 6, wherein a third emission region (W-EA) of the third sub-pixel (W-SP) arranged between the third driver circuit (W-DC) and the second gate line (GL2) displays a different color than the first emission region (R-EA) and the second emission region (G-EA), and / or wherein a fourth emission region (B-EA) of the fourth sub-pixel (B-SP) arranged between the first gate line (GL1) and the fourth driver circuit (B-DC) displays a different color than the first emission region (R-EA), the second emission region (G-EA) and the third emission region (W-EA). [8] A display device according to claim 7, further comprising reference voltage supply lines (RL) arranged in parallel with the first and second data lines (DL1, DL2), wherein the first sub-pixel (R-SP) and the third sub-pixel (W-SP) are arranged between one of the reference voltage supply lines (RL) and the second data line (DL2), and wherein the second sub-pixel (G-SP) and the fourth sub-pixel (B-SP) are arranged between one of the reference voltage supply lines (RL) and the first data line (DL1). [9] Display device comprising: first data lines (DL1) crossing a first gate line (GL1); second data lines (DL2) arranged between the first data lines (DL1), the second data lines (DL2) crossing the first gate line (GL1); a second gate line (GL2) extending parallel to the first gate line (GL1), the second gate line (GL2) crossing the first and second data lines (DL1, DL2); and Pixel regions arranged between the first and second data lines (DL1, DL2), each of the pixel regions including a first sub-pixel (R-SP) and a second sub-pixel (G-SP) arranged along the first gate line (GL1) and the second gate line (GL2), wherein a first emission region (R-EA) of the first sub-pixel (R-SP) is arranged between a first driver circuit (R-DC) of the first sub-pixel (R-SP) and the second gate line (GL2), wherein a second emission region (G-EA) of the second sub-pixel (G-SP) is arranged between the first gate line (GL1) and a second driver circuit (G-DC) of the second sub-pixel (G-SP), and wherein the second driver circuit (G-DC), which is electrically connected to one of the second data lines (DL2) and the second gate line (GL2), has a symmetrical arrangement with the first driver circuit (R-DC), which is electrically connected to one of the first data lines (DL1) and the first gate line (GL1). [10] A display device according to claim 9, wherein the second sub-pixel (G-SP) of each pixel area (PA) displays a different color than the first sub-pixel (R-SP) of the corresponding pixel area (PA), wherein the first sub-pixel (R-SP) of each pixel area (PA) displays a same color as the first sub-pixel (R-SP) of an adjacent pixel area (PA), and wherein the second sub-pixel (G-SP) of each pixel area (PA) displays a same color as the second sub-pixel (G-SP) of an adjacent pixel area (PA). [11] A display device according to claim 9 or 10, wherein each of the first sub-pixel (R-SP) and the second sub-pixel (G-SP) in each pixel region (PA) includes a first switching thin-film transistor (TR1) and a second switching thin-film transistor (TR2), and wherein a semiconductor pattern (221) of the first switching thin-film transistor (TR1) crosses the first or second gate line (GL1, GL2), the first emission region (R-EA) and the second emission region (G-EA) of each pixel region (PA) are preferably arranged between the first and the second gate line (GL1, GL2). [12] A display device according to claim 11, wherein a gate electrode (223) of the second switching thin film transistor (TR1) has a shape protruding from the first or second gate line (GL1, GL2), a semiconductor pattern (221) of the second switching thin film transistor (TR1) is preferably arranged in parallel to the first and second gate lines (GL1, GL2). [13] A display device according to any one of claims 9, 10, 11 or 12, further comprising reference voltage supply lines (RL) arranged between the first and second data lines (DL1, DL2), the reference voltage supply lines (RL) crossing the first and second gate lines (GL1, GL2), each of the reference voltage supply lines (RL) crossing between the first sub-pixel (R-SP) and the second sub-pixel (G-SP) in one of the pixel regions (PA). [14] A display device according to claim 13, wherein each of the reference voltage supply lines (RL) includes a main wiring (R1), an auxiliary wiring (R2) arranged in parallel with the main wiring (R1), and a connecting wiring (Rc) arranged between the main wiring (R1) and the auxiliary wiring (R2), wherein the auxiliary wiring (R2) is electrically connected to the main wiring (R1) via the connecting wiring (Rc), wherein each of the first sub-pixel (R-SP) and the second sub-pixel (G-SP) includes a light-emitting device (300R, 300G) overlapping the corresponding emission region (R-EA, G-EA), and wherein a first electrode (310) of each light-emitting device (300) includes a portion overlapping the auxiliary wiring (R2).

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