Circuit arrangement with dead-time control to reduce power losses

Abstract

Circuit arrangement (SA) and method with dead-time control for reducing power losses, wherein the circuit arrangement comprises a half-bridge circuit (HB) with a first switch (S1) and a second switch (S2) interconnected at a switching node (SK); and a detection unit (DE) designed to detect the duration of a reverse current flowing through one of the two switches (S1; S2) of the half-bridge circuit (HB) for dead-time control.

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