Embedded contact for SPAD applications

Abstract

Systems, devices, and methods for locating a contact for a single-photon avalanche diode (SPAD) in an isolation trench structure of a SPAD-based imager are described. These systems, devices, and methods can include a front-side isolation trench structure positioned between adjacent SPAD pixels. The trench is lined with a continuous passivation layer that has an opening allowing a conductive material filling the trench to contact the substrate and form a buried contact for one or more adjacent SPADs. The trench can include a stepped trench with the opening in the passivation layer located near the stepped area. Alternatively, the trench can include an opening in the passivation layer facing the bottom of the front-side trench. Finally, the trench can include a back-side trench lined with a high-κ dielectric.The back trench can be continuous or segmented and / or overlapping. Buried SPAD contacts, as described here, can enable a reduction in pixel size.

Description

BACKGROUND

[0001] This application relates generally to devices based on single-photon avalanche diodes (SPADs) and in particular to image sensors that use an array of SPAD pixels to detect photons.

[0002] Image sensors (also called image transmitters) can be formed from a two-dimensional array of light-sensitive pixels. Each pixel typically includes a light-sensitive element that receives incident photons and converts them into electrical signals. The light-sensitive element can be a photodiode.

[0003] SPAD-based imagers can use SPADs configured to detect single photons. A photon striking a SPAD device can trigger an avalanche stream, which can be detected by the corresponding switching logic of the SPAD-based imager. During an avalanche, a SPAD pixel can generate photons that travel to neighboring SPAD pixels and trigger an avalanche at one or more of them. These additional avalanche streams are the result of crosstalk and are undesirable. To prevent crosstalk and / or other undesirable behavior, isolation structures can be placed between SPAD pixels.

[0004] SPAD pixels continue to shrink, forcing the cathode and anode of the SPAD device closer together. SPAD devices operate under a high reverse voltage between their cathodes and anodes. With small pixels, the electric field between the anode and cathode becomes large, causing unwanted edge breakdown in the avalanche region of the SPAD.

[0005] It would therefore be desirable to provide improved devices and methods for forming SPAD pixels. BRIEF DESCRIPTION OF THE DRAWING FIGURES Fig. Figure 1 is a circuit diagram showing an exemplary SPAD device according to one embodiment. Fig. Figure 2 is a cross-sectional side view of an exemplary back-illuminated (BSI) SPAD-based semiconductor device. Fig. Figures 3A to E are cross-sectional views at various stages of manufacture of an exemplary SPAD-based semiconductor device with an isolation trench structure comprising a conductive material arranged between annular trenches and electrically coupled to the substrate at the bottom of the trench structure, according to one embodiment. Fig. Figures 4A to E are cross-sectional views at various stages of manufacture of an exemplary SPAD-based semiconductor device with an isolation trench structure comprising a front trench and a back trench, according to one embodiment. Fig. Figure 5A is a top view of an exemplary SPAD-based semiconductor device showing the relative horizontal arrangement of the components of an isolation trench structure having a front trench and a segmented back trench according to one embodiment. Fig. Figures 5B to C are cross-sectional views at various locations in the SPAD-based semiconductor device of Fig. 5A in accordance with an embodiment. Fig. Figures 6A to E are cross-sectional views at various stages of manufacture of an exemplary SPAD-based semiconductor device having a first stepped insulation trench structure enclosing a conductive material which contacts the substrate through an opening in a passivation layer in the stepped area, in accordance with one embodiment. Fig. Figures 7A to E are cross-sectional views at various stages of manufacture of an exemplary SPAD-based semiconductor device having a second stepped insulation trench structure enclosing a conductive material which contacts the substrate through an opening in a passivation layer in the stepped area, in accordance with one embodiment. Fig. Figures 8A to E are cross-sectional views at various stages of manufacture of an exemplary SPAD-based semiconductor device having a third stepped insulation trench structure enclosing a conductive material which contacts the substrate through an opening in a passivation layer in the stepped area, in accordance with one embodiment. Fig. Figures 9A to E are cross-sectional views at various stages of manufacture of an exemplary SPAD-based semiconductor device having a fourth stepped insulation trench structure enclosing a conductive material which contacts the substrate through an opening in a passivation layer in the stepped area, in accordance with one embodiment. Fig. Figure 10A is a top view showing the relative horizontal arrangement of the components of an exemplary SPAD-based semiconductor device, which has the third stepped isolation trench structure located substantially at the corners of the SPAD pixels, in accordance with one embodiment. Fig. Figures 10B to D are cross-sectional views at various locations in the SPAD-based semiconductor device of Fig. 10A in accordance with an embodiment. Fig. Figure 11A is a top view showing the relative horizontal arrangement of the components of an exemplary SPAD-based semiconductor device with an isolation trench structure having a front trench and a segmented back trench and contact with the substrate substantially at the corners of the SPAD pixels, in accordance with an embodiment. Fig. Figures 11B to C are cross-sectional views at various locations in the SPAD-based semiconductor device of Fig. 11A in accordance with an embodiment. Fig. Figure 12A is a top view showing the relative horizontal arrangement of the components of an exemplary SPAD-based semiconductor device with a further isolation trench structure having a front trench and a segmented back trench and contact with the substrate substantially at the corners of the SPAD pixels, in accordance with an embodiment. Fig. Figures 12B to C are cross-sectional views at various locations in the SPAD-based semiconductor device of Fig. 12A in accordance with an embodiment. Fig. Figures 13A to D are cross-sectional views at various stages of manufacture of an exemplary SPAD-based semiconductor device having an insulation trench structure enclosing a conductive material which contacts the substrate through an opening in a passivation layer close to the front of the substrate, in accordance with one embodiment. Fig. Figures 14A to D are cross-sectional views at various stages of manufacture of an exemplary SPAD-based semiconductor device, which has an insulation trench structure partially filled with a passivation layer and enclosing a conductive material that contacts the substrate near the front of the substrate, in accordance with one embodiment. Fig. Figures 15A to E are cross-sectional views at various stages of fabrication of an exemplary SPAD-based semiconductor device comprising an insulation trench structure filled with a first conductive material and a second conductive material contacting the substrate at an opening in a passivation layer near the front of the substrate, in accordance with one embodiment. Fig. Figures 16A to D illustrate exemplary geometric arrangements of representative isolation trench structures in accordance with one embodiment. SUMMARY

[0006] Various embodiments relate to systems, devices and methods for trench insulation structures that have a buried contact for one or more SPAD pixels.

[0007] In various embodiments, a semiconductor device can include a substrate having a front and a back, a first single-photon avalanche diode (SPAD) in the substrate having a first contact near the front of the substrate, wherein the first contact is either a cathode or an anode of the SPAD, a second SPAD in the substrate arranged adjacent to the first SPAD, and a trench insulation structure in the substrate arranged between the first and the second SPAD, comprising: a front-side trench, a continuous passivation layer lining the front-side trench, the passivation layer including an opening on a horizontal surface of the front-side trench, and a conductive material arranged within the front-side trench and laterally separated from the substrate by the passivation layer.wherein: the conductive material is electrically coupled to the substrate through the opening in the passivation layer to form a second contact, and wherein the second contact is either the cathode or the anode of the SPAD.

[0008] In various embodiments, a semiconductor device can include a substrate having a first surface and a second surface, wherein the first surface is either the front or the back of the substrate and the second surface is the other of the front or back of the substrate. The semiconductor device can include a first single-photon avalanche diode (SPAD) in the substrate and a first contact near the first surface of the substrate, wherein the first contact is either a cathode or an anode of the SPAD, as well as a second SPAD in the substrate located adjacent to the first SPAD. The semiconductor device can include a trench insulation structure in the substrate arranged between the first and second SPADs, comprising: a trench, including a wide trench located near the first surface of the substrate, and a narrow trench.extending through a bottom surface of the wide trench towards the second surface of the substrate, the trench comprising a transition region between the wide trench and the narrow trench, a continuous passivation layer lining the wide trench and the narrow trench, the passivation layer enclosing an opening in the transition region, and a conductive material arranged within the trench and laterally separated from the substrate by the passivation layer, wherein: the conductive material is electrically coupled to the substrate through the opening in the passivation layer to form a second contact, and wherein the second contact is either the cathode or the anode of the SPAD.

[0009] In various embodiments, a method for forming a trench isolation structure between a first single-photon avalanche diode (SPAD) and a second SPAD in a substrate, wherein the substrate has a front and a back side and the first SPAD has a first electrical contact near the front side of the substrate, includes etching a front-side trench between the first SPAD and the second SPAD, forming a continuous passivation layer in the front-side trench, opening the continuous passivation layer at a horizontal surface of the front-side trench, and forming a conductive material in the front-side trench, wherein the conductive material is electrically coupled to the substrate through the opening of the passivation layer to form a second electrical contact.

[0010] These and other examples are described in more detail below. DETAILED DESCRIPTION

[0011] The following detailed description is intended to provide several examples illustrating the broader concepts set forth herein, but it is not intended to limit the invention or its application and use. Furthermore, there is no intention to be bound by the theory set forth in the preceding background or in the detailed description that follows.

[0012] According to various embodiments, trench isolation structures can be located between adjacent pixels of an imaging device. The trench isolation structures can enclose a buried contact, whether anode or cathode, for the photodetector diode of one or more adjacent pixels. The buried contact can be referred to as an embedded contact. In some embodiments, the other anode or cathode can be located close to or at the front of the substrate and substantially centered within the pixel. In some embodiments, the photodetector diode can be a SPAD.

[0013] Some embodiments may include a stepped insulation trench, which provides contact in the stepped area. Some embodiments may include a front trench and a back trench, and the back trench may be segmented and / or self-overlapping. Some embodiments may include a trench lined with a continuous passivation layer, wherein an opening in the continuous passivation layer allows a conductive material filling the trench to come into contact with the substrate to form the buried contact.

[0014] Advantageously, devices and methods according to this description feature an increased distance between the anode and the cathode of the SPADs of each pixel, resulting in a reduced risk of edge penetration of the avalanche area of ​​the respective SPADs. Devices and methods according to this description enable a smaller pixel pitch and smaller critical dimensions, thereby improving image sensor resolution and light detection performance while simultaneously isolating neighboring pixels and preventing crosstalk and other undesirable behaviors.

[0015] Fig. Figure 1 illustrates an exemplary SPAD-based imager 100, which is also referred to herein as the SPAD imager 100. SPAD imagers 100 can be used in any number of exemplary systems. The SPAD imager 100 can be a sensor device comprising one or more single-photon avalanche diode devices (SPAD devices) 102 for detecting an incident photon. In some embodiments, the SPAD imager 100 can be a silicon photomultiplier device (SiPM device) comprising a plurality of SPAD devices 102. A SPAD 104 can include a semiconductor diode and can be configured to receive incident photons. In some embodiments, the SPAD-based imager 100 can include one or more microlenses to further direct the light into one or more SPADs 104 of the SPAD-based imager 100.

[0016] In some embodiments, a system using a SPAD imager 100 may include a LiDAR imaging system. The LiDAR imaging system may be an enveloping LiDAR system, for example, for navigation, obstacle avoidance, distance measurement, or other safety functions. The LiDAR system may also be, additionally or alternatively, a surveillance system, a machine vision system, a surveying system, a rangefinder system, or any other suitable system.

[0017] The SPAD imager 100 can be incorporated into other suitable systems and is not limited to the exemplary embodiments described herein. For example, a SPAD imager 100 can be incorporated into other systems that use light, such as visible light, near-infrared (NIR) light, infrared (IR) light, or the like, to determine information about an environment in which the device is located.

[0018] An exemplary SPAD device 102 includes a SPAD 104, which has a cathode and an anode biased by power supply voltage terminals 108 and 110, respectively. During operation of the SPAD device 102, the voltage terminals 108 and 110 can reverse-bias the SPAD 104 to a voltage higher than its breakdown voltage. With a reverse bias above the breakdown voltage, the absorption of a single photon by the SPAD 104 due to impact ionization can cause a large avalanche current in the SPAD 104.

[0019] The avalanche process in the SPAD 104 can, and in some cases will, continue indefinitely. As long as the avalanche current persists, subsequent photons striking the SPAD 104 cannot be detected. In some embodiments, the avalanche process is stopped by means of the quenching logic 106, which can include passive or active quenching. The quenching logic 106 can be used to reduce the bias voltage of the SPAD 104 below the breakdown level. In some embodiments, the passive quenching logic 106 can include a resistor in series between the cathode of the SPAD 104 and a positive bias terminal 108, as shown in Fig. Figure 1 shows. A SPAD 104 coupled in series with a quenching resistor or other quenching logic 106 can be called a microcell or SPAD pixel.

[0020] The avalanche current can generate an electrical signal that can be detected by the readout logic 112. For example, the triggering of the avalanche current due to the detection of an incident photon by the microcell and the subsequent quenching of the avalanche current can generate a pulse current signal that the readout logic 112 can identify as a photon detection. This pulse current signal can be referred to here as the avalanche pulse.

[0021] The readout logic 112 can process the detected current signal for a variety of purposes, for example, counting the number of incident photons by counting the number of avalanche current pulses using analog or digital pulse counting circuits, and controlling the time-of-flight (ToF) of the laser to determine the distance to the target. The example in Fig. Figure 1 of the readout switching logic 112, which is coupled to a node between SPAD 104 and the erase switching logic 106, is for illustrative purposes only. The readout switching logic 112 can be coupled to any suitable section of the SPAD device 102. In some embodiments, the erase switching logic 106 can be integrated with the readout switching logic 112.

[0022] A SPAD 104 must be erased and reset with each initiated avalanche flow. During the time required to erase and reset the SPAD 104, the so-called dead time, no additional photons can be detected by the SPAD 104. The dead time therefore limits the number of photons detectable by the SPAD 104 in a given period. In some embodiments, the dead time of a SPAD 104 can be on the order of nanoseconds, for example, around 3 nanoseconds.

[0023] The SPAD 104 also has the ability to fail to generate an avalanche current in response to an incident photon. Accordingly, the SPAD 104 exhibits a photon detection efficiency (PDE), which is the result of several factors, including the probability that a current carrier (electron and / or hole) is generated when the SPAD 104 receives an incident photon, and the probability that the generated current carrier triggers an avalanche current. For example, the SPAD 104 may have a PDE of approximately 30%, meaning that the SPAD device 102 detects about 30% of the incident photons.

[0024] The SPAD imager 100, which may also be referred to herein as a SPAD-based semiconductor device 100, can include multiple SPAD devices 102 to enhance the photon detection capability of the SPAD imager. In some embodiments, multiple SPAD devices 102 can be coupled in parallel (not shown) between the power supply voltage terminals 108 and 110 and utilize a common readout logic 112. In some embodiments, each of the multiple SPAD devices 102 can have its own individual readout logic 112. In some embodiments, the SPAD devices 102 can be arranged as a one-dimensional or two-dimensional array, and the array can include dozens, hundreds, thousands, tens of thousands (or more) of SPAD pixels.

[0025] Fig. Figure 2 is a cross-sectional side view of an exemplary SPAD-based semiconductor device 100 with multiple SPAD devices arranged in an array, the individual SPADs being separated by insulating structures. The SPAD imager 100 includes a SPAD 104-1 adjacent to other SPADs of the imager, for example, the neighboring SPAD 104-2 and SPAD 104-3. Each SPAD can be part of a respective SPAD device 102, a microcell, a SPAD pixel 260, or the like. The in Fig. The SPAD image sensor 100 illustrated in Figure 2 is a back-illuminated device (e.g., an image sensor) in which incident light passes through the back side (BS) of the substrate 254. Embodiments according to the present disclosure can be suitably adapted to front-illuminated devices (e.g., image sensors).

[0026] The substrate 254 has a back surface 256 and a front surface (FS) 258. In some embodiments, for example, in a backside imaging configuration, the FS 258 can be adjacent to a wiring layer 206. The wiring layer 206 can include one or more metallization layers with conductive signal lines 212, 214, which, for example, consist of a metal and are embedded in one or more dielectric layers 208, 210. The dielectric layers can be formed from any desired material, for example, silicon dioxide, silicon nitride, an organic or inorganic material, or the like. Different layers of conductive signal lines 212, 214 can be coupled through the one or more dielectric layers 208, 210 using conductive vias 216.

[0027] In some embodiments, at least a portion of the wiring layer 206 can be enclosed in a separate substrate, which is attached directly or indirectly to substrate 254 during fabrication. In some embodiments, the substrate 254 and one or more layers of the wiring layer 206 can be connected to the separate substrate by wafer bonding. In some embodiments, the separate substrate can further include the readout switching logic 112 and / or other desired switching logic and structures.

[0028] SPAD 104-1 can be formed in a substrate 254 extending between BS 256 and FS 258. The substrate can include a semiconductor substrate made of a material such as silicon. The substrate can have any suitable depth D1, measured between BS 256 and FS 258. In some embodiments, the depth D1 can be from 1 µm to 12 µm, for example, from 2 µm to 9 µm, 3 µm, or 6 µm. A SPAD pixel can have any suitable width, which may also be referred to herein as the pixel pitch. In some embodiments, the pixel pitch can be from 1 µm to 20 µm, from 1 µm to 10 µm, or from 1 µm to 6 µm, for example, 2 µm, 3 µm, or 6 µm.

[0029] A SPAD pixel 260 of the SPAD imager 100 can enclose the SPAD 104-1. The SPAD pixel 260 can enclose the portion of the substrate 254 in which the SPAD 104-1 is located, for example, the portion of the substrate 254 between FS 258 and BS 256, which is surrounded by insulating structures 252. The SPAD pixel 260 can enclose other components and connections of the SPAD device 102, for example, the quenching logic 106 (not shown). The SPAD pixel 260 can enclose other similarly arranged and related structures, for example, corresponding doped regions 202, 204, corresponding sections of the wiring layer 206, and / or other features formed within the substrate within the respective insulating structures 252 and between FS 258 and BS 256.

[0030] In some embodiments, the substrate 254 can be formed by a p-type doped semiconductor layer, for example, p-type doped epitaxial silicon. The SPAD 104-1 can be formed by the p-type doped semiconductor layer, a p-type doped enhancement layer 202, and an n-type doped region 204. The n-type doped region 204 can serve as the cathode for SPAD 104-1. The cathode and anode (not shown) of each SPAD pixel 260 can be connected to respective sections of the wiring layer 206 by conductive vias 216. The doping types of the p-type and n-type regions described herein can be reversed if required.

[0031] One or more microlenses 286 can be formed over the SPADs 104-1, 104-2, 104-3. The microlenses 286 can focus light onto the respective SPADs 104-1, 104-2, 104-3. Optionally, a planarization layer 282 can be formed between the microlenses 286 and the BS 256 of the substrate 254. The planarization layer 282 can consist of any suitable material or combination of materials, for example, one or more oxide layers such as silicon dioxide, silicon nitride, or the like.

[0032] Still referring to Fig. 2 SPAD 104-1 can be isolated from adjacent SPADs by isolation structures 252 in the substrate 254. Adjacent SPADs 104-1, 104-2, 104-3 can also be referred to herein as neighboring SPADs, and adjacent pixels 260 can also be referred to herein as neighboring pixels. To reduce crosstalk and / or achieve other performance goals, the isolation structures 252 can be formed partially or completely around each SPAD 104-1, 104-2, 104-3. For example, the isolation structures 252 can be formed along one or more sides of each SPAD pixel 260. One side of a SPAD pixel 260 can enclose the substantially linear region between a first SPAD 104-1 and a second adjacent SPAD 104-2. A corner of a SPAD pixel 260 can enclose the area where at least three SPAD pixels 260 are adjacent to each other.

[0033] The isolation structures 252 may include trench structures formed from the FS 258 and / or the BS 256. A trench formed from the FS 258 may be referred to herein as an FS trench, and a trench formed from the BS 256 may be referred to herein as a BS trench. In some embodiments, the isolation structures 252 may include deep trench isolation structures that extend partially or completely through the substrate 254.

[0034] The insulation structures 252 can be filled with different materials that fulfill various desired functions. The insulation structures 252 can enclose a filler made of light-absorbing material that absorbs photons and prevents photons, such as those generated by an avalanche, from passing into a neighboring microcell and causing crosstalk. In some embodiments, the light-absorbing material contains a metal such as tungsten.

[0035] The insulating structures 252 can include a conductive material such as metal, polysilicon, and / or the like to provide a conductive path to one or more SPADs, as described in more detail below. In some embodiments, the conductive material can include tungsten, polysilicon, and / or the like. In some embodiments, the conductive material can include multiple conductive materials, for example, tungsten in the direction of FS 258 and polysilicon in the direction of BS 256. As another example, approximately the upper third of the insulating structure 252 near FS 258 can include tungsten, and the remaining approximately two-thirds of the insulating structure 252 can include polysilicon.

[0036] The insulating structures can enclose a low-refractive-index material that causes total internal reflection. The low-refractive-index material can reflect photons and thus keep them within the active region of the SPAD 104-1 to increase efficiency. In some embodiments, the low-refractive-index material can include silicon dioxide or the like. The insulating structures 252 can enclose a high-κ dielectric material, formed, for example, in a trench in the substrate 254, to reduce dark current. In some embodiments, the high-κ dielectric can include an oxide coating, such as aluminum oxide, hafnium oxide, tantalum oxide, and / or the like.The insulation structures 252 can include a passivation layer that can fulfill various desired functions, such as reducing dark current, insulating a conductive filler material from the substrate 254, reflecting photons, and / or the like. The passivation layer can include any suitable material, for example, an oxide such as a high-κ dielectric, silicon dioxide, silicon nitride, another dielectric, and / or the like.

[0037] In some embodiments, the section of the insulating structures 252 that is closer to the front face 258 can include a light-absorbing material such as a metal filler. The cathode and / or anode contact for SPAD 104-1 can be adjacent to the front face 258, and the origin point of photon emission, for example due to an avalanche, can be primarily adjacent to the front face 258. The sections of the insulating structures 252 that are adjacent to the front face 258 can receive the emitted photons at right angles or approximately at right angles. The light-absorbing material in the insulating structures 252 can be arranged appropriately in the direction of the front face 258 to block most or all of the emitted photons and prevent crosstalk.

[0038] In some embodiments, a section of the insulation structures 252 located further away from the FS 258 can enclose a material with a low refractive index. Sections of the insulation structures 252 located further away from the FS 258 can receive emitted photons at higher angles of incidence, and the material with the low refractive index can reflect the light as described above, thus preventing it from reaching the adjacent SPADs 104-2, 104-3.

[0039] The embodiments of the isolation trench structures 252 described herein increase the distance between the first and second SPAD contacts, that is, between the anode and the cathode of the SPAD 104-1. Some of the embodiments of the isolation trench structures 252 described herein generally include a first SPAD contact, either anode or cathode, as part of the trench isolation structures 252, and a second SPAD contact, the other of anode or cathode, on or near the FS 258 and approximately centered within the SPAD pixel 260. In several embodiments, the first SPAD contact is substantially contained within the boundaries of the isolation trench 252 within the substrate. For example, the first SPAD contact must not extend beyond the boundaries of the lateral isolation trench 252.

[0040] The first SPAD contact is thus arranged horizontally (laterally) further away from the second contact than if the first SPAD contact were arranged within the base substrate 254 between the insulating structures 252. Some embodiments of the insulating trench structures 252 described herein arrange the first SPAD contact vertically away from the FS 258, that is, partially or completely to the BS 256. By increasing the horizontal and / or vertical distance between the anode and cathode, the strength of the electric field and the risk of edge breakdown of the SPAD 104-1 are reduced. A SPAD contact that is located substantially within the insulating trench 252 inside the substrate may here be referred to as a buried contact.

[0041] Embodiments of isolation trench structures 252, which may be referred to herein as trenches 252, trench structures 252, or isolation structures 252, may include the trenches 252 surrounding each SPAD pixel 260. While the embodiments described below discuss the anode contact of the SPAD as being located within the trenches 252 (the first SPAD contact), it is understood that the cathode may alternatively be located within the trenches 252. First subset of implementation examples

[0042] Next, a first subset of embodiments for forming an improved trench insulation structure 252 is described. This first subset of embodiments includes a FS trench lined with a passivation layer and filled with a conductive material, wherein the passivation layer is open at the bottom of the FS trench (the section of the trench facing BS 256) to allow conductive coupling between the conductive material and the substrate 254. The bottom of the FS trench need not be lined with the passivation layer.

[0043] With reference to Fig. 3A to E, the first subset of trench insulation embodiments may include some first embodiments which have a conductive material arranged between annular trenches and electrically coupled to the substrate 254 at the bottom of the trench structure 252.

[0044] With reference to Fig. 3A The FS surface 258 of the substrate 254 can be structured with a photoresist to prepare for etching a ring-shaped trench. For the sake of clarity, photoresist and photoresist processes are not depicted in any of the figures included herein, but they are understood. With reference to Fig. 3B can etch one or more ring-shaped trenches 310 through the substrate. Each ring-shaped trench 310 can partially or completely surround a respective SPAD pixel 260.

[0045] The annular grooves 310 can be etched through the substrate 254 to any suitable distance, for example more than half through the substrate 254, half through the substrate 254, or less than half through the substrate 254. In some embodiments, the photoresist can be removed after etching the annular grooves 310.

[0046] With reference to Fig. 3C A passivation layer 320 can be deposited in the etched annular grooves 310. The passivation layer 320 can be a conformal passivation layer. The substrate 254 can be structured with a photoresist suitable for etching the central section 330 of the substrate 254 between adjacent passivation layers 320.

[0047] With reference to Fig. In 3D, the central section 330 can then be etched through the substrate 254 over any suitable distance to form a central trench 340. In some embodiments, the central section 330 can be etched to the same depth as the annular trenches 310, or to a shallower depth than the annular trenches 310, for example, as shown in Fig. 3D shown, or etched to a greater depth than the annular grooves 310. In some embodiments, the photoresist can be removed after etching the central section 330.

[0048] In some embodiments, section 345 of the substrate at the bottom of the central trench 340 can be doped, for example, implanted with charged ions to enable conductive coupling with a conductive material to be deposited in the central trench 340. In some embodiments, ion implantation can be used, for example, the implantation of singly charged positive ions, doubly charged positive ions, and / or the like. For example, the substrate 254 can be suitably structured and positive ion implantation performed, after which the photoresist can be removed. The ion implant can then be activated, for example, by annealing at a suitable temperature for a suitable duration (not shown).

[0049] With reference to Fig. In embodiment 3E, a conductive material 350 can be deposited in the central trench 340. In some embodiments, the conductive material 350 can also be deposited on the FS surface 258 of the substrate 254, which can subsequently be structured and etched as part of the wiring layer 206 (not shown). The conductive material 350 can be coupled via one or more conductive signal lines 212, 214 with corresponding switching logic of the SPAD imager 100 to form the first contact for one or more adjacent SPADs 104-1, 104-2. The conductive material 350 can, for example, enclose tungsten.

[0050] In some embodiments, the substrate 254 can enclose an etch stop 360 near the BS 256. After processing the FS 258, the FS 258 can be attached to a support wafer to enable subsequent processing of the BS 256. The substrate can be etched up to the etch stop 360 to obtain, for example, the desired depth D1 of the substrate. In some embodiments, the substrate can be thinned by the BS 256 to approximately 6 µm to detect IR or NIR photons. Various structures, such as one or more BS trenches, can then be formed from the back side.

[0051] All embodiments described herein may include an etch stop 360 and reverse-side processing, even if this is not explicitly described in relation to a particular embodiment. Therefore, in some embodiments of the structures shown and described herein, a small section of the structures near BS 256 may be removed during subsequent etching.

[0052] With reference to Fig. 4A to E, the first subset of trench insulation embodiments can include some second exemplary embodiments having a trench structure 252 that can extend partially or completely along one or more edges of one or more SPAD pixels 260. The trench structure 252 can include an FS trench structure 400 and a BS trench structure 405.

[0053] With reference to Fig. 4A A wide trench 400 can be formed by structuring the wide trench surface 258 of the substrate 254 with a photoresist to prepare it for etching a wide trench. The wide trench 410 can then be etched through the substrate 254. The wide trenches 410 can be etched through the substrate 254 to any suitable distance, for example, more than half through the substrate 254, half through the substrate 254, or less than half through the substrate 254. In some embodiments, the photoresist can be removed after etching the wide trench 410.

[0054] With reference to Fig. 4B A passivation layer 420 can be deposited in the wide trench 410. The passivation layer 420 can be a conformal passivation layer. With reference to Fig. 4C The substrate 254 can be structured with a photoresist suitable for etching a narrow trench 440 through the wide trench 410. The narrow trench 440 can then be etched through the substrate 254 to any suitable distance, with, for example, at least part of the passivation layer 420 remaining on the side walls of the wide trench 410. In some embodiments, the narrow trench 440 can be etched deeper than the wide trench 410.

[0055] In some embodiments, the section 445 of the substrate at the bottom of the narrow trench 440 can be doped, for example, implanted with charged ions to enable conductive coupling with a conductive material to be deposited in the narrow trench 440. In some embodiments, ion implantation can be used, for example, the implantation of singly charged positive ions, doubly charged positive ions, and / or the like. In some embodiments, the same photoresist used to etch the narrow trench 440 can be used for the ion implantation because it is self-aligning and / or because the implantation can be low-energy and shallow. In other embodiments, the substrate 254 can be structured separately for ion implantation.The one or more photoresist(s) can be removed in a suitable manner, and the ion implant can then be activated as described above.

[0056] With reference to Fig. In 4D, a conductive material 450 can be deposited in the narrow trench 440. In some embodiments, the conductive material 450 can also be deposited on the FS surface 258 of the substrate 254 (not shown), which can subsequently be structured and etched as part of the wiring layer 206 (not shown). The conductive material 450 can be coupled via one or more conductive signal lines 212, 214 with corresponding switching logic of the SPAD imager 100 to form the first contact for one or more adjacent SPADs 104-1, 104-2. The conductive material 450 can, for example, enclose tungsten.

[0057] With reference to Fig. 4E can form a BS trench 405 from the BS surface 256, for example a partial BS deep trench. The trench structure 252 can enclose both the BS trench 405 and the FS trench 400.

[0058] In some embodiments, the BS trench 405 can enclose a passivation layer. In some embodiments, the BS trench 405 can be lined with a high-κ dielectric 470 and filled with a passivation layer 460, for example, silicon dioxide. In some embodiments, the BS trench 405 does not contact the structures of the FS trench 400, such as the passivation layer 420 and the conductive material 450, and can leave a conductive path between the conductive material 450 and one or more adjacent SPADs 104-1, 104-2.

[0059] The BS trench 405 can be formed adjacent to pyramidal light scattering structures 480 for the neighboring SPADs 104-1, 104-2. The light scattering structures 480 can be configured to increase the path length of photons to detect light with longer wavelengths, such as IR or NIR. In some embodiments, the BS trench 405 can be enclosed to prevent, among other things, light leakage (which can be termed crosstalk) from one 260 to another due to scattering from the light scattering structures 480 or due to photons generated during an avalanche of a respective SPAD pixel 260.

[0060] With reference to Fig. 5A to C, the first subset of trench insulation embodiments can include some third exemplary embodiments featuring a trench structure 252 that may extend partially or completely along one or more edges of one or more SPAD pixels 260. The trench structure 252 may include an FS trench structure 500 and a BS trench structure 505. In some embodiments, the trench structure 252, for example, the BS trench structure 505, may include several separate segments of a BS trench that overlap to provide both distinct conductor paths to the SPADs 104-1, 104-2, 104-3, 104-4 and light blocking. The BS trench 505 may be a deep trench and may be connected to the FS trench 500.

[0061] Fig. Figure 5A illustrates the relative horizontal arrangement of the various components of the trench structure 252 without considering the vertical positions of such structures. Fig. 5B and Fig. Figure 5C illustrates the relative vertical arrangement of the different components of the trench structure.

[0062] With reference to Fig. 5A can enclose the array of SPADs 104-1, 104-2, 104-3, 104-4 a conductive material 550 surrounding the pixels 260 in an FS trench 500 lined with a passivation layer 560, and can enclose a segmented BS trench 505 enclosing a high-κ dielectric 570 and / or a passivation layer 560. The FS trench 500 can, for example, be formed using similar or the same methods as described in the Fig. Sections 4A to 4E illustrated the FS trench 400.

[0063] With reference to Fig. 5B, which has a first cross-section as in Fig. As referenced in Figure 5A, a first section of the segmented BS trench 505 can include a passivation layer 560 and / or high-κ dielectric 570, which touches or is otherwise connected to the bottom of the FS trench 500 on one side of the trench structure 252. The BS trench 505 can, in particular, be connected to the passivation layer 520 of the FS trench 500 on the same side of the trench structure 252. The section of the BS trench 505 that includes only one side of the passivation layer 560 and / or the high-κ dielectric 570, as shown in Figure 5A, is Fig. Figure 5B shows a BS trench that can be described as a one-sided segmented BS trench.

[0064] As in Fig. As shown in Figure 5A, in some embodiments a one-sided segmented BS trench can cross the conductive material 550 of the FS trench 500 in a horizontal direction, such that the passivation layer 560 and / or the high-κ dielectric 570 of the one-sided segmented BS trench is adjacent to two SPADs, for example, SPADs 104-1 and 104-2. In some alternative embodiments, the passivation layer 560 and / or the high-κ dielectric 570 of the one-sided segmented BS trench can remain adjacent to a single SPAD and need not cross the conductive material 550 of the FS trench 500. Each arrangement can provide overlapping one-sided BS trenches 505.

[0065] A conductive trace from the conductive material 550 to the SPAD 104-2 on the opposite side of the trench structure 252 remains provided, and no conductive trace is provided from the conductive material 550 to the other adjacent SPAD 104-1. Each SPAD 104-1, 104-2, 104-3, 104-4 may be provided with a conductive trace between the conductive material 550 and the respective SPAD at the respective first sections of the BS trench 505. The conductive material 550 may, for example, include tungsten.

[0066] With reference to Fig. 5C, which has a second cross-section as in Fig. As referenced in Figure 5A, a second section of the segmented BS trench 505 can include a passivation layer 560 and / or high-kκ dielectric 570, which contacts or is otherwise connected to the bottom of the FS trench 500 on both sides of the trench structure 252. The BS trench 505 can, in particular, be connected to the passivation layers 520 of the FS trench 500 on both sides of the trench structure 252. In some embodiments, the second section of the BS trench 505 can include two deep back trenches coated with a high-kκ dielectric and filled with an oxide, each deep back trench being connected to a respective passivation layer 520 of the FS trench 500, with the substrate 254 remaining between the two deep back trenches.

[0067] The second section of the segmented BS trench 505 can block a direct lateral conductor path to each adjacent SPAD 104-3, 104-4. The second section of the segmented BS trench 505, which can be formed from several partially overlapping first sections of the BS trench 505, can serve to prevent some or all of the light emission between adjacent pixels 260.

[0068] In some embodiments, the BS trench 505 can enclose a passivation layer 560. In some embodiments, the BS trench 505 can be lined with a high-κ dielectric 570 and filled with a passivation layer 560, for example, silicon dioxide. The BS trench 505 can be formed adjacent to pyramidal light-scattering structures 480 for the neighboring SPADs 104-1, 104-2, 104-3, 104-4, as described above in relation to other embodiments. In some embodiments, the substrate 254 can enclose an etch stop 360 as described above. BS trenches 505 can be suitably adapted to the other embodiments described herein. Second subset of exemplary implementations

[0069] Next, a second subset of embodiments for forming an improved trench insulation structure 252 is described. This second subset of embodiments includes a multi-width FS trench lined with a passivation layer and featuring an opening at the transition between a first and a second width of the FS trench. The opening allows a conductive fill material within the trench structure 252 to couple conductively with the substrate 254, forming the first contact of the SPAD 104-1. In some embodiments, the bottom of the FS trench may not be lined with the passivation layer to allow a second conductive coupling of the conductive fill material with the substrate 254.

[0070] The opening in the passivation layer at the transition between the first and second widths of the FS trench can be an opening in an otherwise continuous passivation layer, formed, for example, in a single deposition step, rather than in separate deposition steps to form the passivation layer separately for each width. Thus, substrate 254 in the stepped area of ​​the stepped trench can be exposed to the conductive backfill material. The multi-width FS trench can be referred to as a stepped trench, and the transition area between the first and second widths of the FS trench can be referred to as a stepped area.

[0071] More generally, a horizontal surface or region of a trench structure 252 can include the surface or section of the trench structure 252 located between two vertical walls of the trench structure, the vertical walls being substantially perpendicular to the FS 258 and / or BS 256. In some embodiments, the horizontal surface or region is determined by one or more etching steps, and therefore the resulting horizontal region or surface may or may not be substantially flat and perpendicular to the vertical walls, depending on the methods used. In some embodiments, the bottom of an FS trench or BS trench can be a horizontal surface or region of the trench structure 252. In some embodiments, the transition region can include a horizontal surface or region located between the vertical walls of the wide trench and the narrow trench.

[0072] With reference to Fig. 6A to E, the second subset of trench insulation embodiments may include some fourth exemplary embodiments having a trench structure 252 that may extend partially or completely along one or more edges of one or more SPAD pixels 260. The trench structure 252 may include a stepped FS trench having a wide trench 600 and a narrow trench 605 lined with a passivation layer, the passivation layer being open in a transition region to allow electrical coupling of a conductive filler material to the substrate 254.

[0073] With reference to Fig. 6A A wide FS trench 600 can be formed by structuring the FS surface 258 of the substrate 254 with a photoresist to prepare it for etching the wide trench. The wide trench 600 can then be etched through the substrate 254. The wide trench 600 can be etched through the substrate 254 to any suitable distance, for example, more than half through the substrate 254, half through the substrate 254, or less than half through the substrate 254. In some embodiments, the photoresist can be removed after etching the wide trench 600.

[0074] In some embodiments, section 610 of the substrate at the bottom of the wide trench 600 can be doped, for example, implanted with charged ions to enable conductive coupling with a conductive material to be deposited in the trench 252. In some embodiments, ion implantation as described above can be used. In some embodiments, the same photoresist used to etch the wide trench 600 can be used for ion implantation prior to photoresist removal, because it is self-aligning and / or because the implantation may be low-energy and shallow. In other embodiments, the substrate 254 can be structured separately for ion implantation, for example, allowing ion implantation only in the wide trench 600.The one or more photoresist(s) can be removed in a suitable manner, and the ion implant can then be activated as described above.

[0075] With reference to Fig. In 6B, a narrow trench 605 can be etched through the wide trench 600. A photoresist can be appropriately structured, and then the narrow trench 605 can be etched through the substrate 254. The narrow trench 605 can be etched through the substrate 254 over any suitable distance. In some embodiments, the narrow trench 605 can be etched to a depth that is one to five times the depth of the wide trench 600, for example, two to four times the depth of the wide trench 600. In some embodiments, the narrow trench 605 is formed with a depth that is approximately twice the depth of the wide trench 600. In some embodiments, the photoresist can be removed after etching the narrow trench 605.

[0076] With reference to Fig. 6C, a passivation layer 620 can be deposited in both the wide trench 600 and the narrow trench 605. The passivation layer 620 can be a continuous and discontinuous conformal passivation layer, formed, for example, simultaneously, in a single deposit, or the like. With reference to Fig. 6D, the continuous passivation layer 620 can then be opened at the transition between the narrow trench 605 and the wide trench 600.

[0077] In some embodiments, the passivation layer 620 can be etched away in the transition region. For example, spacer etching can be performed to remove part or all of the passivation layer 620 from the horizontal trench surfaces. In some embodiments, the passivation layer can be removed from the bottom of the narrow trench 605. In some of these embodiments, the portion of the substrate 254 exposed at the bottom of the narrow trench 605 can subsequently be doped, for example, by ion implantation, as described above.

[0078] With reference to Fig. In embodiment 6E, a conductive material 630 can be deposited in the wide trench 600 and in the narrow trench 605. The conductive material 630 can be in electrical contact with the substrate 254 in the transition zone between the narrow trench 605 and the wide trench 600, and in some embodiments also through the bottom of the narrow trench 605. The conductive material 630 can, for example, include tungsten.

[0079] In some embodiments, the conductive material 630 can also be deposited on the FS surface 258 of the substrate 254 (not shown), which can then be structured and etched as part of the wiring layer 206 (not shown). The conductive material 630 can be coupled via one or more conductive signal lines 212, 214 with suitable switching logic of the SPAD imager 100 to form the first contact for one or more adjacent SPADs 104-1, 104-2, for example in the stepped area on one or both sides of the insulation trench 252 and in some cases also through the bottom of the narrow trench 605.

[0080] Embodiments of the fourth embodiment, which have an electrical contact between the conductive material 630 and the substrate 254 at the bottom of the narrow trench, are also examples of embodiments of the first subset of trench insulation embodiments.

[0081] In some embodiments, the substrate 254 can include an etch stop 360 near the BS 256. After processing the FS 258, the FS 258 can be attached to a support wafer to allow subsequent processing of the BS 256. The back side of the substrate can be etched up to the etch stop 360. In some embodiments, the back side of the substrate is etched up to the narrow trench 605, and in some embodiments, the back side etching ends before the narrow trench 605 is reached.

[0082] With reference to Fig. 7A to E, the second subset of trench insulation embodiments can include some fifth embodiments having a trench structure 252 that can extend partially or completely along one or more edges of one or more SPAD pixels 260. The trench structure 252 can include a stepped FS trench having a wide trench 600 and a narrow trench 605 lined with a passivation layer, the passivation layer being open in a transition region to allow electrical coupling of a conductive fill material to the substrate 254. A trench structure 252 according to the fifth embodiment can be an alternative embodiment of the fourth embodiment, having multiple conductive materials within the trench structure 252.

[0083] With reference to Fig. 7A, as described in relation to the fourth embodiment, a wide trench 600 can be formed in the substrate 254, the bottom section 610 of which can be doped as described above, and subsequently a narrow trench 605 can be formed at the bottom of the wide trench 600.

[0084] With reference to Fig. 7B and Fig. As described in relation to the fourth embodiment, a passivation layer with an opening in the transition region can be formed in 7C. For example, a passivation layer 620 can be deposited in both the wide trench 600 and the narrow trench 605. The passivation layer 620 can be a conformal passivation layer formed in a single deposit. In some embodiments, the continuous passivation layer 620 in the transition region can be etched away. For example, spacer etching can be performed to remove part or all of the passivation layer 620 from the horizontal trench surfaces, for example, removing enough to allow contact with a conductive filler material.

[0085] In some embodiments, the passivation layer can be removed from the bottom of the narrow trench 605, for example by spacer etching. In some of these embodiments, the portion of the substrate 254 exposed at the bottom of the narrow trench 605 can subsequently be doped, for example by ion implantation, as described above.

[0086] With reference to Fig. In 7D, a first conductive material 730 can be deposited in the wide trench 600 and in the narrow trench 605. The first conductive material 730 can be in electrical contact with the substrate 254 in the transition area between the narrow trench 605 and the wide trench 600, and in some embodiments also through the bottom of the narrow trench 605. The first conductive material 730 can enclose polysilicon. In some embodiments, the narrow trench 605 can be filled with polysilicon and the wide trench 600 can be coated with polysilicon, for example, in the same process step. The polysilicon does not have to completely fill the wide trench 600 and may, for example, leave a cavity 750 in the polysilicon.

[0087] With reference to Fig. 7E A second conductive material 740 can be deposited within the first conductive material 730 within the wide trench 600, for example within the cavity 750. In some embodiments, the first conductive material 730 can be etched or otherwise processed to change the shape of the cavity 750. The second conductive material 740 can, for example, include tungsten.

[0088] In some embodiments, the second conductive material 740 can also be deposited on the FS surface 258 of the substrate 254 (not shown), which can then be structured and etched as part of the wiring layer 206 (not shown). The second conductive material 740 can be coupled via one or more conductive signal lines 212, 214 with corresponding switching logic of the SPAD imager 100 to form, in combination with the first conductive material 730, the first contact for one or more adjacent SPADs 104-1, 104-2. For example, the first contact in the stepped area can run on one or both sides of the insulation trench 252 and, in some cases, also through the bottom of the narrow trench 605.

[0089] Embodiments of the fifth embodiment, which have an electrical contact between the conductive material 730 and the substrate 254 at the bottom of the narrow trench, are also examples of embodiments of the first subset of trench insulation embodiments.

[0090] With reference to Fig. 8A to E, the second subset of trench insulation embodiments may include some sixth embodiments having a trench structure 252 that may extend partially or completely along one or more edges of one or more SPAD pixels 260. The trench structure 252 may include a stepped FS trench having a wide trench 600 and a narrow trench 605 lined with a passivation layer, the passivation layer being open in a transition region to allow electrical coupling of a conductive fill material to the substrate 254. A trench structure 252 according to the sixth embodiment may be an alternative embodiment of the fourth and / or fifth embodiments having multiple conductive materials within the trench structure 252, the second conductive material contacting the substrate 254 in the transition region.

[0091] With reference to Fig. 8A, as described in relation to the fifth embodiment, a wide trench 600 can be formed in the substrate 254, the bottom section 610 of which can be doped as described above, and subsequently a narrow trench 605 can be formed at the bottom of the wide trench 600. The wide trench 600 and the narrow trench 605 can be lined with a conformal passivation layer 620, as also described in relation to the fifth embodiment.

[0092] With reference to Fig. As described in relation to the fifth embodiment, a first conductive material 730 can be deposited in the wide trench 600 and the narrow trench 605 in embodiment 8B. The first conductive material 730 can include polysilicon. In some embodiments, the narrow trench 605 can be filled with polysilicon and the wide trench 600 can be coated with polysilicon, for example, in the same process step. The polysilicon need not completely fill the wide trench 600 and may, for example, leave a cavity 750 in the polysilicon.

[0093] With reference to Fig. In some embodiments, a photoresist can be structured to suitably etch the first conductive material 730 out of the wide trench 600. The first conductive material 730 can be etched out of the wide trench 600, for example, by completely removing it from the wide trench 600. The etching can create a second cavity 850 in the first conductive material 730 in the narrow trench 605. The photoresist can be removed as required.

[0094] With reference to Fig. In 8D, the continuous passivation layer 620 in the transition area can be etched away. For example, a spacer etching can be performed to remove part or all of the passivation layer 620 from the horizontal trench surfaces, for example, removing enough to allow contact with a conductive filler material. In some embodiments, which, for example, have polysilicon as the first conductive material 730, the bottom of the second cavity 850 can also be etched.

[0095] With reference to Fig. In embodiment 8E, a second conductive material 840 can be deposited in the wide trench 600. In some embodiments, the second conductive material can also be deposited within the first conductive material 730 within the narrow trench 605, for example, within the second cavity 850. The second conductive material 840 can be in electrical contact with the substrate 254 in the transition region between the narrow trench 605 and the wide trench 600 through the opening in the passivation layer 620. The second conductive material 840 can, for example, enclose tungsten.

[0096] In some embodiments, the second conductive material 840 can also be deposited on the FS surface 258 of the substrate 254 (not shown), which can subsequently be structured and etched as part of the wiring layer 206 (not shown). The second conductive material 840 can be coupled via one or more conductive signal lines 212, 214 with appropriate switching logic of the SPAD imager 100 to form the first contact for one or more adjacent SPADs 104-1, 104-2. For example, the first contact can be located in the stepped area on one or both sides of the insulation trench 252.

[0097] With reference to Fig. 9A to E, the second subset of trench insulation embodiments may include some seventh embodiments featuring a trench structure 252 that may extend partially or completely along one or more edges of one or more SPAD pixels 260. The trench structure 252 may include a stepped FS trench with a wide trench 600 and a narrow trench 605, each lined with a passivation layer, wherein a separation of the passivation layers in a transition region enables electrical coupling of a conductive fill material to the substrate 254. Some trench structures 252 according to the seventh embodiment may, for example, be variations of the second and / or sixth embodiments, featuring a separate narrow FS trench formed by the conductive material.

[0098] With reference to Fig. 9A, as described in relation to the sixth embodiment, a wide trench 600 can be formed in the substrate 254, the bottom section 610 of which can be doped as described above. In some seventh embodiments, a first passivation layer 920 can be formed in the wide trench 600. As described above, the first passivation layer 920 can be a deposited conformal passivation layer.

[0099] The passivation layer 920 can be removed from the bottom of the wide trench 600. For example, spacer etching can be performed to remove part or all of the passivation layer 920 from the horizontal trench surfaces, for instance, removing enough to allow contact between a conductive filler material and the substrate 254. In other embodiments, the passivation layer 920 can be formed on the side walls of the wide trench 600 without forming the passivation layer on the bottom of the wide trench 600. The formation of the passivation layer 920 and the doping of the bottom section 610 of the wide trench 600 can be carried out in any suitable sequence.

[0100] With reference to Fig. In embodiment 9B, a conductive material 930 can be deposited in the wide trench 600. The conductive material 930 can be in electrical contact with the substrate 254 at the bottom of the wide trench 600. The conductive material 930 can, for example, enclose tungsten. In some embodiments, the conductive material 930 can also be deposited on the FS surface 258 of the substrate 254 (not shown), which can subsequently be structured and etched as part of the wiring layer 206 (not shown). The conductive material 930 can be coupled via one or more conductive signal lines 212, 214 with corresponding switching logic of the SPAD imager 100 to form the first contact for one or more adjacent SPADs 104-1, 104-2.

[0101] With reference to Fig. In step 9C, a narrow trench 605 can be etched through the conductive material 930 into the wide trench 600. A photoresist can be appropriately structured, and then the narrow trench 605 can be etched through the conductive material 930 and the substrate 254. The narrow trench 605 can be etched through the substrate 254 over any suitable distance.

[0102] In some embodiments, the narrow trench 605 can be etched to a depth that is one to five times the depth of the wide trench 600, for example, two to four times the depth of the wide trench 600. In some embodiments, the narrow trench 605 is formed with a depth that is approximately twice the depth of the wide trench 600. In some embodiments, the photoresist can be removed after etching the narrow trench 605.

[0103] With reference to Fig. 9D A second passivation layer 950 can be formed in the narrow trench 605, for example including on the conductive material 930 of the wide trench 600. The second passivation layer 950 can be a conformal passivation layer. With reference to Fig. 9E The narrow trench 605, including within the wide trench 600, can be filled with a filler material 960. In some embodiments, the filler material 960 can include a conductive material, for example, polysilicon. The filler material 960 can also be deposited on the FS 258, which can then be structured, etched, and coupled to the corresponding switching logic of the SPAD imager 100 as described above.

[0104] The conductive material 930 can be in electrical contact with the substrate 254 in the transition zone between the narrow trench 605 and the wide trench 600, for example, between the two passivation layers 620 and 950. The conductive material 930 can form the first contact for one or more adjacent SPADs 104-1 and 104-2. For example, the first contact can be located in the stepped area on one or both sides of the insulation trench 252. Third subset of implementation examples

[0105] Next, a third subset of embodiments for forming an improved trench insulation structure 252 is described. This third subset of embodiments includes a trench structure 252 having a buried first contact located substantially at the corner of one or more SPAD pixels 260, and no or substantially no first contact located along any side of the one or more SPAD pixels 260. The third subset of embodiments may include the buried first contact located substantially at the point where four SPAD pixels 260 meet, and the buried first contact may, for example, be electrically coupled to one, two, three, or four of the adjacent SPAD pixels 260.Arranging the first contact essentially at the corner intersections of the SPAD pixels 260 can allow for a smaller critical dimension of the trench structure 252 and a smaller spacing of the SPAD pixels 260.

[0106] Embodiments of the third subset of embodiments of trench structures 252 restrict the first contact for each SPAD 104-1 to one or more corner regions of the respective SPAD pixel 260, thereby further increasing the distance between the first and second contacts of the SPAD 104-1 compared to when the first contact is located along a side of the SPAD pixel 260. This greater distance further reduces the electric field and the risk of edge breakdown of the SPAD 104-1.

[0107] The other subsets of embodiments described above and below include variations that are also included in this third subset of embodiments. For example, with reference to Fig. 10A to E, the sixth embodiments described above include a variant in which the reference to Fig. The trench structures 252 described in sections 8A to E are essentially located at the corners of the respective SPAD pixels 260.

[0108] Fig. Figure 10A illustrates the relative horizontal arrangement of the various components of the trench structure 252 without considering the vertical positions of such structures. Fig. Figures 10B to D illustrate the relative vertical arrangement of the various components of the trench structure.

[0109] With reference to Fig. 10A can enclose the array of SPADs 104-1, 104-2, 104-3, 104-4, 104-5, 104-6, 104-7 within the narrow trench 605, which is lined with the passivation layer 620 that essentially surrounds the SPAD pixels 260, the passivation layer having no opening and therefore preventing the formation of the first contact at the sides of the respective SPAD pixels 260. The array of SPADs 104-1, 104-2, 104-3, 104-4, 104-5, 104-6, 104-7 can enclose the trench structure 252, as described in relation to Fig. 8E described and illustrated, which is located at the outermost end(s) of one or more sides of the respective SPAD pixel(s) 260. That is, which in relation to Fig. The trench structure 252 described in 8E can be located at one or more corners of each SPAD pixel 260 to provide initial contact for one or more adjacent SPADs.

[0110] Fig. 10C to D are second and third cross-sections as in Fig. Reference 10A illustrates how a Fig. In these sixth embodiments, the trench insulation structure 252 described and illustrated above can be formed at the corners of one or more SPAD pixels 260. The trench structure 252 can enclose the wide trench 600 and the narrow trench 605 and can be filled with the first conductive material 730 and the second conductive material 840. In some embodiments, the first conductive material 730 can include polysilicon and the second conductive material can include tungsten.

[0111] The trench structure 252 can enclose the opening at the passivation layer 620 in the transition region to enable electrical coupling of the second conductive material 840 with the substrate 254, in order to establish initial contact with the respective SPADs 104-3, 104-4, 104-5, 104-6, 104-7 at one or more corners of the respective SPAD pixels 260. In some embodiments, the trench structure 252 can be planar to FS 258 and BS 256 in two orthogonal directions at the corners of the SPAD pixels 260, for example as shown in the cross-sections of Fig. 10C and Fig. 10D shown.

[0112] With reference to Fig. 10B, which has a first cross-section as in Fig. As referenced in Figure 10A, the wide trench 600 and the transition area with the opening of the passivation layer do not need to be formed along the remaining sides of the SPAD pixels 260. In some embodiments, only the narrow trench section 605 of the trench structure 252 can be formed along the remaining sides of the SPAD pixels 260. The narrow trench structures 605 along the sides of the SPAD pixels 260 can be formed simultaneously with the narrow trench structures 605 at the corners of the SPAD pixels 260 and can be suitably filled with the first conductive material 730 and the second conductive material 840.

[0113] The narrow trench structures 605 along the sides of the SPAD pixels 260 can therefore have the same or a similar arrangement of structures and materials as the narrow trench structures 605 formed in the corners of the SPAD pixels 260. An electrical connection between the second conductive material 840 and the substrate 254 is prevented by the continuous passivation layer 620 of the narrow trench.

[0114] As another example, with reference to Fig. 11A to C the above with reference to Fig. The third embodiments described in 5A to C include variations in which the [unclear] with reference to Fig. The FS trench 500 described in 5B is essentially located at the corners of the respective SPAD pixels 260 and is related to Fig. The trench structures 252 described in 5C are located along the remaining sides of the respective SPAD pixels 260. The variations may include a segmented BS trench 505. Fig. Figure 11A illustrates the relative horizontal arrangement of the various components of the trench structure 252 without considering the vertical positions of such structures. Fig. 11B and Fig. Figure 11C illustrates the relative vertical arrangement of the various components of the trench structure.

[0115] With reference to Fig. 11A can include the array of SPADs 104-1, 104-2, 104-3, 104-4 and the isolation trench structure 252, as described in relation to Fig. 11C described and illustrated, which essentially surrounds the SPAD pixels 260. Similar to in Fig. 5C closes the isolation trench structure 252 here in Fig. 11C includes both the FS trench structure 500 and the BS trench structure 505. These FS trench 500 and BS trench structures 505 do not need to have an opening between the opposing sections of the BS trench 505 and the FS trench 500, thus preventing the formation of first contact at the sides of the respective SPAD pixels 260.

[0116] The array of SPADs 104-1, 104-2, 104-3, 104-4 can penetrate the FS trench 500 as in relation to Fig. 11B described and illustrated, including, but not including, the BS trench 505 located at the outermost end(s) 1110 of one or more sides of the respective SPAD pixels 260. That is to say, the one relating to Fig. The FS trench 500 described in 11B can be arranged adjacent to one or more corners of each SPAD pixel 260 to provide the first contact for one or more adjacent SPADs 104-1, 104-2, 104-3, 104-4.

[0117] With reference to Fig. 11B, which has a first cross-section as in Fig. As referenced in Figure 11A, a trench insulation structure 252 according to the FS trench 500, which was described in relation to the preceding third embodiments, can be formed at the corners of one or more SPAD pixels 260. Similar to the Fig. 5B can be used by the FS trench 500 in Fig. 11B enclose the opening on the underside of the FS trench 500 to allow electrical coupling of the conductive material 550 with the substrate 254 to form the first contact at the corners of one or more respective SPAD pixels 260.

[0118] In some embodiments, the trench structure 252 at the corners of the SPAD pixels 260 can be planar and symmetrical to FS 258 and BS 256 in two orthogonal directions. In some of these embodiments, there is no BS trench 505 at the corner intersections of the SPAD pixels 260, which may have a negligible or minor negative impact on the SPAD pixel isolation.

[0119] With reference to Fig. 11C, which represents a second cross-section, as in Fig. Referenced in Figure 11A, a trench insulation structure 252 along the remaining sides of the SPAD pixels 260 can enclose both the FS trench 500 and the BS trench 505 described above in relation to the third embodiments, wherein the high-κ dielectric 570 and / or the passivation layer 560 of the BS trench is in contact with the passivation layer 520 of the FS trench 500, thereby preventing electrical coupling of the conductive material 550 with the adjacent SPADs 104-3, 104-4. In some embodiments, the FS trench 500 can be formed at the corners of the SPAD pixels 260 simultaneously with the FS trench 500 along the sides of the SPAD pixels 260.

[0120] As another example, with reference to Fig. 12A to C the above with reference to Fig. The third embodiments described in 5A to C include a variation in which the features relating to Fig. The trench structures described in 5B are essentially located at the corners of the respective SPAD pixels 260, and are related to Fig. The trench structures 252 described in 5C are located along the remaining sides of the respective SPAD pixels 260. The variations may include a segmented BS trench 505.

[0121] Fig. Figure 12A illustrates the relative horizontal arrangement of the various components of the trench structure 252 without considering the vertical positions of such structures. Fig. 12B and Fig. Figures 12C illustrate the relative vertical arrangement of the various components of the trench structure.

[0122] As in Fig. As shown in Figure 12A, the array of SPADs 104-1, 104-2, 104-3, 104-4 can enclose the isolation trench structure 252, as shown in relation to Fig. 12C described and illustrated, which essentially surrounds the SPAD pixels 260. Similar to in Fig. 5C closes the isolation trench structure 252 in Fig. 12C here includes both the FS trench structure 500 and the BS trench structure 505. These FS trench 500 and BS trench structures 505 do not need to have an opening between the opposing sections of the BS trench 505 and the FS trench 500, thus preventing the formation of first contact at the sides of the respective SPAD pixels 260.

[0123] Also in Fig. 12A can the array of SPADs 104-1, 104-2, 104-3, 104-4 the isolation trench structure 252 as in relation to Fig. 12B described and illustrated, include, which are located at the outermost end(s) 1110 of one or more sides of the respective SPAD pixels 260. Similar to in Fig. 5B closes the isolation trench structure 252 of Fig. 12B here the FS trench 500 and the BS trench 505 on one side of the isolation trench structure 252.

[0124] In some embodiments, the trench structure 252 at the corners of the SPAD pixels 260 can be open only to an adjacent SPAD pixel 260. That is, the one with respect to Fig. The arrangement of the FS trench 500 and the BS trench 505 described in Figure 12B can be located at a corner of each SPAD pixel 260 to provide initial contact only with an adjacent SPAD 104-1. In some of these embodiments, SPAD pixel isolation can be maintained because the substrate 254 of each SPAD pixel remains laterally isolated from neighboring SPAD pixels.

[0125] In some embodiments, the FS trench 500 can be formed at the corners of the SPAD pixels 260 simultaneously with the FS trench 500 along the sides of the SPAD pixels 260, and the BS trench 505 at the corners of the SPAD pixels 260 can be formed simultaneously with the BS trench 505 along the sides of the SPAD pixels 260. Fourth subset of exemplary implementations

[0126] Next, a fourth subset of embodiments for forming an improved trench insulation structure 252 is described. This fourth subset includes a trench structure 252 in which the first contact within the trench structure 252 is located substantially on the same surface of the substrate as the second contact of the SPAD 104-1. In some embodiments, the SPAD 104-1 has the second contact, for example, the cathode, at or near the front face of the substrate, and the first contact, for example, the anode, at or near the front face. The fourth subset of embodiments may include the first contact being electrically coupled to one, two, three, or four of the adjacent SPAD pixels 260.

[0127] With reference to Fig. References 13A to D can include the fourth subset of trench insulation embodiments, comprising several eighth embodiments, which have a trench structure 252 that can extend partially or completely along one or more edges of one or more SPAD pixels 260. The trench structure 252 can enclose an FS trench lined with a passivation layer, wherein an opening in the passivation layer near the FS 258 allows a conductive filler material to couple electrically with the substrate 254 near the FS 258.

[0128] With reference to Fig. As described above, 13A can form an FS trench 1300 at any suitable depth in the substrate 254. With reference to Fig. 13B A passivation layer 1320 can be formed in the FS trench 1300. The passivation layer 1320 can be a deposited conformal passivation layer.

[0129] With reference to Fig. In 13C, a portion of the passivation layer 1320 can be removed from the top of the FS trench 1300. For example, a spacer etch can be performed to completely remove the passivation layer 1320 from an upper section of the FS trench 1300 near the FS 258. In some embodiments, the passivation layer 1320 at the bottom of the FS trench 1300 can also be partially or completely removed, for example, by the same spacer etch.

[0130] Section 1310 of substrate 254 near the opening of the passivation layer 1320 at the top of the FS trench 1300 can be doped, for example, implanted with charged ions, as described above. In some embodiments, the same photoresist used for spacer etching can be used for ion implantation before photoresist removal. In other embodiments, substrate 254 and / or the FS trench 1300 can be structured separately for ion implantation. The one or more photoresists can be removed appropriately, and the ion implant can then be activated as described above.

[0131] With reference to Fig. In embodiment 13D, a conductive material 1330 can be deposited in the FS trench 1300. The conductive material 1330 can be in electrical contact with the substrate 254 near the FS 258 and, in some embodiments, also through the bottom of the FS trench 1300. The conductive material 1330 can, for example, include tungsten.

[0132] In some embodiments, the conductive material 1330 can also be deposited on the FS 258 of the substrate 254 (not shown), which can then be structured and etched as part of the wiring layer 206 (not shown). The conductive material 1330 can be coupled via one or more conductive signal lines 212, 214 with suitable switching logic of the SPAD imager 100 to form the first contact for one or more adjacent SPADs 104-1, 104-2, for example near the FS 258 on one or both sides of the insulation trench 252.

[0133] With reference to Fig. References 14A to D can include the fourth subset of trench insulation embodiments, comprising several ninth embodiments, which have a trench structure 252 that can extend partially or completely along one or more edges of one or more SPAD pixels 260. The trench structure 252 can include an FS trench which, except near the FS 258, is filled with a passivation layer, wherein a conductive fill material in the FS trench near the FS 258 is electrically coupled to the substrate 254.

[0134] With reference to Fig. As described above, 14A can form an FS trench 1300 at any suitable depth in the substrate 254. With reference to Fig. 14B The FS trench 1300 can be filled with a passivation material 1420, for example an oxide such as silicon dioxide. In some embodiments, the FS trench 1300 can be completely filled with the passivation material 1420. In some embodiments, an upper section of the FS trench 1300 can be left without the passivation material 1420.

[0135] With reference to Fig. 14C allows a portion of the passivation material 1420 to be removed from the top of the FS trench 1300. For example, a spacer etch can be performed to completely remove the passivation material 1420 from an upper section of the FS trench 1300 near the FS 258. The passivation material 1420 can be removed to any suitable depth within the FS trench 1300.

[0136] Section 1310 of substrate 254 near the removed or otherwise missing passivation material 1420 at the top of the FS trench 1300 can be doped, for example, implanted with charged ions, as described above. In some embodiments, the same photoresist used for spacer etching can be used for ion implantation prior to photoresist removal. In other embodiments, substrate 254 and / or the FS trench 1300 can be structured separately for ion implantation. The one or more photoresists can be removed appropriately, and the ion implant can then be activated as described above.

[0137] With reference to Fig. In 14D, a conductive material 1430 can be deposited in the FS trench 1300. The conductive material 1430 can be in electrical contact with the substrate 254 near the FS 258. The conductive material 1430 can, for example, enclose tungsten.

[0138] In some embodiments, the conductive material 1430 can also be deposited on the FS 258 of the substrate 254 (not shown), which can then be structured and etched as part of the wiring layer 206 (not shown). The conductive material 1430 can be coupled via one or more conductive signal lines 212, 214 with suitable switching logic of the SPAD imager 100 to form the first contact for one or more adjacent SPADs 104-1, 104-2, for example near the FS 258 on one or both sides of the insulation trench 252.

[0139] With reference to Fig. References 15A to E can include several tenth embodiments of the fourth subset of trench insulation configurations, which have a trench structure 252 that can extend partially or completely along one or more edges of one or more SPAD pixels 260. The trench structure 252 can enclose an FS trench lined with a passivation layer and filled with a first conductive material, wherein an opening in the passivation layer near the FS 258 allows a second conductive material to couple electrically with the substrate 254 near the FS 258.

[0140] With reference to Fig. As described above, 15A can form an FS trench 1300 at any suitable depth in the substrate 254. With reference to Fig. 15B A passivation layer 1320 can be formed in the FS trench 1300. The passivation layer 1320 can be a deposited conformal passivation layer. With reference to Fig. In 15C, the FS trench 1300 can be filled with a first conductive material 1540. In some embodiments, the first conductive material 1540 can include polysilicon.

[0141] With reference to Fig. In some embodiments, a portion of the passivation layer 1320 can be removed from the top of the FS trench 1300. For example, spacer etching can be performed to completely remove the passivation layer 1320 from an upper section of the FS trench 1300 near the FS 258. In some embodiments, the first conductive material 1540 remains essentially the same before and after the removal of the passivation layer 1320.

[0142] Section 1310 of substrate 254 near the opening of the passivation layer 1320 at the top of the FS trench 1300 can be doped, for example, implanted with charged ions, as described above. In some embodiments, the same photoresist used for spacer etching can be used for ion implantation before photoresist removal. In other embodiments, substrate 254 and / or the FS trench 1300 can be structured separately for ion implantation. The one or more photoresists can be removed appropriately, and the ion implant can then be activated as described above.

[0143] With reference to Fig. 15E A second conductive material 1530 can be deposited in the FS trench 1300, for example in the cavity created by removing the passivation layer 1320. The second conductive material 1530 can be in electrical contact with the substrate 254 near the FS 258. The second conductive material 1530 can, for example, enclose tungsten.

[0144] In some embodiments, the first conductive material 1540 and / or the second conductive material 1530 can also be deposited on the FS 258 of the substrate 254 (not shown), which can then be structured and etched as part of the wiring layer 206 (not shown). The conductive first conductive material 1540 and / or the second conductive material 1530 can be coupled via one or more conductive signal lines 212, 214 with suitable switching logic of the SPAD imager 100 to form the first contact for one or more adjacent SPADs 104-1, 104-2, for example near the FS 258 on one or both sides of the insulation trench 252. Fifth subset of exemplary implementations

[0145] Next, a fifth subset of embodiments for forming an improved trench insulation structure 252 is described. This fifth subset includes an FS trench with a passivation layer and a conductive fill material arranged to form a first contact of one or more SPADs 104-1, as described in numerous preceding embodiments. The fifth subset further includes a segmented BS trench with a first section contacting a single side of the bottom of the FS trench and a second section contacting both sides of the bottom of the FS trench.

[0146] The segmented BS trench can be applied to embodiments of the first to fourth subset of the exemplary embodiments described above.

[0147] For example, embodiments of the fifth subset of embodiments can be trench structures 252 according to the third embodiment and as in relation to Fig. 5, 11A to C and 12A to C include segmented BS trench structures, such as those described in relation to Fig. The embodiments described in sections 5, 11A to C, and 12A to C can also be used in conjunction with the FS trench structures described above. Therefore, embodiments of the fifth subset of embodiments also include variations of the first, second, fourth, fifth, sixth, seventh, eighth, ninth, and tenth embodiments described above.

[0148] Therefore, according to the various embodiments of the several subsets of the exemplary embodiments described above, an isolation trench 252 can enclose a trench with a single passivation layer and a metal within the trench and contact the substrate 254 through an opening in the passivation layer. An isolation trench 252 can enclose a single passivation layer in an annular ring around each SPAD pixel 260 and a metal between the annular rings and contact the substrate 254 away from the FS 258.

[0149] An isolation trench 252 can enclose a stepped region. For example, an isolation trench 252 can enclose an FS trench with a single passivation layer, which is filled with polysilicon towards the BS section of the FS trench and also with a metal towards the FS of the FS trench, the metal contacting the substrate 254 through an opening in the passivation layer in the stepped region. An isolation trench 252 can enclose an FS trench with a single passivation layer, which is filled with polysilicon and also with a metal towards the FS of the FS trench, the polysilicon contacting the substrate 254 through an opening in the passivation layer in the stepped region.

[0150] An insulation trench 252 can enclose an FS trench, which has a single passivation layer with a metal filling in the trench, the metal contacting the substrate 254 away from the FS 258, and can enclose a BS trench, which can be formed as a deep trench from the BS 256 using a high-κ dielectric and silicon dioxide. The FS trench and the BS trench can be separate and / or connected. In some of these embodiments, the FS trench and the BS trench are connected in segments to provide a path for the electric field for the anode / cathode and to have overlaps to prevent light leakage (e.g., crosstalk) due to scattering by scattering structures in or near the pixels 260.

[0151] An isolation trench 252 can enclose an FS trench with two passivation layers, wherein an inner passivation layer is filled with polysilicon and a metal is located between an outer and the inner passivation layer and contacts the substrate 254. The metal can be formed in a ring shape around the polysilicon. An isolation trench 252 can enclose an FS trench line or be filled with a passivation layer and enclose a metal near the FS 258 where the metal contacts the substrate 254.

[0152] An isolation trench 252 can include embodiments in which the first contact of the SPAD 104-1 is located only at the intersections of three or more pixels, for example, at the corners. The contact at the intersections can include an opening in a single passivation layer, allowing a metal of the trench 252 to touch the substrate, and no opening in the single passivation layer along the remaining sides of the pixels 260.

[0153] Fig. Figures 16A to D illustrate exemplary geometric arrangements of representative isolation trench structures. For example, stepped trench structures 252, according to one of the first to fourth stepped isolation trench structures, can enclose a narrow trench 605 that is approximately twice as deep as the wide trench 600 of the stepped trench structure 252. The SPAD pixel 260 can have any suitable spacing as described above, for example, from about 2 µm to about 3 µm.

[0154] With reference to Fig. In 16A, substrate 254 can have a depth D1 of approximately 3 µm, the wide trench 600 can have a depth of approximately 1 µm, and the narrow trench 605 can have a depth of approximately 2 µm. The wide trench 600 can have a critical dimension (CD) of approximately 150 nm, and the narrow trench 605 can have a critical dimension of approximately 100 nm. Therefore, the wide trench 600 can have an aspect ratio (AR) of approximately 6.7, and the narrow trench 605 an aspect ratio of approximately 20.

[0155] With reference to Fig. In 16B, substrate 254 can have a depth D1 of approximately 3 µm, the wide trench 600 can have a depth of approximately 1 µm, and the narrow trench 605 can have a depth of approximately 2 µm. The wide trench 600 can have a critical dimension (CD) of approximately 400 nm, and the narrow trench 605 can have a critical dimension of approximately 200 nm. Therefore, the wide trench 600 can have an AR of approximately 2.5, and the narrow trench 605 an AR of approximately 10.

[0156] With reference to Fig. In 16C, substrate 254 can have a depth D1 of approximately 6 µm, the wide trench 600 can have a depth of approximately 2 µm, and the narrow trench 605 can have a depth of approximately 4 µm. The wide trench 600 can have a critical dimension (CD) of approximately 400 nm, and the narrow trench 605 can have a critical dimension of approximately 200 nm. Therefore, the wide trench 600 can have an AR of approximately 5, and the narrow trench 605 an AR of approximately 20.

[0157] With reference to Fig.In substrate 254, 16D can have a depth D1 of approximately 6 µm, the wide trench 600 can have a depth of approximately 2 µm, and the narrow trench 605 can have a depth of approximately 4 µm. The wide trench 600 can have a critical dimension (CD) of approximately 600 nm, and the narrow trench 605 can have a critical dimension of approximately 400 nm. Therefore, the wide trench 600 can have an AR of approximately 3.3, and the narrow trench 605 an AR of approximately 10.

[0158] Other embodiments may similarly use one or more of the narrow or wide trench geometries, even without a stepped trench arrangement. For example, some embodiments according to the eighth, ninth, and / or tenth embodiments may have a critical dimension, as described with respect to the wide trench 600 or the narrow trench 605. As another example, some embodiments according to the first embodiments may have the annular trenches 310 formed with the critical dimensions of the wide trench 600 and the central trench 340 formed with the critical dimensions of the narrow trench 605.

[0159] Various embodiments therefore provide SPAD-based systems, devices, and methods with a buried contact. Different embodiments may enclose one of the anode or the cathode of a SPAD within isolation trench structures. The buried contact may be located within the isolation trench near the same side of the substrate as the other anode or cathode and / or may be located some distance from the side of the substrate on which the other anode or cathode is located.

[0160] The systems, devices, and methods described here provide a greater distance between the anode and cathode of the respective SPADs and reduce the probability of edge penetration in the avalanche zone of the respective SPADs. Various embodiments allow for smaller pixels, smaller critical dimensions of the pixels and / or trench structures, or similar features. Therefore, different embodiments enable improved image sensor resolution.

[0161] It is understood that the embodiments described above with respect to SPAD-based pixels can also be applied to other imaging pixels, for example, CMOS image sensors or the like. It is understood that embodiments according to the present description can be applied to back-facing and / or front-facing imaging devices. The various image sensor device structures, isolation trench structures, buried contacts, materials, processing steps, and the like shown and described above can be arranged in any number of equivalent embodiments.

[0162] The general concepts set forth herein can be adapted to any number of alternative but equivalent embodiments. The term "exemplary" is used herein to represent an example, instance, or illustration that may have any number of alternatives. Each implementation described herein as "exemplary" is not necessarily to be construed as preferable or advantageous over other implementations, nor is it necessarily intended as a model that must be duplicated in other implementations. Although several exemplary embodiments have been presented in the preceding detailed description, it should be evident that a large number of alternative but equivalent variations exist, and the examples presented herein are not intended to limit the scope of protection, applicability, or configuration of the invention in any way.In contrast, various changes can be made to the function and arrangement of the described elements without affecting the scope of protection of the claims and their legal equivalents.

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