Semiconductor device structure with dielectric nanostructure and method for its formation

Abstract

A semiconductor device structure is provided. The semiconductor device structure comprises a substrate. The semiconductor device structure includes a channel nanostructure and a dielectric nanostructure above the substrate. The dielectric nanostructure is located between the substrate and the channel nanostructure. The semiconductor device structure includes a gate-cut structure that extends through the channel nanostructure and the dielectric nanostructure. The semiconductor device structure includes a first source / drain structure above the substrate and connected to the channel nanostructure. The inner spacer is located between the first source / drain structure and the dielectric nanostructure.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over the preliminary US application No. 63 / 655,153 filed on June 3, 2024, which is hereby incorporated in full by reference into the present text. BACKGROUND

[0002] The integrated semiconductor (IC) industry has experienced rapid growth. Technological advances in IC materials and design have led to generations of ICs, each with smaller and more complex circuits than the previous one. However, these advances have also increased the complexity of IC processing and manufacturing.

[0003] In the course of IC development, the functional density (that is, the number of interconnected components per chip area) has generally increased, while the geometric size (that is, the smallest component (or trace) that can be produced by a manufacturing process) has decreased. This miniaturization process generally offers advantages by increasing production efficiency and reducing production costs.

[0004] However, as the structural element sizes continue to decrease, the manufacturing processes become increasingly difficult. Therefore, producing reliable semiconductor devices in ever smaller sizes has become a challenge. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood by referring to the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. Rather, the dimensions of the various structural elements may be enlarged or reduced as necessary for the sake of clarity in this discussion. Fig. Figure 1 is a top view of a semiconductor device structure according to some embodiments. Fig. 2A-1 is a cross-sectional view showing the semiconductor device structure along a section line II' in Fig. 1 illustrates, according to some embodiments. Fig. Figures 2A-1 to 2J-1 are cross-sectional views of different stages of a process for forming a semiconductor device structure according to some embodiments. Fig. 2A-2 is a cross-sectional view showing the semiconductor device structure along a section line II-II' in Fig. 1 illustrates, according to some embodiments. Fig. Figures 2A-2 to 2J-2 are cross-sectional views of different stages of a process for forming a semiconductor device structure according to some embodiments. Fig. 2A-3 is a cross-sectional view showing the semiconductor device structure along a section line III-III' in Fig. 1 illustrates, according to some embodiments. Fig. 2A-4 is a cross-sectional view showing the semiconductor device structure along a section line IV-IV' in Fig. 1 illustrates, according to some embodiments. Fig. 2F-3 is a top view of the semiconductor device structure of Fig. 2F-1 and 2F-2 according to some embodiments. Fig. 2G-3 is a top view of the semiconductor device structure of Fig. 2G-1 and 2G-2 according to some embodiments. Fig. 2G-4 is a cross-sectional view showing the semiconductor device structure along a section line III-III' in Fig. 2G-3 illustrates, according to some embodiments. Fig. 2I-3 is a top view of the semiconductor device structure of Fig. 2I-1 and 2I-2 according to some embodiments. Fig. 2J-3 is a top view of the semiconductor device structure of Fig. 2J-1 and 2J-2 according to some embodiments. Fig. 2J-4 is a cross-sectional view showing the semiconductor device structure along a section line IV-IV' in Fig. 2J-3 illustrates, according to some embodiments. Fig. 2J-5 is a cross-sectional view showing the semiconductor device structure along a section line VV' in Fig. 2J-3 illustrates, according to some embodiments. Fig. 2J-6 is a cross-sectional view showing the semiconductor device structure along a section line IV-IV' in Fig. 2J-3 illustrates, according to some embodiments. Fig. Figure 3 is a cross-sectional view illustrating a semiconductor device structure according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter under discussion. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs and / or facilities discussed.

[0007] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0008] The term "essentially" in the description, such as in "essentially flat" or "essentially coplanar," etc., is understood by those skilled in the art. In some embodiments, the adjective "essentially" may be omitted. Where appropriate, the term "essentially" may also encompass embodiments with "entirely," "completely," "all," etc. The term "essentially" may vary in different technologies and fall within the range of deviation understood by those skilled in the art. For example, the term "essentially" may also refer to 90% or more of what is specified, such as 95% or more of what is specified, in particular 99% or more of what is specified, including 100% of what is specified, although the present invention is not limited to such a range.Furthermore, terms such as "essentially parallel" or "essentially perpendicular" can be interpreted to not preclude insignificant deviations from the specified arrangement and may, for example, include deviations of up to 10°. The word "essentially" does not exclude "completely." For example, a compound that is "essentially free" of Y may be completely free of Y.

[0009] The term "approximately" can be varied in different technologies and may fall within the range of deviation understood by a person skilled in the art. The term "approximately" in conjunction with a specific distance or size is to be interpreted in such a way as not excluding an insignificant deviation from the specified distance or size. For example, the term "approximately" may include deviations of up to 10% of what is specified, although the present invention is not limited to such deviations. The term "approximately" in relation to a numerical value x may mean that x is ± 5% or 10% of what is specified, although the present invention is not limited to such deviations.

[0010] Several embodiments of the disclosure are described. Additional operations may be performed before, during, and / or after the steps described in these embodiments. Some of the described steps may be substituted or omitted to obtain other embodiments. Additional features may be added to the semiconductor device structure. Some of the structural elements described below may be substituted or omitted to obtain other embodiments. Although some embodiments are discussed with operations performed in a specific order, these operations may also be performed in a different logical sequence.

[0011] The nanostructured transistor described below (for example, nanolayer transistor structures, nanowire transistor structures, multi-bridge channel structures, nanoband FET structures, gate all-around transistor (GAA) structures) can be structured by any suitable method. For example, the structures can be structured using one or more photolithography processes, including dual-structuring or multiple-structuring processes. In general, dual-structuring or multiple-structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, center-to-center distances smaller than those obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithography process.Spacers are formed along the structured sacrificial layer using a self-adjusting process. The sacrificial layer is then removed, and the remaining spacers can then be used to structure the GAA structure. "Source / drain structure(s)" can refer to a source or a drain, either individually or collectively, depending on the context.

[0012] Fig. Figure 1 is a top view of a semiconductor device structure according to some embodiments. Fig. 2A-1 is a cross-sectional view showing the semiconductor device structure along a section line II' in Fig. 1 illustrates, according to some embodiments.

[0013] Fig. 2A-2 is a cross-sectional view showing the semiconductor device structure along a section line II-II' in Fig. 1 illustrates, according to some embodiments. Fig. 2A-3 is a cross-sectional view showing the semiconductor device structure along a section line III-III' in Fig. 1 illustrates, according to some embodiments.

[0014] Fig. 2A-4 is a cross-sectional view showing the semiconductor device structure along a section line IV-IV' in Fig. 1 illustrates, according to some embodiments. Fig. Figures 2A-1 to 2J-1 are cross-sectional views of different stages of a process for forming a semiconductor device structure according to some embodiments. Fig. Figures 2A-2 to 2J-2 are cross-sectional views of different stages of a process for forming a semiconductor device structure according to some embodiments.

[0015] As in Fig. As shown in Figures 1, 2A-1, and 2A-2, a substrate 110 is provided according to some embodiments. According to some embodiments, the substrate 110 has a device region 110D and a peripheral region 110P. According to some embodiments, the device region 110D is used to form devices such as active or passive devices. According to some embodiments, the peripheral region 110P is used to form a sealing ring structure. According to some embodiments, the sealing ring structure is designed to protect the devices in the device region 110D from exposure to moisture.

[0016] According to some embodiments, the substrate 110 has a base 112 and fins 114A and 114B above the base 112. According to some embodiments, fin 114A has a longitudinal axis A1. According to some embodiments, fin 114B has a longitudinal axis A2. According to some embodiments, the longitudinal axis A1 is not parallel to the longitudinal axis A2. In some embodiments, the longitudinal axis A1 is substantially perpendicular to the longitudinal axis A2.

[0017] Substrate 110, for example, has a semiconductor substrate. Substrate 110 has, for example, a semiconductor wafer (such as a silicon wafer) or a section of a semiconductor wafer.

[0018] In some embodiments, the substrate 110 is formed from an elemental semiconductor material, including silicon or germanium in a single-crystal, polycrystal, or amorphous structure. In some other embodiments, the substrate 110 is formed from a composite semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, a semiconductor alloy such as SiGe or GaAsP, or a combination thereof. The substrate 110 may also comprise multilayer semiconductors, semiconductor-on-insulator (SOI) structures (such as silicon-on-insulator or germanium-on-insulator), or a combination thereof.

[0019] In some embodiments, the substrate 110 is a device wafer comprising various device elements. In some embodiments, the various device elements are formed in and / or above the substrate 110. For the sake of simplicity and clarity, the device elements are not shown in the figures.

[0020] Examples of the various device elements include active devices, passive devices, other suitable elements, or a combination thereof. Active devices may include transistors or diodes (not shown) formed on a surface of substrate 110. Passive devices include resistors, capacitors, or other suitable passive devices.

[0021] For example, the transistors can be metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOS transistors), bipolar transistors (bipolar junction transistors, BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field-effect transistors (PFETs / NFETs), etc.

[0022] Various processes, such as front-end-of-line semiconductor fabrication (FEOL) processes, are used to create the various device elements. FEOL semiconductor fabrication processes can include deposition, etching, implantation, photolithography, annealing, planarization, one or more other suitable processes, or a combination thereof.

[0023] In some embodiments, (not shown) insulating structural elements are formed in the substrate 110. These insulating structural elements are used to surround active regions and to electrically insulate various device elements formed in and / or above the substrate 110 in the active regions. In some embodiments, the insulating structural elements include shallow trench insulation (STI) structural elements, local oxidation of silicon (LOCOS) structural elements, other suitable insulating structural elements, or a combination thereof.

[0024] As in Fig. Figures 1, 2A-1 and 2A-2 show that, according to some embodiments, nanostructure stacks 120 are formed over the fins 114A and 114B, respectively. Each nanostructure stack 120 comprises, according to some embodiments, sacrificial nanostructures 121, 123 and 125 and channel nanostructures 122, 124 and 126.

[0025] According to some embodiments, the sacrificial nanostructures 121, 123 and 125 and the channel nanostructures 122, 124 and 126 are stacked alternately and sequentially over the fins 114A and 114B. According to some embodiments, the sacrificial nanostructures 121, 123 and 125 and the channel nanostructures 122, 124 and 126 comprise nanowires or nanolayers.

[0026] According to some embodiments, the sacrificial nanostructures 121, 123, and 125 are all made from the same first material. According to some embodiments, the first material differs from the material of the substrate 110. According to some embodiments, the first material comprises an elemental semiconductor material, including silicon or germanium in a single-crystal, polycrystal, or amorphous structure.

[0027] According to some embodiments, the first material comprises a composite semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor such as SiGe or GaAsP, or a combination thereof.

[0028] According to some embodiments, the channel nanostructures 122, 124, and 126 are all made from the same second material. According to some embodiments, the second material differs from the first material. According to some embodiments, the second material is the same as the material of the substrate 110. According to some embodiments, the second material comprises an elemental semiconductor material, including silicon or germanium in a single-crystal, polycrystal, or amorphous structure.

[0029] The second material comprises, according to some embodiments, a composite semiconductor, an alloy semiconductor, or a combination thereof. The composite semiconductor comprises, according to some embodiments, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, a combination thereof, or another suitable composite semiconductor material. The alloy semiconductor comprises, according to some embodiments, SiGe, SiGeSn, SiGeC, SiSn, GaAsP, GeSn, a combination thereof, or another suitable alloy semiconductor material.

[0030] As in Fig. As shown in Figures 1, 2A-2 and 2A-3, an insulating layer 130 is formed over the base 112 according to some embodiments. The fins 114A and 114B are partially embedded in the insulating layer 130 according to some embodiments. The fins 114A and 114B are surrounded by the insulating layer 130 according to some embodiments.

[0031] According to some embodiments, the insulating layer 130 is made from a dielectric material, such as an oxide-containing material (for example, silicon oxide), an oxynitride-containing material (for example, silicon oxynitride), a material with a low k-value (low dielectric constant), a porous dielectric material, glass, or a combination thereof. According to some embodiments, the glass is borosilicate glass (BSG), phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), fluorinated silicate glass (FSG), or a combination thereof.

[0032] The insulating layer 130 is formed according to some embodiments using a deposition process (or a spin-on process), a chemical-mechanical polishing process, and a back-etching process. According to some embodiments, the deposition process comprises a chemical vapor deposition (CVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a flowable chemical vapor deposition (FCVD) process, a sputtering process, or a combination thereof.

[0033] As in Fig. Figures 1, 2A-1, 2A-2, 2A-3 and 2A-4 show that, according to some embodiments, gate stacks 140A and 140B are each formed over the nanostructure stacks 120, gate stacks 140C are formed over the insulation layer 130, and a mask layer 150 is formed over the gate stacks 140A, 140B and 140C.

[0034] More precisely, as in Fig. As shown in Figures 1, 2A-1 and 2A-3, the gate stack 140A is formed above the nanostructure stack 120, the fin 114A and the insulating layer 130 according to some embodiments. The gate stack 140A is placed around the nanostructure stack 120 and a top portion of the fin 114A according to some embodiments.

[0035] As in Fig. As shown in Figures 1, 2A-2 and 2A-4, the gate stacks 140B are formed above the nanostructure stack 120 and the fin 114B according to some embodiments. The gate stacks 140B are spaced apart from the insulating layer 130 according to some embodiments. The longitudinal axis A3 of the gate stacks 140B and 140C runs substantially parallel to the longitudinal axis A2 of the fin 114B according to some embodiments.

[0036] According to some embodiments, each of the gate stacks 140A, 140B or 140C comprises a gate dielectric layer 142 and a gate electrode 144. According to some embodiments, the gate electrode 144 is located above the gate dielectric layer 142.

[0037] According to some embodiments, the gate dielectric layer 142 is positioned between the gate electrode 144 and the nanostructure stack 120. According to some embodiments, the gate dielectric layer 142 is also positioned between the gate electrode 144 and the fin 114A. According to some embodiments, the gate dielectric layer 142 is positioned between the gate electrode 144 and the insulating layer 130.

[0038] According to some embodiments, the gate dielectric layer 142 is produced from an oxide-containing material such as silicon oxide. According to some embodiments, the gate dielectric layer 142 is formed using a chemical vapor deposition process and an etching process.

[0039] According to some embodiments, the mask layer 150 is positioned over the gate stacks 140A, 140B, and 140C. According to some embodiments, the mask layer 150 is made of a different material than the gate stacks 140A, 140B, and 140C. According to some embodiments, the mask layer 150 is made of a different material than the gate dielectric layers 142 of the gate stacks 140A, 140B, and 140C. According to some embodiments, the mask layer 150 is made of nitrides (for example, silicon nitride) or oxynitrides (for example, silicon oxynitride).

[0040] As in Fig. As shown in 2A-3, according to some embodiments a gate spacer 160 is formed over side walls 142a of the gate dielectric layer 142, side walls 144a of the gate electrode 144 and side walls 152 of the mask layer 150.

[0041] As in Fig. As shown in Figures 1, 2A-1, 2A-2, 2A-3 and 2A-4, the gate spacer 160 surrounds the gate stacks 140A, 140B and 140C and the mask layer 150 according to some embodiments. The gate spacer 160 is positioned above the nanostructure stacks 120, the fins 114A and 114B and the insulation layer 130 according to some embodiments.

[0042] According to some embodiments, the gate spacer 160 comprises layers 162 and 164. In some embodiments, layer 162 conformally covers the side walls 142a of the gate dielectric layer 142, the side walls 144a of the gate electrode 144, the side walls 150 of the mask layer 150, and a top surface 132 of the insulating layer 130. In some embodiments, layer 164 is formed above layer 162.

[0043] Layers 162 and 164 are made of different materials according to some embodiments. Layer 162 comprises insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide, according to some embodiments. Layer 164 comprises insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide, according to some embodiments.

[0044] According to some embodiments, the gate spacer 160 is made from a different material than the gate dielectric layers 142 of the gate stacks 140A, 140B and 140C and the mask layer 150. The formation of the gate spacer 160, according to some embodiments, comprises deposition processes and an anisotropic etching process.

[0045] As in Fig. As shown in Figures 2B-1 and 2B-2, according to some embodiments, sections of the sacrificial nanostructures 121, 123, and 125 and the channel nanostructures 122, 124, and 126 that are not covered by the gate stacks 140A and 140B and the gate spacer 160 are removed. According to some embodiments, the removal process forms trenches TR1 in the nanostructure stack 120 above the fin 114A. According to some embodiments, the trenches TR1 extend into the fin 114A.

[0046] According to some embodiments, the ablation process forms a trench TR2 in the nanostructure stack 120 above the fin 114B. According to some embodiments, the trench TR2 extends into the fin 114B.

[0047] As in Fig. As shown in 2B-1 and 2B-2, according to some embodiments, the side walls of the sacrificial nanostructures 121, 123 and 125 and the channel nanostructures 122, 124 and 126 are essentially aligned with (or essentially coplanar to) the side walls of the gate spacer 160 above the nanostructure stack 120.

[0048] According to some embodiments, the ablation process removes sections of the insulation layer 130 that are not covered by the gate stacks 140A, 140B, and 140C, thus forming trenches TR3 in the insulation layer 130. According to some embodiments, the trench TR3 is located between the gate stacks 140B and 140C.

[0049] According to some embodiments, the ablation process includes an etching process. In some embodiments, the etching process includes an anisotropic etching process, such as a dry etching process.

[0050] As in Fig. As shown in Figures 2C-1 and 2C-2, according to some embodiments, the sacrificial nanostructures 121, 123, and 125 are removed through the trenches TR1 and TR2. In some embodiments, gaps GA1 are formed between the fin 114A or 114B and the channel nanostructures 122, 124, and 126 after the sacrificial nanostructures 121, 123, and 125 have been removed. According to some embodiments, the removal process includes an etching process, such as a dry etching process and / or a wet etching process.

[0051] As in Fig. As shown in Figures 2C-1 and 2C-2, according to some embodiments a dielectric layer 170 is formed over the substrate 110 and therefore covers the fins 114A and 114B, the nanostructure stacks 120 and the gate stacks 140A, 140B and 140C. According to some embodiments, the dielectric layer 170 is filled into the column GA1.

[0052] The dielectric layer 170 is produced according to some embodiments from semiconductor oxide materials (for example SiO2 or SiO2:F), metal oxide materials (for example Al2O3), nitrogen-containing materials (for example SiN or SiCON) and carbon-containing materials (for example SiCO).

[0053] The dielectric layer 170 is formed according to some embodiments using a deposition process such as an atomic layer deposition process, a chemical evaporation process or a physical evaporation process.

[0054] As in Fig. As shown in 2D-1 and 2D-2, according to some embodiments the dielectric layer 170 is removed outside the column GA1, which is located between the fin 114A or 114B and the channel nanostructures 122, 124 and 126, and sections of the dielectric layer 170 are removed in the columns GA1.

[0055] According to some embodiments, the dielectric layer 170 remaining in columns GA1 forms dielectric nanostructures 171, 172, and 173. According to some embodiments, dielectric nanostructure 171 is located between fin 114A or 114B and channel nanostructure 122. According to some embodiments, dielectric nanostructure 172 is located between channel nanostructures 122 and 124. According to some embodiments, dielectric nanostructure 173 is located between channel nanostructures 124 and 126.

[0056] In some embodiments, recesses r1 are formed in the nanostructure stacks 120 after the ablation process. According to some embodiments, the recesses r1 are located next to the dielectric nanostructures 171, 172 and 173. According to some embodiments, the ablation process includes an etching process, such as a dry etching process.

[0057] As in Fig. As shown in Figures 2D-1 and 2D-2, according to some embodiments, a layer 180 for internal spacers is formed in the recesses r1 of the nanostructure stacks 120. According to some embodiments, the layer 180 for internal spacers and the dielectric nanostructures 171, 172 and 173 are made of different materials.

[0058] The layer 180 for internal spacers is produced according to some embodiments from an insulating material, such as an oxide-containing material (for example, silicon oxide), a nitride-containing material (for example, silicon nitride), an oxynitride-containing material (for example, silicon oxynitride), a carbide-containing material (for example, silicon carbide), a material with a high k-value (for example, HfO2, ZrO2, HfZrO2 or Al2O3), or a material with a low k-value.

[0059] According to some embodiments, the term "material with a high k-value" refers to a material with a dielectric constant greater than that of silicon dioxide. According to some embodiments, the term "material with a low k-value" refers to a material with a dielectric constant lower than that of silicon dioxide.

[0060] In some embodiments, the layer 180 for internal spacers is formed using a deposition process and an etching process. According to some embodiments, the deposition process comprises a physical evaporation process, a chemical evaporation process, an atomic layer deposition process, or the like. In some other embodiments, the layer 180 for internal spacers is formed using a selective deposition process, such as an atomic layer deposition process.

[0061] As in Fig. As shown in Figures 2E-1 and 2E-2, according to some embodiments an insulating layer 190 is formed over the fin 114A exposed by the trenches TR1 and the fin 114B exposed by the trench TR2. According to some embodiments, the insulating layer 190 is made of an insulating material, such as an oxide material (for example, silicon oxide), a nitride material (for example, silicon nitride), or an undoped semiconductor material (for example, undoped silicon).

[0062] According to some embodiments, the insulating layer 190 is used to electrically insulate the fin 114A or 114B of source / drain structures subsequently formed above the insulating layer 190.

[0063] According to some embodiments, the formation of the insulating layer 190 comprises depositing an insulating material layer over the gate stacks 140A, 140B and 140C and in the trenches TR1, TR2 and TR3; removing the insulating material layer over the gate stacks 140A, 140B and 140C and in the trenches TR3 using a photolithography process and an etching process; removing the insulating material layer over the inner walls of the trenches TR1 and TR2 using an etching process, wherein the remaining insulating material layer forms the insulating layer 190.

[0064] In some other embodiments, the formation of the insulating layer 190 includes carrying out an epitaxial process.

[0065] As in Fig. As shown in Figure 2E-1, the source / drain structures 210 are formed in the trenches TR1 and TR2 according to some embodiments. The channel nanostructures 122, 124, and 126 and the dielectric nanostructures 171, 172, and 173 are located between the source / drain structures 210 according to some embodiments. According to some embodiments, the source / drain structures 210 are in direct contact with the channel nanostructures 122, 124, and 126, the gate spacer 160, and the inner spacer layer 180.

[0066] According to some embodiments, the source / drain structure 210 has lightly doped sections 212 and a heavily doped section 214. The dopant concentration of the lightly doped sections 212 is lower than that of the heavily doped section 214, according to some embodiments. The lightly doped sections 212 are connected to the channel nanostructures 122, 124, and 126, according to some embodiments. The lightly doped sections 212 are embedded within the heavily doped section 214, according to some embodiments.

[0067] According to some embodiments, the source / drain structures 210 are made from a semiconductor material (for example, silicon-germanium) with phosphorus dopants, such as the group IIIA element. The group IIIA element comprises boron or another suitable material.

[0068] In some other embodiments, the source / drain structures 210 are fabricated from a semiconductor material (for example, silicon) with N dopants, such as the group VA element. The group VA element comprises phosphorus (P), antimony (Sb), or another suitable group VA material. According to some embodiments, the source / drain structures 210 are formed using an epitaxial process.

[0069] As in Fig. As shown in Figures 2E-1 and 2E-2, a dielectric structure 220 is formed over the source / drain structures 210 according to some embodiments. According to some embodiments, the dielectric structure 220 comprises an etch stop layer 222 and a dielectric layer 224. According to some embodiments, the etch stop layer 222 conformally covers the source / drain structures 210 and the gate spacer 160. According to some embodiments, the dielectric layer 224 is formed over the etch stop layer 222.

[0070] According to some embodiments, the etch stop layer 222 and the dielectric layer 224 are made of different materials. According to some embodiments, the etch stop layer 222 comprises a dielectric material, such as a nitride-containing material (for example, silicon nitride), an oxynitride-containing material (for example, silicon oxynitride), or a combination thereof.

[0071] According to some embodiments, the dielectric layer 224 comprises a dielectric material, such as an oxide-containing material (for example, silicon oxide), an oxynitride-containing material (for example, silicon oxynitride), a material with a low k-value, a porous dielectric material, glass, or a combination thereof.

[0072] According to some embodiments, the glass is borosilicate glass (BSG), phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), fluorinated silicate glass (FSG), or a combination thereof. According to some embodiments, the dielectric layer 224 is formed by a deposition process (for example, a chemical vapor deposition process) and a planarization process (for example, a chemical-mechanical polishing process).

[0073] As in Fig. As shown in Figures 2E-1 and 2E-2, a cover layer 230 is formed over the dielectric structure 220 according to some embodiments. The etch resistance of the cover layer 230 is greater than that of the dielectric structure 220 according to some embodiments. The cover layer 230 is made of an etch-resistant material such as a nitride material (for example, silicon nitride) according to some embodiments.

[0074] Fig. 2F-3 is a top view of the semiconductor device structure of Fig. 2F-1 and 2F-2 according to some embodiments. Fig. 2F-1 is a cross-sectional view showing the semiconductor device structure along a section line II' in Fig. 2F-3 illustrates, according to some embodiments. Fig. 2F-2 is a cross-sectional view showing the semiconductor device structure along a section line II-II' in Fig. 2F-3 illustrates, according to some embodiments.

[0075] As in Fig. As shown in Figures 2F-1, 2F-2, and 2F-3, a mask layer 240 is formed over the substrate 110 according to some embodiments to cover the cover layer 230, the mask layer 150, and the gate spacer 160. According to some embodiments, the mask layer 240 has an opening 242. According to some embodiments, the opening 242 exposes the mask layer 150 over the right-hand gate stack 140A and the gate spacer 160. According to some embodiments, the mask layer 240 is made of an etch-resistant material such as a nitride material (for example, silicon nitride).

[0076] Fig. 2G-3 is a top view of the semiconductor device structure of Fig. 2G-1 and 2G-2 according to some embodiments. Fig. 2G-1 is a cross-sectional view showing the semiconductor device structure along a section line II' in Fig. 2G-3 illustrates, according to some embodiments.

[0077] Fig. 2G-2 is a cross-sectional view showing the semiconductor device structure along a section line II-II' in Fig. 2G-3 illustrates, according to some embodiments. Fig. 2G-4 is a cross-sectional view showing the semiconductor device structure along a section line III-III' in Fig. 2G-3 illustrates, according to some embodiments.

[0078] As in Fig. As shown in Figures 2G-1, 2G-2, 2G-3, and 2G-4, according to some embodiments, the mask layer 150, the gate stack 140A, the channel nanostructures 122, 124, and 126, and the dielectric nanostructures 171, 172, and 173 are partially removed to form a trench TR4 that passes through the gate stack 140A, the channel nanostructures 122, 124, and 126, and the dielectric nanostructures 171, 172, and 173. Fig. As shown in 2G-3, according to some embodiments the gate stack 140A is divided by trench TR4 into sections 140A1 and 140A2.

[0079] The ablation process can further remove a section of the substrate 110 beneath the ablated dielectric nanostructure 171. Therefore, according to some embodiments, the trench TR4 extends into the fin 114A. In some embodiments, the trench TR4 passes through the fin 114A. In some embodiments, the trench TR4 extends further into the base 112.

[0080] According to some embodiments, in the trench TR4 the inner walls 154, S140A1 and 134 of the mask layer 150, the section 140A1 of the gate stack 140A and the insulation layer 130 are essentially flush with each other, and the inner walls 156, S140A2 and 136 of the mask layer 150, the section 140A2 of the gate stack 140A and the insulation layer 130 are essentially flush with each other.

[0081] As in Fig. As illustrated in Figure 2G-1, the ablation process can further remove an upper section of the gate spacer 160. Therefore, according to some embodiments, the width W1 of the trench TR4 increases towards the top 160a of the gate spacer 160. In some embodiments, the width W1 can narrow through the channel nanostructures 122, 124, and 126. The width W1 can increase below the channel nanostructures 122, 124, and 126 and then progressively taper as the trench TR4 extends further into the fin 114A. According to some embodiments, the ablation process includes an etching process, such as a dry etching process.

[0082] As in Fig. As shown in Figures 2H-1 and 2H-2, according to some embodiments a lining layer 252 is formed above the mask layer 240 and in the trench TR4. According to some embodiments, the lining layer 252 covers the inner walls TR4a and the bottom surface TR4b of the trench TR4 conformally.

[0083] According to some embodiments, the lining layer 252 is made from an insulating material such as an oxide material (for example, SiO2, SiCO, or SiO2:F). According to some embodiments, the lining layer 252 is produced using a deposition process, such as an atomic layer deposition process. In some embodiments, the lining layer 252 is produced using a deposition process, such as a chemical evaporation process or a physical evaporation process.

[0084] As in Fig. As shown in 2H-1 and 2H-2, according to some embodiments an etch resist layer 254 is formed above the lining layer 252. According to some embodiments, the etch resist layer 254 has an air gap AG. In some embodiments, air is contained in the air gap AG. According to some embodiments, the etch resist layer 254 is made of a dielectric material with good etch resistance, such as a nitride material (for example, SiN, SiCN, or SiCON).

[0085] In some embodiments, the etch resist layer 254 is produced from oxide materials or carbon-containing materials (for example, SiCO). According to some embodiments, the oxide materials include semiconductor oxide materials (for example, SiO2 or SiO2:F) or metal oxide materials (for example, Al2O3).

[0086] The etch resist layer 254 is produced according to some embodiments using a deposition process, such as an atomic layer deposition process. In some other embodiments, the etch resist layer 254 is produced using a deposition process, such as a chemical evaporation process or a physical evaporation process.

[0087] As in Fig. In the 2H-1 and 2H-2 shown, a planarization layer 256 is formed above the etch resist layer 254 according to some embodiments. The planarization layer 256 is made from a dielectric material such as a nitride material (for example, silicon nitride) according to some embodiments.

[0088] In some embodiments, the planarization layer 256 is produced using a deposition process, such as a chemical evaporation process (for example, plasma-assisted chemical evaporation). In some other embodiments, the planarization layer 256 is formed using a deposition process, such as a physical evaporation process.

[0089] As in Fig. In the 2H-1 and 2H-2 reactions shown, a planarization layer 258 is formed above the planarization layer 256 according to some embodiments. The planarization layer 258 is made from a dielectric material such as an oxide material (for example, silicon oxide) according to some embodiments.

[0090] According to some embodiments, the planarization layer 258 is produced using a deposition process, such as a chemical evaporation process (for example, plasma-assisted chemical evaporation). In some other embodiments, the planarization layer 258 is formed using a deposition process, such as a physical evaporation process.

[0091] Fig. 2I-3 is a top view of the semiconductor device structure of Fig. 2I-1 and 2I-2 according to some embodiments. Fig. 2I-1 is a cross-sectional view showing the semiconductor device structure along a section line II' in Fig. 2I-3 illustrates, according to some embodiments. Fig. 2I-2 is a cross-sectional view showing the semiconductor device structure along a section line II-II' in Fig. 2I-3 illustrates, according to some embodiments.

[0092] As in Fig. 2H-1, 2I-1, 2I-2 and 2I-3 shown, according to some embodiments, sections of the lining layer 252 and the etch resist layer 254 outside the trench TR4, the planarization layers 256 and 258, the mask layer 240, the ceiling layer 230, the mask layer 150 and upper sections of the gate stacks 140A, 140B and 140C, the gate spacer 160 and the dielectric structure 220 are removed.

[0093] The lining layer 252 and the etch resist layer 254, which remain in the trench TR4, together form a gate-cut structure 250 according to some embodiments. The gate-cut structure 250 extends through the gate spacer 160, the gate stack 140A, the channel nanostructures 122, 124 and 126 and the dielectric nanostructures 171, 172 and 173 according to some embodiments.

[0094] According to some embodiments, the gate-cut structure 250 extends into the substrate 110. According to some embodiments, the gate-cut structure 250 extends into the fin 114A. In some embodiments, the gate-cut structure 250 passes through the fin 114A. In some embodiments, the gate-cut structure 250 extends further into the base 112.

[0095] According to some embodiments, the dielectric nanostructure 171 is located between the inner spacer 180 and the gate-cut structure 250. According to some embodiments, the dielectric nanostructure 172 is located between the inner spacer 180 and the gate-cut structure 250. According to some embodiments, the dielectric nanostructure 173 is located between the inner spacer 180 and the gate-cut structure 250.

[0096] According to some embodiments, the inner spacer 180 is located between the source / drain structures 210 and the dielectric nanostructures 172 and 173. According to some embodiments, the inner spacer 180 is located between the insulating layer 190 and the dielectric nanostructure 171.

[0097] In some embodiments, the width W250 of the gate-cut structure 250 decreases from the top surface 160a of the gate spacer 160 towards the channel nanostructures 122, 124, and 126. According to some embodiments, the gate-cut structure 250 has a section 251 in the fin 114A.

[0098] Section 251 has, according to some embodiments, an upper part 251a and a lower part 251b. In some embodiments, the width W251a of the upper part 251a decreases in the direction of the dielectric nanostructures 171, 172 and 173. In some embodiments, the width W251b of the lower part 251b decreases in the direction of the base 112.

[0099] According to some embodiments, the dielectric nanostructures 171, 172, and 173 are in contact with the gate-cut structure 250 and the inner spacer 180. According to some embodiments, the dielectric nanostructure 171 is in contact with the channel nanostructure 122. According to some embodiments, the dielectric nanostructure 172 is in contact with the channel nanostructures 122 and 124.

[0100] According to some embodiments, the dielectric nanostructure 173 is in contact with the channel nanostructures 124 and 126. According to some embodiments, the gate-cut structure 250 is located between the source / drain structures 210, which are electrically isolated from each other by the gate-cut structure 250. According to some embodiments, the ablation process includes a planarization process, such as a chemical-mechanical polishing process.

[0101] Fig. 2J-3 is a top view of the semiconductor device structure of Fig. 2J-1 and 2J-2 according to some embodiments. Fig. 2J-1 is a cross-sectional view showing the semiconductor device structure along a section line II' in Fig. 2J-3 illustrates, according to some embodiments.

[0102] Fig. 2J-2 is a cross-sectional view showing the semiconductor device structure along a section line II-II' in Fig. 2J-3 illustrates, according to some embodiments. Fig. 2J-4 is a cross-sectional view showing the semiconductor device structure along a section line IV-IV' in Fig. 2J-3 illustrates, according to some embodiments.

[0103] Fig. 2J-5 is a cross-sectional view showing the semiconductor device structure along a section line V-V' in Fig. 2J-3 illustrates, according to some embodiments. Fig. 2J-6 is a cross-sectional view showing the semiconductor device structure along a section line VI-VI' in Fig. 2J-3 illustrates, according to some embodiments.

[0104] As in Fig. In 2J-1, 2J-2, 2J-3, 2J-4, 2J-5 and 2J-6, gate stacks 140A, 140B and 140C are removed according to some embodiments. According to some embodiments, the removal process forms trenches 162 in the gate spacer 160.

[0105] As in Fig. As shown in Figures 2J-1 and 2J-4, according to some embodiments, the dielectric nanostructures 171, 172 and 173 are removed through the grooves 162. The ablation process for removing the gate stacks 140A, 140B and 140C and the dielectric nanostructures 171, 172 and 173 comprises, according to some embodiments, an etching process, such as a wet etching process or a dry etching process.

[0106] As in Fig. In 2J-1, 2J-2, 2J-3, 2J-4, 2J-5 and 2J-6, gate stacks 260A, 260A1 and 260A2 and sealing gate stacks 260B and 260C are formed in the trenches 162 according to some embodiments. In this step, a semiconductor device structure 100 is essentially formed according to some embodiments.

[0107] As in Fig. As shown in 2J-4, according to some embodiments, the gate stack 260A surrounds the channel nanostructures 122, 124 and 126. As shown in Fig. As shown in Figures 2J-2 and 2J-3, according to some embodiments the sealing gate stacks 260B are located above the channel nanostructures 122, 124 and 126. In some embodiments, a longitudinal axis A3 of the sealing gate stacks 260B runs substantially parallel to the longitudinal axis A2 of the fin 114B.

[0108] According to some embodiments, the longitudinal axis A1 of the fin 114A does not run parallel to the longitudinal axis A3 of the sealing gate stack 260B. In some embodiments, the longitudinal axis A1 runs substantially perpendicular to the longitudinal axis A3. As in Fig. As shown in 2J-2 and 2J-3, according to some embodiments the sealing gate stacks 260C are located above the insulation layer 130.

[0109] According to some embodiments, the sealing gate stacks 260B and 260C and the fin 114B together form a sealing ring structure 270. According to some embodiments, the sealing ring structure 270 is used to protect the devices in the device region 110D from attack by moisture.

[0110] As in Fig. As shown in Figure 2J-2, according to some embodiments, a side wall S260B of the sealing gate stack 260B is connected to a side wall S126 of the channel nanostructure 126. According to some embodiments, the side wall S126 of the channel nanostructure 126 is connected between the side wall S260B of the sealing gate stack 260B and a side wall S173 of the dielectric nanostructure 173.

[0111] In some embodiments, a side wall S171 of the dielectric nanostructure 171 is connected to a side wall S114B of the fin 114B. According to some embodiments, the channel nanostructures 122, 124, and 126 are located between the gate stack 260B and the dielectric nanostructure 171.

[0112] As in Fig. As shown in Figure 2J-1, the dielectric nanostructures 172 and 173 are located between the gate-cut structure 250 and the source / drain structure 210 according to some embodiments. The dielectric nanostructure 171 is located between the gate-cut structure 250 and the insulating layer 190 according to some embodiments.

[0113] Each of the gate stacks 260A, 260B, or 260C comprises, according to some embodiments, a gate dielectric layer 262, an exit metal layer 264, and a gate electrode layer 266. According to some embodiments, the gate dielectric layer 262 conformally covers the channel nanostructures 122, 124, and 126 in Fig. 2J-1 and interior walls and floor surfaces of trenches 162.

[0114] According to some embodiments, the gate dielectric layer 262 is made from a material with a high k-value, such as HfO2, ZrO2, HfZrO2, or Al2O3. The gate dielectric layer 262 is produced using an atomic layer deposition process or another suitable process.

[0115] The exit metal layer 264 is formed conformally over the gate dielectric layer 262 according to some embodiments. The exit metal layer 264 is made of titanium-containing material (for example, TiN or TiSiN) or tantalum-containing material (for example, TaN) or another suitable conductive material. The exit metal layer 264 is produced using an atomic layer deposition process or another suitable process.

[0116] According to some embodiments, the gate electrode layer 266 is formed above the exit metal layer 264. The gate electrode layer 266 is made of W, Co, Al, or another suitable conductive material. The gate electrode layer 266 is produced using an atomic layer deposition process or another suitable process.

[0117] In some embodiments, the sacrificial nanostructures 121, 123, and 125, which are made of SiGe, for example, are replaced by the dielectric nanostructures 171, 172, and 173 before the source / drain structures 210 are formed. This prevents Ge atoms in the sacrificial nanostructures 121, 123, and 125 from diffusing into the channel nanostructures 122, 124, and 126 during the formation of the source / drain structures 210. This improves the planarity of the channel surfaces of the channel nanostructures 122, 124, and 126. Therefore, in some embodiments, the channel resistance is reduced, and the mobility of the channel nanostructures 122, 124, and 126 is improved, thus enhancing the performance of the semiconductor device structure 100.

[0118] Fig. Figure 3 is a cross-sectional view illustrating a semiconductor device structure 300 according to some embodiments. As shown in Fig. Figure 3 shows that, according to some embodiments, the semiconductor device structure 300 is similar to the semiconductor device structure 100, except that the dielectric nanostructure 171 has sections 171a and 171b, the dielectric nanostructure 172 has sections 172a and 172b, and the dielectric nanostructure 173 has sections 173a and 173b.

[0119] According to some embodiments, the gate-cut structure 250 is located between sections 171a and 171b. According to some embodiments, the gate-cut structure 250 is located between sections 172a and 172b. According to some embodiments, the gate-cut structure 250 is located between sections 173a and 173b.

[0120] The processes and materials for forming the semiconductor device structure 300 may be similar to or identical with those for forming the semiconductor device structure 100 described above. Elements with the same or similar reference numerical values ​​as in Fig. Items numbered 1 to 3 have the same or similar structures and materials. Therefore, their detailed descriptions are not repeated here.

[0121] According to some embodiments, semiconductor device structures and methods for their formation are provided. The methods (for forming the semiconductor device structure) replace sacrificial nanostructures, made of SiGe for example, with dielectric nanostructures before source / drain structures are formed. Ge atoms in the sacrificial nanostructures are prevented from diffusing into channel nanostructures during the formation of the source / drain structures, which improves the planarity of the channel surfaces of the channel nanostructures. This reduces the channel resistance and improves the mobility of the channel nanostructures, thus enhancing the performance of the semiconductor device structure.

[0122] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure comprises a substrate. The semiconductor device structure includes a channel nanostructure and a dielectric nanostructure above the substrate. The dielectric nanostructure is located between the substrate and the channel nanostructure. The semiconductor device structure includes a gate-cut structure that extends through the channel nanostructure and the dielectric nanostructure. The semiconductor device structure includes an inner spacer between the channel nanostructure and the substrate. The dielectric nanostructure is located between the inner spacer and the gate-cut structure. The semiconductor device structure includes a first source / drain structure above the substrate and associated with the channel nanostructure.The inner spacer is located between the first source / drain structure and the dielectric nanostructure.

[0123] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure comprises a substrate having a base and a fin above the base. The semiconductor device structure includes a channel nanostructure and a dielectric nanostructure above the fin. The dielectric nanostructure is located between the fin and the channel nanostructure. The semiconductor device structure includes a sealing gate stack above the channel nanostructure, wherein a first longitudinal axis of the sealing gate stack is substantially parallel to a second longitudinal axis of the fin.

[0124] According to some embodiments, a method for forming a semiconductor device structure is provided. The method comprises providing a substrate, a first sacrificial nanostructure, a first channel nanostructure, and a first gate stack. The first sacrificial nanostructure is located between the substrate and the first channel nanostructure, and the first gate stack surrounds the first sacrificial nanostructure and the first channel nanostructure. The method includes removing the first sacrificial nanostructure to form a first gap between the substrate and the first channel nanostructure. The method includes forming a first dielectric nanostructure in the first gap. The method includes forming a first source / drain structure above the substrate, which is connected to the first channel nanostructure.The method involves the partial removal of the first gate stack, the first channel nanostructure, and the first dielectric nanostructure to form a trench extending through these structures. The method then includes the formation of a gate-cut structure within the trench, with a portion of the first dielectric nanostructure located between the gate-cut structure and the first source / drain structure.

[0125] The above outlines features of various embodiments so that the person skilled in the art can better understand the aspects of the present disclosure. It is clear to the person skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as in the embodiments presented in this text. It should also be clear to the person skilled in the art that such equivalent designs do not depart from the essence and scope of protection of the present disclosure, and that they can make various changes, substitutions, and modifications to the present invention without departing from the essence and scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 655,153

[0001]

Claims

[1] Semiconductor device comprising: a substrate; a channel nanostructure and a dielectric nanostructure above the substrate, wherein the dielectric nanostructure is located between the substrate and the channel nanostructure; a gate-cut structure that passes through the channel nanostructure and the dielectric nanostructure; an inner spacer between the channel nanostructure and the substrate, wherein the dielectric nanostructure is located between the inner spacer and the gate-cut structure; and a first source / drain structure above the substrate, which is connected to the channel nanostructure, with the inner spacer located between the first source / drain structure and the dielectric nanostructure. [2] Semiconductor device according to claim 1, further comprising: a gate spacer above the channel nanostructure, wherein the gate cut structure passes through the gate spacer. [3] Semiconductor device according to claim 2, wherein the width of the gate cut structure decreases from a top side of the gate spacer towards the channel nanostructure. [4] Semiconductor device according to one of claims 1 to 3, wherein the substrate comprises a base and a fin above the base, the channel nanostructure and the dielectric nanostructure are located above the fin, and the gate-cut structure extends into the fin. [5] Semiconductor device according to claim 4, wherein the gate-cut structure extends through the fin. [6] Semiconductor device according to claim 5, wherein the gate-cut structure has a section in the fin, the section has an upper part and a lower part, and a first width of the upper part decreases in the direction of the dielectric nanostructure. [7] Semiconductor device according to claim 6, wherein a second width of the lower part decreases towards the base. [8] Semiconductor device according to any one of claims 1 to 7, wherein the dielectric nanostructure is in contact with the gate-cut structure, the inner spacer and the channel nanostructure. [9] Semiconductor device according to any one of claims 1 to 8, further comprising: a second source / drain structure above the substrate, which is connected to the channel nanostructure, wherein the channel nanostructure, the dielectric nanostructure and the gate-cut structure are located between the first source / drain structure and the second source / drain structure. [10] Semiconductor device comprising: a substrate, wherein the substrate comprises a base and a fin above the base; a channel nanostructure and a dielectric nanostructure above the fin, wherein the dielectric nanostructure is located between the fin and the channel nanostructure; and a sealing gate stack over the channel nanostructure, wherein a first longitudinal axis of the sealing gate stack is essentially parallel to a second longitudinal axis of the fin. [11] Semiconductor device according to claim 10, wherein a first side wall of the sealing gate stack is connected to a second side wall of the channel nanostructure. [12] Semiconductor device according to claim 11, wherein the second side wall of the channel nanostructure is located between the first side wall of the sealing gate stack and a third side wall of the dielectric nanostructure. [13] Semiconductor device according to one of claims 10 to 12, wherein a first side wall of the dielectric nanostructure is connected to a second side wall of the fin. [14] Semiconductor device according to any one of claims 10 to 13, further comprising: an internal spacer between the channel nanostructure and the fin and next to the dielectric nanostructure. [15] Method for forming a semiconductor device comprising: Providing a substrate, a first sacrificial nanostructure, a first channel nanostructure and a first gate stack, wherein the first sacrificial nanostructure is located between the substrate and the first channel nanostructure and the first gate stack surrounds the first sacrificial nanostructure and the first channel nanostructure; Removing the first sacrificial nanostructure to create an initial gap between the substrate and the first channel nanostructure; Formation of a first dielectric nanostructure in the first slit; Forming a first source / drain structure above the substrate, which is connected to the first channel nanostructure; Partial removal of the first gate stack, the first channel nanostructure, and the first dielectric nanostructure to form a trench passing through the first gate stack, the first channel nanostructure, and the first dielectric nanostructure; and Forming a gate-cut structure in the trench, with a section of the first dielectric nanostructure located between the gate-cut structure and the first source / drain structure. [16] The method of claim 15, further comprising: Providing a gate spacer that surrounds the first gate stack, with the gate-cut structure continuing through the gate spacer. [17] Method according to claim 16, wherein the partial removal of the first gate stack, the first channel nanostructure and the first dielectric nanostructure further removes a section of the gate spacer and decreases a width of the gate cut structure in the direction of the first channel nanostructure. [18] Method according to any one of claims 15 to 17, wherein the substrate has a base, a first fin and a second fin above the base, the first channel nanostructure and the first dielectric nanostructure are located above the first fin, and the method further comprises: Providing a second sacrificial nanostructure, a second channel nanostructure, and a second gate stack, wherein the second sacrificial nanostructure is located between the second fin and the second channel nanostructure, the second gate stack is located above the second channel nanostructure, and a first longitudinal axis of the second gate stack is substantially parallel to a second longitudinal axis of the second fin. The removal of the first sacrificial nanostructure further includes the removal of the second sacrificial nanostructure to form a second gap between the second fin and the second channel nanostructure, the formation of the first dielectric nanostructure further includes the formation of a second dielectric nanostructure in the second slit, and The formation of the first source / drain structure further includes the formation of a second source / drain structure above the second fin, which is connected to the second channel nanostructure. [19] Method according to claim 18, wherein the second longitudinal axis of the second fin does not run parallel to a third longitudinal axis of the first fin. [20] The method of claim 18 or 19, further comprising: Removing the second gate stack; and Forming a third gate stack above the second channel nanostructure, wherein the second channel nanostructure is located between the third gate stack and the second dielectric nanostructure.

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