Using one or more neural networks to generate three-dimensional (3D) models

Abstract

Apparatus, systems, and techniques for using one or more neural networks to perform one or more tasks. In at least one embodiment, the one or more neural networks use one or more textual descriptions to generate one or more three-dimensional (3D) models of one or more first objects based, at least in part, on two or more images of one or more second objects from two or more viewpoints.

Description

TECHNICAL FIELD

[0001] At least one embodiment relates to processing resources for using one or more neural networks to generate one or more three-dimensional (3D) models of an object from text based at least in part on one or more images of an object obtained from two or more cameras placed at different angles. BACKGROUND

[0002] Using a neural network to generate three-dimensional (3D) models can sometimes lead to inaccuracies if training data (e.g., images) used to train the neural network lack information due to occlusions, restricted angles, corrupted data, and the like. For example, the training data may only contain a frontal view of an object from an image used to train the neural network. Therefore, improvements can be made to better train a neural network and generate 3D models. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a system for training one or more neural networks to use one or more textual descriptions to generate one or more three-dimensional (3D) models, according to at least one embodiment; Fig. 2 shows a collage of images of one or more objects from two or more viewpoints, according to at least one embodiment; Fig. 3 shows a system for optimizing 3D objects according to at least one embodiment; Fig. 4 is a flowchart illustrating fine-tuning of a 2D model according to at least one embodiment; Fig. 5 is a flowchart illustrating optimization of 3D objects according to at least one embodiment; Fig. 6 shows an example of a processor according to at least one embodiment; Fig. 7 is a block diagram including a driver and / or runtime including one or more libraries for providing one or more APIs according to at least one embodiment; Fig. 8A shows logic according to at least one embodiment; Fig. 8B shows logic according to at least one embodiment; Fig. 9 shows training and deployment of a neural network according to at least one embodiment; Fig. 10 shows an example of a data center system according to at least one embodiment; Fig. 11A shows an example of an autonomous vehicle according to at least one embodiment; Fig. Figure 11B shows an example of camera locations and fields of view for the autonomous vehicle of Fig. 11A according to at least one embodiment; Fig. 11C is a block diagram showing an example system architecture for the autonomous vehicle of Fig. 11A according to at least one embodiment; Fig. 11D is a diagram illustrating a system for communication between one or more cloud-based servers and the autonomous vehicle of Fig. 11A according to at least one embodiment; Fig. 12 is a block diagram illustrating a computer system according to at least one embodiment; Fig. 13 is a block diagram illustrating a computer system according to at least one embodiment; Fig. 14 shows a computer system according to at least one embodiment; Fig. 15 shows a computer system according to at least one embodiment; Fig. 16A shows a computer system according to at least one embodiment; Fig. 16B shows a computer system according to at least one embodiment; Fig. 16C shows a computer system according to at least one embodiment; Fig. 16D shows a computer system according to at least one embodiment; Fig. 16E and Fig. 16F illustrate a common programming model according to at least one embodiment; Fig. 17 shows exemplary integrated circuits and associated graphics processors according to at least one embodiment; Fig. 18A-18B illustrate exemplary integrated circuits and associated graphics processors according to at least one embodiment; Fig. 19A-19B illustrate additional exemplary graphics processor logic according to at least one embodiment; Fig. 20 shows a computer system according to at least one embodiment; Fig. 21A shows a parallel processor according to at least one embodiment; Fig. 21B shows a partition unit according to at least one embodiment; Fig. 21C shows a processing cluster according to at least one embodiment; Fig. 21D shows a graphics multiprocessor according to at least one embodiment; Fig. 22 shows a system with multiple graphics processing units (GPU) according to at least one embodiment; Fig. 23 shows a graphics processor according to at least one embodiment; Fig. 24 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment; Fig. 25 shows a deep learning application processor according to at least one embodiment; Fig. 26 is a block diagram illustrating a neuromorphic processor according to at least one embodiment; Fig. 27 shows at least portions of a graphics processor according to one or more embodiments; Fig. 28 shows at least portions of a graphics processor according to one or more embodiments; Fig. 29 shows at least portions of a graphics processor according to one or more embodiments; Fig. 30 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment; Fig. 31 is a block diagram of at least portions of a graphics processor core according to at least one embodiment; Fig. 32A-32B illustrate thread execution logic including an arrangement of processing elements of a graphics processor core according to at least one embodiment; Fig. 33 illustrates a parallel processing unit ("PPU") according to at least one embodiment; Fig. 34 illustrates a general processing cluster ("GPC"), according to at least one embodiment; Fig. 35 illustrates a memory partition unit of a parallel processing unit ("PPU"), according to at least one embodiment; Fig. 36 illustrates a streaming multiprocessor, according to at least one embodiment; Fig. 37 is an example data flow diagram for an advanced computing pipeline according to at least one embodiment; Fig. 38 is a system diagram for an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline according to at least one embodiment; Fig. 39 includes an example illustration of an advanced computer pipeline 3810A for processing image data in accordance with at least one embodiment; Fig. 40A includes an example data flow diagram of a virtual instrument supporting an ultrasound device, according to at least one embodiment; Fig. 40B includes an example data flow diagram of a virtual instrument supporting a CT scanner, according to at least one embodiment; Fig. 41A shows a data flow diagram for a process for training a machine learning model according to at least one embodiment; and Fig. 41B is an exemplary illustration of a client-server architecture for enhancing annotation tools with pre-trained annotation models, according to at least one embodiment. Fig. 42 shows components of a system for accessing a large language model according to at least one embodiment. DETAILED DESCRIPTION

[0003] In at least one embodiment, systems and methods implemented in accordance with this disclosure are used to use software to train one or more neural networks to generate a three-dimensional (3D) model from an input text description, wherein the one or more neural networks are trained using multiple viewpoints of an object. In at least one embodiment, systems and methods implemented in accordance with this disclosure are used to use software to train one or more neural networks to generate a three-dimensional (3D) model from an input image.In at least one embodiment, the one or more neural networks generate the 3D model using multiple images from different viewpoints, and during training, the loss is calculated based on whether the 3D model simultaneously matches the multiple images.

[0004] In at least one embodiment, one or more neural networks generate one or more 3D models from text without bias in shape and appearance. In at least one embodiment, the one or more 3D models are generated by defusing a text-to-image diffusion model. In at least one embodiment, a dataset of image-text pairs is created, where the images are rendered from a corpus of 3D computer-aided design (CAD) models. In at least one embodiment, the diffusion model is refined to generate N viewpoints of the same object simultaneously, where the N viewpoints are specific angles apart, organized as tiled images. In at least one embodiment, when the fine-tuned diffusion model is used as a critique: "critic") is used for text-to-3D generation, the critique ensures that rendered images from any set of N viewpoints that are similar and relatively spaced should fall into a common distribution of images at those viewpoints. In at least one embodiment, this ensures that the shape and appearance of the viewpoints are always rendered and modeled together, resulting in viewpoint-decoupled text-to-3D generation.

[0005] In at least one embodiment, a text-to-3D generator generates one or more 3D representations from textual descriptions of an object using one or more images of an object captured by two or more cameras at different angles. In at least one embodiment, a textual description is input text (e.g., text strings, words, speech-to-text generator results, images, etc.) entered by a user. In at least one embodiment, a text-to-3D generator is an image-to-3D generator and generates one or more 3D representations from image input by a user. In at least one embodiment, a text-to-3D generator includes one or more neural networks that train a text-to-image diffusion model on a dataset including a dataset of image-text pairs.In at least one embodiment, the text-to-image diffusion model is de-empowered (e.g., with respect to one or more particular viewpoints, such as frontal views that predominantly depict faces) by retraining it on a dataset comprising one or more images of one or more objects obtained from two or more cameras positioned at different angles.

[0006] In at least one embodiment, the desensitized dataset for retraining comprises one or more digitally rotatable 3D CAD representations of two or more images of one or more objects. In at least one embodiment, another dataset of image-text pairs is created using images rendered from a corpus of 3D CAD models. In at least one embodiment, the two or more images comprise digitally rotatable 3D CAD representations with N viewpoints, where N is two or more. In at least one embodiment, an N-viewpoint CAD representation is acquired from cameras positioned substantially in a plane surrounding one or more objects, referred to as a target. In at least one embodiment, the cameras are evenly spaced and occupy the plane in its entirety. In at least one embodiment, the two or more images are combined as one (desensitized,: "debiased"]) collage. In at least one embodiment, the collage is linked to descriptive text as an image-text pair. In at least one embodiment, the image-text pair is converted into a digitally rotatable 3D CAD representation of the target.

[0007] In at least one embodiment, the diffusion model acts as a critique for training images to train the text-to-3D generator. In at least one embodiment, the 2D diffusion model requires only relative angular offsets, which are known during collage assembly. In at least one embodiment, the 2D diffusion model provides guidance from multiple viewpoints simultaneously during 3D asset optimization. In at least one embodiment, the 2D diffusion model interprets these views as coming from the same underlying object.

[0008] In at least one embodiment, the text-to-3D generator generates a 3D model from an unbiased collage. In at least one embodiment, the diffusion model evaluates the 3D model. In at least one embodiment, the diffusion model is fine-tuned to generate N viewpoints of the target object simultaneously. In at least one embodiment, the diffusion model indicates which versions of the generated model are of high confidence. In at least one embodiment, the diffusion model is trained to select only 3D models without artifacts, thereby reducing artifacts if the text-to-3D generator were to attempt to generate a 3D model from a set of images taken at random times and / or from random viewpoints.

[0009] In at least one embodiment, a loss function is used to compare the 3D object representation generated by the text-to-3D generator with a ground-truth representation. In at least one embodiment, the weights of the text-to-3D generator are adjusted according to the output of the loss function. In at least one embodiment, a loss function includes mean square error, regression, classification, autoencoder, and diffusion model loss, etc.

[0010] In at least one embodiment, one or more neural networks are trained to generate models (e.g., predictions or inferring information) from input data that includes, but is not limited to, image data. In at least one embodiment, one or more neural networks generate 3D models using multiple images captured using photo stocks or randomly from cameras from different viewpoints and / or at different times (e.g., models created using view-dependent prompts). In this way, 3D models can be constructed rather than using separate networks for different models. In at least one embodiment, a model is constructed using training data specifically designed for 3D modeling and with minimal bias toward a particular viewpoint.In at least one embodiment, a model is further constructed using training data simultaneously collected from certain random viewpoints. In at least one embodiment, to improve the ability of a neural network to generate 3D models using the techniques described herein, a processor having one or more circuits is caused to generate information about the one or more objects during training of a neural network.

[0011] Neural networks that generate 3D models of objects from text generate 3D models with parts of an object that shouldn't be present, such as a nose on one side of a face. This is because neural networks are trained by generating 3D models, using the 3D model to generate a 2D image of an object from a viewpoint for which there is a ground-truth 2D image from a same viewpoint, and adjusting the weights based on the loss measure of how well the 2D images match. However, ground-truth 2D images are aligned to the same viewpoints (meaning neural networks learn parts of objects from those viewpoints) and are not trained with information that indicates how different viewpoints should appear at the same time relative to each other (for example, that if one viewpoint has a nose, another viewpoint shouldn't have an additional nose).In at least one embodiment, the techniques described herein train a neural network to generate a 3D model from text, wherein the neural network is trained using multiple viewpoints of the object.

[0012] The preceding and following descriptions describe various techniques. For explanatory purposes, specific configurations and details are presented to provide a thorough understanding of possible ways to implement the techniques. However, it is also understood that the techniques described below may be implemented in various configurations without specific details. Furthermore, well-known features may be omitted or simplified to avoid obscuring the described techniques.

[0013] Fig. 1 shows an example / system 100 for training 102 a neural network 108 to generate 110 one or more three-dimensional (3D) models of an object 112 from text 112, according to at least one embodiment. In at least one embodiment, training data 104 is used as input by a training framework 106 to train 102 one or more untrained neural networks 108 using a generative adversarial network (GAN) that includes a discriminator for bidirectional encoder representations of transformers (BERT), as described further below in connection with Fig. 2 and Fig. 3. In at least one embodiment, the training data 104 is a set of images or image data, along with optional labels or classifications, to provide a set of examples from which one or more untrained neural networks 108 learn to perform a function, such as translating one type of image 112 into another type of image 116.

[0014] In at least one embodiment, the training data 104 is a set of data, such as image data, on which one or more untrained neural networks 108 are to be trained to operate. In at least one embodiment, the training data 104 comprises a set of images. In at least one embodiment, the training data 104 comprises a set of images with labels or classifications. In at least one embodiment, the training data 104 comprises image data. In at least one embodiment, the training data 104 comprises images from CAD. In at least one embodiment, the training data 104 comprises a medical image.In at least one embodiment, the training data 104 is one or more other types of data for which one or more untrained neural networks 108 are trained 102 by a training framework 106 to perform operations such as image generation, as described below in connection with . Fig. 2-7 described.

[0015] In at least one embodiment, a training framework 106 is a set of software instructions that, when executed on one or more computing devices, control the training 102 of one or more untrained neural networks 108 using training data 104, such as the image training data 104 described above. In at least one embodiment, one or more untrained neural networks 108 are trained by a training framework 106 that facilitates learning by one or more untrained neural networks 108 based on training data 104. In at least one embodiment, a training framework 106 trains one or more untrained neural networks using a GAN, which is described further below in connection with Fig. 2 and Fig. 3 is described.

[0016] In at least one embodiment, a training framework 106 trains one or more untrained neural networks 108 without supervision. In at least one embodiment, a training framework 106 trains one or more untrained neural networks 108 without supervision and using only training data 104. In at least one embodiment, a training framework 106 trains one or more untrained neural networks 108 using any available supervision in conjunction with training data 104.

[0017] In at least one embodiment, a training framework 106 uses training data 104 with supervision, where the supervision is in the form of classification, labels, bounding boxes, pixel-level annotation, image-level annotation, points containing locations corresponding to an object, or lines containing locations corresponding to an object. In at least one embodiment, a training framework 106 uses training data 104 to train one or more untrained neural networks 108, using any other form of supervision to facilitate the training 102 of the one or more untrained neural networks 108. In at least one embodiment, a training framework 106 uses no supervision for some or all of the training data 104.

[0018] In at least one embodiment, one or more untrained neural networks 108 are trained by a training framework 106 using supervision. In at least one embodiment, supervision includes multiple types of support used to facilitate training 102 of one or more untrained neural networks 108 by a training framework 106, as described above. In at least one embodiment, supervision includes input data describing one or more aspects of the training data 104, such as objects or styles, or a classification for the training data 104, to support training of one or more untrained neural networks 108 by a training framework 106.In at least one embodiment, the supervision is strong, where the input data provides a direct identification of an object, a style, or other aspect of an item, such as an image, in the training data 104. In at least one embodiment, the supervision is weak, where the input information provides a partial identification of an object, a style, or other aspect of an element in the input data of the training data 104. In at least one embodiment, the strong supervision consists of input information such as bounding boxes in which one or more objects are outlined in an element of the input data of the training data 104. In at least one embodiment, the weak supervision includes input information such as points in which individual locations in the input data of the training data 104 are identified as lying within one or more objects.In at least one embodiment, the weak supervision includes input information such as lines, where each point in a line within an input training data set 104 is identified by the weak supervision as being within an object or objects. In at least one embodiment, the weak supervision includes input information such as markers or labels, where a marker or label identifies that an input training data 104 contains a particular object or objects or belongs to a particular classification.

[0019] In at least one embodiment, one or more untrained neural networks 108 are trained by a training framework 106 to perform an operation such as translating a collage of images 112 into a 3D model 116. In at least one embodiment, one or more neural networks 108, 114 are individually each type of neural network described further herein. In at least one embodiment, each of one or more neural networks 108, 114 includes a set of nodes, each node calculating a value based on one or more inputs using an activation function. In at least one embodiment, one or more neural networks 108, 116 are embodied in software with instructions for performing an operation upon execution and with memory for storing computation results based on an input data item.In at least one embodiment, each of one or more neural networks 108, 114 is any type of neural network further described herein.

[0020] In at least one embodiment, one or more trained neural networks 114 perform inference 110 using a text description 112. In at least one embodiment, one or more trained neural networks 114 translate a collage image 112 into a 3D model 116. In at least one embodiment, one or more trained neural networks 114 perform inference 110, wherein a medical image, such as a collage image 112, is translated into another image, such as a 3D model 116, by the one or more trained neural networks 114. In at least one embodiment, the input data 112 includes any type of data on which one or more trained neural networks 114 are trained 102 to operate by a training framework 106.

[0021] In at least one embodiment, one or more trained neural networks 114 are one or more untrained neural networks 106 trained by a training framework 106 based on training data 104 to perform an operation. In at least one embodiment, one or more trained neural networks 114 are one or more untrained neural networks 108 trained 102 by a training framework 106 based on training data 104 and without supervision. In at least one embodiment, one or more trained neural networks 114 are one or more untrained neural networks 108 trained by a training framework 106 based on training data 104 with supervision.

[0022] In at least one embodiment, one or more trained neural networks 114 generate output data 116 based on input data 112. In at least one embodiment, one or more trained neural networks 114 perform an operation for which they were trained 102 through a training framework 106 on input data 112 to generate output data 116. In at least one embodiment, the output data 116 comprises a generated set of images, such as a 3D model 116.

[0023] In at least one embodiment, the system 100 generates, at inference 114, high-resolution 3D content from an input text prompt 112 in a coarse-to-fine manner, as shown in the Fig. 2-5 below. In at least one embodiment, a low-resolution diffusion prior is used in a first stage to optimize neural field representations (color, density, and normal patches) to obtain the coarse model. In at least one embodiment, a textured 3D mesh is differentiably extracted from the density and color patches of the coarse model. In at least one embodiment, the textured 3D mesh is fine-tuned using a high-resolution latent diffusion model. In at least one embodiment, after optimization, the model produces, at inferencing 114, high-quality 3D meshes with detailed textures.

[0024] Fig. 2 shows a quadrant image collage dataset for use in training for fine-tuning a 2D model for one or more neural networks and as used in connection with the method 400 of Fig. 4, to generate one or more three-dimensional (3D) models of an object from text based at least in part on one or more images of an object captured by two or more cameras at different angles. In at least one embodiment, this diffusion model is fine-tuned using a new data set. In at least one embodiment, a new data set includes multiple viewpoints 202, 204, 206, 208 at the same time. In at least one embodiment, a new data set including viewpoints 202, 204, 206, 208 is a data set of 3D object renderings, and these 3D auto-renderings are pre-created or generated for fine-tuning a diffusion model. In at least one embodiment, a fine-tuned 2D diffusion model enables the simultaneous modeling of what an object should look like at multiple viewpoints.In at least one embodiment, this fine-tuned diffusion model provides consistent 2D guidance when used in conjunction with the methods described in . Fig. 3-6 described systems and / or flowcharts.

[0025] Fig. 3 shows a system 300 for training one or more neural networks to generate one or more 3D models of one or more first objects based, at least in part, on four images of a second object from four viewpoints, according to at least one embodiment. In at least one embodiment, the system 300 includes four cameras 310A-D with fixed relative poses that train one or more neural networks for 3D asset optimization, as described in connection with the process 500 of Fig. 5 to generate one or more three-dimensional (3D) models of an object from text based at least in part on one or more images of an object obtained from four cameras placed at different angles. In at least one embodiment, the cameras 310A-D are randomly sampled during an iteration. In at least one embodiment, a 3D object is projected onto these cameras 310A-D, resulting in four images that are stitched together to form a collage of images in the quadrant. In at least one embodiment, this collage falls within a distribution of the viewpoint data set 202, 204, 206, 208, as described above in connection with Fig. 2. In at least one embodiment, the process 200 may be as described above in connection with Fig. 2, can be used to fine-tune a diffusion model in process 300 to update what a projection of multiple viewpoints should look like, and will inform and update a 3D model to be generated.

[0026] Fig. 4 shows an exemplary flowchart of a process 400 for generating a 3D model from a collage of 2D images, which, in at least one embodiment, includes fine-tuning the 2D model. In at least one embodiment, part or all of the process 400 (or other processes described herein, or variations and / or combinations thereof) is performed under the control of one or more computer systems, such as those described in Fig. 8-42, configured with computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that execute collectively on one or more processors, by hardware, software, or combinations thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program that includes a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, a computer-readable storage medium is a non-transitory computer-readable medium.

[0027] In at least one embodiment, process 400 may implement an algorithm as follows: Creating a data set Given: 3D assets {A1 ... A m} (3D CAD models) For each object A1 1. Random selection of N camera viewpoints with fixed relative offsets (default N=4) 2. Rendering the images (I i1 ... I N} and combine them into a collage c i . 3. (Optional) Repeat to create multiple collages 4. Output: a dataset of collage of images {c1... c K}

[0028] In at least one embodiment, a 2D model fine-tuning process 412 may randomly initialize the creation of a dataset of collage images in step 402. In at least one embodiment, this process may be initialized in another way, for example, by setting it to all zeros.

[0029] In at least one embodiment, in step 404, a data set of 3D assets {A1...A N} is provided. In at least one embodiment, the dataset of 3D assets comprises CAD models. A noise value t is set to T, a maximum noise value.

[0030] In at least one embodiment, NN viewpoints are randomly sampled with fixed relative angular offsets. In step 406, a value s g calculated. In at least one embodiment, NN = 4, as shown above. In at least one embodiment, s g as the gradient of a mean square error of an input reference image x ref (for example, a single 2D image, such as input image 202) and a rendering of a 3D model with current value from a first camera position, where R refers to a rendering function.

[0031] In at least one embodiment, as shown in lines 1-4 of the data set creation above and / or as described below with reference to Fig. 5, in step 408 images {I1...I N} rendered.

[0032] In at least one embodiment, process 400 is optionally repeated and looped back to step 408 to generate multiple collages. In at least one embodiment, these images are generated by a neural network, such as neural network 108 and / or 114, as described above and as discussed in more detail below.

[0033] In at least one embodiment, in step 410, a pre-trained diffusion model D0 is input, and in step 412, as shown, a 2D diffusion model is applied to a collage dataset {c1...c N} fine-tuned.

[0034] In at least one embodiment, a fine-tuned diffusion model D is output in step 414.

[0035] Fig. Figure 5 shows an exemplary flowchart of a process 500 that includes generating consistent 2D images with multiple views used in generating a 3D model from a single 2D image. In at least one embodiment, Fig. 5 implement an algorithm as follows.

[0036] In at least one embodiment, in step 502, a text prompt is entered to create a 3D model of a first object.

[0037] In at least one embodiment, in step 504, a learning 3D model Θ comprising hash dictionaries and at least one neural network and a fine-tuned diffusion model D are input.

[0038] In at least one embodiment, in step 506, embeddings of an input text prompt are pre-extracted from a text-to-image diffusion model.

[0039] In at least one embodiment, in step 508, a 3D asset is randomly initialized, for example, an index i is set to 1 (where the count of i can start with any value).

[0040] In at least one embodiment, in step 510, N camera viewpoints are randomly assigned as {v i1 ...v in}, with the viewpoints having the same angular offset as when fine-tuning the 2D model.

[0041] In at least one embodiment, in step 512, N selected viewpoints are rendered to create images {x i1 ...x iN} f(θ;) to obtain.

[0042] In at least one embodiment, in step 514, images {xi1...xiN} of two or more second objects are combined into a collage xi.

[0043] In at least one embodiment, in step 516, a 2D diffusion model is used to calculate an SDS guidance loss, which includes 4 substeps as follows: a) Sample, at 516A, a random time step t for a diffusion model b) Adding, at 516B, Gaussian noise to a rendered image xi(t)=xi+εi(t), where εi(t)~N(0, σ(t) I) c) Using, at 516C, a diffusion model to predict the additional noise ε^(t)~D(xi(t)) d) Calculate, at 516D, a noise difference Δεi(t)=ε^(t)−εi(t)

[0044] In at least one embodiment, in step 518 and as shown in line 5 above, the gradient descent is evaluated to determine a 3D model←Θ−λ⋅1N∑i=1N(Δεi(t)⋅∂xi(t)∂Θ) to optimize. In at least one embodiment, in step 520, i is incremented and in step 522, it is determined whether i has reached its maximum value T. In at least one embodiment, if i has reached T, the process 500 outputs s g (e.g., for use in step 412); otherwise, the process 500 returns to step 504. In at least one embodiment, the process 500 ends in step 524. In at least one embodiment, step 408 and / or lines 1-4, as described above in connection with Fig. 4 as described in Fig. 5 shown, can be implemented.

[0045] Fig. 6 shows an example 600 of a processor according to at least one embodiment. In at least one embodiment, a processor 602 performs one or more processes as described herein to cause one or more neural networks to use one or more textual descriptions to generate one or more three-dimensional (3D) models of one or more first objects based at least in part on two or more images of one or more second objects from two or more viewpoints. In at least one embodiment, the processor 602 performs an active learning process as described in connection with Fig. 1. In at least one embodiment, the processor 602 performs one or more processes as described in connection with Fig. 1-5 are described.

[0046] In at least one embodiment, the processor 602 is one or more processors as described in connection with Fig. 7-42, or otherwise includes them. In at least one embodiment, the processor 602 is any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, DPUs, and / or variations thereof. In at least one embodiment, the processor 602 includes all or any subset of the following models: a neural network training module 604 and a 3D model generation module 606. In at least one embodiment, the neural network training module 604 and the 3D model generation module 606 are part of the processor 602 and / or one or more other processors.In at least one embodiment, the neural network training module 604 and the 3D model generation module 606 are part of the processor 602 and / or one or more other processors distributed across multiple processors that communicate via a bus, a network, by writing to a shared memory, and / or any suitable communication method such as those described herein.

[0047] In at least one embodiment, as used in each implementation described herein, unless the context otherwise indicates or expressly states otherwise, a module refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions, and "hardware" as used in each embodiment described herein may include, for example, individually or in any combination, hard-wired circuitry, programmable circuitry, state machine circuitry, fixed-function circuitry, execution units, and / or firmware storing instructions executed by programmable circuitry.In at least one embodiment, modules may be implemented collectively or individually as circuits that are part of a larger system, such as an integrated circuit (IC), a system-on-chip (SoC), and so forth. In at least one embodiment, a module performs one or more processes in conjunction with any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variations thereof.

[0048] In at least one embodiment, the neural network training module 604 is a module that trains one or more neural networks. In at least one embodiment, the neural network training module 604 performs one or more processes as described herein by at least including or otherwise encoding instructions that cause the performance of the one or more processes (e.g., by the processor 602) or can otherwise be used to perform these processes. In at least one embodiment, the neural network training module 604 receives or is otherwise provided with one or more neural networks (e.g., by one or more systems as described in connection with Fig. 1). In at least one embodiment, the neural network training module 604 trains the one or more neural networks using a training data set by one or more processes as described in connection with Fig. 1-5. In at least one embodiment, the neural network training module 604 trains the one or more neural networks using any suitable training method, such as those described herein. In at least one embodiment, the 3D model generation module 606 is a module for generating 3D models of first objects based on images trained at least in part on images of one or more second objects from two or more viewpoints. For example, a 3D model generation module uses one or more neural networks to use one or more textual descriptions to generate one or more three-dimensional (3D) models of one or more first objects based, at least in part, on two or more images of one or more second objects from two or more viewpoints.In at least one embodiment, the textual description comprises text input by a user that describes an object. In at least one embodiment, the 3D model generation module 606 performs one or more processes as described herein by at least including or otherwise encoding instructions that cause the one or more processes to be performed or that can otherwise be used to perform the one or more processes (e.g., by the processor 602). In at least one embodiment, a 3D model generation module 606 comprises a network trained in conjunction with the neural network training module 604. In at least one embodiment, the 3D model generation module 606 performs data processing by one or more processes as described in conjunction with. Fig. 1-5 are described.

[0049] Fig. 7 is a block diagram 700 illustrating a driver and / or runtime including one or more libraries to provide one or more application programming interfaces (APIs) according to at least one embodiment. In at least one embodiment, a software program 702 is a software module. In at least one embodiment, the software program 702 includes one or more software modules. In at least one embodiment, a software module is Fig. 5 is not exhaustively described. In at least one embodiment, one or more APIs 710 are sets of software instructions that, when executed, instruct one or more processors (e.g., processor 502, Fig. 5) perform one or more computational operations. In at least one embodiment, one or more APIs 710 are distributed or otherwise provided as part of one or more libraries 706, drivers / runtimes 704, and / or other groupings of software and / or executable code, further described herein. In at least one embodiment, one or more APIs 710 perform one or more computational operations in response to being invoked by software programs 702.

[0050] In at least one embodiment, a software program 702 is a collection of software code, commands, instructions, or other text strings for instructing a computing device to perform one or more computational operations and / or to invoke one or more other instruction sets, such as APIs 710 or API functions 712, for execution. In at least one embodiment, the functionality provided by one or more APIs 710 includes software functions 712, such as those that can be used to accelerate one or more portions of software programs 702 using one or more parallel processing units (PPUs), such as graphics processing units (GPUs).

[0051] In at least one embodiment, APIs 710 are hardware interfaces to one or more circuits to perform one or more computational operations. In at least one embodiment, one or more software APIs 710 described herein are implemented as one or more circuits to perform one or more of the following in connection with Fig. 1-5. In at least one embodiment, one or more software programs 702 include instructions that, when executed, cause one or more hardware devices and / or circuits to perform one or more techniques described further below in connection with Fig. 1-6 are described.

[0052] In at least one embodiment, software programs 702, such as user-implemented software programs, use one or more application programming interfaces (APIs) 710 to perform various computational operations, such as memory allocation, matrix multiplication, arithmetic operations, or any computational operations performed by parallel processing units (PPUs), such as graphics processing units (GPUs), as further described herein. In at least one embodiment, one or more APIs 710 provide a set of callable functions 712, referred to herein as APIs, API functions, and / or functions, that individually perform one or more computational operations, such as computational operations related to parallel computing.For example, in one embodiment, one or more APIs 710 provide functions 712 to cause a neural network to, for example, denoise one or more audio signals based at least in part on two or more differently sized segments of one or more audio signals and / or otherwise perform operations described herein.

[0053] In at least one embodiment, one or more software programs 702 interact or communicate with one or more APIs 710 to perform one or more computational operations using one or more PPUs, such as GPUs.

[0054] In at least one embodiment, one or more computational operations using one or more PPUs include at least one or more groups of computational operations that are accelerated by execution at least in part by the one or more PPUs. In at least one embodiment, one or more software programs 702 interact with one or more APIs 710 to perform audio-to-text processing.

[0055] In at least one embodiment, an interface consists of software instructions that, when executed, provide access to one or more functions 712 provided by one or more APIs 710. In at least one embodiment, a software program 702 uses a local interface when a software developer compiles one or more software programs 702 in conjunction with one or more libraries 706 that include or otherwise provide access to one or more APIs 710. In at least one embodiment, one or more software programs 702 are statically compiled in conjunction with precompiled libraries 706 or uncompiled source code that includes instructions for executing one or more APIs 710.In at least one embodiment, one or more software programs 702 are dynamically compiled, and the one or more software programs use a linker to link to one or more precompiled libraries 706 that include one or more APIs 710.

[0056] In at least one embodiment, a software program 702 uses a remote interface when a software developer executes a software program that uses or otherwise communicates with a library 706 comprising one or more APIs 710 over a network or other remote communication medium. In at least one embodiment, one or more libraries 706 comprising one or more APIs 710 are executed by a remote computing service, such as a computing resource service provider. In another embodiment, one or more libraries 706 comprising one or more APIs 710 are executed by any other computer host that provides the one or more APIs 710 to one or more software programs 702.

[0057] In at least one embodiment, a processor (e.g., processor 502) executing or using one or more software programs 702 invokes, uses, executes, or otherwise implements one or more APIs 710 to allocate and otherwise manage memory 714 to be used by the software programs 702. In at least one embodiment, one or more software programs 702 use one or more APIs 710 to allocate and otherwise manage memory 714 to be used by one or more portions of the software programs 702 to be accelerated using one or more PPUs, such as GPUs or another accelerator or processor described herein.These software programs 702 request a neural network to perform signal processing using functions 712 that, in one embodiment, are provided by one or more APIs 710.

[0058] In at least one embodiment, API 710 is an API for facilitating parallel computing. In at least one embodiment, API 710 is any other API further described herein. In at least one embodiment, API 710 is provided by a driver and / or runtime 704. In at least one embodiment, API 710 is provided by a CUDA user-mode driver. In at least one embodiment, API 710 is provided by a CUDA runtime. In at least one embodiment, a driver (e.g., driver / runtime 704) is comprised of data values ​​and software instructions that, when executed, perform or otherwise facilitate the operation of one or more functions 712 of API 710 during the loading and execution of one or more portions of a software program 702.In at least one embodiment, a runtime 704 consists of data values ​​and software instructions that, when executed, perform or otherwise facilitate the operation of one or more functions 712 of an API 710 during execution of a software program 702. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 implemented or otherwise provided by a driver and / or runtime 704 to perform combined arithmetic operations by the one or more software programs 702 during execution by one or more PPUs, such as GPUs.

[0059] In at least one embodiment, one or more software programs 702 use one or more APIs 710 provided by a driver and / or runtime 704 to perform combined arithmetic operations of one or more PPUs, such as GPUs. In at least one embodiment, one or more APIs 710 provide combined arithmetic operations via a driver and / or runtime 704, as described above. In at least one embodiment, one or more software programs 702 use one or more APIs 710 provided by a driver and / or runtime 704 to allocate or otherwise reserve one or more memory blocks 714 to one or more PPUs, such as GPUs.In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 provided by a driver and / or runtime 704 to allocate or otherwise reserve memory blocks 714. In at least one embodiment, one or more APIs 710 invoke a neural network to cause 716 a neural network to use one or more textual descriptions to generate one or more 3D models, such as a neural network used in conjunction with the . Fig. 1-5 is described.

[0060] To improve the usability of software programs 702 and / or to optimize one or more portions of the software programs 702 to be accelerated by one or more PPUs, such as GPUs, in one embodiment, one or more APIs 710 provide one or more API functions 712 to cause 716 a neural network to use one or more textual descriptions to generate one or more 3D models, as described above and further below in connection with Fig. 1-5. In at least one embodiment, an example block diagram 700 depicts a processor (e.g., processor 1102) including one or more circuits for initiating one or more neural networks (e.g., CNNs). LOGIC

[0061] Fig. 8A shows logic 815, which, as described elsewhere herein, may be used in one or more devices to perform operations such as those discussed herein in accordance with at least one embodiment. In at least one embodiment, logic 815 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, logic 815 is inference and / or training logic. Details of logic 815 are described below in connection with Fig. 8A and / or 8B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic to provide the functions or operations described herein, where the logic may be embodied collectively or individually as circuitry that forms part of a larger system, such as an integrated circuit (IC), a system-on-chip (SoC), or one or more processors (e.g., CPU, GPU).

[0062] In at least one embodiment, logic 815 may include, without limitation, code and / or data storage 801 to store feedforward and / or output weights and / or input / output data and / or other parameters to configure neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, logic 815 may include or be coupled to code and / or data storage 801 to store graph code or other software that controls the timing and / or order in which information about weights and / or other parameters is loaded to configure logic, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)).In at least one embodiment, code, such as graph code, loads weights or other parameter information into processor ALUs based on a neural network architecture to which such code corresponds. In at least one embodiment, code and / or data storage 801 stores weight parameters and / or input / output data of each layer of a neural network being trained using aspects of one or more embodiments or used in connection with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inferencing. In at least one embodiment, any portion of code and / or data storage 801 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0063] In at least one embodiment, each portion of the code and / or data storage 801 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 801 may be a cache memory, dynamic random addressable memory ("DRAM"), static random addressable memory ("SRAM"), non-volatile memory (e.g., flash memory), or other memory.In at least one embodiment, the choice of whether the code and / or code and / or data storage 801 is, for example, internal or external to a processor or comprises DRAM, SRAM, Flash, or another type of memory may depend on the available on-chip versus off-chip memory, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inferencing and / or training a neural network, or a combination of these factors.

[0064] In at least one embodiment, logic 815 may include, without limitation, a code and / or data storage 805 to store backward and / or output weight and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 805 stores weight parameters and / or input / output data of each layer of a neural network trained during backpropagation of input / output data and / or weight parameters during training and / or inferencing using aspects of one or more embodiments or used in connection with one or more embodiments.In at least one embodiment, logic 815 may include or be coupled to code and / or data memory 805 for storing graph code or other software that controls the timing and / or order in which information about weights and / or other parameters is loaded to configure logic, including integer and / or floating-point units (collectively referred to as arithmetic logic units (ALUs)).

[0065] In at least one embodiment, code, such as graph code, causes information about weights or other parameters to be loaded into processor ALUs based on a neural network architecture to which such code corresponds. In at least one embodiment, any portion of code and / or data storage 805 may include other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 805 may be internal or external to one or more processors or other hardware logic devices or circuitry. In at least one embodiment, code and / or data storage 805 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory.In at least one embodiment, the choice of whether the code and / or data memory 805 is, for example, internal or external to a processor, or comprises DRAM, SRAM, flash memory, or another type of memory, may depend on the available on-chip versus off-chip memory, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inferencing and / or training a neural network, or a combination of these factors.

[0066] In at least one embodiment, code and / or data memory 801 and code and / or data memory 805 may be separate memory structures. In at least one embodiment, code and / or data memory 801 and code and / or data memory 805 may be a combined memory structure. In at least one embodiment, code and / or data memory 801 and code and / or data memory 805 may be partially combined and partially separate. In at least one embodiment, each portion of code and / or data memory 801 and code and / or data memory 805 may include other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0067] In at least one embodiment, logic 815 may include, without limitation, one or more arithmetic logic unit(s) ("ALU(s)") 810, including integer and / or floating-point units, to perform logical and / or mathematical operations based at least in part on or specified by training and / or inference code (e.g., graph code), the result of which may produce activations stored in activation memory 820 (e.g., output values ​​of layers or neurons within a neural network) that are functions of input / output and / or weight parameter data stored in code and / or data memory 801 and / or code and / or data memory 805.In at least one embodiment, activations stored in an activation memory 820 are generated according to linear algebraic and / or matrix-based mathematics executed by ALU(s) 810 in response to execution instructions or other code, using weight values ​​stored in code and / or data memory 805 and / or data memory 801 as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data memory 805 or code and / or data memory 801 or other on-chip or off-chip memory.

[0068] In at least one embodiment, ALU(s) 810 are included in one or more processors or other logical hardware devices or circuits, while in another embodiment, ALU(s) 810 may be external to a processor or other logical hardware device or circuit that uses them (e.g., a co-processor). In at least one embodiment, ALU(s) 810 may be included in the execution units of a processor or otherwise in a bank of ALUs accessible by the execution units of a processor, either within the same processor or distributed among different processors of different types (e.g., central processing units, graphics processing units, fixed functional units, etc.).In at least one embodiment, code and / or data memory 801, code and / or data memory 805, and enable memory 820 may share a processor or other logical hardware device or circuitry, while in another embodiment, they may be located in different processors or other logical hardware devices or circuitry, or in a combination of the same and different processors or other logical hardware devices or circuitry. In at least one embodiment, each portion of enable memory 820 may include other on-chip or off-chip data stores, including a processor's L1, L2, or L3 cache or system memory.Furthermore, the inference and / or training code may be stored along with other code accessible by a processor or other hardware logic or circuitry, and retrieved and / or processed using the fetch, decode, scheduler, execution, retiring, and / or other logic circuitry of a processor.

[0069] In at least one embodiment, the activation memory 820 may be a cache memory, a DRAM, an SRAM, a non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the activation memory 820 may be located entirely or partially within or external to one or more processors or other logic circuitry. In at least one embodiment, the choice of whether the activation memory 820 is, for example, internal or external to a processor, or comprises DRAM, SRAM, flash memory, or another type of memory, may depend on the available on-chip versus off-chip memory, the latency requirements of the training and / or inference functions performed, the batch size of the data used in inferencing and / or training a neural network, or a combination of these factors.

[0070] In at least one embodiment, the Fig. 8A may be used in conjunction with an application-specific integrated circuit (“ASIC”), such as a TensorFlow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp. In at least one embodiment, the logic 815 shown in Fig. 8A may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as field programmable gate arrays (“FPGAs”).

[0071] Fig. 8B shows logic 815 according to at least one embodiment. In at least one embodiment, logic 815 is inference and / or training logic. In at least one embodiment, logic 815 may include, without limitation, hardware logic in which computational resources associated with weight values ​​or other information corresponding to one or more layers of neurons within a neural network are dedicated or otherwise exclusively used. In at least one embodiment, the logic 815 may Fig. 8B may be used in conjunction with an application-specific integrated circuit (ASIC), such as Google's TensorFlow® Processing Unit, a Graphcore™ Inference Processing Unit (IPU), or a Nervana® (e.g., "Lake Crest") processor from Intel Corp. In at least one embodiment, the logic 815 shown in Fig. 8B may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU), or other hardware, such as field-programmable gate arrays (FPGAs). In at least one embodiment, logic 815 includes, without limitation, code and / or data memory 801 and code and / or data memory 805, which may be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, pulse values, and / or other parameter or hyperparameter information. In at least one embodiment, Fig. 8B, each code and / or data memory 801 and each code and / or data memory 805 is connected to a dedicated computing resource, such as computer hardware 802 and computer hardware 806, respectively. In at least one embodiment, each computer hardware 802 and each computer hardware 806 includes one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on information stored in the code and / or data memory 801 and the code and / or data memory 805, respectively, the result of which is stored in the activation memory 820.

[0072] In at least one embodiment, each of the code and / or data memories 801 and 805 and the corresponding computer hardware 802 and 806 correspond to different layers of a neural network, such that the resulting activation from one memory / computing pair 801 / 802 of code and / or data memory 801 and computer hardware 802 is provided as input to a next memory / computing pair 805 / 806 of code and / or data memory 805 and computer hardware 806 to reflect a conceptual organization of a neural network. In at least one embodiment, each of the memory / computing pairs 801 / 802 and 805 / 806 may correspond to more than one layer of the neural network. In at least one embodiment, additional memory / compute pairs (not shown) may be included in logic 815 subsequent to or in parallel with memory / compute pairs 801 / 802 and 805 / 806. TRAINING AND DEPLOYMENT OF A NEURAL NETWORK

[0073] Fig. 9 illustrates the training and deployment of a deep neural network according to at least one embodiment. In at least one embodiment, the untrained neural network 906 is trained using a training dataset 902. In at least one embodiment, the training framework 904 is a PyTorch framework, while in other embodiments, the training framework 904 is a TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, the training framework 904 trains an untrained neural network 906 and facilitates its training using the processing resources described herein to generate a trained neural network 908. In at least one embodiment, the weights may be selected randomly or by pre-training using a deep belief network.In at least one embodiment, the training may be performed in either a supervised, semi-supervised, or unsupervised manner.

[0074] In at least one embodiment, the untrained neural network 906 is trained using supervised learning, where the training data set 902 has an input paired with a desired output for an input, or where the training data set 902 has an input with a known output and an output of the neural network 906 is manually evaluated. In at least one embodiment, the untrained neural network 906 is trained in a supervised manner and processes inputs from the training data set 902 and compares the resulting outputs to a set of expected or desired outputs. In at least one embodiment, the errors are then backtracked through the untrained neural network 906. In at least one embodiment, the training framework 904 adjusts the weights that govern the untrained neural network 906.In at least one embodiment, the training framework 904 includes tools for monitoring the convergence of the untrained neural network 906 toward a model, e.g., the trained neural network 908, that can generate correct answers, e.g., in the output 914, based on input data, e.g., a new dataset 912. In at least one embodiment, the training framework 904 repeatedly trains the untrained neural network 906 while adjusting the weights to refine an output of the untrained neural network 906 using a loss function and an adaptation algorithm, such as stochastic gradient descent. In at least one embodiment, the training framework 904 trains the untrained neural network 906 until the untrained neural network 906 achieves the desired accuracy.In at least one embodiment, the trained neural network 908 may then be used to implement any number of machine learning operations.

[0075] In at least one embodiment, the untrained neural network 906 is trained using unsupervised learning, where the untrained neural network 906 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 902 comprises input data without associated output data, or "ground truth" data. In at least one embodiment, the untrained neural network 906 can learn groupings within the training dataset 902 and determine how individual inputs relate to the untrained dataset 902. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in a trained neural network 908 capable of performing operations useful in reducing the dimensionality of the new dataset 912.In at least one embodiment, unsupervised training may also be used to perform anomaly detection, which enables the identification of data points in the new data set 912 that deviate from normal patterns of the new data set 912.

[0076] In at least one embodiment, semi-supervised learning may be used, i.e., a technique in which the training dataset 902 includes a mixture of labeled and unlabeled data. In at least one embodiment, the training framework 904 may be used to perform incremental learning, for example, through transfer learning techniques. In at least one embodiment, incremental learning allows the trained neural network 908 to adapt to a new dataset 912 without forgetting the knowledge instilled in the trained neural network 908 during initial training.

[0077] In at least one embodiment, the training framework 904 is a framework processed in conjunction with a software development toolkit such as OpenVINO (Open Visual Inference and Neural Network Optimization). In at least one embodiment, an OpenVINO toolkit is a toolkit such as that developed by Intel Corporation of Santa Clara, CA. In at least one embodiment, OpenVINO includes logic 815 or uses logic 815 to perform the operations described herein. In at least one embodiment, an SoC, integrated circuit, or processor uses OpenVINO to perform the operations described herein.

[0078] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications, particularly neural network applications, for various tasks and operations, such as human vision emulation, speech recognition, natural language processing, recommender systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks such as convolutional neural networks (CNNs), recurrent and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries such as OpenCV, OpenCL, and / or variants thereof.

[0079] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations, such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., humans and / or objects), monocular depth estimation, image painting, style transfer, action recognition, colorization, and / or variations thereof.

[0080] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as model optimizers. In at least one embodiment, a model optimizer is a command-line tool that facilitates the transitions between training and deployment of neural network models. In at least one embodiment, a model optimizer optimizes neural network models for execution on different devices and / or processing units, such as GPU, CPU, PPU, GPGPU, and / or variations thereof. In at least one embodiment, a model optimizer generates an internal representation of a model and optimizes the model to generate an intermediate representation. In at least one embodiment, a model optimizer reduces a number of layers of a model. In at least one embodiment, a model optimizer removes layers of a model used for training.In at least one embodiment, a model optimizer performs various operations of a neural network, such as changing inputs to a model (e.g., changing the size of inputs to a model), changing the size of inputs to a model (e.g., changing the batch size of a model), changing a model structure (e.g., modifying layers of a model), normalization, standardization, quantization (e.g., converting weights of a model from a first representation, e.g., floating point, to a second representation, e.g., integer), and / or variations thereof.

[0081] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also referred to as an inference engine. In at least one embodiment, an inference engine is a C++ library or other suitable library in a programming language. In at least one embodiment, an inference engine is used to derive input data. In at least one embodiment, an inference engine implements various classes to derive input data and produce one or more results. In at least one embodiment, an inference engine implements one or more API functions to process an intermediate representation, specify input and / or output formats, and / or execute a model on one or more devices.

[0082] In at least one embodiment, OpenVINO provides various capabilities for heterogeneously executing one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems using one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions for executing a program on one or more devices. In at least one embodiment, OpenVINO provides various software functions for executing a program and / or portions of a program on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to execute a first portion of the code on a CPU and a second portion of the code on a GPU and / or FPGA.In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., a first set of layers on a first device, such as a GPU, and a second set of layers on a second device, such as a CPU).

[0083] In at least one embodiment, OpenVINO includes various functionalities similar to those associated with a CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or variants thereof. In at least one embodiment, one or more CUDA programming model operations are performed with OpenVINO. In at least one embodiment, various systems, methods, and / or techniques described herein are implemented using OpenVINO. DATA CENTER

[0084] Fig. 10 shows an exemplary data center 1000 in which at least one embodiment may be used. In at least one embodiment, the data center 1000 includes a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030, and an application layer 1040.

[0085] In at least one embodiment, as in Fig. 10, the data center infrastructure layer 1010 may include a resource orchestrator 1012, clustered compute resources 1014, and node compute resources (“Node CRs”) 1016(1)-1016(N), where “N” represents a positive integer (which may be a different integer “N” than used in other figures). In at least one embodiment, the node CRs 1016(1)-1016(N) may include any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), storage devices 1018(1)-1018(N) (e.g., dynamic read-only memory, solid-state storage, or hard disk drives), network input / output devices ("NW I / O"), network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more node CRs among the node CRs 1016(1)-1016(N) may be a server that has one or more of the computing resources listed above.

[0086] In at least one embodiment, the grouped computing resources 1014 may include separate groupings of node CRs housed in one or more racks (not shown), or multiple racks housed in data centers in different geographic locations (also not shown). In at least one embodiment, separate groupings of node CRs within the grouped computing resources 1014 may include grouped compute, network, memory, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, multiple node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads.In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0087] In at least one embodiment, resource orchestrator 1012 may configure or otherwise control one or more node CRs 1016(1)-1016(N) and / or grouped computing resources 1014. In at least one embodiment, resource orchestrator 1012 may include a software design infrastructure ("SDI") management entity of data center 1000. In at least one embodiment, resource orchestrator 1012 may include hardware, software, or a combination thereof.

[0088] In at least one embodiment, as in Fig. 10, the framework layer 1020 includes a job scheduler 1022, a configuration manager 1024, a resource manager 1026, and a distributed file system 1028. In at least one embodiment, the framework layer 1020 may include a framework for supporting the software 1032 of the software layer 1030 and / or one or more applications 1042 of the application layer 1040. In at least one embodiment, the software 1032 or the application(s) 1042 may each include web-based service software or applications such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1020 may be some type of free and open source software web application framework such as Apache Spark™ (hereinafter "Spark"), which may utilize a distributed file system 1028 for processing large amounts of data (e.g., "Big Data"), but is not limited thereto.In at least one embodiment, job scheduler 1022 may include a Spark driver to facilitate scheduling workloads supported by different layers of data center 1000. In at least one embodiment, configuration manager 1024 may be capable of configuring different layers, such as software layer 1030 and framework layer 1020, which include Spark and distributed file system 1028 to support processing large amounts of data. In at least one embodiment, resource manager 1026 may be capable of managing clustered or grouped compute resources allocated to support distributed file system 1028 and job scheduler 1022. In at least one embodiment, clustered or grouped compute resources may include grouped compute resources 1014 in data center infrastructure layer 1010.In at least one embodiment, the resource manager 1026 may be coordinated with the resource orchestrator 1012 to manage these allocated or assigned computing resources.

[0089] In at least one embodiment, the software 1032 included in software layer 1030 may include software used by at least portions of node CRs 1016(1)-1016(N), clustered computer systems 1014, and / or distributed file systems 1028 of framework layer 1020. In at least one embodiment, one or more types of software may include, but are not limited to, internet website search software, email virus scanning software, database software, and streaming video content software.

[0090] In at least one embodiment, the application(s) 1042 included in the application layer 1040 may include one or more types of applications used by at least portions of the node CRs 1016(1)-1016(N), clustered computing resources 1014, and / or the distributed file system 1028 of the framework layer 1020. In at least one embodiment, one or more types of applications may include any number of a genomic application, a cognitive computing application, and a machine learning application, including, but not limited to, training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in connection with one or more embodiments.

[0091] In at least one embodiment, configuration manager 1024, resource manager 1026, and resource orchestrator 1012 may implement any number and type of self-modifying actions based on any amount and type of data collected in any technically feasible manner. In at least one embodiment, self-modifying actions may relieve an operator of a data center 1000 from making potentially poor configuration decisions and potentially avoiding underutilized and / or poorly performing sections of a data center.

[0092] In at least one embodiment, data center 1000 may include tools, services, software, or other resources to train one or more machine learning models or to predict or infer information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weighting parameters according to a neural network architecture using software and computational resources described above with respect to data center 1000.In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to the data center 1000 by using weighting parameters calculated by one or more training techniques described herein.

[0093] In at least one embodiment, the data center may utilize CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or inference using the resources described above. Furthermore, one or more of the software and / or hardware resources described above may be configured as a service to enable users to train or infer information, such as image recognition, speech recognition, or other artificial intelligence services.

[0094] Logic 815 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 815 are described herein in connection with Fig. 8A and / or 8B. In at least one embodiment, logic 815 may be used in data center 1000 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or the neural network use cases described herein.

[0095] In at least one embodiment, the data center 1000 may be used to host the system 100 (see Fig. 1), the collage 200 (see Fig. 2), the System 300 (see Fig. 3), process 400 (see Fig. 4) and / or process 500 (see Fig. 5). In at least one embodiment, at least a portion of the Fig. 10 depicted system(s) to implement one or more systems, techniques, functions and / or processes that are used in conjunction with Fig. 1-7. For example, in at least one embodiment, at least one Fig. 10 may be used to cause one or more neural networks to use one or more textual descriptions to generate one or more 3D models of one or more first objects in accordance with one or more techniques, functions and / or processes described with respect to one of the Fig. 1-7 are described. Autonomous vehicle

[0096] Fig. 11A shows an example of an autonomous vehicle 1100 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 1100 (alternatively referred to herein as "vehicle 1100") may be, without limitation, a passenger vehicle, such as a car, a truck, a bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, the vehicle 1100 may be a semi-trailer truck used for transporting goods. In at least one embodiment, the vehicle 1100 may be an aircraft, a robotic vehicle, or another type of vehicle.

[0097] Autonomous vehicles may be described in terms of automation levels defined by the National Highway Traffic Safety Administration ("NHTSA"), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers ("SAE") "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806, published June 15, 2018, Standard No. J3016-201609, published September 30, 2016, and prior and future versions of this standard). In at least one embodiment, the vehicle 1100 may be capable of performing functions according to one or more of Levels 1 through Level 5 of autonomous driving. For example, in at least one embodiment, the vehicle 1100 may be capable of conditionally automated (Level 3), highly automated (Level 4), and / or fully automated (Level 5), depending on the embodiment.

[0098] In at least one embodiment, vehicle 1100 may include, without limitation, components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle. In at least one embodiment, vehicle 1100 may include, without limitation, a propulsion system 1150, such as an internal combustion engine, a hybrid-electric power plant, an all-electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1150 may be connected to a drivetrain of vehicle 1100, which may include, without limitation, a transmission, to enable propulsion of vehicle 1100. In at least one embodiment, propulsion system 1150 may be controlled in response to receiving signals from one or more gas pedals / accelerators 1152.

[0099] In at least one embodiment, a steering system 1154, which may include, without limitation, a steering wheel, is used to steer the vehicle 1100 (e.g., along a desired path or route) when the propulsion system 1150 is operating (e.g., when the vehicle 1100 is in motion). In at least one embodiment, the steering system 1154 may receive signals from the steering actuator(s) 1156. In at least one embodiment, a steering wheel may be optional for full automation functionality (Level 5). In at least one embodiment, a brake sensor system 1146 may be used to apply the vehicle brakes in response to receiving signals from brake actuator(s) 1148 and / or brake sensors.

[0100] In at least one embodiment, the controller(s) 1136, which may include, without limitation, one or more system-on-chips (“SoCs”) (in Fig. 11A not shown) and / or graphics processing unit(s) ("GPU(s)"), send signals (e.g., representative of commands) to one or more components and / or systems of the vehicle 1100. For example, in at least one embodiment, the controller(s) 1136 may send signals to actuate the vehicle brakes via the brake actuator(s) 1148, to actuate the steering system 1154 via the steering actuator(s) 1156, and to actuate the propulsion system 1150 via the accelerator pedal(s) 1152. In at least one embodiment, the controller(s) 1136 may include one or more built-in (e.g., integrated) computing devices that process sensor signals and issue operational commands (e.g., signals representing commands) to enable autonomous driving and / or to assist a human driver in operating the vehicle 1100.In at least one embodiment, controller(s) 1136 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for emergency redundancy, and / or other controllers. In at least one embodiment, a single controller may perform two or more of the above functions, two or more controllers may perform a single function, and / or any combination thereof.

[0101] In at least one embodiment, the controller(s) 1136 provide(s) signals to control one or more components and / or systems of the vehicle 1100 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be obtained, for example and without limitation, from one or more GNSS sensors 1158 (e.g., Global Positioning System sensors), one or more RADAR sensors 1160, one or more ultrasonic sensors 1162, one or more LIDAR sensors 1164, one or more inertial measurement unit (“IMU”) sensors 1166 (e.g., accelerometers, gyroscopes, magnetic compasses, magnetometers, etc.), microphone(s) 1196, stereo camera(s) 1168, wide-angle camera(s) 1170 (e.g., fisheye cameras), infrared camera(s) 1172, environmental camera(s) 1174 (e.g., 360-degree cameras), long-range cameras (in Fig. 11A not shown), mid-range camera(s) (in Fig. 11A not shown), speed sensor(s) 1144 (e.g., for measuring the speed of the vehicle 1100), vibration sensor(s) 1142, steering sensor(s) 1140, brake sensor(s) (e.g., as part of the brake sensor system 1146), and / or other types of sensors.

[0102] In at least one embodiment, one or more of the controllers 1136 may receive inputs (e.g., represented by input data) from an instrument cluster 1132 of the vehicle 1100 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1134, an audible annunciator, a speaker, and / or via other components of the vehicle 1100. In at least one embodiment, the output data may include information such as vehicle speed, RPM, time, map information (e.g., a high-resolution map (in Fig. 11A not shown)), location data (e.g., the location of the vehicle 1100, e.g., on a map), direction, location of other vehicles (e.g., a grid), information about objects and the status of objects as perceived by the controller(s) 1136, etc. For example, in at least one embodiment, the HMI display 1134 may include information about the presence of one or more objects (e.g., a road sign, a warning sign, a changing traffic light, etc.) and / or information about maneuvers the vehicle has performed, is currently performing, or will perform (e.g., lane change now, exit 34B in two miles, etc.).

[0103] In at least one embodiment, the vehicle 1100 further includes a network interface 1124 that may utilize wireless antenna(s) 1126 and / or modem(s) to communicate over one or more networks. For example, in at least one embodiment, the network interface 1124 may be capable of communicating over Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communication ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, etc. In at least one embodiment, the wireless antenna(s) 1126 may also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using local area networks such as Bluetooth, Bluetooth Low Energy ("LE"), Z-Wave, ZigBee, etc., and / or low-power wide area networks ("LPWANs") such as LoRaWAN, SigFox, etc.

[0104] Logic 815 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 815 are described herein in connection with Fig. 8A and / or 8B. In at least one embodiment, logic 815 in vehicle 1100 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0105] In at least one embodiment, the vehicle 1100 may be used to implement the system 100 (see Fig. 1), the collage 200 (see Fig. 2), the System 300 (see Fig. 3), process 400 (see Fig. 4) and / or process 500 (see Fig. 5). In at least one embodiment, at least a portion of the Fig. 11 depicted system(s) to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-7. For example, in at least one embodiment, at least one Fig. 11 may be used to cause one or more neural networks to use one or more textual descriptions to generate one or more 3D models of one or more first objects in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-7 are described.

[0106] Fig. 11B shows an example of camera positions and fields of view for the autonomous vehicle 1100 of Fig. 11A according to at least one embodiment. In at least one embodiment, the cameras and the respective fields of view represent an exemplary embodiment and are not to be considered limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be arranged at different locations on the vehicle 1100.

[0107] In at least one embodiment, the camera types for cameras may include, but are not limited to, digital cameras that may be adapted for use with components and / or systems of the vehicle 1100. In at least one embodiment, the camera(s) may operate at Automotive Safety Integrity Level ("ASIL") B and / or another ASIL. In at least one embodiment, the camera types may achieve any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the cameras may use rolling shutter, global shutter, another shutter type, or a combination thereof.In at least one embodiment, the color filter array may include a red-clear-clear color filter array ("RCCC"), a red-clear-blue color filter array ("RCCB"), a red-blue-green clear color filter array ("RBGC"), a Foveon X3 color filter array, a Bayer sensor color filter array ("RGGB"), a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, clear-pixel cameras, such as cameras with an RCCC, an RCCB, and / or an RBGC color filter array, may be used to increase light sensitivity.

[0108] In at least one embodiment, one or more cameras may be used to implement advanced driver assistance systems ("ADAS") (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multifunction mono camera may be installed, including functions such as lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more of the cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0109] In at least one embodiment, one or more cameras may be mounted in a mounting fixture, such as a custom-designed (three-dimensional ("3D") printed) fixture, to eliminate stray light and reflections within the vehicle 1100 (e.g., reflections from the dashboard reflected in the windshield mirrors) that may impair the camera's ability to capture images. With respect to the mounting of exterior mirrors, in at least one embodiment, the exterior mirrors may be custom 3D printed such that a camera mounting plate conforms to the shape of an exterior mirror. In at least one embodiment, camera(s) may be integrated into the exterior mirrors. In at least one embodiment, for side-facing cameras, the camera(s) may also be integrated into four pillars at each corner of the cabin.

[0110] In at least one embodiment, cameras with a field of view encompassing portions of an environment in front of the vehicle 1100 (e.g., forward-facing cameras) may be used for the environmental view to help identify forward paths and obstacles, and to provide information critical to generating an occupancy grid and / or determining preferred vehicle paths with the assistance of one or more controllers 1136 and / or control SoCs. In at least one embodiment, forward-facing cameras may be used to perform many similar ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance.In at least one embodiment, forward-facing cameras may also be used for ADAS features and systems, including, without limitation, lane departure warnings (“LDW”), autonomous cruise control (“ACC”), and / or other features such as traffic sign recognition.

[0111] In at least one embodiment, a plurality of cameras may be used in a forward-facing configuration, including, for example, a monocular camera platform comprising a CMOS (complementary metal oxide semiconductor) color imager. In at least one embodiment, a wide-angle camera 1170 may be used to detect objects entering view from the periphery (e.g., pedestrians, crossing traffic, or bicycles). Although in Fig. 11B shows only one wide-angle camera 1170, in other embodiments, the vehicle 1100 may include any number of wide-angle cameras (including zero). In at least one embodiment, any number of long-range cameras 1198 (e.g., a long-range stereo camera pair) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the long-range camera(s) 1198 may also be used for object detection and classification, as well as basic object tracking.

[0112] In at least one embodiment, any number of stereo cameras 1168 may also be in a forward-facing configuration. In at least one embodiment, one or more of the stereo cameras 1168 may include an integrated control unit comprising a scalable processing unit that may provide a programmable logic ("FPGA") and a multi-core microprocessor with an integrated network interface ("CAN") or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 1100 that includes a distance estimate for all points in an image.In at least one embodiment, one or more of the stereo camera(s) 1168 may comprise, without limitation, compact stereo vision sensors, which may comprise, without limitation, two camera lenses (one each on the left and right) and an image processing chip that can measure the distance between the vehicle 1100 and the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo camera(s) 1168 may be used in addition to or alternatively to those described herein.

[0113] In at least one embodiment, cameras with a field of view encompassing portions of the environment on the sides of the vehicle 1100 (e.g., side cameras) may be used for the environment view and provide information used to create and update a grid, as well as to generate side impact collision warnings. In at least one embodiment, for example, environment camera(s) 1174 (e.g., four environment cameras, as in Fig. 11B) may be positioned on the vehicle 1100. In at least one embodiment, the surround camera(s) 1174 may include, without limitation, any number and combination of wide-angle cameras, fisheye cameras, 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye cameras may be positioned on a front, a rear, and the sides of the vehicle 1100. In at least one embodiment, the vehicle 1100 may employ three surround camera(s) 1174 (e.g., left, right, and rear) and may employ one or more other cameras (e.g., a forward-facing camera) as a fourth surround camera.

[0114] In at least one embodiment, cameras with a field of view that includes portions of an environment behind the vehicle 1100 (e.g., rearview cameras) may be used for parking assistance, surround view, rear collision warnings, and grid creation and updating. In at least one embodiment, a variety of cameras may be used that are also suitable as forward-facing cameras (e.g., long-range cameras 1198 and / or mid-range camera(s) 1176, stereo camera(s) 1168, infrared camera(s) 1172, etc.), as described herein.

[0115] In at least one embodiment, the vehicle 1100 may be used to implement the system 100 (see Fig. 1), the collage 200 (see Fig. 2), the System 300 (see Fig. 3), process 400 (see Fig. 4) and / or process 500 (see Fig. 5). In at least one embodiment, at least a portion of the Fig. 10 depicted system(s) to implement one or more systems, techniques, functions and / or processes that are used in conjunction with Fig. 1-7. For example, in at least one embodiment, at least one Fig. 11B may be used to cause one or more neural networks to use one or more textual descriptions to generate one or more 3D models of one or more first objects in accordance with one or more techniques, functions and / or processes described with respect to one of the Fig. 1-7 are described.

[0116] Fig. 11C is a block diagram illustrating an example system architecture for the autonomous vehicle 1100 of Fig. 11A according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 1100 is Fig. 11C as connected via a bus 1102. In at least one embodiment, bus 1102 may include, without limitation, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, a CAN may be a network within vehicle 1100 used to support the control of various features and functions of vehicle 1100, such as brake application, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 1102 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1102 may be read to determine steering wheel angle, vehicle speed, engine speed per minute (RPM), button positions, and / or other vehicle status information.In at least one embodiment, bus 1102 may be a CAN bus that is ASIL B compliant.

[0117] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or alternatively to CAN. In at least one embodiment, there may be any number of buses that comprise bus 1102, which may include, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses with different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functionality and a second bus may be used for actuation control.In at least one embodiment, each bus of bus 1102 can communicate with any components of vehicle 1100, and two or more buses of bus 1102 can communicate with corresponding components. In at least one embodiment, each of any number of system(s) on chip(s) ("SoC(s)") 1104 (such as SoC 1104(A) and SoC 1104(B)), each of controllers 1136, and / or each computer within the vehicle can have access to the same input data (e.g., inputs from sensors of vehicle 1100) and be connected to a common bus, such as a CAN bus.

[0118] In at least one embodiment, the vehicle 1100 may include one or more controllers 1136 as described herein with respect to Fig. 11A. In at least one embodiment, the controller(s) 1136 may be used for a variety of functions. In at least one embodiment, the controller(s) 1136 may be coupled to various other components and systems of the vehicle 1100 and used for control of the vehicle 1100, the artificial intelligence of the vehicle 1100, the infotainment of the vehicle 1100, and / or other functions.

[0119] In at least one embodiment, the vehicle 1100 may include any number of SoCs 1104. In at least one embodiment, each of the SoCs 1104 may include, without limitation, central processing units ("CPU(s)") 1106, graphics processing units ("GPU(s)") 1108, processor(s) 1110, cache(s) 1112, accelerators 1114, data storage 1116, and / or other components and features not shown. In at least one embodiment, SoC(s) 1104 may be used to control the vehicle 1100 in a variety of platforms and systems. For example, in at least one embodiment, SoC(s) 1104 may be combined in a system (e.g., system of the vehicle 1100) with a high-definition ("HD") card 1122 that may be accessed via the network interface 1124 from one or more servers (in Fig. 11C not shown) can receive map updates and / or updates.

[0120] In at least one embodiment, the CPU(s) 1106 may comprise a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, the CPU(s) 1106 may comprise multiple cores and / or level two ("L2") caches. For example, in at least one embodiment, the CPU(s) 1106 may comprise eight cores in a coherent multiprocessor configuration. In at least one embodiment, the CPU(s) 1106 may comprise four dual-core clusters, each cluster having a dedicated L2 cache (e.g., a 2-megabyte (MB) L2 cache). In at least one embodiment, the CPU(s) 1106 (e.g., CCPLEX) may be configured to support concurrent cluster operations, such that any combination of clusters of the CPU(s) 1106 may be active at any given time.

[0121] In at least one embodiment, one or more of the CPU(s) 1106 may implement power management features, including, without limitation, one or more of the following features: individual hardware blocks may be automatically clocked when idle to conserve dynamic power; each core clock may be clocked when such core is not actively executing instructions due to the execution of Wait for Interrupt ("WFI") / Wait for Event ("WFE") instructions; each core may be independently power-driven; each core cluster may be independently clock-driven if all cores are clock-driven or power-driven; and / or each core cluster may be independently power-driven if all cores are power-driven.In at least one embodiment, CPU(s) 1106 may further implement an enhanced power state management algorithm, specifying allowable power states and expected wake-up times, and hardware / microcode determines which power state is most appropriate for the core, cluster, and CCPLEX. In at least one embodiment, processing cores may support simplified sequences for entering power states in software, offloading the work to microcode.

[0122] In at least one embodiment, the GPU(s) 1108 may comprise an integrated GPU (alternatively referred to herein as an "iGPU"). In at least one embodiment, the GPU(s) 1108 may be programmable and efficient for parallel workloads. In at least one embodiment, the GPU(s) 1108 may use an extended instruction set for tensors. In at least one embodiment, the GPU(s) 1108 may comprise one or more streaming microprocessors, where each streaming microprocessor may comprise a Level 1 ("L1") cache (e.g., an L1 cache with a memory capacity of at least 96 KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with a memory capacity of 512 KB). In at least one embodiment, the GPU(s) 1108 may comprise at least eight streaming microprocessors.In at least one embodiment, GPU(s) 1108 may use application programming interface(s) (API(s)) for computation. In at least one embodiment, GPU(s) 1108 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0123] In at least one embodiment, one or more of the GPU(s) 1108 may be power-optimized for best performance in automotive and embedded use cases. For example, in at least one embodiment, the GPU(s) 1108 may be fabricated on fin field-effect transistor ("FinFET") circuits. In at least one embodiment, each streaming microprocessor may include a number of mixed-precision processing cores divided into multiple blocks. For example, 64 PF32 cores and 32 FP64 cores could be divided into four processing blocks. In at least one embodiment, each processing block could be associated with 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two NVIDIA Tensor cores with mixed precision for deep learning matrix arithmetic, a level zero ("L0") instruction cache, a scheduler (e.g., warp scheduler) or sequencer, a dispatch unit, and / or a 64 KB register file.In at least one embodiment, streaming microprocessors may include independent parallel integer and floating-point datapaths to enable efficient execution of workloads with a mix of computations and addressing calculations. In at least one embodiment, streaming microprocessors may include independent thread scheduling capability to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, streaming microprocessors may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0124] In at least one embodiment, one or more of the GPU(s) 1108 may include high-bandwidth memory ("HBM") and / or a 16 GB HBM2 memory subsystem to provide, in some examples, a peak memory bandwidth of approximately 900 GB / second. In at least one embodiment, in addition to or alternatively to the HBM memory, a synchronous graphics random-access memory ("SGRAM") may be used, such as a synchronous graphics double-data-rate random-access memory type 5 ("GDDR5").

[0125] In at least one embodiment, the GPU(s) 1108 may include a unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to allow the GPU(s) 1108 to directly access page tables of the CPU(s) 1106. In at least one embodiment, an address translation request may be communicated to the CPU(s) 1106 when a GPU of the GPU(s) 1108 memory management unit ("MMU") encounters a fault. In response, the CPU of the CPU(s) 1106 may look up a virtual-physical mapping for an address in its page tables and transmit the translation back to the GPU(s) 1108, in at least one embodiment.In at least one embodiment, unified memory technology may enable a single unified virtual address space for the memory of both the CPU(s) 1106 and the GPU(s) 1108, thereby simplifying programming of the GPU(s) 1108 and porting applications to the GPU(s) 1108.

[0126] In at least one embodiment, the GPU(s) 1108 may include any number of access counters that can track the frequency of access by the GPU(s) 1108 to the memory of other processors. In at least one embodiment, access counters can help ensure that memory pages are moved to the physical memory of a processor that accesses pages most frequently, thereby improving the efficiency of memory regions shared between processors.

[0127] In at least one embodiment, one or more of the SoC(s) 1104 may include any number of cache(s) 1112, including those described herein. For example, in at least one embodiment, the cache(s) 1112 may include a Level 3 ("L3") cache available to both the CPU(s) 1106 and the GPU(s) 1108 (e.g., connected to the CPU(s) 1106 and the GPU(s) 1108). In at least one embodiment, the cache(s) 1112 may include a write-back cache that can track line states, for example, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, an L3 cache may include 4 MB of memory or more, depending on the embodiment, although smaller cache sizes may also be used.

[0128] In at least one embodiment, one or more of the SoC(s) 1104 may include one or more accelerators 1114 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoC(s) 1104 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4 MB of SRAM) may enable a hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, a hardware acceleration cluster may be used to supplement the GPU(s) 1108 and offload some tasks from the GPU(s) 1108 (e.g., to free up more cycles of the GPU(s) 1108 to perform other tasks).In at least one embodiment, the accelerator(s) 1114 could be used for targeted workloads (e.g., perception, convolutional neural networks ("CNNs"), recurrent neural networks ("RNNs"), etc.) that are robust enough to be suitable for acceleration. In at least one embodiment, a CNN may include a region-based or regional convolutional neural network ("RCNNs") and fast RCNNs (e.g., for object detection), or another type of CNN.

[0129] In at least one embodiment, the accelerator(s) 1114 (e.g., hardware acceleration clusters) may include one or more deep learning accelerators ("DLAs"). In at least one embodiment, the DLA(s) may include, without limitation, one or more tensor processing units ("TPUs") that may be configured to provide an additional tens of trillion operations per second for deep learning applications and inferencing. In at least one embodiment, TPUs may be accelerators configured and optimized to perform image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, the DLA(s) may be further optimized for a particular set of neural network types and floating-point operations, as well as for inferencing.In at least one embodiment, the design of DLA(s) can provide more performance per millimeter than a typical general-purpose GPU, typically far exceeding the performance of a CPU. In at least one embodiment, the TPU(s) can perform multiple functions, including a single-instance convolution function, supporting, for example, INT8, INT16, and FP16 data types for both features and weights, as well as post-processing functions.In at least one embodiment, DLA(s) can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for a variety of functions, including, for example and without limitation: a CNN for object identification and recognition using data from camera sensors; a CNN for distance estimation using data from camera sensors; a CNN for emergency vehicle detection and identification and recognition using data from microphones; a CNN for facial recognition and vehicle owner identification using data from camera sensors; and / or a CNN for safety-relevant and / or security-related events.

[0130] In at least one embodiment, the DLA(s) may perform any function of the GPU(s) 1108, and by using an inference accelerator, a developer may, for example, target either the DLA(s) or the GPU(s) 1108 for each function. For example, in at least one embodiment, a developer may focus the processing of CNNs and floating-point operations on the DLA(s) and leave other functions to the GPU(s) 1108 and / or accelerator(s) 1114.

[0131] In at least one embodiment, the accelerator(s) 1114 may comprise a programmable image processing accelerator ("PVA"), which may also be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate image processing algorithms for advanced driver assistance systems (ADAS) 1138, autonomous driving, augmented reality (AR) applications, and / or virtual reality (VR) applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may comprise, without limitation, any number of reduced instruction set ("RISC") cores, direct memory access ("DMA") cores, and / or any number of vector processors.

[0132] In at least one embodiment, RISC cores may interact with image sensors (e.g., image sensors of cameras described herein), image signal processor(s), etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, the RISC cores may use any number of protocols, depending on the embodiment. In at least one embodiment, RISC cores may execute a real-time operating system ("RTOS"). In at least one embodiment, RISC cores may be implemented with one or more integrated circuits, application-specific integrated circuits ("ASICs"), and / or memory devices. In at least one embodiment, RISC cores could, for example, include an instruction cache and / or tightly coupled RAM.

[0133] In at least one embodiment, DMA may enable components of the PVA to access system memory independently of the CPU(s) 1106. In at least one embodiment, DMA may support any number of features used to optimize a PVA, including, but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, DMA may support up to six or more dimensions of addressing, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0134] In at least one embodiment, vector processors may be programmable processors that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing functions. In at least one embodiment, a PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, a PVA core may include a processor subsystem, DMA engine(s) (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, a vector processing subsystem may operate as the primary engine of a PVA and include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM").In at least one embodiment, the VPU core may include a digital signal processor, such as a single instruction multiple data ("SIMD") and very long instruction word ("VLIW") digital signal processor. In at least one embodiment, a combination of SIMD and VLIW may increase throughput and speed.

[0135] In at least one embodiment, each of the vector processors may include an instruction cache and be connected to dedicated memory. Consequently, in at least one embodiment, each vector processor may be configured to operate independently of other vector processors. In at least one embodiment, vector processors included in a particular PVA may be configured to use data parallelism. For example, in at least one embodiment, a plurality of vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image.In at least one embodiment, the vector processors included in a particular PVA may simultaneously execute different image processing algorithms on an image, or even different algorithms on consecutive images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in a hardware acceleration cluster, and each PVA may include any number of vector processors. In at least one embodiment, the PVA may include additional error-correcting code ("ECC") memory to increase the security of the overall system.

[0136] In at least one embodiment, the accelerator(s) 1114 may include an on-chip computer vision network and static random access memory ("SRAM") to provide high-bandwidth, low-latency SRAM for the accelerator(s) 1114. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, including, for example and without limitation, eight field-configurable memory blocks accessible by both a PVA and a DLA. In at least one embodiment, each pair of memory blocks may include an extended peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used.In at least one embodiment, a PVA and a DLA may access the memory via a backbone that provides high-speed access to the memory for a PVA and a DLA. In at least one embodiment, a backbone may include an on-chip computer vision network that interconnects a PVA and a DLA to the memory (e.g., using APB).

[0137] In at least one embodiment, an on-chip computer vision network may include an interface that determines that both a PVA and a DLA are providing ready and valid signals before transmitting control signals / addresses / data. In at least one embodiment, an interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst communication for continuous data transmission. In at least one embodiment, an interface may conform to International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0138] In at least one embodiment, one or more of the SoC(s) 1104 may include a hardware accelerator for real-time ray tracing. In at least one embodiment, the real-time ray tracing hardware accelerator may be used for quickly and efficiently determining positions and extents of objects (e.g., within a world model), generating real-time visualization simulations, radar signal interpretation, sound propagation synthesis and / or analysis, simulating sonar systems, general wave propagation simulation, comparing with lidar data for localization and / or other functions, and / or for other purposes.

[0139] In at least one embodiment, the accelerator(s) 1114 may have a wide range of applications for autonomous driving. In at least one embodiment, a PVA may be used for critical processing steps in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of a PVA are well suited to algorithmic domains that require predictable, low-power, and low-latency processing. In other words, a PVA is well suited for semi-dense or dense regular computations, even on small datasets, that require predictable runtimes with low latency and low power consumption. In at least one embodiment, such as in vehicle 1100, PVAs may be designed to execute classical computer vision algorithms because they can be efficient at object detection and integer math processing.

[0140] For example, according to at least one embodiment of the technology, a PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, motion estimation / stereo matching while driving is used in Level 3-5 autonomous driving applications (e.g., structure from motion, pedestrian detection, lane detection, etc.). In at least one embodiment, a PVA may perform computer stereo vision functions on inputs from two monocular cameras.

[0141] In at least one embodiment, a PVA may be used to perform dense optical flow. In at least one embodiment, a PVA could, for example, process raw radar data (e.g., using a 4D Fast Fourier Transform) to provide processed radar data. In at least one embodiment, a PVA is used for depth-of-flight processing, processing raw time-of-flight data to provide, for example, processed time-of-flight data.

[0142] In at least one embodiment, a DLA may be used to power any type of network to improve control and driving safety, including, for example and without limitation, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, confidence may be represented or interpreted as a probability, or as the relative "weight" of each detection compared to other detections. In at least one embodiment, a confidence measure allows the system to make further decisions about which detections should be considered true positives and which should be considered false positives. In at least one embodiment, a system may set a threshold for the confidence measure and consider only detections that exceed the threshold as true positives.In an embodiment using an automatic emergency braking ("AEB") system, false positive detections would cause the vehicle to automatically perform emergency braking, which is clearly undesirable. In at least one embodiment, highly confident detections can be considered as triggers for AEB. In at least one embodiment, a DLA can employ a neural network to regress the confidence value.In at least one embodiment, the neural network may use as input at least a subset of parameters, such as the dimensions of the bounding box, the ground plane estimate obtained (e.g., from another subsystem), the output of the IMU sensor(s) 1166 correlated with the orientation of the vehicle 1100, the range, the 3D position estimates of the object obtained from the neural network and / or other sensors (e.g., LIDAR sensor(s) 1164 or RADAR sensor(s) 1160), and others.

[0143] In at least one embodiment, one or more SoC(s) 1104 may include one or more data stores 1116 (e.g., memories). In at least one embodiment, the data store(s) 1116 may be on-chip memory of the SoC(s) 1104, which may store neural networks to be executed on the GPU(s) 1108 and / or a DLA. In at least one embodiment, the data store(s) 1116 may be large enough to store multiple neural network instances for redundancy and security. In at least one embodiment, the data store(s) 1116 may include L2 or L3 cache(s).

[0144] In at least one embodiment, one or more of the SoC(s) 1104 may include any number of processor(s) 1110 (e.g., embedded processors). In at least one embodiment, the processor(s) 1110 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions and associated security enforcement. In at least one embodiment, a boot and power management processor may be part of a boot sequence of SoC(s) 1104 and provide runtime power management services.In at least one embodiment, a processor for boot power and management may provide clock and voltage programming, support for low-power state transitions, manage the thermal and temperature sensors of the SoC(s) 1104, and / or manage the power states of the SoC(s) 1104. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and SoC(s) 1104 may use ring oscillators to sense the temperatures of the CPU(s) 1106, GPU(s) 1108, and / or accelerator(s) 1114.In at least one embodiment, when temperatures are determined to exceed a threshold, a boot and power management processor may enter a temperature fault routine and place the SoC(s) 1104 into a lower power state and / or place the vehicle 1100 into a chauffeur-to-safe-stop mode (e.g., bring the vehicle 1100 to a safe stop).

[0145] In at least one embodiment, processor(s) 1110 may further comprise a set of embedded processors that may serve as an audio processing engine, which may be an audio subsystem enabling full hardware support for multi-channel audio across multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, an audio processing engine is a dedicated processing core including a digital signal processor with dedicated RAM.

[0146] In at least one embodiment, the processor(s) 1110 may further include an "always on" processor engine that may provide the necessary hardware functions to support low-power sensor management and wake use cases. In at least one embodiment, an "always on" processor engine may include, without limitation, a processor core, tightly coupled memory, supporting peripherals (e.g., timers and interrupt controllers), various I / O control peripherals, and routing logic.

[0147] In at least one embodiment, the processor(s) 1110 may further comprise a safety cluster engine, including, without limitation, a dedicated processor subsystem for handling safety management for automotive applications. In at least one embodiment, a safety cluster engine may include, without limitation, two or more processor cores, tightly coupled memory, supporting peripherals (e.g., timers, an interrupt controller, etc.), and / or routing logic. In a safety mode, in at least one embodiment, two or more cores may operate in a lockstep mode, functioning as a single core with comparison logic for detecting differences between their operations.In at least one embodiment, the processor(s) 1110 may further comprise a real-time camera engine, which may include, without limitation, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, the processor(s) 1110 may further comprise a high dynamic range signal processor, which may include, without limitation, an image signal processor that is a hardware engine that is part of a camera processing pipeline.

[0148] In at least one embodiment, processor(s) 1110 may include a video image compositor, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image for a player window. In at least one embodiment, a video image compositor may perform lens distortion correction on the wide-angle camera(s) 1170, the surround camera(s) 1174, and / or the in-booth surveillance camera(s) sensors. In at least one embodiment, the in-booth surveillance camera(s) sensor(s) is / are preferably monitored by a neural network running on another instance of SoC 1104 and configured to identify and respond to events in the booth.In at least one embodiment, a system within the vehicle may perform lip reading without limitation to activate cellular service and place a call, dictate emails, change a vehicle's destination, activate or change a vehicle's infotainment system and settings, or enable voice-activated internet browsing. In at least one embodiment, certain functions are available to the driver when a vehicle is operating in an autonomous mode and are disabled otherwise.

[0149] In at least one embodiment, a video image compositor may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment where motion occurs in a video, the noise reduction appropriately weights spatial information and reduces the weight of information provided by adjacent frames. In at least one embodiment where an image or a portion of an image does not include motion, the temporal noise reduction performed by the video image compositor may use information from a previous frame to reduce noise in the current frame.

[0150] In at least one embodiment, a video image compositor may also be configured to perform stereo rectification on the input stereo lens images. In at least one embodiment, a video image compositor may further be used for user interface composition when an operating system desktop is in use and the GPU(s) 1108 are not required to continuously render new surfaces. In at least one embodiment, a video image compositor may be used to offload the GPU(s) 1108 to improve performance and responsiveness when the GPU(s) 1108 are turned on and active and performing 3D rendering.

[0151] In at least one embodiment, one or more of SoC(s) 1104 may further include a Mobile Industrial Processor Serial Interface ("MIPI") for receiving video and input from cameras, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functions. In at least one embodiment, one or more of SoC(s) 1104 may further include one or more input / output controllers that may be controlled by software and may be used to receive I / O signals that are not tied to a specific role.

[0152] In at least one embodiment, one or more of SoC(s) 1104 may further include a wide range of peripheral interfaces to enable communication with peripherals, audio encoders / decoders ("codecs"), power management, and / or other devices. In at least one embodiment, SoC(s) 1104 may be used to receive data from cameras (e.g., via Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., LIDAR sensor(s) 1164, RADAR sensor(s) 1160, etc., which may be connected via Ethernet channels), data from bus 1102 (e.g., speed of vehicle 1100, steering wheel position, etc.), data from GNSS sensor(s) 1158 (e.g., connected via an Ethernet bus or a CAN bus), etc.In at least one embodiment, one or more of SoC(s) 1104 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and which may be used to free CPU(s) 1106 from routine data management tasks.

[0153] In at least one embodiment, the SoC(s) 1104 may be an end-to-end platform with a flexible architecture spanning automation levels 3-5, thereby providing a comprehensive functional safety architecture, leveraging computer vision and ADAS techniques for diversity and redundancy, and providing a platform for a flexible, reliable driving software stack along with deep learning tools. In at least one embodiment, the SoC(s) 1104 may be faster, more reliable, and even more power and space efficient than conventional systems. For example, in at least one embodiment, the accelerator(s) 1114, in combination with the CPU(s) 1106, the GPU(s) 1108, and the memory(s) 1116, may form a fast, efficient platform for Level 3-5 autonomous vehicles.

[0154] In at least one embodiment, computer vision algorithms may be executed on CPUs that can be configured with a high-level programming language, such as C, to execute a variety of processing algorithms for a wide variety of visual data. However, in at least one embodiment, CPUs are often unable to meet the performance requirements of many computer vision applications, such as execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and in practical Level 3-5 autonomous vehicles.

[0155] The embodiments described herein enable multiple neural networks to be executed simultaneously and / or sequentially and the results to be combined to enable Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executing on a DLA or a discrete GPU (e.g., GPU(s) 1120) may include text and word recognition enabling the reading and understanding of traffic signs, including signs for which a neural network has not been specifically trained. In at least one embodiment, a DLA may further include a neural network capable of identifying, interpreting, and semantically understanding a sign and passing this semantic understanding to planning modules running on a CPU complex.

[0156] In at least one embodiment, multiple neural networks may run simultaneously, such as in Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign stating "Caution: Flashing lights indicate icing" along with an electric light may be interpreted independently or jointly by multiple neural networks. In at least one embodiment, such a warning sign may itself be identified as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text "Flashing lights indicate icing" may be interpreted by a second deployed neural network, which informs a vehicle's path planning software (preferably running on a CPU complex) that, if flashing lights are detected, icing is present.In at least one embodiment, a turn signal may be identified by running a third neural network across multiple frames, informing a vehicle's path planning software of the presence (or absence) of turn signals. In at least one embodiment, all three neural networks may run concurrently, for example, within a DLA and / or on GPU(s) 1108.

[0157] In at least one embodiment, a facial recognition and vehicle owner identification CNN may use data from camera sensors to identify the presence of an authorized driver and / or owner of the vehicle 1100. In at least one embodiment, an "always on" sensor processing engine may be used to unlock a vehicle when an owner approaches a driver's door and turns on the lights, and to disable such a vehicle in a security mode when an owner exits such a vehicle. In this way, the SoC(s) 1104 provide security against theft and / or carjacking.

[0158] In at least one embodiment, a CNN for detecting and identifying emergency vehicles may use data from microphones 1196 to detect and identify emergency vehicle sirens. In at least one embodiment, the SoC(s) 1104 use a CNN to classify environmental and urban noise, as well as visual data. In at least one embodiment, a CNN running on a DLA is trained to identify the relative approach speed of an emergency vehicle (e.g., by leveraging the Doppler effect). In at least one embodiment, a CNN may also be trained to identify emergency vehicles specific to a local area in which a vehicle is located, as identified by GNSS sensor(s) 1158.In at least one embodiment, when deployed in Europe, a CNN will attempt to detect European sirens, and when deployed in North America, a CNN will attempt to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program may be used to execute an emergency vehicle safety routine, decelerate a vehicle, pull over to the side of the road, park a vehicle, and / or idle a vehicle using ultrasonic sensor(s) 1162 until the emergency vehicles pass by.

[0159] In at least one embodiment, the vehicle 1100 may include one or more CPU(s) 1118 (e.g., discrete CPU(s) or dCPU(s)) that may be connected to the SoC(s) 1104 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the CPU(s) 1118 may include, for example, an x86 processor. The CPU(s) 1118 may be used to perform a variety of functions, including reconciling potentially conflicting results between ADAS sensors and SoC(s) 1104 and / or monitoring the status and health of the controller(s) 1136 and / or an infotainment system on a chip (“infotainment SoC”) 1130, for example. In at least one embodiment, SoC(s) 1104 includes one or more interconnects, and an interconnect may include a Peripheral Component Interconnect Express (PCIe).

[0160] In at least one embodiment, vehicle 1100 may include GPU(s) 1120 (e.g., discrete GPU(s) or dGPU(s)) that may be coupled to SoC(s) 1104 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, GPU(s) 1120 may provide additional artificial intelligence functionality, e.g., by executing redundant and / or distinct neural networks, and may be used to train and / or update neural networks based at least in part on inputs (e.g., sensor data) from sensors of vehicle 1100.

[0161] In at least one embodiment, the vehicle 1100 may further include a network interface 1124, which may include, without limitation, one or more wireless antennas 1126 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, the network interface 1124 may be used to enable wireless connectivity to internet cloud services (e.g., to server(s) and / or other network devices), to other vehicles, and / or to computing devices (e.g., passenger client devices). In at least one embodiment, a direct connection between the vehicle 1100 and another vehicle and / or an indirect connection (e.g., via networks and the internet) may be established for communication with other vehicles.In at least one embodiment, direct connections may be established via a vehicle-to-vehicle communication link. In at least one embodiment, a vehicle-to-vehicle communication link may provide information to vehicle 1100 about vehicles in the vicinity of vehicle 1100 (e.g., vehicles in front of, to one side of, and / or behind vehicle 1100). In at least one embodiment, this aforementioned functionality may be part of a cooperative adaptive cruise control function of vehicle 1100.

[0162] In at least one embodiment, the network interface 1124 may include a SoC that provides modulation and demodulation functions and enables the controller(s) 1136 to communicate over wireless networks. In at least one embodiment, the network interface 1124 may include a radio frequency front-end for upconversion from baseband to radio frequency and downconversion from radio frequency to baseband. In at least one embodiment, the frequency conversions may be performed in any technically feasible manner. For example, frequency conversions may be performed by known methods and / or using superheterodyne techniques. In at least one embodiment, the radio frequency front-end functionality may be provided by a separate chip.In at least one embodiment, the network interfaces may include wireless capabilities for communication via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0163] In at least one embodiment, the vehicle 1100 may further include one or more data stores 1128, which may include, without limitation, off-chip memory (e.g., off-SoC(s) 1104). In at least one embodiment, the data store(s) 1128 may include, without limitation, one or more memory elements, including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, hard drives, and / or other components and / or devices capable of storing at least one bit of data.

[0164] In at least one embodiment, vehicle 1100 may further include GNSS sensor(s) 1158 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, sensing, occupancy grid generation, and / or path planning. In at least one embodiment, any number of GNSS sensor(s) 1158 may be used, including, for example, and without limitation, a GPS using a USB port with an Ethernet-to-serial bridge (e.g., RS-232).

[0165] In at least one embodiment, the vehicle 1100 may further include RADAR sensor(s) 1160. In at least one embodiment, the RADAR sensor(s) 1160 may be used by the vehicle 1100 for long-range vehicle detection, even in darkness and / or adverse weather conditions. In at least one embodiment, the RADAR sensors 1160 may use a CAN bus and / or bus 1102 (e.g., for transmitting the data generated by the RADAR sensors 1160) for control and access to object tracking data, with raw data being accessed via Ethernet channels in some examples. In at least one embodiment, a wide range of RADAR sensors may be used. For example, and without limitation, RADAR sensor(s) 1160 may be suitable for use as front, rear, and side RADAR.In at least one embodiment, one or more sensors of the RADAR sensor(s) 1160 is a pulse Doppler RADAR sensor.

[0166] In at least one embodiment, the RADAR sensor(s) 1160 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR may be used for the adaptive cruise control function. In at least one embodiment, long-range RADAR systems may provide a wide field of view realized by two or more independent scans, for example, within a range of 250 m (meters). In at least one embodiment, RADAR sensor(s) 1160 may assist in distinguishing between static and moving objects and may be used by the ADAS system 1138 for emergency braking assistance and forward collision warning.In at least one embodiment, the sensor(s) 1160 included in a long-range radar system may comprise, without limitation, a monostatic multimodal radar with multiple (e.g., six or more) fixed radar antennas and a high-speed CAN and FlexRay interface. In at least one embodiment with six antennas, four antennas in the center may create a focused beam pattern designed to detect the vehicle's surroundings at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, two additional antennas may expand the field of view, allowing for rapid detection of vehicles entering or exiting a lane of vehicle 1100.

[0167] In at least one embodiment, medium-range radar systems may, for example, include a range of up to 160 m (front) or 80 m (rear) and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, short-range radar systems may include, without limitation, any number of radar sensors 1160 that may be installed at either end of a rear bumper. In at least one embodiment, a radar sensor system, when installed at either end of a rear bumper, may create two beams that continuously monitor blind spots to the rear and to the side of a vehicle. In at least one embodiment, short-range radar systems may be used in ADAS system 1138 for blind spot detection and / or lane change assistance.

[0168] In at least one embodiment, the vehicle 1100 may further include ultrasonic sensor(s) 1162. In at least one embodiment, the ultrasonic sensor(s) 1162, which may be located at a front, rear, and / or side location of the vehicle 1100, may be used for parking assistance and / or for creating and updating a grid. In at least one embodiment, a plurality of ultrasonic sensors 1162 may be used, and different ultrasonic sensors 1162 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensor(s) 1162 may operate at functional safety levels of ASIL B.

[0169] In at least one embodiment, the vehicle 1100 may include the LIDAR sensor(s) 1164. In at least one embodiment, the LIDAR sensor(s) 1164 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the LIDAR sensor(s) 1164 may operate at the ASIL B functional safety level. In at least one embodiment, the vehicle 1100 may include multiple LIDAR sensors 1164 (e.g., two, four, six, etc.) that may use an Ethernet channel (e.g., to deliver data to a Gigabit Ethernet switch).

[0170] In at least one embodiment, the LIDAR sensor(s) 1164 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, the commercially available LIDAR sensor(s) 1164 may have an advertised range of approximately 100 m, with an accuracy of 2 cm to 3 cm, and with support for a 100 Mbps Ethernet connection, for example. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, the LIDAR sensor(s) 1164 may comprise a small device that can be embedded in a front, rear, side, and / or corner location of the vehicle 1100.In at least one embodiment, the LIDAR sensor(s) 1164 in such an embodiment can provide a horizontal field of view of up to 120 degrees and a vertical field of view of up to 35 degrees with a range of 200 m, even for objects with low reflectivity. In at least one embodiment, the front-mounted LIDAR sensor(s) 1164 can be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0171] In at least one embodiment, LIDAR technologies, such as 3D flash LIDAR, may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate the surroundings of the vehicle 1100 up to a distance of approximately 200 m. In at least one embodiment, a flash LIDAR unit includes, without limitation, a receptor that records the time of flight of the laser pulse and the reflected light at each pixel, which in turn corresponds to a distance from the vehicle 1100 to objects. In at least one embodiment, flash LIDAR may enable highly accurate and distortion-free images of the surroundings to be generated with each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of the vehicle 1100.In at least one embodiment, 3D flash LIDAR systems include, without limitation, a solid-state 3D star array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per image and collect the reflected laser light as a 3D range point cloud and co-registered intensity data.

[0172] In at least one embodiment, the vehicle 1100 may further include one or more IMU sensors 1166. In at least one embodiment, the IMU sensor(s) 1166 may be located at the center of a rear axle of the vehicle 1100. In at least one embodiment, the IMU sensor(s) 1166 may include, for example, and without limitation, accelerometers, magnetometers, gyroscopes, a magnetic compass, magnetic compasses, and / or other types of sensors. In at least one embodiment, such as in six-axis applications, the IMU sensor(s) 1166 may include, without limitation, accelerometers and gyroscopes. In at least one embodiment, such as in nine-axis applications, the IMU sensor(s) 1166 may include, without limitation, accelerometers, gyroscopes, and magnetometers.

[0173] In at least one embodiment, the IMU sensor(s) 1166 may be implemented as a miniaturized, high-performance GPS-based inertial navigation system ("GPS / INS") that combines microelectromechanical systems ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filter algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, the IMU sensor(s) 1166 may enable the vehicle 1100 to estimate its heading without requiring input from a magnetic sensor by directly observing velocity changes from a GPS and correlating them with the IMU sensor(s) 1166. In at least one embodiment, the IMU sensor(s) 1166 and the GNSS sensor(s) 1158 may be combined into a single integrated unit.

[0174] In at least one embodiment, vehicle 1100 may include microphone(s) 1196 disposed in and / or around vehicle 1100. In at least one embodiment, microphone(s) 1196 may be used, among other things, for detecting and identifying emergency vehicles.

[0175] In at least one embodiment, the vehicle 1100 may further include any number of camera types, including stereo camera(s) 1168, wide-angle camera(s) 1170, infrared camera(s) 1172, surround camera(s) 1174, long-range camera(s) 1198, medium-range camera(s) 1176, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around the entire perimeter of the vehicle 1100. In at least one embodiment, the types of cameras used depend on the vehicle 1100. In at least one embodiment, any combination of camera types may be used to provide the required coverage around the vehicle 1100. In at least one embodiment, the number of cameras employed may vary depending on the embodiment.In at least one embodiment, the vehicle 1100 may include, for example, six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may support, for example, and without limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communication. In at least one embodiment, each camera may be configured as previously described herein with respect to [ ]. Fig. 11A and Fig. 11B is described in more detail.

[0176] In at least one embodiment, the vehicle 1100 may further include one or more vibration sensors 1142. In at least one embodiment, the vibration sensor(s) 1142 may measure vibrations of components of the vehicle 1100, such as the axle(s). For example, in at least one embodiment, changes in vibrations may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1142 are used, differences between vibrations may be used to determine friction or slippage of the road surface (e.g., when there is a difference in vibration between a driven axle and a free-spinning axle).

[0177] In at least one embodiment, the vehicle 1100 may include the ADAS system 1138. In at least one embodiment, the ADAS system 1138 may include, in some examples, without limitation, an SoC. In at least one embodiment, the ADAS system 1138 may include, without limitation, any number and combination of an autonomous / adaptive / automatic cruise control (“ACC”) system, a cooperative adaptive cruise control (“CACC”) system, a forward crash warning (“FCW”) system, an automatic emergency braking (“AEB”) system, a lane departure warning (“LDW”) system, a lane keep assist (“LKA”) system, a blind spot warning (“BSW”) system, a rear cross traffic warning (“RCTW”) system, a forward collision warning (“CW”) system, a lane centering (“LC”) system, and / or other systems, features, and / or functions.

[0178] In at least one embodiment, the ACC system may use RADAR sensor(s) 1160, LIDAR sensor(s) 1164, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, a longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 1100 and automatically adjusts the speed of the vehicle 1100 to maintain a safe distance from preceding vehicles. In at least one embodiment, a lateral ACC system provides follow-through and advises the vehicle 1100 to change lanes if necessary. In at least one embodiment, a lateral ACC system is connected to other ADAS applications, such as LC and CW.

[0179] In at least one embodiment, a CACC system utilizes information from other vehicles, which may be received via a network interface 1124 and / or wireless antenna(s) 1126 from other vehicles over a wireless connection or indirectly via a network connection (e.g., over the Internet). In at least one embodiment, direct connections may be provided by a vehicle-to-vehicle ("V2V") communication link, while indirect connections may be provided by an infrastructure-to-vehicle ("I2V") communication link. Generally, V2V communication provides information about immediately ahead vehicles (e.g., vehicles immediately in front of and in the same lane as vehicle 1100), while I2V communication provides information about traffic further ahead.In at least one embodiment, a CACC system may include either one or both I2V and V2V information sources. In at least one embodiment, a CACC system may be more reliable given information about vehicles ahead of vehicle 1100 and has the potential to improve traffic flow and reduce congestion on the road.

[0180] In at least one embodiment, an FCW system is designed to warn a driver of a hazard so that the driver can take corrective action. In at least one embodiment, an FCW system uses a forward-facing camera and / or RADAR sensor(s) 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is / are electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibrating component. In at least one embodiment, an FCW system can provide a warning, for example, in the form of a sound, a visual warning, a vibration, and / or a rapid braking pulse.

[0181] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if a driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system can utilize forward-facing camera(s) and / or RADAR sensor(s) 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, upon detecting a hazard, an AEB system will typically first alert a driver to take corrective action to avoid a collision, and if that driver does not take corrective action, the AEB system can automatically apply the brakes to prevent or at least mitigate the effects of a predicted collision.In at least one embodiment, an AEB system may include techniques such as dynamic brake assistance and / or crash-imminent braking.

[0182] In at least one embodiment, an LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when vehicle 1100 crosses lane markings. In at least one embodiment, an LDW system is not activated when a driver indicates an intentional lane departure, for example, by activating a turn signal. In at least one embodiment, an LDW system may utilize forward-facing cameras coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide feedback to the driver, for example, via a display, speaker, and / or vibrating component. In at least one embodiment, an LKA system is a variation of an LDW system.In at least one embodiment, an LKA system provides a steering input or braking to correct the vehicle 1100 when the vehicle 1100 begins to depart from its lane.

[0183] In at least one embodiment, a BSW system detects and warns the driver of vehicles in the vehicle's blind spot. In at least one embodiment, a BSW system may provide a visual, audible, and / or tactile warning to indicate that merging or changing lanes is unsafe. In at least one embodiment, a BSW system may provide an additional warning when a driver activates a turn signal. In at least one embodiment, a BSW system may utilize rear-facing camera(s) and / or RADAR sensor(s) 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to feedback to the driver, such as a display, speaker, and / or vibrating component.

[0184] In at least one embodiment, an RCTW system may provide visual, audible, and / or tactile notification when an object is detected outside the range of the rearview camera when the vehicle 1100 is reversing. In at least one embodiment, an RCTW system includes an AEB system to ensure that the vehicle brakes are applied to avoid a crash. In at least one embodiment, an RCTW system may utilize one or more rear-facing RADAR sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibrating component.

[0185] In at least one embodiment, conventional ADAS systems may be prone to false positive results, which can be annoying and distracting for a driver, but are typically not catastrophic because conventional ADAS systems alert a driver and allow that driver to decide whether a safety condition truly exists and act accordingly. In at least one embodiment, in the case of conflicting results, the vehicle 1100 itself decides whether to consider the result of a primary computer or a secondary computer (e.g., a first controller or a second controller of the controllers 1136). In at least one embodiment, the ADAS system 1138 may, for example, be a backup and / or secondary computer that provides perception information to a rationality module of the backup computer.In at least one embodiment, a backup computer rationality monitor may execute redundant, diverse software on hardware components to detect errors in perception and dynamic driving tasks. In at least one embodiment, the outputs of the ADAS system 1138 may be forwarded to a supervisory MCU. In at least one embodiment, if the outputs of a primary computer and the outputs of a secondary computer conflict, a supervisory MCU determines how to resolve the conflict to ensure safe operation.

[0186] In at least one embodiment, a primary computer may be configured to provide a score to a supervising MCU indicating the primary computer's confidence in a selected outcome. In at least one embodiment, the supervising MCU may follow the primary computer's instruction if that confidence score exceeds a threshold, regardless of whether the secondary computer provides a conflicting or inconsistent outcome. In at least one embodiment, in cases where a confidence score does not meet a threshold and where the primary and secondary computers indicate different outcomes (e.g., a conflict), a supervising MCU may arbitrate between the computers to determine an appropriate outcome.

[0187] In at least one embodiment, a monitoring MCU may be configured to execute a neural network(s) trained and configured to determine, based at least in part on the outputs of a primary computer and the outputs of a secondary computer, the conditions under which the secondary computer provides false alarms. In at least one embodiment, the neural network(s) in a monitoring MCU may learn when the output of a secondary computer can and cannot be trusted. In at least one embodiment, when the secondary computer system is a RADAR-based FCW system, a neural network(s) mayNeural networks in the monitoring MCU can learn when an FCW system identifies metallic objects that are not actually hazards, such as a drain grate or manhole cover, which triggers an alarm. In at least one embodiment, when a secondary computer is a camera-based LDW system, a neural network in a monitoring MCU can learn to override the LDW system when cyclists or pedestrians are present and leaving the lane is indeed the safest maneuver. In at least one embodiment, a monitoring MCU can include at least one DLA or GPU suitable for executing neural networks with associated memory. In at least one embodiment, a monitoring MCU can comprise and / or be included as a component of the SoC(s) 1104.

[0188] In at least one embodiment, ADAS system 1138 may include a secondary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, this secondary computer may use classic computer vision (if-then) rules, and the presence of a neural network(s) in a higher-level MCU may improve reliability, safety, and performance. In at least one embodiment, the different implementations and intentional non-identity make the overall system more fault-tolerant, particularly against errors caused by software functions (or software-hardware interfaces).For example, in at least one embodiment, if a software error occurs in the software running on a primary computer and non-identical software code runs on a secondary computer that produces a consistent overall result, then a supervising MCU may have greater confidence that an overall result is correct and a bug in the software or hardware on that primary computer does not cause a significant error.

[0189] In at least one embodiment, an output of the ADAS system 1138 may be fed to the perception block of a primary computer and / or the dynamic driving task block of a primary computer. For example, in at least one embodiment, if the ADAS system 1138 indicates a forward crash warning due to an object immediately ahead, a perception block may use this information to identify objects. In at least one embodiment, a secondary computer may have its own neural network trained to reduce the risk of false alarms, as described herein.

[0190] In at least one embodiment, the vehicle 1100 may further include an infotainment SoC 1130 (e.g., an in-vehicle infotainment system (IVI)). Although illustrated and described as an SoC, in at least one embodiment, the infotainment system SoC 1130 may not be an SoC and may include, without limitation, two or more discrete components. In at least one embodiment, the infotainment SoC 1130 may include, without limitation, a combination of hardware and software that can be used to provide audio (e.g., music, a personal digital assistant, navigation commands, news, radio, etc.), video (e.g., television, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.).) and / or information services (e.g., navigation systems, rear parking assistance, a radio data system, vehicle-related information such as fuel level, total distance traveled, brake fuel level, oil level, door open / close, air filter information, etc.) to the vehicle 1100. The infotainment SoC 1130 could include, for example, radios, record players, navigation systems, video players, USB and Bluetooth connectivity, car computers, in-car entertainment, WiFi, steering wheel audio controls, hands-free calling, a heads-up display (“HUD”), an HMI display 1134, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, functions, and / or systems), and / or other components.In at least one embodiment, the infotainment SoC 1130 may be further used to provide information (e.g., visual and / or audible) to the user(s) of the vehicle 1100, such as information from the ADAS system 1138, autonomous driving information such as planned vehicle maneuvers, trajectories, environmental information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0191] In at least one embodiment, the infotainment SoC 1130 may include any amount and type of GPU functionality. In at least one embodiment, the infotainment SoC 1130 may communicate with other devices, systems, and / or components of the vehicle 1100 via the bus 1102. In at least one embodiment, the infotainment SoC 1130 may be coupled to a supervisory MCU so that a GPU of an infotainment system may perform some self-driving functions if the primary controller(s) 1136 (e.g., primary and / or backup computers of the vehicle 1100) fail. In at least one embodiment, the infotainment SoC 1130 may place the vehicle 1100 into a chauffeur-to-safe-stop mode, as described herein.

[0192] In at least one embodiment, the vehicle 1100 may further include an instrument cluster 1132 (e.g., a digital instrument panel, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, the instrument cluster 1132 may include, without limitation, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the instrument cluster 1132 may include, without limitation, any number and combination of instruments, such as, but not limited to, speedometer, fuel level, oil pressure, tachometer, odometer, turn signals, gear position indicator, seat belt warning light(s), parking brake warning light(s), engine malfunction light(s), supplemental restraint system information (e.g., airbags), lighting controls, safety system controls, navigation information, etc.In some examples, information may be displayed and / or shared between infotainment SoC 1130 and instrument cluster 1132. In at least one embodiment, instrument cluster 1132 may be included as part of infotainment SoC 1130, or vice versa.

[0193] In at least one embodiment, the vehicle 1100 may be used to implement the system 100 (see Fig. 1), the collage 200 (see Fig. 2), the System 300 (see Fig. 3), process 400 (see Fig. 4) and / or process 500 (see Fig. 5). In at least one embodiment, at least a portion of the Fig. 10 depicted system(s) to implement one or more systems, techniques, functions and / or processes that are used in conjunction with Fig. 1-7. For example, in at least one embodiment, at least one Fig. 11C may be used to cause one or more neural networks to use one or more textual descriptions to generate one or more 3D models of one or more first objects in accordance with one or more techniques, functions and / or processes described with respect to one of the Fig. 1-7 are described.

[0194] Fig. 11D is a diagram of a system for communication between one or more cloud-based servers and the autonomous vehicle 1100 of Fig. 11A according to at least one embodiment. In at least one embodiment, the system may include, without limitation, server(s) 1178, network(s) 1190, and any number and type of vehicles, including vehicle 1100. In at least one embodiment, server(s) 1178 may include, without limitation, a plurality of GPUs 1184(A)-1184(H) (collectively referred to herein as GPUs 1184), PCIe switches 1182(A)-1182(D) (collectively referred to herein as PCIe switches 1182), and / or CPUs 1180(A)-1180(B) (collectively referred to herein as CPUs 1180). In at least one embodiment, the GPUs 1184, the CPUs 1180, and the PCIe switches 1182 may be interconnected with high-speed interconnects, such as, without limitation, the NVLink interfaces 1188 and / or PCIe interconnects 1186 developed by NVIDIA.In at least one embodiment, the GPUs 1184 are connected via an NVLink and / or NVSwitch SoC, and the GPUs 1184 and PCIe switches 1182 are connected via PCIe interconnects. Although eight GPUs 1184, two CPUs 1180, and four PCIe switches 1182 are shown, this is not intended to be limiting. In at least one embodiment, each of the servers 1178 may include, without limitation, any number of GPUs 1184, CPUs 1180, and / or PCIe switches 1182 in any combination. For example, in at least one embodiment, the server(s) 1178 could each include eight, sixteen, thirty-two, and / or more GPUs 1184.

[0195] In at least one embodiment, the server(s) 1178 may receive, via the network(s) 1190 and from vehicles, image data representative of images depicting unexpected or changed road conditions, such as recently commenced roadwork. In at least one embodiment, the server(s) 1178 may transmit, via the network(s) 1190 and to the vehicles, updated or other neural network 1192 and / or map information 1194 including, among other things, information about traffic and road conditions. In at least one embodiment, the updates to the map information 1194 may include, without limitation, updates to the HD map 1122, such as information about construction, potholes, detours, flooding, and / or other obstacles.In at least one embodiment, neural networks 1192 and / or map information 1194 may result from new training and / or experience represented in data received from any number of vehicles in an environment and / or may be based at least in part on training performed in a data center (e.g., using server(s) 1178 and / or other servers).

[0196] In at least one embodiment, the server(s) 1178 may be used to train machine learning models (e.g., neural networks) based at least in part on training data. In at least one embodiment, the training data may be generated by vehicles and / or generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is tagged (e.g., if the associated neural network benefits from supervised learning) and / or subjected to other preprocessing. In at least one embodiment, any amount of training data is untagged and / or subjected to preprocessing (e.g., if the associated neural network does not require supervised learning).In at least one embodiment, once trained, the machine learning models may be used by the vehicles (e.g., by transmission to the vehicles via network(s) 1190), and / or the machine learning models may be used by server(s) 1178 to remotely monitor the vehicles.

[0197] In at least one embodiment, the server(s) 1178 may receive data from vehicles and apply the data to state-of-the-art neural networks for intelligent inference in real time. In at least one embodiment, the server(s) 1178 may include deep learning supercomputers and / or dedicated AI computers powered by GPU(s) 1184, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, the server(s) 1178 may also include a deep learning infrastructure using CPU-powered data centers.

[0198] In at least one embodiment, the deep learning infrastructure of server(s) 1178 may be capable of rapid, real-time inference and utilize this capability to evaluate and verify the health of processors, software, and / or associated hardware in vehicle 1100. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1100, such as a sequence of images and / or objects that vehicle 1100 has located in that sequence of images (e.g., via computer vision and / or other machine object classification techniques).In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to objects identified by the vehicle 1100, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 1100 is not functioning properly, then the server(s) 1178 may send a signal to the vehicle 1100 instructing a fail-safe computer of the vehicle 1100 to take over control, notify the passengers, and perform a safe parking maneuver.

[0199] In at least one embodiment, the server(s) 1178 may include GPU(s) 1184 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, a combination of GPU-driven servers and inference accelerators may enable real-time responsiveness. In at least one embodiment, for example, when performance is less critical, servers with CPUs, FPGAs, and other processors may be used for inferencing. In at least one embodiment, hardware structure(s) 815 are used to perform one or more embodiments. Details of the hardware structure(s) 815 are described herein in connection with Fig. 8A and / or 8B. COMPUTER SYSTEMS

[0200] Fig. 12 is a block diagram illustrating an exemplary computer system, which may be a system with interconnected devices and components, a system-on-a-chip (SOC), or a combination thereof, formed with a processor that may include execution units for executing an instruction, according to at least one embodiment. In at least one embodiment, a computer system 1200 may include, without limitation, a component such as a processor 1202 for utilizing execution units including logic for performing algorithms for processing data in accordance with the present disclosure, as in the embodiment described herein.In at least one embodiment, computer system 1200 may include processors such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs with other microprocessors, technical workstations, set-top boxes, and the like) may be used. In at least one embodiment, computer system 1200 may run a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0201] Embodiments may also be used in other devices such as handheld devices and embedded applications. Some examples of portable devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of executing one or more instructions according to at least one embodiment.

[0202] In at least one embodiment, computer system 1200 may include, without limitation, a processor 1202, which may include, without limitation, one or more execution units 1208 to perform machine learning model training and / or inferencing according to the techniques described herein. In at least one embodiment, computer system 1200 is a desktop or server system having a processor, but in another embodiment, computer system 1200 may be a multiprocessor system. In at least one embodiment, processor 1202 may include, without limitation, a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or any other device, such as a digital signal processor.In at least one embodiment, the processor 1202 may be connected to a processor bus 1210 that may transmit data signals between the processor 1202 and other components in the computer system 1200.

[0203] In at least one embodiment, processor 1202 may include, without limitation, an internal Level 1 ("L1") cache ("cache") 1204. In at least one embodiment, processor 1202 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache may be external to processor 1202. Other embodiments may also include a combination of internal and external caches, depending on the particular implementation and needs. In at least one embodiment, a register file 1206 may store different data types in various registers, including, without limitation, integer registers, floating-point registers, status registers, and an instruction pointer register.

[0204] In at least one embodiment, execution unit 1208, which includes, without limitation, logic for performing integer and floating-point operations, is also located in processor 1202. In at least one embodiment, processor 1202 may also include microcode read-only memory ("ROM") ("ucode") that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1208 may include logic for handling a packed instruction set 1209. In at least one embodiment, by including packed instruction set 1209 in the instruction set of a general-purpose processor, along with associated instruction execution circuitry, operations used by many multimedia applications may be performed using packed data in processor 1202.In at least one embodiment, many multimedia applications can be accelerated and executed more efficiently by utilizing the full width of a processor's data bus to perform operations on packed data, thereby eliminating the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0205] In at least one embodiment, execution unit 1208 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1200 may include, without limitation, a memory 1220. In at least one embodiment, memory 1220 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or another storage device. In at least one embodiment, memory 1220 may store instruction(s) 1219 and / or data 1221 represented by data signals that may be executed by processor 1202.

[0206] In at least one embodiment, a system logic chip may be connected to the processor bus 1210 and the memory 1220. In at least one embodiment, a system logic chip may include, without limitation, a memory control hub ("MCH") 1216, and the processor 1202 may communicate with the MCH 1216 via the processor bus 1210. In at least one embodiment, the MCH 1216 may provide a high-bandwidth memory path 1218 to the memory 1220 for storing instructions and data, as well as for storing graphics instructions, data, and textures. In at least one embodiment, the MCH 1216 may route data signals between the processor 1202, the memory 1220, and other components in the computer system 1200, and may bridge data signals between the processor bus 1210, the memory 1220, and a system I / O interface 1222.In at least one embodiment, a system logic chip may provide a graphics port for connection to a graphics controller. In at least one embodiment, MCH 1216 may be coupled to memory 1220 via a high-bandwidth memory path 1218, and a graphics / video card 1212 may be coupled to MCH 1216 via an Accelerated Graphics Port ("AGP") interconnect 1214.

[0207] In at least one embodiment, computer system 1200 may use system I / O interface 1222 as a proprietary hub interface bus to connect MCH 1216 to an I / O control hub ("ICH") 1230. In at least one embodiment, ICH 1230 may provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, a local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1220, a chipset, and processor 1202. Examples may include, without limitation, an audio controller 1229, a firmware hub (“Flash BIOS”) 1228, a wireless transceiver 1226, a data store 1224, a legacy I / O controller 1223 with user input and keyboard interfaces 1225, a serial expansion port 1227, such as a Universal Serial Bus (“USB”) interface, and a network controller 1234.In at least one embodiment, data storage 1224 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0208] In at least one embodiment, Fig. 12 a system comprising interconnected hardware devices or “chips”, while in other embodiments Fig. 12 may show an exemplary SoC. In at least one embodiment, the Fig. The devices illustrated in Figure 12 may be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of computer system 1200 are interconnected using Compute Express Link (CXL) interconnects.

[0209] Logic 815 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 815 are described herein in connection with Fig. 8A and / or 8B. In at least one embodiment, logic 815 in computer system 1200 may be used for inference or prediction operations based at least in part on weight parameters calculated using neural network training systems, neural network functions and / or architectures, or neural network use cases described herein.

[0210] In at least one embodiment, computer system 1200 may be used to implement system 100 (see Fig. 1), the collage 200 (see Fig. 2), the System 300 (see Fig. 3), process 400 (see Fig. 4) and / or process 500 (see Fig. 5). In at least one embodiment, at least a portion of the Fig. 12 depicted system(s) to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-7. For example, in at least one embodiment, at least one Fig. 12 may be used to cause one or more neural networks to use one or more textual descriptions to generate one or more 3D models of one or more first objects in accordance with one or more techniques, functions and / or processes that are related to any of the Fig. 1-7 are described.

[0211] Fig. 13 is a block diagram illustrating an electronic device 1300 for using a processor 1310 according to at least one embodiment. In at least one embodiment, the electronic device 1300 may be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0212] In at least one embodiment, the electronic device 1300 may include, without limitation, a processor 1310 communicatively connected to any number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1310 is coupled via a bus or interface, such as an I2C bus, a System Management Bus ("SMBus"), a Low Pin Count (LPC) bus, a Serial Peripheral Interface ("SPI"), a High Definition Audio (HDA) bus, a Serial Advance Technology Attachment (SATA) bus, a Universal Serial Bus ("USB") (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter Bus ("UART"). In at least one embodiment, Fig. 13 a system comprising interconnected hardware devices or “chips”, while in other embodiments Fig. 13 may show an exemplary SoC. In at least one embodiment, the Fig. 13 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of Fig. 13 interconnected using CXL (Compute Express Link) connections.

[0213] At least in one embodiment, Fig. 13 a display 1324, a touchscreen 1325, a touchpad 1330, a Near Field Communications unit (“NFC”) 1345, a sensor hub 1340, a thermal sensor 1346, an Express Chipset (“EC”) 1335, a Trusted Platform Module (“TPM”) 1338, BIOS / Firmware / Flash Memory (“BIOS, FW Flash”) 1322, a DSP 1360, a drive 1320 such as a Solid State Disk (“SSD”) or a Hard Drive (“HDD”), a Wireless Local Area Network unit (“WLAN”) 1350, a Bluetooth unit 1352, a Wireless Wide Area Network unit (“WWAN”) 1356, a Global Positioning System (GPS) unit 1355, a camera (“USB 3.0 Camera”) 1354, such as a USB 3.0 Camera, and / or a Low Power Double Data Rate ("LPDDR") memory unit ("LPDDR3") 1315, implemented, for example, according to an LPDDR3 standard. These components may be implemented in any suitable manner.

[0214] In at least one embodiment, other components may be communicatively coupled to processor 1310 via components described herein. In at least one embodiment, an accelerometer 1341, an ambient light sensor ("ALS") 1342, a compass 1343, and a gyroscope 1344 may be communicatively coupled to sensor hub 1340. In at least one embodiment, a thermal sensor 1339, a fan 1337, a keyboard 1336, and a touchpad 1330 may be communicatively coupled to EC 1335. In at least one embodiment, speakers 1363, headphones 1364, and a microphone ("mic") 1365 may be communicatively coupled to an audio unit ("audio codec and class D amp") 1362, which in turn may be communicatively coupled to DSP 1360. In at least one embodiment, the audio unit 1362 may include, for example and without limitation, an audio encoder / decoder ("codec") and a Class D amplifier.In at least one embodiment, a SIM card ("SIM") 1357 may be communicatively coupled to the WWAN unit 1356. In at least one embodiment, components such as the WLAN unit 1350 and the Bluetooth unit 1352, as well as the WWAN unit 1356, may be implemented in a Next Generation Form Factor ("NGFF").

[0215] Logic 815 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 815 are described herein in connection with Fig. 8A and / or 8B. In at least one embodiment, logic 815 in electronic device 1300 may be used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0216] In at least one embodiment, the electronic device 1300 may be used to control the system 100 (see Fig. 1), the collage 200 (see Fig. 2), the System 300 (see Fig. 3), process 400 (see Fig. 4) and / or process 500 (see Fig. 5). In at least one embodiment, at least a portion of the Fig. 13 depicted system(s) to implement one or more systems, techniques, functions and / or processes that are used in conjunction with Fig. 1-7. For example, in at least one embodiment, at least one Fig. 13 may be used to cause one or more neural networks to use one or more textual descriptions to generate one or more 3D models of one or more first objects in accordance with one or more techniques, functions and / or processes described with respect to one of the Fig. 1-7 are described.

[0217] Fig. Figure 14 illustrates a computer system 1400 according to at least one embodiment. In at least one embodiment, the computer system 1400 is configured to implement various processes and methods described in this disclosure.

[0218] In at least one embodiment, computer system 1400 includes, without limitation, at least one central processing unit ("CPU") 1402 connected to a communications bus 1410 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or another bus or point-to-point communications protocol. In at least one embodiment, computer system 1400 includes, without limitation, main memory 1404 and control logic (e.g., in the form of hardware, software, or a combination thereof), and data is stored in main memory 1404, which may take the form of random access memory ("RAM").In at least one embodiment, a network interface subsystem ("network interface") 1422 provides an interface to other computing devices and networks for using computing system 1400 to receive data from other devices and to transmit data to other systems.

[0219] In at least one embodiment, computer system 1400 includes, without limitation, input devices 1408, a parallel processing system 1412, and display devices 1406, which may be implemented using a conventional cathode ray tube ("CRT"), a liquid crystal display ("LCD"), a light-emitting diode ("LED"), a plasma display, or other suitable display technology. In at least one embodiment, user input is provided via input devices 1408 such as a keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each module described herein may be packaged on a single semiconductor platform to form a processing system.

[0220] Logic 815 is used to perform inference and / or training operations in connection with one or more embodiments. Details of inference and / or training logic 815 are described herein in connection with Fig. 8A and / or 8B. In at least one embodiment, logic 815 in computer system 1400 may be used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0221] In at least one embodiment, computer system 1400 may be used to implement system 100 (see Fig. 1), the collage 200 (see Fig. 2), the System 300 (see Fig. 3), process 400 (see Fig. 4) and / or process 500 (see Fig. 5). In at least one embodiment, at least a portion of the Fig. 14 depicted system(s) to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-7. For example, in at least one embodiment, at least one Fig. 14 may be used to cause one or more neural networks to use one or more textual descriptions to generate one or more 3D models of one or more first objects in accordance with one or more techniques, functions and / or processes described with respect to one of the Fig. 1-7 are described.

[0222] Fig. 15 shows a computer system 1500 according to at least one embodiment. In at least one embodiment, the computer system 1500 includes, without limitation, a computer 1510 and a USB flash drive 1520. In at least one embodiment, the computer 1510 may include, without limitation, any number and type of processor(s) (not shown) and memory (not shown). In at least one embodiment, the computer 1510 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0223] In at least one embodiment, USB flash drive 1520 includes, without limitation, a processing unit 1530, a USB interface 1540, and USB interface logic 1550. In at least one embodiment, processing unit 1530 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1530 may include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, processing unit 1530 includes an application-specific integrated circuit ("ASIC") optimized to perform any number and type of machine learning-related operations.For example, in at least one embodiment, processing unit 1530 is a tensor processing unit ("TPC") optimized for performing machine learning inference operations. In at least one embodiment, processing unit 1530 is a vision processing unit ("VPU") optimized for performing machine vision and machine learning operations.

[0224] In at least one embodiment, USB interface 1540 may be any type of USB connector or receptacle. For example, in at least one embodiment, USB interface 1540 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1540 is a USB 3.0 Type-A connector. In at least one embodiment, the logic of USB interface 1550 may include any amount and type of logic that enables processing unit 1530 to communicate with devices (e.g., computer 1510) via USB port 1540.

[0225] Logic 815 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 815 are described herein in connection with Fig. 8A and / or 8B. In at least one embodiment, logic 815 in computer system 1500 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training systems, neural network functions and / or architectures, or neural network use cases described herein.

[0226] In at least one embodiment, computer system 1500 may be used to implement system 100 (see Fig. 1), the collage 200 (see Fig. 2), the System 300 (see Fig. 3), process 400 (see Fig. 4) and / or process 500 (see Fig. 5). In at least one embodiment, at least a portion of the Fig. 15 depicted system(s) to implement one or more systems, techniques, functions and / or processes that are used in conjunction with Fig. 1-7. For example, in at least one embodiment, at least one Fig. 15 may be used to cause one or more neural networks to use one or more textual descriptions to generate one or more 3D models of one or more first objects in accordance with one or more techniques, functions and / or processes described with respect to one of the Fig. 1-7 are described.

[0227] Fig. 16A illustrates an example architecture in which a plurality of GPUs 1610(1)-1610(N) are communicatively coupled to a plurality of multi-core processors 1605(1)-1605(M) via high-speed interconnects 1640(1)-1640(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, the high-speed interconnects 1640(1)-1640(N) support communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or more. In at least one embodiment, various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In various figures, "N" and "M" represent positive integers, the values ​​of which may vary from figure to figure. In at least one embodiment, one or more GPUs in a plurality of GPUs 1610(1)-1610(N) includes one or more graphics cores (also referred to simply as “cores”) 1900, as shown in the Fig. 19A and Fig. 19B. In at least one embodiment, one or more graphics cores 1900 may be referred to as streaming multiprocessors ("SMs"), stream processors ("SPs"), stream processing units ("SPUs"), compute units ("CUs"), execution units ("EUs"), and / or slices, where a slice in this context may refer to a portion of processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director, or scheduler).

[0228] Additionally, and in at least one embodiment, two or more GPUs 1610 are interconnected via high-speed interconnects 1629(1)-1629(2), which may be implemented using similar or different protocols / connections than those used for high-speed interconnects 1640(1)-1640(N). Similarly, two or more multi-core processors 1605 may be interconnected via a high-speed interconnect 1628, which may be symmetric multiprocessor (SMP) buses operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, all communication between the various Fig. 16A using similar protocols / connections (e.g., via a common interconnection structure).

[0229] In at least one embodiment, each multi-core processor 1605 is communicatively connected to a processor memory 1601(1)-1601(M) via memory interconnects 1626(1)-1626(M), and each GPU 1610(1)-1610(N) is communicatively connected to GPU memory 1620(1)-1620(N) via GPU memory interconnects 1650(1)-1650(N). In at least one embodiment, memory interconnects 1626 and 1650 may use similar or different memory access technologies. For example, the processor memories 1601(1)-1601(M) and the GPU memories 1620 may be volatile memories, such as dynamic random access memories (DRAMs) (including stacked DRAMs), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or they may be non-volatile memories, such as 3D XPoint or Nano-Ram.In at least one embodiment, a portion of the processor memory 1601 may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0230] As described herein, various multi-core processors 1605 and GPUs 1610 may be physically connected to a particular memory 1601 or 1620, respectively, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as "effective address space") is distributed across different physical memories. For example, processor memories 1601(1)-1601(M) may each comprise 64 GB of system address space, and GPU memories 1620(1)-1620(N) may each comprise 32 GB of system address space, resulting in a total of 256 GB of addressable memory when M=2 and N=4. Other values ​​for N and M are possible.

[0231] Fig. 16B shows additional details for an interconnect between a multi-core processor 1607 and a graphics acceleration module 1646 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1646 may include one or more GPU chips integrated on a line card connected to the processor 1607 via a high-speed interconnect 1640 (e.g., a PCIe bus, NVLink, etc.). Alternatively, in at least one embodiment, the graphics acceleration module 1646 may be integrated on a package or die with the processor 1607.

[0232] In at least one embodiment, processor 1607 includes a plurality of cores 1660A-1660D (which may be referred to as "execution units"), each with a translation lookaside buffer ("TLB") 1661A-1661D and one or more caches 1662A-1662D. In at least one embodiment, cores 1660A-1660D may include various other components for executing instructions and processing data, not shown. In at least one embodiment, caches 1662A-1662D may include Level 1 (L1) and Level 2 (L2) caches. Additionally, one or more shared caches 1656 may be included in caches 1662A-1662D that are shared by multiple cores 1660A-1660D. For example, one embodiment of processor 1607 includes 24 cores, each with its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches.In this embodiment, one or more L2 and L3 caches are shared between two adjacent cores. In at least one embodiment, processor 1607 and graphics acceleration module 1646 are coupled to system memory 1614, which includes processor memories 1601(1)-1601(M) of FIG. Fig. 16A may include.

[0233] In at least one embodiment, coherency for data and instructions stored in various caches 1662A-1662D, 1656, and system memory 1614 is maintained via inter-core communication over a coherency bus 1664. For example, in at least one embodiment, each cache may have cache coherency logic / circuitry associated with it to communicate over the coherency bus 1664 in response to detected reads or writes to specific cache lines. In at least one embodiment, a cache coherency protocol is implemented over the coherency bus 1664 to snoop on cache accesses.

[0234] In at least one embodiment, a proxy circuit 1625 communicatively couples the graphics acceleration module 1646 to the coherence bus 1664 so that the graphics acceleration module 1646 can participate in a cache coherence protocol as a peer of the cores 1660A-1660D. Specifically, in at least one embodiment, an interface 1635 provides connectivity to the proxy circuit 1625 via the high-speed interconnect 1640, and an interface 1637 connects the graphics acceleration module 1646 to the high-speed interconnect 1640.

[0235] In at least one embodiment, an accelerator integration circuit 1636 provides cache management, memory access, context management, and interrupt management services to a plurality of graphics processing engines 1631(1)-1631(N) of the graphics acceleration module 1646. In at least one embodiment, the graphics processing engines 1631(1)-1631(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, a plurality of graphics processing engines 1631(1)-1631(N) of the graphics acceleration module 1646 include one or more graphics cores 1900, as described in connection with the Fig. 19A and Fig. 19B. In at least one embodiment, the graphics processing engines 1631(1)-1631(N) may alternatively comprise different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1646 may be a GPU with a plurality of graphics processing engines 1631(1)-1631(N), or the graphics processing engines 1631(1)-1631(N) may be individual GPUs integrated on a common package, line card, or die.

[0236] In at least one embodiment, accelerator integration circuitry 1636 includes a memory management unit (MMU) 1639 for performing various memory management functions, such as virtual-to-physical memory translations (also referred to as effective-to-real memory translations) and memory access protocols for accessing system memory 1614. In at least one embodiment, MMU 1639 may also include a translation lookaside buffer (TLB) (not shown) to cache virtual / effective to physical / real address translations. In at least one embodiment, a cache 1638 may store instructions and data for efficient access by graphics processing engines 1631(1)-1631(N).In at least one embodiment, the data stored in cache 1638 and graphics memories 1633(1)-1633(M) is kept coherent with core caches 1662A-1662D, 1656, and system memory 1614, possibly using a fetch unit 1644. As noted, this may be done via proxy circuitry 1625 on behalf of cache 1638 and memories 1633(1)-1633(M) (e.g., sending updates to cache 1638 regarding changes / accesses to cache lines in processor caches 1662A-1662D, 1656 and receiving updates from cache 1638).

[0237] In at least one embodiment, a set of registers 1645 stores context data for threads executed by graphics processing engines 1631(1)-1631(N), and context management circuitry 1648 manages thread contexts. For example, context management circuitry 1648 may perform save and restore operations to save and restore the contexts of different threads during a context switch (e.g., when a first thread is saved and a second thread is saved to allow a second thread to be executed by a graphics processing engine). For example, during a context switch, context management circuitry 1648 may store current register values ​​in a specific region of memory (e.g., to be identified by a context pointer). The register values ​​may then be restored upon return to a context.In at least one embodiment, an interrupt management circuit 1647 receives and processes interrupts received from system devices.

[0238] In at least one embodiment, virtual / effective addresses from a graphics processing engine 1631 are translated by the MMU 1639 into real / physical addresses in system memory 1614. In at least one embodiment, the accelerator integration circuit 1636 supports multiple (e.g., 4, 8, 16) graphics acceleration modules 1646 and / or other acceleration devices. In at least one embodiment, the graphics acceleration module 1646 may be dedicated to a single application executing on the processor 1607, or it may be shared among multiple applications. In at least one embodiment, a virtualized graphical execution environment is depicted in which the resources of the graphics processing engines 1631(1)-1631(N) are shared among multiple applications or virtual machines (VMs).In at least one embodiment, the resources may be divided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0239] In at least one embodiment, accelerator integration circuitry 1636 acts as a bridge to a system for graphics acceleration module 1646 and provides address translation and system memory caching services. Furthermore, in at least one embodiment, accelerator integration circuitry 1636 may provide virtualization facilities to a host processor to manage the virtualization of graphics processing engines 1631(1)-1631(N), interrupts, and memory management.

[0240] Because, in at least one embodiment, the hardware resources of graphics processing engines 1631(1)-1631(N) are explicitly mapped to a real address space seen by host processor 1607, each host processor can directly address these resources via an effective address value. In at least one embodiment, a function of accelerator integration circuitry 1636 is to physically separate graphics processing engines 1631(1)-1631(N) so that they appear to a system as independent entities.

[0241] In at least one embodiment, one or more graphics memories 1633(1)-1633(M) are coupled to each of the graphics processing engines 1631(1)-1631(N), where N=M. In at least one embodiment, the graphics memories 1633(1)-1633(M) store instructions and data processed by each of the graphics processing engines 1631(1)-1631(N). In at least one embodiment, the graphics memories 1633(1)-1633(M) may be volatile memories such as DRAMs (including stacked DRAMs), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3D XPoint or Nano-RAM.

[0242] In at least one embodiment, to reduce data traffic over high-speed interconnect 1640, bias techniques may be used to ensure that the data stored in graphics memories 1633(1)-1633(M) is data most frequently used by graphics processing engines 1631(1)-1631(N) and preferably not used by cores 1660A-1660D (at least not frequently). Similarly, in at least one embodiment, a bias mechanism attempts to keep data needed by cores (and preferably not by graphics processing engines 1631(1)-1631(N)) in caches 1662A-1662D, 1656, and system memory 1614.

[0243] Fig. 16C shows another exemplary embodiment in which accelerator integration circuitry 1636 is integrated into processor 1607. In this embodiment, graphics processing engines 1631(1)-1631(N) communicate directly over high-speed interconnect 1640 with accelerator integration circuitry 1636 via interface 1637 and interface 1635 (which may again be any form of bus or interface protocol). In at least one embodiment, accelerator integration circuitry 1636 may perform operations similar to those described in Fig. 16B, but possibly with higher throughput due to its proximity to the coherence bus 1664 and caches 1662A-1662D, 1656. In at least one embodiment, an accelerator integration circuit supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and shared programming models (with virtualization), which may include programming models controlled by the accelerator integration circuit 1636 and programming models controlled by the graphics acceleration module 1646.

[0244] In at least one embodiment, graphics processing engines 1631(1)-1631(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can forward requests from other applications to graphics processing engines 1631(1)-1631(N), thus enabling virtualization within a VM / partition.

[0245] In at least one embodiment, the graphics processing engines 1631(1)-1631(N) may be shared between multiple VM / application partitions. In at least one embodiment, shared models may use a system hypervisor to virtualize the graphics processing engines 1631(1)-1631(N) to allow access by any operating system. In at least one embodiment, for systems with a single partition without a hypervisor, the graphics processing engines 1631(1)-1631(N) are owned by an operating system. In at least one embodiment, an operating system may virtualize the graphics processing engines 1631(1)-1631(N) to allow access to any process or application.

[0246] In at least one embodiment, the graphics acceleration module 1646 or an individual graphics processing engine 1631(1)-1631(N) selects a process element using a process handle. In at least one embodiment, process elements are stored in system memory 1614 and are addressable using an effective address to real address translation technique described herein. In at least one embodiment, a process handle may be an implementation-specific value provided to a host process when it registers its context with the graphics processing engine 1631(1)-1631(N) (i.e., when it calls system software to add a process element to a linked process element list). In at least one embodiment, the lower 16 bits of a process handle may be an offset of a process element within a process element list.

[0247] Fig. 16D shows an example accelerator integration slice 1690. In at least one embodiment, a "slice" comprises a particular portion of the processing resources of accelerator integration circuitry 1636. In at least one embodiment, an application stores process elements 1683 in an effective address space 1682 in system memory 1614. In at least one embodiment, process elements 1683 are stored in response to GPU calls 1681 from applications 1680 executing on processor 1607. In at least one embodiment, a process element 1683 contains the state of the corresponding application 1680. In at least one embodiment, a work description (WD) 1684 contained in process element 1683 may be a single job requested by an application or may contain a pointer to a queue of jobs.In at least one embodiment, the WD 1684 is a pointer to a job request queue in the effective address space 1682 of an application.

[0248] In at least one embodiment, the graphics acceleration module 1646 and / or individual graphics processing engines 1631(1)-1631(N) may be shared by all or a subset of the processes in a system. In at least one embodiment, an infrastructure for establishing process states and sending a WD 1684 to a graphics acceleration module 1646 to start a job in a virtualized environment may be included.

[0249] In at least one embodiment, a programming model for dedicated processes is implementation-specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1646 or an individual graphics processing engine 1631. In at least one embodiment, when the graphics acceleration module 1646 is owned by a single process, a hypervisor initializes the accelerator integration circuit 1636 for an owning partition, and an operating system initializes the accelerator integration circuit 1636 for an owning process when the graphics acceleration module 1646 is allocated.

[0250] In at least one embodiment, a WD fetch unit 1691 in accelerator integration slice 1690 operatively fetches the next WD 1684, which includes an indication of the work to be performed by one or more graphics processing engines of graphics acceleration module 1646. In at least one embodiment, the data from WD 1684 may be stored in registers 1645 and used by MMU 1639, interrupt management circuitry 1647, and / or context management circuitry 1648, as shown. For example, one embodiment of MMU 1639 includes segment / page browsing circuitry for accessing segment / page tables 1686 within an OS virtual address space 1685. In at least one embodiment, circuitry 1647 may process interrupt events 1692 received from graphics acceleration module 1646.In at least one embodiment, when performing graphics operations, an effective address 1693 generated by a graphics processing engine 1631(1)-1631(N) is translated into a real address by the MMU 1639.

[0251] In at least one embodiment, registers 1645 are duplicated for each graphics processing engine 1631(1)-1631(N) and / or each graphics acceleration module 1646 and may be initialized by a hypervisor or an operating system. In at least one embodiment, each of these duplicated registers may be included in an accelerator integration slice 1690. Example registers that may be initialized by a hypervisor are shown in Table 1. Table 1 - Initialized hypervisor registers Register # Beschreibung 1 Slice-Steuerregister 2 Real Address (RA) Pointer to the area for scheduled processes 3 Authority mask override register 4 Interrupt vector table entry offset 5 Interrupt vector table entry boundary 6 Condition register 7 Logical partition ID 8 Real Address (RA) Hypervisor Accelerator Workload Set Pointer 9 Memory description register

[0252] Example registers that can be initialized by an operating system are shown in Table 2. Table 2 - Initialized operating system registers Register # Description 1 Process and thread identification 2 Effective Address (EA) Context Store / Restore Pointer 3 Virtual Address (VA) Accelerator Workload Set Pointer 4 Virtual Address (VA) Pointer to memory segment table 5 Authority mask 6 Job description

[0253] In at least one embodiment, each WD 1684 is specific to a particular graphics acceleration module 1646 and / or graphics processing engines 1631(1)-1631(N). In at least one embodiment, it contains all the information required by a graphics processing engine 1631(1)-1631(N) to perform work, or it may be a pointer to a memory location where an application has established a command queue of work to be performed.

[0254] Fig.16E shows additional details for an exemplary embodiment of a joint model. This embodiment includes a real hypervisor address space 1698 in which a process element list 1699 is stored. In at least one embodiment, the real hypervisor address space 1698 is accessible via a hypervisor 1696 that virtualizes graphics acceleration engine engines for the operating system 1695.

[0255] In at least one embodiment, shared programming models allow all or a subset of processes from all or a subset of partitions in a system to use a graphics acceleration module 1646. In at least one embodiment, there are two programming models where the graphics acceleration module 1646 is shared among multiple processes and partitions: time-slice sharing and graphics sharing.

[0256] In at least one embodiment, in this model, the system hypervisor 1696 has the graphics acceleration module 1646 and makes its functionality available to all operating systems 1695. In at least one embodiment, a graphics acceleration module 1646 may meet certain requirements to support virtualization by the system hypervisor 1696, such as (1) the job request of an application must be autonomous (i.e.the state does not need to be maintained between jobs), or the graphics acceleration module 1646 must provide a mechanism for saving and restoring the context, (2) the graphics acceleration module 1646 guarantees that an application's job request will be completed in a specified amount of time, including any translation errors, or the graphics acceleration module 1646 provides the ability to preempt processing of a job, and (3) the graphics acceleration module 1646 must be guaranteed fairness between processes when operating in a directed joint programming model.

[0257] In at least one embodiment, application 1680 must make a system call to operating system 1695 with a graphics acceleration module type, a work description (WD), an authority mask register value (AMR), and a context save / restore pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes a targeted acceleration function for a system call. In at least one embodiment, the graphics acceleration module type may be a system-specific value. In at least one embodiment, WD is formatted specifically for graphics acceleration module 1646 and may be in the form of a graphics acceleration module 1646 instruction, a pointer to the effective address of a user-defined structure, a pointer to the effective address of an instruction queue, or another data structure describing the work to be performed by graphics acceleration module 1646.

[0258] In at least one embodiment, an AMR value is an AMR state to be used for a current process. In at least one embodiment, a value passed to an operating system is similar to an application setting an AMR. In at least one embodiment, if accelerator integration circuitry 1636 (not shown) and graphics acceleration module 1646 do not support an authority mask override register (UAMOR), an operating system may apply a current UAMOR value to an AMR value before passing an AMR in a hypervisor call. In at least one embodiment, hypervisor 1696 may optionally apply a current authority mask override register (AMOR) value before placing an AMR into process element 1683.In at least one embodiment, CSRP is one of the registers 1645 that contains an effective address of a region in an application's effective address space 1682 for the graphics acceleration module 1646 to save and restore state. In at least one embodiment, this pointer is optional if no state needs to be saved between jobs or if a job aborts prematurely. In at least one embodiment, the context save / restore region may be anchored in system memory.

[0259] Upon receiving a system call, the operating system 1695 may verify whether the application 1680 has and has been granted permission to use the graphics acceleration module 1646. In at least one embodiment, the operating system 1695 then invokes the hypervisor 1696 with the information shown in Table 3. Table 3 - Parameters for calling the operating system to the hypervisor Parameters # Description 1 A job description (WD) 2 An authority mask register (AMR) value (possibly masked) 3 An effective address (EA) Context save / restore pointer (CSRP) 4 A process ID (PID) and optionally a thread ID (TID) 5 A virtual address (VA) accelerator utilization set pointer (AURP) 6 Virtual address of the pointer to the memory segment table (SSTP) 7 A logical interrupt service number (LISN)

[0260] In at least one embodiment, upon receiving a hypervisor call, hypervisor 1696 checks whether operating system 1695 has and has been granted permission to use graphics acceleration module 1646. In at least one embodiment, hypervisor 1696 then places process element 1683 in a process element list for a corresponding type of graphics acceleration module 1646. In at least one embodiment, a process element may include the information shown in Table 4. Table 4 - Process element information Item # Description 1 A job description (WD) 2 An Authority Mask Register (AMR) value (possibly masked). 3 An effective address (EA) Context save / restore pointer (CSRP) 4 A process ID (PID) and optionally a thread ID (TID) 5 A virtual address (VA) accelerator utilization set pointer (AURP) 6 Virtual address of the pointer to the memory segment table (SSTP) 7 A logical interrupt service number (LISN) 8 Interrupt vector table derived from hypervisor call parameters 9 A status register value (SR) 10 A logical partition ID (LPID) 11 A pointer to the hypervisor's accelerator utilization set with RealAddress (RA) 12 Memory Description Register (SDR)

[0261] In at least one embodiment, the hypervisor initializes a plurality of accelerator integration slice 1690 registers 1645.

[0262] As in Fig.16F, in at least one embodiment, a unified memory addressable via a common virtual memory address space is used to access physical processor memories 1601(1)-1601(N) and GPU memories 1620(1)-1620(N). In this implementation, operations performed on GPUs 1610(1)-1610(N) use the same virtual / effective address space to access processor memories 1601(1)-1601(M) and vice versa, simplifying programmability. In at least one embodiment, a first portion of a virtual / effective address space is mapped to processor memory 1601(1), a second portion is mapped to second processor memory 1601(N), a third portion is mapped to GPU memory 1620(1), and so on.In at least one embodiment, this distributes a total virtual / effective memory space (sometimes referred to as effective address space) across each of the processor memories 1601 and GPU memories 1620, such that each processor or GPU can access each physical memory with a virtual address associated with that memory.

[0263] In at least one embodiment, the bias / coherence management circuitry 1694A-1694E within one or more MMUs 1639A-1639E ensures cache coherence between the caches of one or more host processors (e.g., 1605) and GPUs 1610 and implements bias techniques that indicate in which physical memories certain data types should be stored. In at least one embodiment, while multiple instances of the bias / coherence management circuitry 1694A-1694E in Fig.16F, the bias / coherence circuitry may be implemented within an MMU of one or more host processors 1605 and / or within the accelerator integration circuitry 1636.

[0264] In one embodiment, GPU memories 1620 may be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without the performance penalty associated with full system cache coherence. In at least one embodiment, the ability to access GPU memories 1620 as system memory without burdensome cache coherence overhead provides a favorable operating environment for GPU offload. In at least one embodiment, this arrangement allows host processor 1605 software to set operands and access computation results without the overhead of traditional I / O DMA data copies. In at least one embodiment, such traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient compared to simple memory accesses.In at least one embodiment, the ability to access GPU memory 1620 without cache coherence overheads may be critical to the execution time of an offloaded computation. For example, in at least one embodiment, the cache coherence overhead may significantly reduce the effective write bandwidth of a graphics processor 1610 in cases with significant streaming write memory traffic. In at least one embodiment, operand construction efficiency, result access efficiency, and GPU computation efficiency may play a role in determining the effectiveness of a GPU offload.

[0265] In at least one embodiment, the selection of the GPU bias and the host processor bias is controlled by a bias tracker data structure. For example, in at least one embodiment, a bias table may be used, which may be a page-granular structure (e.g., controlled at the granularity of a memory page) comprising 1 or 2 bits per GPU-attached memory page. In at least one embodiment, a bias table may be implemented in a stolen memory region of one or more GPU memories 1620, with or without a bias cache in a GPU 1610 (e.g., to cache frequently / recently used bias table entries). Alternatively, in at least one embodiment, an entire bias table may be maintained in a GPU.

[0266] In at least one embodiment, a bias table entry associated with each access to GPU-attached memory 1620 is accessed prior to the actual GPU memory access, causing the following operations. In at least one embodiment, local requests from a GPU 1610 that find their page GPU-biased are forwarded directly to a corresponding GPU memory 1620. In at least one embodiment, local requests from a GPU that find their page in the host's bias are forwarded to processor 1605 (e.g., over a high-speed connection, as described herein). In at least one embodiment, requests from processor 1605 that find a requested page in the host processor's bias complete a request like a normal memory read.Alternatively, requests directed to a GPU-biased page may be forwarded to a GPU 1610. In at least one embodiment, a GPU may then forward a page to a host processor bias if it is not currently using the page. In at least one embodiment, a page's bias state may be changed either by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited number of cases, a purely hardware-based mechanism.

[0267] In at least one embodiment, a mechanism for changing the bias state uses an API call (e.g., OpenCL), which in turn calls a graphics processor's device driver, which in turn sends a message (or command descriptor) to a graphics processor instructing it to change a bias state and, on some transitions, perform a cache flush operation in a host. In at least one embodiment, a cache flush operation is used for a transition from the host processor 1605 bias to the GPU bias, but not for an opposite transition.

[0268] In at least one embodiment, cache coherence is maintained by temporarily making GPU-biased pages uncacheable by host processor 1605. In at least one embodiment, to access these pages, processor 1605 may request access from GPU 1610, which may or may not grant access immediately. Therefore, in at least one embodiment, to reduce communication between processor 1605 and GPU 1610, it is advantageous to ensure that GPU-biased pages are those required by a GPU but not by the host processor 1605, and vice versa.

[0269] Hardware structure(s) 815 are used to carry out one or more embodiments. Details of a hardware structure (or more hardware structures) 815 may be described herein in connection with Fig. 8A and / or 8B must be specified.

[0270] Fig.Figure 17 illustrates exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to the illustrated embodiments, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0271] Fig.17 is a block diagram illustrating an exemplary system-on-a-chip integrated circuit 1700 that may be fabricated using one or more IP cores, in accordance with at least one embodiment. In at least one embodiment, the integrated circuit 1700 includes one or more application processors 1705 (e.g., CPUs), at least one graphics processor 1710, and may additionally include an image processor 1715 and / or a video processor 1720, each of which may be a modular IP core. In at least one embodiment, the integrated circuit 1700 includes peripheral or bus logic, including a USB controller 1725, a UART controller 1730, an SPI / SDIO controller 1735, and an I22S / I22C controller 1740.In at least one embodiment, integrated circuit 1700 may include a display device 1745 coupled to one or more of the following interfaces: a High-Definition Multimedia Interface (HDMI) controller 1750 and a Mobile Industry Processor Interface (MIPI) interface 1755. In at least one embodiment, memory may be provided by a flash memory subsystem 1760 comprising flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1765 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1770.

[0272] Logic 815 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 815 are described herein in connection with Fig. 8A and / or 8B. In at least one embodiment, logic 815 in integrated circuit 1700 may be used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0273] In at least one embodiment, the integrated circuit 1700 may be used to implement the system 100 (see Fig. 1), the collage 200 (see Fig. 2), the System 300 (see Fig. 3), process 400 (see Fig. 4) and / or process 500 (see Fig.5). In at least one embodiment, at least a portion of the Fig. 17 depicted system(s) to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-7. For example, in at least one embodiment, at least one Fig. 17 may be used to cause one or more neural networks to use one or more textual descriptions to generate one or more 3D models of one or more first objects in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-7 are described.

[0274] Fig.18A-18B illustrate exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to the illustrated embodiments, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0275] Fig. 18A-18B are block diagrams illustrating example graphics processors for use in an SoC according to the embodiments described herein. Fig. 18A illustrates an exemplary system-on-chip integrated circuit graphics processor 1810 that may be fabricated using one or more IP cores in accordance with at least one embodiment. Fig.18B shows another exemplary graphics processor 1840 of an integrated circuit for a system on a chip that can be manufactured with one or more IP cores in accordance with at least one embodiment. In at least one embodiment, the graphics processor 1810 is Fig. 18A is a low-power graphics processor core. In at least one embodiment, the graphics processor 1840 is Fig. 18B, a higher performance graphics processor core. In at least one embodiment, each of the graphics processors 1810, 1840 may be a variant of the graphics processor 1710 of Fig. be 17.

[0276] In at least one embodiment, graphics processor 1810 includes a vertex processor 1805 and one or more fragment processors 1815A-1815N (e.g., 1815A, 1815B, 1815C, 1815D, through 1815N-1, and 1815N). In at least one embodiment, graphics processor 1810 may execute different shader programs via separate logic, such that vertex processor 1805 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1815A-1815N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1805 performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data.In at least one embodiment, fragment processor(s) 1815A-1815N use the primitive and vertex data generated by vertex processor 1805 to generate a framebuffer displayed on a display device. In at least one embodiment, fragment processor(s) 1815A-1815N are optimized for executing fragment shader programs as provided in an OpenGL API, which can be used to perform similar operations as a pixel shader program as provided in a Direct 3D API.

[0277] In at least one embodiment, graphics processor 1810 additionally includes one or more memory management units (MMUs) 1820A-1820B, cache(s) 1825A-1825B, and circuit interconnect(s) 1830A-1830B. In at least one embodiment, one or more MMU(s) 1820A-1820B provide virtual-to-physical address mapping for graphics processor 1810, including vertex processor 1805 and / or fragment processor(s) 1815A-1815N, which may reference vertex or image / texture data stored in memory in addition to the vertex or image / texture data stored in one or more cache(s) 1825A-1825B. In at least one embodiment, one or more MMU(s) 1820A-1820B may be synchronized with other MMUs within a system, including one or more MMUs associated with one or more application processors 1705, image processors 1715, and / or video processors 1720 of Fig.17, so that each processor 1705-1720 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1830A-1830B enable the graphics processor 1810 to interface with other IP cores within the SoC, either via an internal bus of the SoC or via a direct connection.

[0278] In at least one embodiment, the graphics processor 1840 includes one or more shader cores 1855A-1855N (e.g., 1855A, 1855B, 1855C, 1855D, 1855E, 1855F, through 1855N-1 and 1855N), as shown in Fig.18B, which provides a unified shader core architecture in which a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1840 includes an inter-core task manager 1845 acting as a thread dispatcher to distribute execution threads to one or more shader cores 1855A-1855N and a tiling unit 1858 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are divided in image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0279] Logic 815 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 815 are described herein in connection with Fig. 8A and / or 8B. In at least one embodiment, logic 815 in graphics processor 1810 and / or 1840 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0280] In at least one embodiment, the graphics processor 1810 may be used to operate the system 100 (see Fig. 1), the collage 200 (see Fig. 2), the System 300 (see Fig. 3), process 400 (see Fig. 4) and / or process 500 (see Fig.5). In at least one embodiment, at least a portion of the Fig. 18 depicted system(s) to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-7. For example, in at least one embodiment, at least one Fig. 18 may be used to cause one or more neural networks to use one or more textual descriptions to generate one or more 3D models of one or more first objects in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-7 are described.

[0281] Fig. 19A-19B illustrate additional exemplary graphics processor logic according to the embodiments described herein. In at least one embodiment, the Fig.19A-19B are integrated into a single system, such as a graphics processing unit (GPU), an SoC, or other type of processor. Fig. 19A shows a graphics core 1900 that, in at least one embodiment, includes the graphics processor 1710 of Fig. 17 and in at least one embodiment, a unified shader core 1855A-1855N as in Fig. 18B can be. Fig.19B illustrates a highly parallel general-purpose graphics processing unit (“GPGPU,” which may also be referred to as a “graphics processing unit”) 1930, which in at least one embodiment is suitable for use on a multi-chip module. In at least one embodiment, the graphics processing unit 1930 is a GPGPU that includes a graphics processor. In at least one embodiment, the integrated circuit 1700 includes the graphics core 1900, for example, to form an integrated circuit and / or an SoC, such an integrated circuit and / or SoC performing the operations described herein.

[0282] In at least one embodiment, the graphics core 1900 includes a shared instruction cache 1902, a texture unit 1918, and a cache / shared memory 1920 (e.g., including L1, L2, L3, last-level cache, or other caches) common to the execution resources within the graphics core 1900. In at least one embodiment, the graphics core 1900 may include multiple slices 1901A-1901N or a partition for each core, and a graphics processor may include multiple instances of the graphics core 1900. In at least one embodiment, each slice 1901A-1901N relates to the graphics core 1900. In at least one embodiment, the slices 1901A-1901N include subslices that are part of a slice 1901A-1901N. In at least one embodiment, slices 1901A-1901N are independent of other slices or dependent on other slices.In at least one embodiment, slices 1901A-1901N may include support logic including a local instruction cache 1904A-1904N, a thread scheduler (sequencer) 1906A-1906N, a thread dispatcher 1908A-1908N, and a set of registers 1910A-1910N. In at least one embodiment, slices 1901A-1901N may include a set of additional functional units (AFUs 1912A-1912N), floating-point units (FPUs 1914A-1914N), integer arithmetic logic units (ALUs 1916A-1916N), address calculation units (ACUs 1913A-1913N), double-precision floating-point units (DPFPUs 1915A-1915N), and matrix processing units (MPUs 1917A-1917N). In at least one embodiment, MPUs 1917A-1917N are referred to as matrix engines.

[0283] In at least one embodiment, each slice 1901A-1901N includes one or more engines for floating-point and integer vector operations and one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large dataset workloads. In at least one embodiment, one or more slices 1901A-1901N include one or more vector engines for computing a vector (e.g., computing mathematical operations on vectors). In at least one embodiment, a vector engine can compute a vector operation in 16-bit floating point (also referred to as "FP16"), 32-bit floating point (also referred to as "FP32"), or 64-bit floating point (also referred to as "FP64").In at least one embodiment, one or more slices 1901A-1901N comprise 16 vector engines paired with 16 matrix math units for computing matrix / tensor operations, where the vector engines and math units are accessible via matrix extensions. In at least one embodiment, a slice comprises a particular portion of the processing resources of a processing unit, for example, 16 cores and a ray tracing unit, or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units for a processor. In at least one embodiment, the graphics core 1900 comprises one or more matrix engines for computing matrix operations, for example, in computing tensor operations.

[0284] In at least one embodiment, one or more slices 1901A-1901N include one or more ray tracing units for computing ray tracing operations (e.g., 16 ray tracing units per slice 1901A-1901N). In at least one embodiment, a ray tracing unit computes ray traversal, triangle intersection, bounding box intersection, or other ray tracing operations.

[0285] In at least one embodiment, one or more slices 1901A-1901N comprise a media slice that encodes, decodes, and / or transcodes data, scales and / or formats data, and / or performs video quality operations on video data.

[0286] In at least one embodiment, one or more slices 1901A-1901N are connected to an L2 cache and memory structure, interconnect ports, HBM stacks (e.g., HBM2e, HDM3), and a media engine. In at least one embodiment, one or more slices 1901A-1901N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 1901A-1901N include one or more L1 caches. In at least one embodiment, one or more slices 1901A-1901N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing data, e.g.,B, corresponding instructions; one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometries for performing operations in geometry pipelines and / or for applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector graphics format (e.g., shape) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed, combine to form an image represented by shapes); one or more Hierarchical Depth Buffers (Hiz) for buffering data; and / or one or more pixel backends. In at least one embodiment, a slice 1901A-1901N includes a structure of memory, such as an L2 cache.

[0287] In at least one embodiment, the FPUs 1914A-1914N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 1915A-1915N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1916A-1916N can perform variable-precision integer operations at 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1917A-1917N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations. In at least one embodiment, the MPUs 1917-1917N may perform a variety of matrix operations to accelerate machine learning application frameworks, including support for accelerated generalized matrix-matrix multiplication (GEMM).In at least one embodiment, AFUs 1912A-1912N may perform additional logical operations not supported by floating point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0288] Logic 815 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 815 are described herein in connection with Fig. 8A and / or 8B. In at least one embodiment, logic 815 in graphics core 1900 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or the neural network use cases described herein.

[0289] In at least one embodiment, the graphics core 1900 includes an interconnect and a sublayer of the link fabric connected to a switch and a GPU-GPU bridge that enables multiple graphics processors 1900 (e.g., 8) to be interconnected without glue, with load / store units (LSUs), data transfer units, and synchronization semantics across multiple graphics processors 1900. In at least one embodiment, the interconnects include standardized interconnects (e.g., PCIe) or a combination thereof.

[0290] In at least one embodiment, the graphics core 1900 includes multiple tiles. In at least one embodiment, a tile is a single die or one or more dies, where individual dies may be connected to an interconnect (e.g., Embedded Multi-Die Interconnect Bridge (EMIB)). In at least one embodiment, the graphics core 1900 includes a compute tile, a memory tile (e.g., where a memory tile can be exclusively accessed by different tiles or different chipsets, such as a Rambo tile), a substrate tile, a base tile, an HMB tile, a link tile, and an EMIB tile, all of which tiles are packaged together in the graphics core 1900 as part of a GPU. In at least one embodiment, the graphics core 1900 may include multiple tiles in a single package (also referred to as a "multi-tile package").In at least one embodiment, a compute tile may include 8 graphics cores 1900, an L1 cache, and a base tile; a host interface with PCIe 5.0, HBM2e, MDFI, and EMIB; and a link tile with 8 links, 8 ports, and an embedded switch. In at least one embodiment, the tiles are connected using face-to-face (F2F) chip-on-chip bonding via finely pitched 36-micrometer microbumps (e.g., copper pillars). In at least one embodiment, the graphics core 1900 includes a fabric that includes memory and is accessible by multiple tiles. In at least one embodiment, the graphics core 1900 stores, accesses, or loads its own hardware contexts into memory. A hardware context is a set of data loaded from registers before a process continues, and a hardware context may indicate a state of the hardware (e.g., the state of a GPU).

[0291] In at least one embodiment, the graphics core 1900 includes a serialization / deserialization circuit (SERDES) that converts a serial data stream to a parallel data stream or converts a parallel data stream to a serial data stream.

[0292] In at least one embodiment, the graphics core 1900 includes a high-speed coherent fabric (GPU to GPU), load / store units, bulk data transfer, and synchronization semantics, and GPUs connected via an embedded switch, with a GPU-GPU bridge controlled by a controller.

[0293] In at least one embodiment, the graphics core 1900 executes an API, where the API abstracts the hardware of the graphics core 1900 and accesses libraries of instructions for performing mathematical operations (e.g., math kernel library), deep neural network operations (e.g., deep neural network library), vector operations, collective communication, thread blocks, video processing, data analysis library, and / or ray tracing operations.

[0294] In at least one embodiment, the graphics core 1900 may be used to operate the system 100 (see Fig. 1), the collage 200 (see Fig. 2), the System 300 (see Fig. 3), process 400 (see Fig. 4) and / or process 500 (see Fig. 5). In at least one embodiment, at least a portion of the Fig.19 depicted system(s) to implement one or more systems, techniques, functions and / or processes that are used in conjunction with Fig. 1-7. For example, in at least one embodiment, at least one Fig. 19 may be used to cause one or more neural networks to use one or more textual descriptions to generate one or more 3D models of one or more first objects in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-7 are described.

[0295] Fig.19B shows the GPGPU 1930, which in at least one embodiment can be configured to perform highly parallel computational operations by an array of graphics processing units. In at least one embodiment, the GPGPU 1930 can be directly connected to other instances of the GPGPU 1930 to form a multi-GPU cluster and improve training speed for deep neural networks. In at least one embodiment, the GPGPU 1930 includes a host interface 1932 to enable connection to a host processor. In at least one embodiment, the host interface 1932 is a PCI Express interface. In at least one embodiment, the host interface 1932 can be a vendor-specific communication interface or communication fabric.In at least one embodiment, GPGPU 1930 receives instructions from a host processor and uses a global scheduler 1934 (which may be referred to as a thread sequencer and / or asynchronous compute engine) to distribute the execution threads associated with those instructions among a number of compute clusters 1936A-1936H. In at least one embodiment, compute clusters 1936A-1936H share a cache 1938. In at least one embodiment, cache 1938 may serve as a high-level cache for caches in compute clusters 1936A-1936H. In at least one embodiment, compute clusters 1936A-1936H comprise a slice or are referred to as "slices." In at least one embodiment, GPGPU 1930 is part of an SoC, for example, part of integrated circuit 1700 (FIG. 1). Fig. 17).

[0296] In at least one embodiment, GPGPU 1930 includes memory 1944A-1944B coupled to compute clusters 1936A-1936H via a set of memory controllers 1942A-1942B (e.g., one or more controllers for HBM2e). In at least one embodiment, memory 1944A-1944B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate memory (GDDR).

[0297] In at least one embodiment, the compute clusters 1936A-1936H each comprise a set of graphics cores, such as the graphics core 1900 of Fig.19A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with a range of precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of floating-point units in each of compute clusters 1936A-1936H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of floating-point units may be configured to perform 64-bit floating-point operations.

[0298] In at least one embodiment, multiple instances of the GPGPU 1930 can be configured to operate as a compute cluster. In at least one embodiment, the communication used by the compute clusters 1936A-1936H for synchronization and data exchange varies between embodiments. In at least one embodiment, multiple instances of the GPGPU 1930 communicate via the host interface 1932. In at least one embodiment, the GPGPU 1930 includes an I / O hub 1939 that couples the GPGPU 1930 to a GPU interconnect 1940 that enables direct connection to other instances of the GPGPU 1930. In at least one embodiment, the GPU interconnect 1940 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of the GPGPU 1930.In at least one embodiment, GPU interconnect 1940 is coupled to a high-speed interconnect for sending and receiving data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1930 are located in separate computing systems and communicate via a network interface accessible via host interface 1932. In at least one embodiment, GPU interconnect 1940 may be configured to enable connection to a processor in addition to, or alternatively to, host interface 1932.

[0299] In at least one embodiment, GPGPU 1930 may be configured to train neural networks. In at least one embodiment, GPGPU 1930 may be used within an inference platform. In at least one embodiment where GPGPU 1930 is used for inference, GPGPU 1930 may include fewer compute clusters 1936A-1936H than when GPGPU 1930 is used for training a neural network. In at least one embodiment, the memory technology associated with memory 1944A-1944B may differ between inference and training configurations, with higher-bandwidth memory technologies being allocated to the training configurations. In at least one embodiment, an inference configuration of GPGPU 1930 may support inferencing specific instructions.For example, in at least one embodiment, an inference configuration may provide support for one or more 8-bit integer dot product instructions that may be used during inference operations for deployed neural networks.

[0300] Logic 815 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 815 are described herein in connection with Fig. 8A and / or 8B. In at least one embodiment, logic 815 in GPGPU 1930 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0301] In at least one embodiment, GPGPU 1930 may be used to implement System 100 (see Fig. 1), Collage 200 (see Fig. 2), System 300 (see Fig. 3), Process 400 (see Fig. 4) and / or process 500 (see Fig. 5) may be used. In at least one embodiment, at least a portion of the Fig. 19 depicted system(s) to implement one or more systems, techniques, functions and / or processes that are used in conjunction with Fig. 1-7. For example, in at least one embodiment, at least one Fig.19 may be used to cause one or more neural networks to use one or more textual descriptions to generate one or more 3D models of one or more first objects in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-7 are described.

[0302] Fig.20 is a block diagram illustrating a computer system 2000 according to at least one embodiment. In at least one embodiment, computer system 2000 includes a processing subsystem 2001 having one or more processors 2002 and a system memory 2004 communicating via an interconnect path that may include a memory hub 2005. In at least one embodiment, memory hub 2005 may be a separate component within a chipset component or integrated with one or more processors 2002. In at least one embodiment, memory hub 2005 is coupled to an I / O subsystem 2011 via a communications link 2006. In at least one embodiment, I / O subsystem 2011 includes an I / O hub 2007 that may enable computer system 2000 to receive input from one or more input devices 2008.In at least one embodiment, the I / O hub 2007 may enable a display controller, which may be included in one or more processors 2002, to provide output to one or more display devices 2010A. In at least one embodiment, one or more display devices 2010A connected to the I / O hub 2007 may comprise a local, internal, or embedded display device.

[0303] In at least one embodiment, the processing subsystem 2001 includes one or more parallel processors 2012 connected to the storage hub 2005 via a bus or other communication link 2013. In at least one embodiment, the communication link 2013 may use any number of standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or communication structure. In at least one embodiment, one or more parallel processors 2012 form a compute-intensive parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as a Many Integrated Core (MIC) processor.In at least one embodiment, some or all of the parallel processors 2012 form a graphics processing subsystem that can output pixels to one or more display devices 2010A coupled via I / O hub 2007. In at least one embodiment, the parallel processor(s) 2012 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 2010B. In at least one embodiment, the parallel processor(s) 2012 include one or more cores, such as the graphics cores 1900 discussed herein.

[0304] In at least one embodiment, a system storage unit 2014 may be connected to the I / O hub 2007 to provide a storage mechanism for the computer system 2000. In at least one embodiment, an I / O switch 2016 may be used to provide an interface that enables connections between the I / O hub 2007 and other components, such as a network adapter 2018 and / or a wireless network adapter 2019 that may be integrated into the platform, and various other devices that may be added via one or more add-in devices 2020. In at least one embodiment, the network adapter 2018 may be an Ethernet adapter or other wired network adapter.In at least one embodiment, the wireless network adapter 2019 may include one or more of the following devices: Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices that include one or more wireless radios.

[0305] In at least one embodiment, the computer system 2000 may include other components not explicitly shown, including USB or other connectors, optical storage devices, video capture devices, and the like, which may also be connected to the I / O hub 2007. In at least one embodiment, communication paths connecting various components in Fig.20 interconnection may be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI Express) or other bus or point-to-point communication links and / or protocols, such as NV-Link high-speed links or interconnection protocols.

[0306] In at least one embodiment, the parallel processor(s) 2012 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and form a graphics processing unit (GPU). For example, the parallel processor(s) 2012 includes a graphics core 1900. In at least one embodiment, the parallel processor(s) 2012 include circuitry optimized for general processing. In at least one embodiment, the components of the computer system 2000 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, the parallel processor(s) 2012, the memory hub 2005, the processor(s) 2002, and the I / O hub 2007 may be integrated into a system-on-a-chip (SoC) integrated circuit.In at least one embodiment, the components of computer system 2000 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computer system 2000 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computer system.

[0307] Logic 815 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 815 are described herein in connection with Fig. 8A and / or 8B. In at least one embodiment, logic 815 in computer system 2000 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training systems, neural network functions and / or architectures, or neural network use cases described herein.

[0308] In at least one embodiment, computer system 2000 may be used to implement system 100 (see Fig. 1), the collage 200 (see Fig. 2), the System 300 (see Fig. 3), process 400 (see Fig. 4) and / or process 500 (see Fig. 5). In at least one embodiment, at least a portion of the Fig. 20 system(s) depicted is used to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-7. For example, in at least one embodiment, at least one Fig. 20 may be used to cause one or more neural networks to use one or more textual descriptions to generate one or more 3D models of one or more first objects in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-7 are described. PROCESSORS

[0309] Fig. 21A shows a parallel processor 2100 according to at least one embodiment. In at least one embodiment, various components of the parallel processor 2100 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the parallel processor 2100 shown is a variant of one or more parallel processors 2102 as described in Fig. 20 according to an exemplary embodiment. In at least one embodiment, a parallel processor 2100 includes one or more graphics cores 1900.

[0310] In at least one embodiment, parallel processor 2100 includes a parallel processing unit 2102. In at least one embodiment, parallel processing unit 2102 includes an I / O unit 2104 that enables communication with other devices, including other instances of parallel processing unit 2102. In at least one embodiment, I / O unit 2104 can be directly connected to other devices. In at least one embodiment, I / O unit 2104 is connected to other devices via a hub or switch interface, such as a storage hub 2105. In at least one embodiment, the connections between storage hub 2105 and I / O unit 2104 form a communication link 2113.In at least one embodiment, the I / O unit 2104 is coupled to a host interface 2106 and a memory crossbar 2116, where the host interface 2106 receives commands to perform processing operations and the memory crossbar 2116 receives commands to perform memory operations.

[0311] In at least one embodiment, when host interface 2106 receives a command buffer via I / O unit 2104, host interface 2106 may direct work operations to a front end 2108 to execute those commands. In at least one embodiment, front end 2108 is coupled to a scheduler 2110 (which may also be referred to as a sequencer) configured to dispatch commands or other work items to a processing cluster array 2112. In at least one embodiment, scheduler 2110 ensures that processing array 2112 is properly configured and in a valid state before dispatching tasks to a cluster of processing array 2112. In at least one embodiment, scheduler 2110 is implemented via firmware logic executing on a microcontroller.In at least one embodiment, the microcontroller-implemented scheduler 2110 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on the processing array 2112. In at least one embodiment, host software may allocate workloads for scheduling on the processing cluster array 2112 via one of several graphics processing paths. In at least one embodiment, the workloads may then be automatically distributed across the processing array cluster 2112 by the logic of the scheduler 2110 within a microcontroller that includes the scheduler 2110.

[0312] In at least one embodiment, the processing array 2112 may include up to "N" processing clusters (e.g., cluster 2114A, cluster 2114B, and finally cluster 2114N), where "N" represents a positive integer (which may be a different integer "N" than used in other figures). In at least one embodiment, each cluster 2114A-2114N of the processing cluster array 2112 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2110 may allocate work to the clusters 2114A-2114N of the processing array 2112 using various scheduling and / or work distribution algorithms, which may vary depending on the workload associated with each type of program or computation.In at least one embodiment, scheduling may be performed dynamically by scheduler 2110 or assisted at least in part by compiler logic during compilation of program logic configured for execution by processing cluster array 2112. In at least one embodiment, different clusters 2114A-2114N of processing cluster array 2112 may be allocated for processing different program types or for performing different types of computations.

[0313] In at least one embodiment, processing cluster array 2112 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2112 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 2112 may include logic to perform processing tasks, including filtering video and / or audio data, performing modeling operations, including physics operations, and performing data transformations.

[0314] In at least one embodiment, the processing cluster array 2112 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2112 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2112 may be configured to execute graphics processing-related shader programs, such as vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2102 may transfer data from system memory via the I / O unit 2104 for processing.In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2122) during processing and then written back to system memory.

[0315] In at least one embodiment, when parallel processing unit 2102 is used to perform graphics processing, scheduler 2110 may be configured to divide a workload into approximately equal-sized tasks to enable better distribution of graphics processing operations across multiple clusters 2114A-2114N of processing array 2112. In at least one embodiment, portions of processing cluster array 2112 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen operations to generate a rendered image for display.In at least one embodiment, intermediate data generated by one or more of clusters 2114A-2114N may be stored in buffers to allow intermediate data to be transferred between clusters 2114A-2114N for further processing.

[0316] In at least one embodiment, processing cluster array 2112 may receive processing tasks to be executed via scheduler 2110, which receives commands defining processing tasks from frontend 2108. In at least one embodiment, the processing tasks may include indices of the data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands that define how the data should be processed (e.g., which program should be executed). In at least one embodiment, scheduler 2110 may be configured to retrieve or receive indices corresponding to the tasks from frontend 2108.In at least one embodiment, the front end 2108 may be configured to ensure that the processing cluster array 2112 is configured in a valid state before initiating a workload specified by incoming command buffers (e.g., batch buffers, push buffers, etc.).

[0317] In at least one embodiment, each of one or more instances of parallel processing unit 2102 may be coupled to a parallel processor memory 2122. In at least one embodiment, parallel processor memory 2122 may be accessed via memory crossbar 2116, which may receive memory requests from processing cluster array 2112 as well as from I / O unit 2104. In at least one embodiment, memory crossbar 2116 may access parallel processor memory 2122 via a memory interface 2118. In at least one embodiment, memory interface 2118 may include multiple partition units (e.g., partition unit 2120A, partition unit 2120B, through partition unit 2120N), each of which may be coupled to a portion (e.g., memory unit) of parallel processor memory 2122.In at least one embodiment, a number of partition units 2120A-2120N is configured to be equal to a number of storage units, such that a first partition unit 2120A has a corresponding first storage unit 2124A, a second partition unit 2120B has a corresponding storage unit 2124B, and an Nth partition unit 2120N has a corresponding Nth storage unit 2124N. In at least one embodiment, a number of partition units 2120A-2120N may not be equal to a number of storage units.

[0318] In at least one embodiment, memory units 2124A-2124N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate memory (GDDR). In at least one embodiment, memory units 2124A-2124N may also include 3D stacks, including, but not limited to, high-width memory (HBM), HBM2e, or HDM3. In at least one embodiment, rendering targets, such as frame buffers or texture maps, may be stored across memory units 2124A-2124N, allowing partition units 2120A-2120N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of parallel processor memory 2122.In at least one embodiment, a local instance of parallel processor memory 2122 may be eliminated in favor of a unified memory design that utilizes system memory in conjunction with the local cache memory.

[0319] In at least one embodiment, each of the clusters 2114A-2114N of the processing array 2112 can process data written to each of the memory units 2124A-2124N within the parallel processor memory 2122. In at least one embodiment, the memory crossbar 2116 can be configured to transfer an output of each cluster 2114A-2114N to any partition unit 2120A-2120N or to another cluster 2114A-2114N that can perform additional processing operations on an output. In at least one embodiment, each cluster 2114A-2114N can communicate with the memory interface 2118 via the memory crossbar 2116 to read from or write to various external devices.In at least one embodiment, the memory crossbar 2116 includes a connection to the memory interface 2118 to communicate with the I / O unit 2104, as well as a connection to a local instance of the parallel processor memory 2122, which enables the processing units in the different processing clusters 2114A-2114N to communicate with system memory or other memory not local to the parallel processing unit 2102. In at least one embodiment, the memory crossbar 2116 may use virtual channels to separate traffic flows between clusters 2114A-2114N and partition units 2120A-2120N.

[0320] In at least one embodiment, multiple instances of the parallel processing unit 2102 may be deployed on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2102 may be configured to work together, even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences.

[0321] For example, in at least one embodiment, some instances of parallel processing unit 2102 may include higher-precision floating-point units compared to other instances. In at least one embodiment, systems including one or more instances of parallel processing unit 2102 or parallel processor 2100 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0322] Fig. 21B is a block diagram of a partition unit 2120 according to at least one embodiment. In at least one embodiment, the partition unit 2120 is an example of one of the partition units 2120A-2120N of Fig. 21A. In at least one embodiment, partition unit 2120 includes an L2 cache 2121, a frame buffer interface 2125, and a ROP 2126 (raster operation unit). In at least one embodiment, L2 cache 2121 is a read / write cache configured to perform load and store operations received from memory crossbar 2116 and ROP 2126. In at least one embodiment, read misses and urgent writeback requests are issued from L2 cache 2121 to frame buffer interface 2125 for processing. In at least one embodiment, updates may also be sent to a frame buffer via frame buffer interface 2125 for processing. In at least one embodiment, frame buffer interface 2125 has an interface to one of the memory units in parallel processor memory, such as memory units 2124A-2124N of Fig. 21A (for example, within the parallel processor memory 2122).

[0323] In at least one embodiment, ROP 2126 is a processing unit that performs raster operations such as stenciling, Z-testing, blending, etc. In at least one embodiment, ROP 2126 then outputs processed graphics data, which is stored in graphics memory. In at least one embodiment, ROP 2126 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic using one or more of several compression algorithms. In at least one embodiment, the type of compression performed by ROP 2126 may vary based on the statistical properties of the data to be compressed.For example, in at least one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[0324] In at least one embodiment, ROP 2126 is in each processing cluster (e.g., clusters 2114A-2114N of Fig. 21A) instead of in the partition unit 2120. In at least one embodiment, read and write requests for pixel data are transmitted via the memory crossbar 2116 instead of pixel fragment data. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display devices 2010 of Fig. 20, for further processing by processor(s) 2002 or for further processing by one of the processing units within the parallel processor 2100 of Fig. 21A.

[0325] Fig. 21C is a block diagram of a processing cluster 2114 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is an instance of one of the processing clusters 2114A-2114N of Fig. 21A. In at least one embodiment, the processing cluster 2114 may be configured to execute many threads in parallel, where "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction issuance techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit configured to issue instructions to a number of processing engines in each of the processing clusters.

[0326] In at least one embodiment, the operation of the processing cluster 2114 may be controlled by a pipeline manager 2132, which distributes processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2132 receives instructions from the scheduler 2110 of Fig. 21A and manages the execution of these instructions via a graphics multiprocessor 2134 and / or a texture unit 2136. In at least one embodiment, the graphics multiprocessor 2134 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 2114 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, one or more graphics multiprocessors 2134 may be included in a processing cluster 2114. In at least one embodiment, the graphics multiprocessor 2134 may process data, and a data crossbar 2140 may be used to distribute the processed data to one of several possible destinations, including other shader units.In at least one embodiment, the pipeline manager 2132 may facilitate the distribution of processed data by specifying destinations for processed data to be distributed across the data crossbar 2140.

[0327] In at least one embodiment, each graphics multiprocessor 2134 within the processing cluster 2114 may include an identical set of functional execution logic (e.g., arithmetic logic units, load / store units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipeline in which new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and the computation of various algebraic functions. In at least one embodiment, the same hardware with functional units may be used to perform different operations, and any combination of functional units may be present.

[0328] In at least one embodiment, the instructions transferred to the processing cluster 2114 form a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program on different input data. In at least one embodiment, each thread within a thread group may be assigned to a different engine within a graphics multiprocessor 2134. In at least one embodiment, a thread group may include fewer threads than a number of processing engines within the graphics multiprocessor 2134.In at least one embodiment, when a thread group includes fewer threads than a number of processing engines, one or more of the processing engines may be idle during the cycles in which that thread group is processing. In at least one embodiment, a thread group may also include more threads than a number of processing engines within the graphics multiprocessor 2134. In at least one embodiment, when a thread group includes more threads than the number of processing engines in the graphics multiprocessor 2134, processing may occur in consecutive clock cycles. In at least one embodiment, multiple thread groups may execute concurrently on a graphics multiprocessor 2134.

[0329] In at least one embodiment, the graphics multiprocessor 2134 includes an internal cache for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2134 may forgo an internal cache and utilize a cache (e.g., L1 cache 2148) within the processing cluster 2114. In at least one embodiment, each graphics multiprocessor 2134 also has access to L2 caches within partition units (e.g., partition units 2120A-2120N of Fig. 21A) that are shared by all processing clusters 2114 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2134 can also access off-chip global memory, which can include one or more of the parallel processor local memories and / or system memories. In at least one embodiment, any memory external to parallel processing unit 2102 can be used as global memory. In at least one embodiment, processing cluster 2114 includes multiple instances of graphics multiprocessor 2134 and can utilize common instructions and data that can be stored in L1 cache 2148.

[0330] In at least one embodiment, each processing cluster 2114 may include a memory management unit (MMU) 2145 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2145 may reside in the memory interface 2118 of Fig. 21A. In at least one embodiment, MMU 2145 includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile, and optionally a cache line index. In at least one embodiment, MMU 2145 may include address translation lookaside buffers (TLBs) or caches, which may be located in graphics multiprocessor 2134 or L1 2148 cache, or in processing cluster 2114. In at least one embodiment, a physical address is processed to distribute access to surface data locally to enable efficient interleaving of requests between partition units. In at least one embodiment, a cache line index may be used to determine whether a request for a cache line is a hit or miss.

[0331] In at least one embodiment, a processing cluster 2114 may be configured such that each graphics multiprocessor 2134 is coupled to a texture unit 2136 to perform texture mapping operations, such as determining texture pattern positions, reading texture data, and filtering texture data. In at least one embodiment, the texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2134 and retrieved from an L2 cache, local parallel processor memory, or system memory as needed.In at least one embodiment, each graphics multiprocessor 2134 issues processed tasks to the data crossbar 2140 to provide the processed task to another processing cluster 2114 for further processing via the memory crossbar 2116, or to store the processed task in an L2 cache, parallel processor local memory, or system memory. In at least one embodiment, a pre-raster operations unit (preROP) 2142 is configured to receive data from the graphics multiprocessor 2134 and forward data to ROP units, which may be arranged with partition units as described herein (e.g., partition units 2120A-2120N of FIG. Fig. 21A). In at least one embodiment, the preROP unit 2142 may perform optimizations for mixing colors, organizing pixel color data, and performing address translations.

[0332] Logic 815 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 815 are described herein in connection with Fig. 8A and / or 8B. In at least one embodiment, logic 815 in graphics processing cluster 2114 may be used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0333] In at least one embodiment, the parallel processor 2100 may be used to implement the system 100 (see Fig. 1), the collage 200 (see Fig. 2), the System 300 (see Fig. 3), process 400 (see Fig. 4) and / or process 500 (see Fig. 5). In at least one embodiment, at least a portion of the Fig. 21 depicted system(s) to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-7. For example, in at least one embodiment, at least one Fig. 21 may be used to cause one or more neural networks to use one or more textual descriptions to generate one or more 3D models of one or more first objects in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-7 are described.

[0334] Fig. Figure 21D illustrates a graphics multiprocessor 2134 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2134 is coupled to the pipeline manager 2132 of the processing cluster 2114. In at least one embodiment, the graphics multiprocessor 2134 includes an execution pipeline including, among other things, an instruction cache 2152, an instruction unit 2154, an address mapping unit 2156, a register file 2158, one or more general purpose graphics processing units (GPGPU cores) 2162, and one or more load / store units 2166, where one or more load / store units 2166 may perform load / store operations to load / store instructions according to the performance of an operation. In at least one embodiment, the GPGPU cores 2162 and the load / store units 2166 are coupled to the cache memory 2172 and the shared memory 2170 via a memory and cache interconnect 2168.In at least one embodiment, the GPGPU cores 2162 are part of a SoC, such as part of the integrated circuit 1700 in . Fig. 17.

[0335] In at least one embodiment, instruction cache 2152 receives a stream of instructions to be executed from pipeline manager 2132. In at least one embodiment, the instructions are cached in instruction cache 2152 and forwarded for execution by an instruction unit 2154. In at least one embodiment, instruction unit 2154 may dispatch instructions in the form of thread groups (e.g., warps, wavefronts, waves), where each thread of a thread group is associated with a different execution unit within GPGPU cores 2162. In at least one embodiment, an instruction may access a local, shared, or global address space by specifying an address within a unified address space.In at least one embodiment, address mapping unit 2156 may be used to translate addresses in a unified address space into a unique memory address accessible by load / store units 2166.

[0336] In at least one embodiment, register file 2158 provides a set of registers for functional units of graphics multiprocessor 2134. In at least one embodiment, register file 2158 provides temporary storage for operands associated with data paths of functional units (e.g., GPGPU cores 2162, load / store units 2166) of graphics multiprocessor 2134. In at least one embodiment, register file 2158 is partitioned among individual functional units such that each functional unit is assigned its own section of register file 2158. In at least one embodiment, register file 2158 is partitioned among different warps (which may be referred to as wavefronts and / or waves) executed by graphics multiprocessor 2134.

[0337] In at least one embodiment, GPGPU cores 2162 may each include floating-point units (FPUs) and / or integer arithmetic logic units (ALUs) used to execute instructions of graphics multiprocessor 2134. In at least one embodiment, GPGPU cores 2162 may be similar in architecture or different in architecture. In at least one embodiment, a first portion of GPGPU cores 2162 includes a single-precision FPU and an integer ALU, while a second portion of GPGPU cores includes a double-precision FPU. In at least one embodiment, FPUs may implement IEEE 754-2008 standard floating-point arithmetic or enable variable-precision floating-point arithmetic.In at least one embodiment, the graphics multiprocessor 2134 may additionally include one or more fixed-function or special-purpose functional units to perform specific functions such as copying rectangles or blending pixels. In at least one embodiment, one or more of the GPGPU cores 2162 may also include fixed-function logic or special-purpose logic.

[0338] In at least one embodiment, GPGPU cores 2162 include SIMD logic capable of applying a single instruction to multiple data sets. In at least one embodiment, GPGPU cores 2162 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU cores can be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for SPMD or SIMT (Single Program Multiple Data) architectures. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0339] In at least one embodiment, the memory and cache interconnect 2168 is an interconnect network that connects each functional unit of the graphics multiprocessor 2134 to the register file 2158 and the shared memory 2170. In at least one embodiment, the memory and cache interconnect 2168 is a crossbar interconnect that enables the load / store unit 2166 to perform load and store operations between the shared memory 2170 and the register file 2158. In at least one embodiment, the register file 2158 may operate at the same frequency as the GPGPU cores 2162, so that data transfer between the GPGPU cores 2162 and the register file 2158 may have very low latency. In at least one embodiment, a shared memory 2170 may be used to enable communication between threads executing on functional units within the graphics multiprocessor 2134.For example, in at least one embodiment, cache 2172 may be used as a data cache to cache texture data transferred between functional units and texture unit 2136. In at least one embodiment, shared memory 2170 may also be used as a program-managed cache. In at least one embodiment, threads executing on GPGPU cores 2162 may programmatically store data in shared memory in addition to the automatically cached data stored in cache 2172.

[0340] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to host processor cores to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, a GPU may be communicatively coupled to the host processor cores via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, an SoC includes a parallel processor or GPGPU, as described herein, with the parallel processor or GPGPU executing on the SoC. In at least one embodiment, a GPU may be integrated on a package or die as cores and communicatively interconnected to the cores via an internal processor bus / interconnect within a package or die.In at least one embodiment, regardless of how a GPU is connected, the processor cores can assign work to that GPU in the form of sequences of instructions contained in a work description. In at least one embodiment, the GPU then uses special circuitry / logic to efficiently process these instructions / instructions.

[0341] Logic 815 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 815 are described herein in connection with Fig. 8A and / or 8B. In at least one embodiment, logic 815 in graphics multiprocessor 2134 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0342] In at least one embodiment, the graphics multiprocessor 2134 may be used to operate the system 100 (see Fig. 1), the collage 200 (see Fig. 2), the System 300 (see Fig. 3), process 400 (see Fig. 4) and / or process 500 (see Fig. 5). In at least one embodiment, at least a portion of the Fig. 21 depicted system(s) to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-7. For example, in at least one embodiment, at least one Fig. 21 may be used to cause one or more neural networks to use one or more textual descriptions to generate one or more 3D models of one or more first objects in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-7 are described.

[0343] Fig. 22 shows a multi-GPU computer system 2200 according to at least one embodiment. In at least one embodiment, the multi-GPU computer system 2200 may include a processor 2202 connected to a plurality of general-purpose graphics processing units (GPGPUs) 2206A-D via a host interface switch 2204. In at least one embodiment, the host interface switch 2204 is a PCI Express switch device that connects the processor 2202 to a PCI Express bus over which the processor 2202 can communicate with the GPGPUs 2206A-D. In at least one embodiment, the GPGPUs 2206A-D may be interconnected via a series of high-speed point-to-point GPU-to-GPU interconnects 2216. In at least one embodiment, the GPU-to-GPU connections 2216 are connected to each of the GPGPUs 2206A-D via a separate GPU connection.In at least one embodiment, P2P GPU connections 2216 enable direct communication between the individual GPGPUs 2206A-D without requiring communication through the host interface 2204 to which the processor 2202 is connected. In at least one embodiment where GPU-to-GPU traffic is routed on P2P GPU connections 2216, the host interface bus 2204 remains available for accessing system memory or for communicating with other instances of the multi-GPU computer system 2200, for example, via one or more network devices. While in at least one embodiment the GPGPUs 2206A-D are connected to the processor 2202 via the host interface switch 2204, in at least one embodiment the processor 2202 includes direct support for P2P GPU connections 2216 and can be connected directly to the GPGPUs 2206A-D.In at least one embodiment, the GPGPUs 2206A-D are part of a SoC, such as part of the integrated circuit 1700 in . Fig. 17, wherein the GPGPUs 2206A-D perform the operations described herein.

[0344] Logic 815 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 815 are described herein in connection with Fig. 8A and / or 8B. In at least one embodiment, logic 815 in multi-GPU computing system 2200 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0345] In at least one embodiment, the multi-GPU computer system 2200 includes one or more graphics cores 1900.

[0346] In at least one embodiment, the multi-GPU computer system 2200 may be used to implement the system 100 (see Fig. 1), the collage 200 (see Fig. 2), the System 300 (see Fig. 3), process 400 (see Fig. 4) and / or process 500 (see Fig. 5). In at least one embodiment, at least a portion of the Fig. 22 depicted system(s) to implement one or more systems, techniques, functions and / or processes associated with Fig. 1-7. For example, in at least one embodiment, at least one Fig. 22 may be used to cause one or more neural networks to use one or more textual descriptions to generate one or more 3D models of one or more first objects in accordance with one or more techniques, functions and / or processes described with respect to one of the Fig. 1-7 are described.

[0347] Fig. 23 is a block diagram of a graphics processor 2300, according to at least one embodiment. In at least one embodiment, the graphics processor 2300 includes a ring interconnect 2302, a pipelined front end 2304, a media engine 2337, and graphics cores 2380A-2380N. In at least one embodiment, the ring interconnect 2302 connects the graphics processor 2300 to other processing units, including other graphics processors or one or more general-purpose processing cores. In at least one embodiment, the graphics processor 2300 is one of many processors integrated into a multi-core processing system. In at least one embodiment, the graphics processor 2300 includes the graphics core 1900.

[0348] In at least one embodiment, graphics processor 2300 receives batches of instructions via a ring interconnect 2302. In at least one embodiment, the incoming instructions are interpreted by an instruction streamer 2303 in pipeline front-end 2304. In at least one embodiment, graphics processor 2300 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2380A-2380N. In at least one embodiment, instruction streamer 2303 provides instructions to geometry pipeline 2336 for 3D geometry processing instructions. In at least one embodiment, instruction streamer 2303 provides instructions to a video front-end 2334 coupled to media engine 2337 for at least some media processing instructions.In at least one embodiment, the media engine 2337 includes a video quality engine (VQE) 2330 for video and image post-processing and a multi-format encoder / decoder (MFX) 2333 engine for hardware-accelerated encoding and decoding of media data. In at least one embodiment, the geometry pipeline 2336 and the media pipeline 2337 each generate execution threads for thread execution resources provided by at least one graphics core 2380.

[0349] In at least one embodiment, graphics processor 2300 includes scalable threaded execution resources with graphics cores 2380A-2380N (which may be modular and are sometimes referred to as core slices), each having a plurality of sub-cores 2350A-2350N, 2360A-2360N (sometimes referred to as core slices). In at least one embodiment, graphics processor 2300 may include any number of graphics cores 2380A. In at least one embodiment, graphics processor 2300 includes a graphics core 2380A having at least a first sub-core 2350A and a second sub-core 2360A. In at least one embodiment, graphics processor 2300 is a low-power processor with a single sub-core (e.g., 2350A).In at least one embodiment, the graphics processor 2300 includes a plurality of graphics cores 2380A-2380N, each including a group of first sub-cores 2350A-2350N and a group of second sub-cores 2360A-2360N. In at least one embodiment, each sub-core in the first sub-cores 2350A-2350N includes at least a first group of execution units 2352A-2352N and media / texture units 2354A-2354N. In at least one embodiment, each sub-core in the second sub-cores 2360A-2360N includes at least a second group of execution units 2362A-2362N and samplers 2364A-2364N. In at least one embodiment, each subcore 2350A-2350N, 2360A-2360N shares a set of shared resources 2370A-2370N. In at least one embodiment, the shared resources include a shared cache memory and pixel operation logic.In at least one embodiment, the graphics processor 2300 includes load / store units in the pipeline front end 2304.

[0350] Logic 815 is used to perform inference and / or training operations in connection with one or more embodiments. Details of logic 815 are described herein in connection with Fig. 8A and / or 8B. In at least one embodiment, logic 815 in graphics processor 2300 may be used for inference or prediction operations based at least in part on weighting parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0351] In at least one embodiment, the graphics processor 2300 may be used to operate the system 100 (see Fig. 1), the collage 200 (see Fig. 2), the System 300 (see Fig. 3), process 400 (see Fig. 4) and / or process 500 (see Fig. 5). In at least one embodiment, at least a portion of the Fig. 23 depicted system(s) to implement one or more systems, techniques, functions and / or processes that are used in conjunction with Fig. 1-7. For example, in at least one embodiment, at least one Fig. 23 may be used to cause one or more neural networks to use one or more textual descriptions to generate one or more 3D models of one or more first objects in accordance with one or more techniques, functions and / or processes described with respect to any of the Fig. 1-7 are described.

[0352] Fig. 24 is a block diagram illustrating the microarchitecture of a processor 2400 that may include logic circuitry for executing instructions in accordance with at least one embodiment. In at least one embodiment, the processor 2400 may execute instructions including x86 instructions, ARM instructions, special instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 2400 may include registers for storing packed data, such as 64-bit wide MMX™ registers in microprocessors employing MMX technology from Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, which are available as both integer and floating-point registers, may operate on packed data elements accompanying Single Instruction, Multiple Data (SIMD) and Streaming SIMD Extensions (SSE) instructions.In at least one embodiment, 128-bit XMM registers related to SSE2, SSE3, SSE4, AVX, or beyond technologies (commonly referred to as "SSEx") may contain such packed data operands. In at least one embodiment, the processor 2400 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inferencing.

[0353] In at least one embodiment, processor 2400 includes an in-order front-end ("front-end") 2401 for fetching instructions to be executed and preparing instructions to be used later in a processor pipeline. In at least one embodiment, front-end 2401 may include multiple units. In at least one embodiment, an instruction prefetcher 2426 fetches instructions from memory and passes them to an instruction decoder 2428, which in turn decodes or interprets instructions. In at least one embodiment, instruction decoder 2428, for example, decodes a received instruction into one or more operations, referred to as "micro-instructions" or "micro-operations" (also called "microOps" or "uOps"), that may be executed by a machine.In at least one embodiment, instruction decoder 2428 decomposes an instruction into opcode and corresponding data and control fields that can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, a trace cache 2430 can assemble decoded uOps into program-ordered sequences or traces in a uOps queue 2434 for execution. In at least one embodiment, when trace cache 2430 encounters a complex instruction, a microcode ROM 2432 provides uOps needed to complete an operation.

[0354] In at least one embodiment, some instructions may be converted into a single micro-op, while others may require multiple micro-ops to perform a complete operation. In at least one embodiment, instruction decoder 2428 may access microcode ROM 2432 to execute the instruction if more than four micro-ops are required to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-ops for processing in instruction decoder 2428. In at least one embodiment, an instruction may be stored in microcode ROM 2432 if a number of micro-ops are required to perform such an operation.In at least one embodiment, trace cache 2430 refers to a programmable logic array ("PLA") as an entry point to determine a correct microinstruction pointer for reading microcode sequences to complete one or more instructions from microcode ROM 2432 according to at least one embodiment. In at least one embodiment, after microcode ROM 2432 finishes sequencing microinstructions for an instruction, machine front-end 2401 may resume fetching microinstructions from trace cache 2430.

[0355] In at least one embodiment, the out-of-order execution engine (2403) may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic includes a series of buffers to smooth and reorder the flow of instructions to optimize performance as they traverse a pipeline and are scheduled for execution. In at least one embodiment, the out-of-order execution engine 2403 includes, without limitation, an allocator / register renamer 2440, a memory uOps queue 2442, an integer / floating point uOps queue 2444, a memory scheduler 2446, a fast scheduler 2402, a slow / general FP scheduler 2404, and a simple FP scheduler 2406.In at least one embodiment, the fast scheduler 2402, the slow / general floating-point scheduler 2404, and the simple floating-point scheduler 2406 are also collectively referred to herein as "uOps scheduler 2402, 2404, 2406." In at least one embodiment, the allocator / register renamer 2440 allocates machine buffers and resources required by each uOps for execution. In at least one embodiment, the allocator / register renamer 2440 renames logical registers to entries in a register file. In at least one embodiment, the allocator / register renamer 2440 also assigns each uOps an entry in one of two uOps queues, the memory uOps queue 2442 for memory operations and the integer / floating point uOps queue 2444 for non-memory operations, prior to the memory scheduler 2446 and the uOps schedulers 2402, 2404, 2406.In at least one embodiment, the uOps schedulers 2402, 2404, 2406 determine when a uOp is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resources that the uOps require to perform their operation. In at least one embodiment, the fast scheduler 2402 may schedule every half of a main clock cycle, while the slow / general floating-point scheduler 2404 and the simple floating-point scheduler 2406 may schedule once per main clock cycle of the processor. In at least one embodiment, the schedulers 2402, 2404, 2406 arbitrate for dispatch ports to schedule uOps for execution.

[0356] In at least one embodiment, execution block 2411 includes, without limitation, an integer register file / bypass network 2408, a floating-point register file / bypass network (“FP register file / bypass network”) 2410, address generation units (“AGUs”) 2412 and 2414, fast arithmetic logic units (ALUs) (“fast ALUs”) 2416 and 2418, a slow arithmetic logic unit (“slow ALU”) 2420, a floating-point shift unit (“FP”) 2422, and a floating-point move unit (“FP move”) 2424. In at least one embodiment, integer register file / bypass network 2408 and floating-point register file / bypass network 2410 are also referred to herein as “register files 2408, 2410.” In at least one embodiment, the AGUSs 2412 and 2414, the fast ALUs 2416 and 2418, the slow ALU 2420, the floating-point ALU 2422, and the floating-point shift unit 2424 are also referred to herein as "execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424."In at least one embodiment, execution block 2411 may include, without limitation, any number (including zero) and type of register files, bypass networks, address generation units, and execution units in any combination.

[0357] In at least one embodiment, register networks 2408, 2410 may be arranged between uOps schedulers 2402, 2404, 2406 and execution units 2412, 2414, 2416, 2418, 2420, 2422, and 2424. In at least one embodiment, integer register file / bypass network 2408 performs integer operations. In at least one embodiment, floating-point register file / bypass network 2410 performs floating-point operations. In at least one embodiment, each of register networks 2408, 2410 may include, without limitation, a bypass network that can bypass just-completed results that have not yet been written to a register file or forward them to new dependent uOps. In at least one embodiment, register networks 2408, 2410 may exchange data with each other.In at least one embodiment, the integer register / bypass network 2408 may include, without limitation, two separate register files, one register file for 32 low-order data bits and a second register file for 32 high-order data bits. In at least one embodiment, the floating-point register file / bypass network 2410 may include, without limitation, 128-bit wide entries, since floating-point instructions typically have operands 64 to 128 bits wide.

[0358] In at least one embodiment, execution units 2412, 2414, 2416, 2418, 2420, 2422, 2424 may execute instructions. In at least one embodiment, register networks 2408, 2410 store integer and floating-point data operand values ​​required for microinstruction execution. In at least one embodiment, processor 2400 may include, without limitation, any number and combination of execution units 2412, 2414, 2416, 2418, 2420, 2422, 2424. In at least one embodiment, floating-point ALU 2422 and floating-point shift unit 2424 may perform floating-point, MMX, SIMD, AVX, and SSE operations or other operations, including special machine learning instructions. In at least one embodiment, the floating-point ALU 2422 may include, without limitation, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations.In at least one embodiment, instructions involving a floating-point value may be processed using floating-point hardware. In at least one embodiment, ALU operations may be forwarded to fast ALUs 2416, 2418. In at least one embodiment, fast ALUs 2416, 2418 may perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most comple...

Claims

[1] Processor comprising: one or more circuits for causing one or more neural networks to use one or more textual descriptions to generate one or more three-dimensional (3D) models of one or more first objects based, at least in part, on two or more images of one or more second objects from two or more viewpoints. [2] The processor of claim 1, wherein the one or more neural networks are to generate the one or more 3D models based at least in part on the two or more images after being trained at least in part on the two or more images of the one or more second objects from the two or more viewpoints. [3] The processor of claim 1, wherein the one or more neural networks are trained based at least in part on one or more loss measurements corresponding to a comparison of a 3D model of the one or more second objects from the two or more viewpoints with the two or more images of the one or more second objects. [4] The processor of claim 1, wherein the two or more images of the one or more second objects from the two or more viewpoints are combined into a collage of images used to train the one or more neural networks. [5] The processor of claim 1, wherein the one or more neural networks comprise one or more diffusion models. [6] The processor of claim 1, wherein the two or more images of the one or more second objects are from the two or more viewpoints in a collage of images used to fine-tune a two-dimensional (2D) diffusion model. [7] The processor of claim 1, wherein the one or more circuits further cause the one or more 3D models to be refined based at least in part on the one or more textual descriptions and the two or more images of the one or more second objects. [8] System comprising: one or more processors to cause one or more neural networks to use one or more textual descriptions to generate one or more three-dimensional (3D) models of one or more first objects based, at least in part, on two or more images of one or more second objects from two or more viewpoints. [9] The system of claim 8, wherein the one or more neural networks are to generate the one or more 3D models based at least in part on the two or more images as a result of training based at least in part on one or more loss measures identified by comparing the two or more images of the one or more second objects from the two or more viewpoints and the generated one or more 3D models. [10] The system of claim 8, wherein the one or more neural networks are trained based at least in part on a loss measure of how well a 3D model of the one or more second objects from the two or more viewpoints matches the two or more images of the one or more second objects. [11] The system of claim 8, wherein the two or more images of the two or more second objects are from the two or more viewpoints in a collage of images used to train the one or more neural networks. [12] The system of claim 8, wherein the one or more neural networks comprise one or more diffusion models. [13] The system of claim 8, wherein the one or more processors randomly sample one or more camera viewpoints with fixed relative angular offsets to generate images based on a three-dimensional (3D) computer-aided design (CAD) model to create an image collage for training the one or more neural networks. [14] The system of claim 8, wherein the two or more viewpoints are captured by one or more cameras positioned at locations that are evenly spaced from each other. [15] Method comprising: Using one or more neural networks to use one or more textual descriptions to generate one or more three-dimensional (3D) models of one or more first objects based, at least in part, on two or more images of one or more second objects from two or more viewpoints. [16] The method of claim 15, further comprising generating the one or more 3D models based at least in part on the two or more images after being trained at least in part on the two or more images of the one or more second objects from the two or more viewpoints. [17] The method of claim 15, wherein the one or more neural networks are trained based at least in part on a loss measure of how well a 3D model of the one or more second objects from the two or more viewpoints matches the two or more images of the one or more second objects. [18] The method of claim 15, wherein the two or more images of the two or more second objects are from the two or more viewpoints in a collage of images used to train the one or more neural networks. [19] The method of claim 15, wherein the one or more neural networks comprise a text-to-image diffusion model. [20] The method of claim 15, wherein the two or more viewpoints are captured by four or more cameras that are evenly spaced from each other.

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