STORAGE DEVICE AND METHOD FOR FORMING THE SAME

Abstract

A device comprises a cross-lock, a first, a second, a third, and a fourth transistor, and a first read bit line. The first transistor has a first gate extending in a first direction and located on a first layer. The second transistor includes a second gate on a second layer below the first layer. The third transistor is coupled to the first memory node and includes a third gate on the first layer. The fourth transistor is coupled to a first memory node and includes a fourth gate on the second layer. The first read bit line extends in a second direction, lies on a first metal layer above a front face of a substrate, and is coupled to the third and fourth transistors. The third and fourth transistors correspond to a first port of the device.

Description

PRIORITY CLAIM

[0001] This application claims the benefits of the preliminary U.S. application No. 63 / 701,274, which was filed on September 30, 2024, and is incorporated herein by reference in its entirety. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has developed various digital devices to solve problems in different fields. Some of these digital devices, such as memory macros, are designed for data storage. As ICs have become smaller and more complex, the resistance of the traces within these digital devices has also changed, affecting their operating voltages and overall performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this revelation are best understood through the following detailed description, when read in conjunction with the accompanying figures. It should be noted that various elements are not drawn to scale, as is common practice in the industry. In fact, the dimensions of the various elements may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 is a block diagram of an integrated memory circuit according to some embodiments. Fig. 2A to 2B are corresponding circuit diagrams of corresponding memory cells, which are located in Fig. 1 can be used, according to some embodiments. Fig. 3A to 3F are corresponding diagrams of corresponding sections of a layout design of a corresponding integrated circuit according to some embodiments. Fig. Figures 4A to 4L are diagrams of an integrated circuit according to some embodiments. Fig. Figures 5A to 5E are diagrams of an integrated circuit according to some embodiments. Fig. Figure 6A is a diagram of a section of a floor plan of an integrated circuit according to some embodiments. Fig. Figure 6B is a diagram of a section of a floor plan of the integrated circuit according to some embodiments. Fig. 7 is a time diagram of the waveforms of the storage circuit in Fig. 2A according to some embodiments. Fig. Figure 8 is a functional flowchart of a method for manufacturing an integrated circuit according to some embodiments. Fig. Figure 9 is a flowchart of a method for manufacturing an integrated circuit according to some embodiments. Fig. Figure 10 is a flowchart of a method for generating a layout design for an integrated circuit according to some embodiments. Fig. Figure 11 is a schematic view of a system for designing an IC layout design and for manufacturing an IC circuit according to some embodiments. Fig. Figure 12 is a block diagram of an IC manufacturing system and an associated IC manufacturing process according to at least one embodiment of this disclosure. Fig. Figures 13A to 13B are a flowchart of an operating procedure of a circuit according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides various embodiments or examples for implementing elements of the provided element. Specific examples of devices, materials, values, steps, arrangements, or the like are discussed below to simplify this disclosure. These are, of course, only examples and are not limiting. Other components, materials, values, steps, arrangements, or the like are considered. For example, forming a first element or a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and it may also include embodiments in which further elements may be formed between the first and second elements, so that the first and second elements need not be in direct contact.Furthermore, this disclosure may repeat reference numbers and / or letters from the various examples. This repetition serves the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or devices discussed.

[0005] Furthermore, spatially relative terms such as "below," "underneath," "lower," "above," "upper," and the like may be used herein for a simpler description of the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to encompass various orientations of the device during use or operation. The device may be oriented differently (rotated by 90 degrees or in another orientation), and the spatially relative terms used herein may be interpreted accordingly.

[0006] In some embodiments, a multiport memory cell includes a cross-locking mechanism.

[0007] In some embodiments, the cross-locking mechanism comprises a first storage node and a second storage node.

[0008] In some embodiments, the multiport memory cell further comprises a first transistor of a first type. In some embodiments, the first transistor comprises a first gate extending in a first direction. In some embodiments, the first gate is located on a first plane.

[0009] In some embodiments, the multiport memory cell further comprises a second transistor of a second type, which differs from the first type. In some embodiments, the second transistor comprises a second gate. In some embodiments, the second gate is located on a second level below the first level.

[0010] In some embodiments, the multiport memory cell further includes a third transistor of the first type.

[0011] In some embodiments, the third transistor is coupled to the first memory node. In some embodiments, the third transistor includes a third gate at the first level.

[0012] In some embodiments, the multiport memory cell further includes a fourth transistor of the second type.

[0013] In some embodiments, the fourth transistor is coupled to the first memory node. In some embodiments, the fourth transistor includes a fourth gate at the second level.

[0014] In some embodiments, the multiport memory cell also includes a first read bit line.

[0015] In some embodiments, the first read bit line extends in a second direction that differs from the first. In some embodiments, the first read bit line is located on a first metal layer above a front face of a substrate. In some embodiments, the first read bit line is coupled to the third and fourth transistors.

[0016] In some embodiments, the third transistor and the fourth transistor correspond to at least one first port of the multiport memory cell.

[0017] In some embodiments, the multiport memory cell further comprises a first gate isolation layer between the first gate and the second gate. In some embodiments, the first gate isolation layer electrically isolates the first gate and the second gate from each other.

[0018] In some embodiments, the memory cell can be used as a multiport memory cell with the first port and the second port by electrically isolating the first gate and the second gate from each other, thus occupying less space than other approaches.

[0019] Fig. Figure 1 is a block diagram of a memory circuit 100 according to some embodiments.

[0020] Fig. Figure 1 is simplified for illustrative purposes. In some embodiments, the memory circuit includes 100 in addition to those shown in Fig. The elements shown in 1 are further elements or are otherwise arranged so that the processes discussed below can be carried out.

[0021] The memory circuit 100 is an IC that includes memory partitions 102A to 102D, a global control circuit 100GC and global input-output (GIO) circuits 100BL.

[0022] Each memory partition 102A to 102D comprises memory banks 110U and 110L, which are adjacent to a word line driver circuit (WL driver circuit) 110AC and a local control circuit 110LC. Each memory bank 110U and 110L comprises a memory cell array 110AR and a local input / output circuit (LIO circuit) 110BS.

[0023] A storage partition, e.g., a storage partition 102A to 102D, is a section of the storage circuit 100 that contains a subset of storage devices (in Fig. 1 not shown) and includes adjacent circuits configured to selectively access the subset of memory devices during program and read operations. In Fig. In embodiment 1, the memory circuit 100 comprises a total of four partitions. In some embodiments, the memory circuit 100 comprises a total number of partitions that is greater or less than four.

[0024] The GIO circuit 100BL is configured to control access to one or more electrical paths, e.g., bit lines, to each memory device of the corresponding memory bank 110U or 110L of each memory partition 102A to 102D, e.g., by generating one or more bit line signals. In some embodiments, the GIO circuit 100BL includes a global bit line driver circuit. In some embodiments, the GIO circuit 100BL is coupled to each memory bank 110U and 110L via a corresponding global bit line (not shown).

[0025] The global control circuit 100GC is configured to control some or all program and read operations on each memory partition 102A to 102D, e.g. by generating and / or outputting one or more control and / or enable signals.

[0026] In some embodiments, the global control circuit 100GC comprises one or more analog circuits configured to interface with the memory partitions 102A to 102D, initiate the programming of data in one or more memory devices, and / or use data received from one or more memory devices in one or more circuit operations. In some embodiments, the global control circuit 100GC comprises one or more global address decoder or pre-decoder circuits configured to output one or more address signals to the WL driver circuit 110AC of each memory partition 102A to 102D.

[0027] Each WL driver circuit 110AC is configured to generate word line signals on the corresponding word lines WL. In some embodiments, each WL driver circuit 110AC is configured to output word line signals on corresponding word lines WL to the adjacent memory banks 110U and 110L of the corresponding memory partition 102A to 102D.

[0028] Each local control circuit 110LC is an electronic circuit configured to receive one or more address signals. Each local control circuit 110LC is configured to generate signals corresponding to adjacent subsets of memory devices identified by the one or more address signals. In some embodiments, the adjacent subsets of memory devices correspond to columns of memory devices. In some embodiments, each local control circuit 110LC is configured to generate each signal as a complementary pair of signals. In some embodiments, each local control circuit 110LC is configured to output the signals to corresponding word line driver circuits within the adjacent WL driver circuit 110AC of the corresponding memory partition 102A to 102D.In some embodiments, the local control circuit 110LC includes a bank decoder circuit.

[0029] Each LIO 110BS circuit is configured to selectively access one or more bit lines (shown in Fig. 2) which are coupled to adjacent subsets of memory devices of the corresponding memory cell array 110AR and respond to the GIO circuit 100BL, e.g., based on one or more BL control signals. In some embodiments, the adjacent subsets of memory devices correspond to rows of memory devices. In some embodiments, the LIO circuit 110BS includes a bit line selection circuit.

[0030] Each LIO circuit 110BS comprises one or more circuits 114. For clarity, the circuit 114 in memory banks 110U and 110L of memory partitions 102B, 102C, and 102D is not shown. In some embodiments, each circuit 114 comprises at least one read amplifier circuit. In some embodiments, the read amplifier circuit is configured during a read operation to read data from at least one memory cell 112 in a corresponding column of memory cells in the corresponding memory cell array 110AR. In some embodiments, each circuit 114 in the LIO circuit 110BS is coupled to a corresponding column of memory devices 112 in the memory cell array 110AR.

[0031] Each memory bank 110U and 110L comprises the corresponding memory cell array 110AR with memory cells or memory devices 112, which are arranged so that they can be accessed during programming and reading operations by the adjacent LIO circuit 110BS and the adjacent WL driver circuit 110AC.

[0032] Each memory cell array 110AR comprises an array of memory devices 112 with N rows and M columns, where M and N are positive integers. The rows of the cells in the memory cell array 110AR are arranged in a first direction X. The columns of the cells in the memory cell array 110AR are arranged in a second direction Y. The second direction Y differs from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X. In some embodiments, each memory cell array 110AR is subdivided into an upper region and a lower region (not shown). In some embodiments, each column of the memory devices 112 in the memory cell array 110AR is coupled to a corresponding circuit 114 in the LIO circuit 110BS.

[0033] The storage device 112 is shown in memory banks 110U and 110L of storage partition 102A. For clarity, the storage device 112 is not shown in memory banks 110U and 110L of storage partitions 102B, 102C, and 102D.

[0034] The storage device 112 is an electrical, electromechanical, electromagnetic, or other device configured to store bit data represented by logical states. At least one logical state of the storage device 112 can be programmed during a write operation and detected during a read operation. In some embodiments, a logical state corresponds to a voltage level of an electrical charge stored in a particular storage device 112. In some embodiments, a logical state corresponds to a physical property, such as a voltage, current, resistance, or magnetic orientation, of a component of a particular storage device 112.

[0035] In some embodiments, the storage device 112 comprises one or more static random-access memory cells (SRAM cells) with multiple ports. In some embodiments, the storage device 112 comprises one or more dual-port SRAM cells (DP SRAM cells). In some embodiments, the storage device 112 comprises one or more single-port SRAM cells (SPP SRAM cells). In some embodiments, the storage device 112 comprises one or more SRAM cells with complementary FET transistors (CFET transistors). Various types of memory cells in the storage device 112 are conceivable within the scope of this disclosure. In some embodiments, the storage device 112 comprises one or more dynamic random-access memory cells (DRAM).In some embodiments, the storage device 112 comprises one or more one-time programmable memory devices (OTP storage devices), such as electronic fuse devices (eFuse devices) or anti-fuse devices, flash memory devices, random access memory (RAM), resistive RAM devices, ferroelectric RAM devices, magnetoresistive RAM devices, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) devices, or the like. In some embodiments, the storage device 112 is an OTP storage device with one or more OTP memory cells.

[0036] Other features of the storage circuit 100 fall within the scope of this disclosure.

[0037] Fig. 2A to 2B are corresponding circuit diagrams for the respective memory cells 200A and 200B, which are in Fig. 1 are usable, according to some embodiments.

[0038] Fig. 2A is a circuit diagram of a 200A memory cell, which is in Fig. 1 is usable according to some embodiments.

[0039] At least one of the memory cells 200A or 200B is configured as one or more memory cells MCB in at least one of the memory cell arrays 110AR. Fig. 1 or the storage device 112 from Fig. 1 usable.

[0040] At least one of the memory cells 200A or 200B is a ten-transistor multiport SRAM memory cell (10T-MP-SRAM memory cell) with a CMOS read port. In some embodiments, at least one of the memory cells 200A or 200B has a different number of transistors than ten. Other memory types are possible within various embodiments. In some embodiments, a multiport memory cell is a type of RAM configured to support multiple read or write operations occurring simultaneously at different addresses within a memory cell array (e.g., memory cell array 110AR in [reference]). Fig. 1) In some embodiments, a multiport memory cell is configured to support corresponding multiple accesses to the memory cell (e.g., reading or writing) per clock cycle.

[0041] The 200A memory cell comprises P-type field-effect transistors (PFETs) PU1, PU2, RPD2, and RPG2, as well as NFET transistors PD1, PD2, WPG1, WPG2, RPD1, and RPG1. The PFET transistors PU1 and PU2 and the NFET transistors PD1 and PD2 form a cross-latching or pair of cross-coupled inverters. For example, the PFET transistor PU1 and the NFET transistor PD1 form a first inverter, while the PFET transistor PU2 and the NFET transistor PD2 form a second inverter.

[0042] One source terminal of each of the PFET transistors PU1 and PU2 is configured as a power supply node NODE_1. Each power supply node NODE_1 is coupled to a first power supply VDD.

[0043] Each of the following is coupled together: a drain terminal of the PFET transistor PU1, a drain terminal of the NFET transistor PD1, a gate terminal of the PFET transistor PU2, a gate terminal of the NFET transistor PD2, a source terminal of the NFET transistor WPG1, a gate terminal of the PFET transistor RPD2 and a gate terminal of the NFET transistor RPD1 are connected and configured as a storage node NDB.

[0044] Each drain terminal of the PFET transistor PU2, drain terminal of the NFET transistor PD2, gate terminal of the PFET transistor PU1, gate terminal of the NFET transistor PD1 and source terminal of the NFET transistor WPG2 are coupled together and configured as a storage node ND.

[0045] One source terminal of each of the NFET transistors PD1 and PD2 is configured as a supply reference voltage node (unlabeled) with a supply reference voltage VSS. The source terminal of each NFET transistor PD1 and PD2 is also coupled to the reference voltage supply VSS.

[0046] A write word line (WWL) is coupled to a gate terminal of each of the NFET transistors WPG1 and WPG2. The write word line (WWL) is also referred to as the write control line because the NFET transistors WPG1 and WPG2 are configured to be controlled by a signal on the write word line (WWL) to transfer data between the write bit line strip (WBLB) and the corresponding node (ND).

[0047] In some embodiments, the signal of the write word line WWL is equal to a supply voltage VDD. In some embodiments, the NFET transistors WPG1 and WPG2 are switched on when the signal of the write word line WWL is equal to the supply voltage VDD.

[0048] One drain terminal of the NFET transistor WPG1 is coupled to a write bit line WBLB. One drain terminal of the NFET transistor WPG2 is coupled to a write bit line WBL.

[0049] The write bit line strip WBLB and the write bit line WBL are configured as data inputs for memory cell 200A.

[0050] One source terminal of the PFET transistor RPG2 is coupled to the first supply voltage VDD.

[0051] A gate terminal of the PFET transistor RPG2 is coupled to a read word line strip RWLB. In some embodiments, the gate terminal of the PFET transistor RPG2 is configured to receive a read word line strip signal from the read word line strip RWLB. A drain terminal of the PFET transistor RPG2 and a source terminal of the PFET transistor RPD2 are coupled together.

[0052] One drain terminal of the PFET transistor RPD2 and one drain terminal of the NFET transistor RPD1 are coupled together and are further coupled to a read bit line RBL. In some embodiments, the drain terminal of the PFET transistor RPD2 and the drain terminal of the NFET transistor RPD1 are configured to generate the read bit line signal RBL. In other embodiments, the drain terminal of the PFET transistor RPD2 and the drain terminal of the NFET transistor RPD1 are configured to output the read bit line signal RBL to the read bit line RBL.

[0053] The gate terminal of the NFET transistor RPD1 and the gate terminal of the PFET transistor RPD2 are each coupled to the storage node NDB. In some embodiments, both the gate terminal of the NFET transistor RPD1 and the gate terminal of the PFET transistor RPD2 are configured to receive the data stored in the node NDB or ND.

[0054] A gate terminal of the NFET transistor RPG1 is coupled to a read word line RWL. In some embodiments, the gate terminal of the NFET transistor RPG1 is configured to receive a read word line signal from the read word line RWL. A drain terminal of the NFET transistor RPG1 and a source terminal of the NFET transistor RPD1 are coupled together.

[0055] One source terminal of the NFET transistor RPG1 is coupled to the reference supply voltage VSS.

[0056] In some embodiments, the NFET transistor RPD1, the NFET transistor RPG1, the PFET transistor RPD2 and the PFET transistor RPG2 are configured to read the data stored in memory cell 200A at node ND or NDB.

[0057] The read bit line RBL is configured to output the data stored in memory cell 200A.

[0058] In some embodiments, in a single read operation, applying a logical value to the read word line bar RWLB and the opposite logical value to the read word line RWL enables the reading of the logical values ​​stored at the nodes ND or NDB from memory cell 200A to 200B via the read bit line RBL.

[0059] In some embodiments, during a write operation, by applying a logical value to the write bit line WBLB and the opposite logical value to the write bit line WBL, the writing of the logical values ​​on the write bit lines into the memory cells 200A to 200B is made possible.

[0060] Other features of memory cell 200A fall within the scope of this disclosure.

[0061] Fig. 2B is a circuit diagram of a 200B memory cell, which is in Fig. 1 can be used, according to some embodiments.

[0062] The 200B memory cell is a variant of the 200A memory cell. Fig. 2A, which is why a similarly detailed description is omitted. Compared to the 200A memory cell from Fig. 2A, replaces one line of words WL in Fig. 2B the corresponding spelling word lines WWL in Fig. 2A, a bit line BL in Fig. 2B replaces the corresponding write bit line WBL in Fig. 2A, and a bit line strip BLB in Fig. 2B replaces the corresponding write bit strip WBLB in Fig. 2A, which is why a similarly detailed description is omitted.

[0063] Other features of memory cell 200B fall within the scope of this disclosure.

[0064] Fig. 3A to 3F are corresponding diagrams of the corresponding sections 300A to 300F of a layout design 300 of a corresponding integrated circuit according to some embodiments.

[0065] The layout design 300 is a layout of an integrated circuit 400. Fig. 4A to 4L or 200A memory cell. The 300 layout design is a layout of the 200A memory cell made of Fig. 2A.

[0066] Section 300A includes one or more elements of the layout design 300 of an active layer or oxide diffusion layer (OD layer), a gate layer (POLY or PO layer), a cut-gate or cut-POLY layer (CPOLY layer or CPO layer), a metal-over-diffusion layer (MD layer), a metal-over-diffusion local interconnect layer (MDLI layer), a via-gate layer (VG layer), and a via-diffusion layer (VD layer).

[0067] Section 300B includes one or more elements of the Layout Design 300 of the OD layer, the POLY layer, the CPO layer, a backside metal-over-diffusion layer (BMD layer), the MDLI layer, a via-to-MD busbar layer (VDR layer), a backside via-gate layer (BVG layer), and a backside via-diffusion layer (BVD layer).

[0068] Section 300C comprises one or more elements of the layout design 300 of the metal-o-level (Mo-level).

[0069] Section 300D comprises one or more elements of the layout design 300 of a back-side metal-o-plane (BMo-plane).

[0070] Section 300E includes one or more elements of the layout design 300 of the OD level, the POLY level, the CPO level, the MD level, the MDLI level, the VG level, the VD level and the Mo level.

[0071] Section 300F includes one or more elements of the Layout Design 300 of the OD level, the POLY level, the CPO level, the BMD level, the MDLI level, the VDR level, the BVG level, the BVD level and the BMo level.

[0072] Fig. 3A to 3F are corresponding diagrams of the corresponding sections 300A to 300F of layout design 300, which have been simplified for better illustration.

[0073] For better illustration, some of the labeled elements of one or more of the Fig. 1 to 6B in one or more of the Fig. 1 to 6B are not marked. In some embodiments, the layout design includes 300 additional elements, which are located in the Fig. 3A to 3F are not shown. Layout design 300 includes one or more elements of the OD level, the POLY level, the CPO level, the MD level, the MDLI level, the VG level, the VD level, the Mo level, the BMD level, the VDR level, the BVG level, the BVD level, and the BMo level.

[0074] In some embodiments, the layout design comprises at least 300 or the integrated circuit 400 or 500 additional elements, which are located in the Fig. 3A to 3F, 4A to 4L or 5A to 5E are not shown.

[0075] The layout design 300 can be used to manufacture the integrated circuit 400. Fig. 4A to 4L can be used.

[0076] Section 300A is a layout of section 400A of the integrated circuit 400. Fig. 4A, Section 300B is a layout of Section 400B of the integrated circuit 400 from Fig. Section 300C of section 4B is a layout of section 400C of the integrated circuit 400. Fig. 4C, Section 300D is a layout of Section 400D of the integrated circuit 400 from Fig. Section 300E of section 4D is a layout of section 400E of the integrated circuit 400. Fig. Section 300F of section 4E is a layout of section 400F of the integrated circuit 400. Fig. 4F, and a similarly detailed description is omitted for the sake of brevity.

[0077] Layout design 300 comprises a cell 301. Cell 301 has cell boundaries 301a and 301b extending in a first direction X, and cell boundaries 301c and 301d extending in a second direction Y. In some embodiments, at least one of the first direction X, the second direction Y, or a third direction Z differs from another of the first direction X, the second direction Y, or the third direction Z. In some embodiments, layout design 300 abuts other cell layout designs (not shown) along cell boundaries 301c and 301d. In some embodiments, layout design 300 abuts other cell layout designs (not shown) along cell boundaries 301a and 301b extending in the first direction X. In some embodiments, layout design 300 is a standard single-height cell.In some embodiments, cell 301 can be used to manufacture cell 401.

[0078] In some embodiments, cell 301 is a standard cell, and the layout design 300 corresponds to a standard cell layout defined by cell boundaries 301a, 301b, 301c, and 301d. In some embodiments, a cell 301 is a predefined section of the layout design 300 with one or more transistors and electrical connections configured to perform one or more circuit functions. In some embodiments, cell 301 is bounded by cell boundaries 301a, 301b, 301c, and 301d, and thus corresponds to a region of functional circuit components or devices that are a section of a standard cell. In some embodiments, the layout design 300 is a memory cell layout design, such as memory cell 200A from [reference missing]. Fig. 2A or Fig. 200B out Fig. 2B.

[0079] The layout design 300 comprises one or more active region layout structures 302a, 302b or 302c (collectively referred to as the "set of active region layout structures 302") or one or more active region layout structures 304a, 304b or 304c (collectively referred to as the "set of active region layout structures 304") that extend in the second direction Y.

[0080] In embodiments of this disclosure, the term “layout structure” is used for brevity, which is also referred to as “structure” in this disclosure below.

[0081] The set Active Region Structures 302 is above the set Active Region Structures 304.

[0082] Active region structures 302a, 302b, and 302c of the set Active Region Structures 302 are separated from each other in the first direction X. Active region structures 304a, 304b, and 304c of the set Active Region Structures 304 are separated from each other in the first direction X.

[0083] Active region structures 302a and 304a are separated from each other in a third direction Z. Active region structures 302b and 304b are separated from each other in a third direction Z. Active region structures 302c and 304c are separated from each other in a third direction Z.

[0084] The set of active region structures 302 can be used to create a corresponding set of active regions 402 for the integrated circuits 100, 200A, 200B, 400, or 500. The set of active region structures 304 can be used to create a corresponding set of active regions 404 for the integrated circuits 100, 200A, 200B, 400, or 500.

[0085] In some embodiments, at least one of the active regions 402 or 404 is located on the front face 403a of the integrated circuit 100, 200A, 200B, 400, or 500. In some embodiments, at least one of the active regions 402 or 404 corresponds to the source and drain regions of one or more complementary solid-state transistors (CFETs). In some embodiments, at least one of the active regions 402 or 404 corresponds to the source and drain regions of one or more nanosheet transistors or nanowire transistors. Other transistor types are within the scope of this disclosure. In some embodiments, at least one of the active regions 402 or 404 corresponds to the source and drain regions of one or more finFET transistors.

[0086] In some embodiments, the active region structures 302a, 302b, 302c can be used to fabricate the corresponding active regions 402a, 402b, 402c of the set of active regions 402 of the integrated circuit 100, 200A, 200B, 400 or 500. In some embodiments, the active region structures 304a, 304b, 304c can be used to fabricate the corresponding active regions 404a, 404b, 404c of the set of active regions 404 of the integrated circuit 100, 200A, 200B, 400 or 500.

[0087] In some embodiments, the set of active region structures 302 and 304 is referred to as the oxide diffusion region (OD region), which defines the source or drain diffusion regions of at least the integrated circuit 100, 200A, 200B, 400 or 500 or the layout design 300.

[0088] In some embodiments, the active region structures 302a, 302b and 302c can be used to fabricate source and drain regions of NFET transistors of the integrated circuits 100, 200A, 200B, 400 or 500, and the active region structures 304a, 304b and 304c can be used to fabricate source and drain regions of PFET transistors of the integrated circuits 100, 200A, 200B, 400 or 500.

[0089] In some embodiments, the active region structures 302a, 302b and 302c can be used to fabricate source and drain regions of PFET transistors of the integrated circuits 100, 200A, 200B, 400 or 500, and the active region structures 304a, 304b and 304c can be used to fabricate source and drain regions of NFET transistors of the integrated circuits 100, 200A, 200B, 400 or 500.

[0090] In some embodiments, the set of active region structures 302 or 304 is placed in a first layout layer. In some embodiments, the first layout layer corresponds to an active layer or an OD layer of one or more layout designs 300 or integrated circuits 100, 200A, 200B, 400, or 500. In some embodiments, the OD layer is located at least above the BMo layer.

[0091] Other facilities, arrangements on other layout levels, or sets of structures in the set Active Region Structures 302 or 304 fall within the scope of this disclosure.

[0092] The layout design 300 further comprises one or more gate structures 306a or 306b (collectively referred to as the “set of gate structures 306”), one or more gate structures 308a or 308b (collectively referred to as the “set of gate structures 308”), extending in the first direction X.

[0093] The set Gate Structures 306 lies above the set Gate Structures 308.

[0094] In some embodiments, the gate structures 306a and 308a are separated from each other in the third direction Z. In some embodiments, the gate structures 306b and 308b are separated from each other in the third direction Z.

[0095] The set of gate structures 306 can be used to manufacture a corresponding set of gates 406 for the integrated circuits 100, 200A, 200B, 400 or 500. The set of gate structures 308 can be used to manufacture a corresponding set of gates 408 for the integrated circuits 100, 200A, 200B, 400 or 500.

[0096] In some embodiments, gate structures 306a or 306b can be used to fabricate the corresponding gate 406a or 406b of the set of gates 406 of the integrated circuit 100, 200A, 200B, 400 or 500. In some embodiments, gate structures 308a or 308b can be used to fabricate the corresponding gate 408a or 408b from the set of gates 408 of the integrated circuit 100, 200A, 200B, 400 or 500.

[0097] In some embodiments, at least one of the sets of gates 406 or 408 is placed on the front side 403a of the integrated circuit 100, 200A, 200B, 400 or 500.

[0098] In some embodiments, each of the gate structures in the set of gate structures 306 and 308 is in Fig. 3A to 3F with the designations "PD1, PU1, PD2, PU2, WPG1, WPG2, RPD1, RPD2, RPG1, RPG2, X1, X2", which are the corresponding transistors of the Fig. 2A to 2B, identify, through the corresponding gate structures in Fig. 3A to 3F were manufactured, and are omitted for the sake of brevity.

[0099] In some embodiments, at least one of the labels X1 or X2 is a corresponding dummy transistor on the back side of the layout design 300. In some embodiments, at least one of the labels X1 or X2 is the corresponding dummy transistor in the integrated circuit 600B. Fig. 6B is shown. In some embodiments, a dummy transistor is a non-functional transistor. In some embodiments, a dummy transistor is a transistor in which the source and / or drain is replaced by appropriate insulating regions, such as the insulating regions 480a in Fig. 4I.

[0100] In some embodiments, the set of gate structures 306 or 308 encapsulates the set of active region structures 302 and 304. In some embodiments, at least one section of the set of gate structures 306 or 308 lies above the set of active region structures 302 and 304. In some embodiments, at least one further section of the set of gate structures 306 or 308 lies below the set of active region structures 302 and 304.

[0101] The set of gate structures 306 or 308 is arranged on a second layout level. In some embodiments, the second layout level differs from the first layout level. In some embodiments, the second layout level corresponds to the POLY level (also referred to as the PO level or MG level) of one or more layout designs 300 or integrated circuits 100, 200A, 200B, 400, or 500. In some embodiments, the POLY level is located above the BMD and BMo levels.

[0102] Other facilities, arrangements on other layout levels, or sets of structures in the set of gate structures 306 or 308 fall within the scope of this disclosure.

[0103] The layout design 300 further comprises one or more section element structures 340a, 340b, 340c or 340d (collectively referred to as the “set of section element structures 340”) that extend in the second direction Y.

[0104] The set of section element structures 340 is above the set of section element structures 306 or 308.

[0105] At least one section element structure 340a, 340b, 340c or 340d is separated from another of the section element structures 340a, 340b, 340c or 340d in at least one of the first direction X or the second direction Y.

[0106] In some embodiments, the set of cutting element structures 340 overlaps at least one section of a gate structure from the set of gate structures 306 or 308. In some embodiments, the set of cutting element structures 340 overlaps with other underlying structures (not shown) of other layout levels (e.g., BMo, BMD, Active, MD, or the like) of the layout design 300.

[0107] In some embodiments, the cutting element structures 340a, 340b, 340c or 340d identify the corresponding locations of the corresponding removed gate sections 440a, 440b, 440c or 440d of the set of removed gate sections 440 that are removed in process 904 of process 900 ( Fig. 9).

[0108] In some embodiments, the cutting element structure 340b can be used to separate gate 406a3 and gate 406a2 from each other. In some embodiments, the cutting element structure 340b can be used to separate gate 408a3 and gate 408a2 from each other.

[0109] In some embodiments, the cutting element structure 340b can be used to separate gate 406b2 and gate 406b1 from each other. In some embodiments, the cutting element structure 340b can be used to separate gate 408b2 and gate 408b1 from each other.

[0110] In some embodiments, the cutting element structure 340c can be used to separate gate 406a2 and gate 406a1 from each other. In some embodiments, the cutting element structure 340c can be used to separate gate 408a2 and gate 408a1 from each other.

[0111] Other arrangements, configurations on other layout levels, or sets of structures in the set of section element structures 340 are not covered by this disclosure. In some embodiments, at least one section element structure from the set of section element structures 340 is not included in the layout design 300.

[0112] The set of section element structures 340 is placed on the second layout level.

[0113] Other facilities, arrangements on other layout levels, or sets of structures in the set Section Element Structures 340 fall within the scope of this disclosure.

[0114] The layout design 300 further comprises one or more isolation region structures 394a (collectively referred to as the “set of isolation region structures 394”) extending in the second direction Y.

[0115] In some embodiments, the set of insulating region structures 394 is located between the set of gate structures 306 and the set of gate structures 308. In some embodiments, the set of insulating region structures 394 is located above the set of gate structures 308. In some embodiments, the set of insulating region structures 394 is located below the set of gate structures 306.

[0116] In some embodiments, the gate structure 306a and the gate structure 308a are separated from each other in the third direction Z by the insulating region structure 394a of the set of insulating region structures 394. In some embodiments, a section 306a1 of the gate structure 306a and a section 308a1 of the gate structure 308a are separated from each other in the third direction Z by the insulating region structure 394a of the set of insulating region structures 394.

[0117] The set of isolation region structures 394 can be used to manufacture a corresponding set of isolation regions 494 for the integrated circuit 100, 200A, 200B, 400 or 500. The set of isolation region structures 394 can also be used to manufacture a corresponding set of isolation region structures 494a for the integrated circuit 100, 200A, 200B, 400 or 500.

[0118] Other facilities, arrangements at other levels of arrangement, or a different number of sections in the isolation region structure 394 fall within the scope of this disclosure.

[0119] The layout design 300 further comprises one or more contact structures 310a, 310b, 310c, 310d, 310e, 310f (collectively referred to as the “set of contact structures 310”) extending in the first direction X.

[0120] Each of the contact structures of the set Contact structures 310 is separated from a neighboring contact structure of the set Contact structures 310 in at least the first direction X or the second direction Y.

[0121] The set of contact structures 310 can be used to manufacture a corresponding set of contacts 410 for the integrated circuit 100, 200A, 200B, 400 or 500.

[0122] In some embodiments, the contact structure 310a, 310b, 310c, 310d, 310e, 310f of the set of contact structures 310 can be used to produce the corresponding contact 410a, 410b, 410c, 410d, 410e, 410f of the set of contact structures 410. In some embodiments, the set of contact structures 310 is also referred to as the set of metal-over-diffusion structures (MD structures).

[0123] In some embodiments, at least one of the contact structures 310a, 310b, 310c, 310d, 310e, 310f from the set of contact structures 310 can be used to create source or drain connections of the NFET of the integrated circuit 100, 200A, 200B, 400 or 500.

[0124] In some embodiments, at least one of the contact structures 310a, 310b, 310c, 310d, 310e, 310f from the set of contact structures 310 can be used to produce source or drain connections of the PFET transistors of the integrated circuit 100, 200A, 200B, 400 or 500.

[0125] In some embodiments, the contact structure 310a can be used to create source / drain connections of the NFET transistor PD1, the contact structure 310b can be used to create source / drain connections of the NFET transistor WPG1, the contact structure 310c can be used to create source / drain connections of the NFET transistor WPG2, the contact structure 310d can be used to create source / drain connections of the NFET transistor PD2, the contact structure 310e can be used to create source / drain connections of the NFET transistor RPG1, and the contact structure 310f can be used to create drain / source connections of the NFET transistor RPG1 and source / drain connections of the NFET transistor RPD1.

[0126] In some embodiments, the set of contact structures 310 overlaps the set of active region structures 302 or 304. The set of contact structures 310 is placed on a third layout level. In some embodiments, the third layout level corresponds to the contact level or an MD level of one or more layout designs 300 or integrated circuits 100, 200A, 200B, 400, or 500. In some embodiments, the third layout level differs from at least one of the first and second layout levels. Other arrangements, configurations on other layout levels, or numbers of structures in the set of contact structures 310 are possible within the scope of this disclosure.

[0127] The layout design 300 further comprises one or more contact structures 312a, 312b, 312c, 312d, 312e, 312f (collectively referred to as the “set of contact structures 312”) extending in the first direction X.

[0128] Each of the contact structures of the set Contact Structures 312 is separated from a neighboring contact structure of the set Contact Structures 312 in at least the first direction X or the second direction Y.

[0129] The set of contact structures 310 and 312 are separated from each other in the third direction Z. In some embodiments, contact structures 310a and 312a are separated from each other in the third direction Z. In some embodiments, contact structures 310b and 312b are separated from each other in the third direction Z. In some embodiments, contact structures 310c and 312c are separated from each other in the third direction Z. In some embodiments, contact structures 310d and 312d are separated from each other in the third direction Z. In some embodiments, contact structures 310e and 312e are separated from each other in the third direction Z. In some embodiments, contact structures 310f and 312f are separated from each other in the third direction Z.

[0130] The set of contact structures 312 can be used to manufacture a corresponding set of contacts 412 for the integrated circuit 100, 200A, 200B, 400 or 500.

[0131] In some embodiments, the contact structure 312a, 312b, 312c, 312d, 312e, 312f of the set of contact structures 312 can be used to create the corresponding contact 412a, 412b, 412c, 412d, 412e, 412f of the set of contacts 412. In some embodiments, the set of contacts 412 is located on the back side 403b of the integrated circuit 400. In some embodiments, the back side 403b of the integrated circuit 400 is opposite the front side of the integrated circuit 400. In some embodiments, the set of contact structures 312 is also referred to as the set of back-side MD structures (BMD).

[0132] In some embodiments, the contact structure 312a can be used to create source / drain connections of the PFET transistor PU1, the contact structure 312b can be used to create source / drain connections of the PFET transistor X1, the contact structure 312c can be used to create source / drain connections of the PFET transistor X2, the contact structure 312d can be used to create source / drain connections of the PFET transistor PU2, the contact structure 312e can be used to create source / drain connections of the PFET transistor RPG2, and the contact structure 312f can be used to create drain / source connections of the PFET transistor RPG2 and source / drain connections of the PFET transistor RPD2.

[0133] In some embodiments, at least one of the PFET transistors X1 or X2 is a corresponding dummy transistor.

[0134] In some embodiments, the set of contact structures 312 is overlapped by the set of active region structures 302 or 304. The set of contact structures 312 is located in a fourth layout level. In some embodiments, the fourth layout level corresponds to the backside contact level or a backside MD level (BMD) of one or more layout designs 300 or integrated circuits 100, 200A, 200B, 400, or 500. In some embodiments, the fourth layout level differs from at least one of the first, second, or third layout levels.

[0135] In some embodiments, the BMD layer is located above the BMo layer. In some embodiments, the BMD layer is located below the back side 403b of the integrated circuit 400. In some embodiments, the BMD layer is located below the OD layer, the POLY layer, the MD layer, and the Mo layer.

[0136] Other facilities, arrangements on other layout levels, or sets of structures in the set Contact Structures 312 fall within the scope of this disclosure.

[0137] The layout design 300 further comprises one or more contact structures 314a, 314b, 314c (collectively referred to as the “set of contact structures 314”) extending in the second direction Y.

[0138] Each of the contact structures of the set Contact Structures 314 is separated from a neighboring contact structure of the set Contact Structures 314 in at least the first direction X or the second direction Y.

[0139] In some embodiments, the set of contact structures 314 is located between the set of contact structures 310 and 312. Contact structure 314a is located between contact structures 310a and 310b. Contact structure 314a is located between contact structures 312a and 312b. Contact structure 314b is located between contact structures 310c and 31od. Contact structure 314b is located between contact structures 312c and 312d.

[0140] The contact structure 314c lies between the contact structures 312d and 312f.

[0141] The contact structure 314c lies between the contact structures 310d and 310f.

[0142] In some embodiments, the contact structure 314a comprises one or more separate interrupted structures. In some embodiments, the contact structure 314b comprises one or more separate interrupted structures. In some embodiments, the contact structure 314c comprises one or more separate interrupted structures.

[0143] The contact structures 314a and 314b are separated from each other in the first direction X.

[0144] The contact structure 314c is separated from at least one of the contact structures 314a or 314b in the first direction X or the second direction Y.

[0145] The set of contact structures 314 can be used to manufacture a corresponding set of contacts 414 for the integrated circuit 100, 200A, 200B, 400 or 500.

[0146] In some embodiments, the contact structure 314a, 314b, 314c from the set of contact structures 314 can be used to create the corresponding contact 414a, 414b, 414c from the set of contacts 414. In some embodiments, the set of contacts 414 is located on the front face 403a of the integrated circuit 400. In some embodiments, the set of contact structures 314 is also referred to as a set of local interconnect structures (MDLI structures).

[0147] In some embodiments, at least one of the contact structures 314a, 314b, 314c of the set of contact structures 314 can be used to create interconnect structures that can be used to connect source or drain terminals of one of the NFET or PFET transistors of the integrated circuit 100, 200A, 200B, 400 or 500.

[0148] In some embodiments, the contact structure 314a can be used to create drain / source terminals of the NFET transistor PD1, drain / source terminals of the NFET WPG1, drain / source terminals of the PFET transistor PU1 and drain / source terminals of the PFET X1.

[0149] In some embodiments, the contact structure 314a corresponds to the node NDB from Fig. 2A to 2B, and a similarly detailed description is omitted for the sake of brevity.

[0150] In some embodiments, the contact structure 314b can be used to create drain / source terminals of the NFET transistor WPG2, drain / source terminals of the NFET transistor PD2, drain / source terminals of the PFET transistor X2 and drain / source terminals of the PFET transistor PU2.

[0151] In some embodiments, the contact structure 314b corresponds to node ND from Fig. 2A to 2B, and a similarly detailed description is omitted for the sake of brevity.

[0152] In some embodiments, the contact structure 314c can be used to create drain / source connections of the NFET transistor RPD1 and drain / source connections of the PFET transistor RPD2.

[0153] In some embodiments, at least one first section of the set of contact structures 314 is overlapped by one or more of the set of active region structures 302 or 304. In some embodiments, at least one second section of the set of contact structures 314 lies between the set of active region structures 302 or 304. In some embodiments, at least one third section of the set of contact structures 314 is coplanar with the set of contact structures 310 or the set of contact structures 312.

[0154] The set of contact structures 314 is located on a fifth layout level. In some embodiments, the fifth layout level corresponds to the MDLI level of one or more layout designs 300 or of the integrated circuits 100, 200A, 200B, 400, or 500. In some embodiments, the fifth layout level differs from at least one of the first and second layout levels.

[0155] In some embodiments, the MDLI plane comprises the MD plane and the BMD plane. In some embodiments, the MDLI plane lies below the Mo plane. In some embodiments, the MDLI plane lies above the BMo plane.

[0156] Other facilities, arrangements on other layout levels, or sets of structures in the set Contact Structures 314 fall within the scope of this disclosure.

[0157] The layout design 300 further comprises one or more conductive element structures 316a and 316b (collectively referred to as the “set of conductive element structures 316”) extending in the first direction X and the second direction Y.

[0158] Each of the conductive element structures of the set of conductive element structures 316 is separated from a neighboring conductive element structure of the set of conductive element structures 316 in at least the first direction X or the second direction Y.

[0159] The conductive structures 316a and 316b are separated from each other at least in the first direction X or in the second direction Y.

[0160] The set of conductive structures 316 can be used to manufacture a corresponding set of conductors 416 for the integrated circuit 100, 200A, 200B, 400 or 500.

[0161] In some embodiments, the conductive element structures 316a, 316b of the set of conductive element structures 316 can be used to fabricate the corresponding conductors 416a, 416b of the set of conductors 416. The conductors 416 are located on the back side 403b of the integrated circuit 400. The conductor 416a or 416b is located on the back side 403b of the integrated circuit 400. In some embodiments, the set of conductive element structures 316 is also referred to as a set of conductive VDR element structures. In some embodiments, the set of conductors 416 is also referred to as a set of VDR conductors.

[0162] In some embodiments, at least one of the conductive element structures 316a, 316b of the set of conductive element structures 316 can be used to create interconnect structures that can be used to connect at least one gate terminal of one of the NFET or PFET transistors of the integrated circuit 100, 200A, 200B, 400 or 500 to one or more source or drain terminals of another of the NFET or PFET transistors of the integrated circuit 100, 200A, 200B, 400 or 500.

[0163] In some embodiments, the set of conductive element structures 316 is overlapped by one or more from the set of active region structures 302, the set of active region structures 304, the set of gate structures 306, the set of gate structures 308 or the set of contact structures 314.

[0164] In some embodiments, the conductive element structure 316a is overlapped by at least one of the following structures: gate structure 306b, gate structure 308b, or contact structure 314a. In some embodiments, the conductive element structure 316b is overlapped by at least one of the structures 306a, 308a, or 314b.

[0165] The set of conductive element structures 316 is placed on a sixth layout level. In some embodiments, the sixth layout level corresponds to the VDR level of one or more layout designs 300 or 600, or of the integrated circuits 100, 200A, 200B, 400, or 500. In some embodiments, the sixth layout level differs from at least one of the first, second, third, fourth, or fifth layout levels. In some embodiments, the VDR level lies between the BMo level and the OD level, the POLY level, the BMD level, or the MDLI level, and / or one of these.

[0166] Other facilities, arrangements on other layout levels, or sets of structures in the set of conductive structures 316 fall within the scope of this disclosure.

[0167] The layout design 300 further comprises one or more conductive element structures 330a, 330b, 330c, 330d, 330e, 330f (collectively referred to as the “set of conductive element structures 330”) extending in the second direction Y.

[0168] Each of the conductive element structures in the set of conductive element structures 330 is separated from another conductive element structure in the set of conductive element structures 330 in the first direction X.

[0169] The set of conductive element structures 330 overlaps at least one from the set of active region structures 302 or 304, the set of gate structures 306 or 308, the set of contact structures 310, 312 or 314 or the set of conductive element structures 316.

[0170] The set of conductive structures 330 can be used to fabricate a corresponding set of conductors 430 of the integrated circuit 100, 200A, 200B, 400, or 500. The conductive element structures 330a, 330b, 330c, 330d, 330e, and 330f can be used to fabricate the corresponding conductors 430a, 430b, 430c, 430d, 430e, and 430f of the integrated circuit 100, 200A, 200B, 400, or 500. In some embodiments, at least one conductor of the set of conductors 430 is placed on the front face 403a of the integrated circuit 100, 200A, 200B, 400, or 500.

[0171] In some embodiments, the set of conductive element structures 330 is placed on a seventh layout level. In some embodiments, the seventh layout level differs from at least one of the first, second, third, fourth, fifth, or sixth layout levels. In some embodiments, the seventh layout level corresponds to the Mo level of one or more layout designs 300 or integrated circuits 100, 200A, 200B, 400, or 500. In some embodiments, the Mo level is located above the OD level, the POLY level, the MD level, the BMD level, the MDLI level, the VDR level, and the BMo level.

[0172] In some embodiments, the set of conductive element structures corresponds to 330 6 Mo conductors. Other numbers of Mo guide tracks are possible within the scope of this disclosure.

[0173] Other facilities, arrangements on other layout levels, or sets of structures in the set of conductive structures 330 fall within the scope of this disclosure.

[0174] The layout design 300 further comprises one or more conductive element structures 332a, 332b, 332c, 332d, 332e (collectively referred to as the “set of conductive element structures 332”) extending in the first direction X.

[0175] Each conductive element structure in the set of conductive element structures 332 is separated from another conductive element structure in the set of conductive element structures 332 in the second direction Y.

[0176] The set of conductive element structures 332 is overlapped by at least one of the sets of active region structures 302 or 304, the set of gate structures 306 or 308, the set of contact structures 310, 312 or 314 or the set of conductive element structures 316.

[0177] The set of conductive element structures 330 and 332 is separated from each other in the third direction Z. In some embodiments, the conductive element structure 330a is separated from at least one of the conductive element structures 332a or 332b in the third direction Z. In some embodiments, structures 330c and 332c are separated from each other in the third direction Z. In some embodiments, structures 330d and 332d are separated from each other in the third direction Z. In some embodiments, structures 330f and 332e are separated from each other in the third direction Z.

[0178] The set of conductive structures 332 can be used to fabricate a corresponding set of conductors 432 of the integrated circuit 100, 200A, 200B, 400, or 500. The conductive element structures 332a, 332b, 332c, 332d, and 332e can be used to fabricate the corresponding conductors 432a, 432b, 432c, 432d, and 432e of the integrated circuit 100, 200A, 200B, 400, or 500. In some embodiments, at least one conductor of the set of conductors 432 is placed on the back side 403b of the integrated circuit 100, 200A, 200B, 400, or 500.

[0179] In some embodiments, the set of conductive element structures 332 is placed on an eighth layout level. In some embodiments, the eighth layout level differs from at least one of the first, second, third, fourth, fifth, sixth, or seventh layout levels. In some embodiments, the eighth layout level corresponds to the BMo level of one or more layout designs 300 or integrated circuits 100, 200A, 200B, 400, or 500. In some embodiments, the BM0 level is located below the OD level, the POLY level, the MD level, the BMD level, the MDLI level, the VDR level, and the BM0 level.

[0180] In some embodiments, the set of conductive element structures corresponds to 332 4 BMo guide tracks. Other numbers of BMo guide tracks are possible within the scope of this disclosure.

[0181] Other facilities, arrangements on other layout levels, or sets of structures in the set of conductive structures 332 fall within the scope of this disclosure.

[0182] The layout design 300 further includes one or more via structures 320a, 320b, 320c, 320d, 320e, 320f (collectively referred to as the “set of via structures 320”).

[0183] The set of via structures 320 can be used to fabricate a corresponding set of vias 420 of the integrated circuit 100, 200A, 200B, 400 or 500. In some embodiments, the via structures 320a, 320b, 320c, 320d, 320e, 320f of the set of via structures 320 can be used to fabricate corresponding vias 420a, 420b, 420c, 420d, 420e, 420f of the set of vias 420 of the integrated circuit 100, 200A, 200B, 400 or 500.

[0184] In some embodiments, the set of via structures 320 is located between the set of contact structures 310 and the set of conductive element structures 330.

[0185] The through-hole structure 320a lies between the contact structure 310a and the conductive element structure 330a.

[0186] The through-hole structure 320b lies between the contact structure 310b and the conductive element structure 330b.

[0187] The through-hole structure 320c lies between the contact structure 310c and the conductive element structure 330c.

[0188] The through-hole structure 320d lies between the contact structure 310d and the conductive element structure 330d.

[0189] The through-hole plating structure 320e lies between the contact structure 310e and the conductive element structure 330d.

[0190] The through-hole structure 320f lies between the contact structure 314c and the conductive element structure 330e.

[0191] The set of via structures 320 is placed on a via-diffusion (VD) layer of one or more layout designs 300 or integrated circuits 100, 200A, 200B, 400, or 500. In some embodiments, the VD layer is located above the OD layer, the POLY layer, the MD layer, the BMD layer, the MDLI layer, the VDR layer, and the BMo layer. In some embodiments, the VD layer is located below the Mo layer. In some embodiments, the VD layer is located between the MD layer and the Mo layer. In some embodiments, the VD layer is located between the third and seventh layout layers. Other layout layers are possible within the scope of this disclosure.

[0192] Other arrangements, configurations on other layout levels, or sets of structures in at least one set of via structures 320 are within the scope of this disclosure.

[0193] The layout design 300 further includes one or more via structures 322a, 322b, 322c (collectively referred to as the “set of via structures 322”).

[0194] The set of via structures 322 can be used to fabricate a corresponding set of vias 422 of the integrated circuit 100, 200A, 200B, 400 or 500. In some embodiments, the via structures 322a, 322b, 322c of the set of via structures 322 can be used to fabricate the corresponding vias 422a, 422b, 422c of the set of vias 422 of the integrated circuit 100, 200A, 200B, 400 or 500.

[0195] In some embodiments, the set of via structures 322 is located between the set of contact structures 312 and the set of conductive element structures 332.

[0196] The through-hole structure 322a lies between the contact structure 312a and the conductive element structure 332b.

[0197] The through-hole structure 322b lies between the contact structure 312d and the conductive element structure 332d.

[0198] The through-hole structure 322c lies between the contact structure 312e and the conductive element structure 332d.

[0199] The set of via structures 322 is placed on a backside via layer (BVD layer) of one or more layout designs 300 or integrated circuits 100, 200A, 200B, 400, or 500. In some embodiments, the BVD layer is located below the OD layer, the POLY layer, the MD layer, the BMD layer, and the Mo layer. In some embodiments, the BVD layer is located above the BMo layer. In some embodiments, the BVD layer is located between the BMD layer and the BMo layer. In some embodiments, the BVD layer is located between the fourth and eighth layout layers. Other layout layers are possible within the scope of this disclosure.

[0200] Other arrangements, configurations on other layout levels, or sets of structures in at least one set of via structures 322 fall within the scope of this disclosure.

[0201] The layout design 300 further includes one or more via structures 324a (collectively referred to as the “set of via structures 324”).

[0202] The set of via structures 324 can be used to fabricate a corresponding set of vias 424 of the integrated circuit 100, 200A, 200B, 400 or 500. In some embodiments, the via structures 324a of the set of via structures 324 can be used to fabricate corresponding vias 424a of the set of vias 424 of the integrated circuit 100, 200A, 200B, 400 or 500.

[0203] In some embodiments, the set of via structures 324 is located between the set of gate structures 306 and the set of conductive element structures 330. The via structure 324a is located between the gate structure 306a and the conductive element structure 330f.

[0204] The set of via structures 324 is placed on a via-over-gate (VG) layer of one or more layout designs 300 or integrated circuits 100, 200A, 200B, 400, or 500. In some embodiments, the VG layer is located above the OD layer, the POLY layer, the MD layer, the MDLI layer, the VDR layer, the BMD layer, and the BMo layer. In some embodiments, the VG layer is located below the Mo layer. In some embodiments, the VG layer is located between the POLY layer and the Mo layer. In some embodiments, the VG layer is located between the second and seventh layout layers. Other layout layers are possible within the scope of this disclosure.

[0205] Other arrangements, configurations on other layout levels or sets of structures in at least one set of via structures 324 fall within the scope of this disclosure.

[0206] The layout design 300 further includes one or more via structures 326a, 326b, 326c (collectively referred to as the “set of via structures 326”).

[0207] The set of via structures 326 can be used to fabricate a corresponding set of vias 426 of the integrated circuit 100, 200A, 200B, 400 or 500. In some embodiments, the via structures 326a, 326b, 326c of the set of via structures 326 can be used to fabricate the corresponding vias 426a, 426b, 426c of the set of vias 426 of the integrated circuit 100, 200A, 200B, 400 or 500.

[0208] In some embodiments, the set of via structures 326 is located between the set of gate structures 308 and the set of conductive element structures 332.

[0209] The via structure 326a lies between the gate structure 308b and the conductive element structure 332a.

[0210] The via structure 326b lies between the gate structure 308a and the conductive element structure 332c.

[0211] The via structure 326c lies between the gate structure 308a and the conductive element structure 332e.

[0212] The set of via structures 326 is placed on a backside via-gate layer (BVG layer) of one or more layout designs 300 or integrated circuits 100, 200A, 200B, 400, or 500. In some embodiments, the BVG layer is located below the OD layer, the POLY layer, the MD layer, the MDLI layer, the VDR layer, the BMD layer, and the Mo layer. In some embodiments, the BVG layer is located above the BMo layer. In some embodiments, the BVG layer is located between the POLY layer and the BMo layer. In some embodiments, the BVG layer is located between the second and eighth layout layers. Other layout layers are possible within the scope of this disclosure.

[0213] Other arrangements, configurations on other layout levels or sets of structures in at least one set of via structures 326 fall within the scope of this disclosure.

[0214] In some embodiments, by including the set of isolating region structures 394 in the layout design 300, the gate structures 306a and 308a are separated from each other by the isolating region structures 394a. This allows the NFET transistor RPG1 and the PFET transistor RPG2 to be used as separate transistors, configured to operate independently in a CMOS configuration of at least one read port of a multiport memory cell produced by the layout design 300, resulting in a multiport memory cell layout design that occupies less area than other approaches.

[0215] In some embodiments, the NFET transistor RPG1 and the PFET transistor RPG2 are configured to be used as separate transistors and are configured to operate independently of each other in a CMOS configuration of at least one read port of a multiport memory cell produced by the layout design 300, resulting in a multiport memory cell layout design that has improved speed compared to other approaches.

[0216] Other facilities, arrangements on other layout levels, or sets of structures in Layout Design 300 fall within the scope of this disclosure.

[0217] Fig. Figures 4A to 4L are diagrams of an integrated circuit 400 according to some embodiments.

[0218] Fig. 4A to 4F are corresponding diagrams of the corresponding sections 400A to 400F of an integrated circuit 400, which have been simplified for better illustration.

[0219] Section 400A comprises one or more elements of the 400 integrated circuit at the OD level, the POLY level, the CPO level, the MD level, the MDLI level, the VG level, and the VD level. Section 400A is manufactured from Section 300A.

[0220] Section 400B comprises one or more elements of the 400 integrated circuit at the OD level, POLY level, CPO level, BMD level, MDLI level, VDR level, BVG level, and BVD level. Section 400B is manufactured from Section 300B.

[0221] Section 400C comprises one or more elements of the Mo-level integrated circuit 400. Section 400C is manufactured from Section 300C.

[0222] Section 400D comprises one or more elements of the BMo 400 integrated circuit. Section 400D is manufactured from section 300D.

[0223] Section 400E comprises one or more elements of the 400 integrated circuit at the OD level, POLY level, CPO level, MD level, MDLI level, VG level, VD level, and Mo level. Section 400E is manufactured from Section 300E.

[0224] Section 400F comprises one or more elements of the 400 integrated circuit at the OD level, POLY level, CPO level, BMD level, MDLI level, VDR level, BVG level, BVD level, and BMo level. Section 400F is manufactured from Section 300F.

[0225] Fig. Figures 4G to 4L are corresponding cross-sectional views of the integrated circuit 400 according to some embodiments. Fig. 4G is a cross-sectional view of the integrated circuit 400, cut through the plane A to A', according to some embodiments. Fig. 4H is a cross-sectional view of the integrated circuit 400, cut through the plane BB', according to some embodiments. Fig. 4I is a cross-sectional view of the integrated circuit 400, cut through the plane CC', according to some embodiments. Fig. 4J is a cross-sectional view of the integrated circuit 400, cut through the plane DD', according to some embodiments. Fig. 4K is a cross-sectional view of the integrated circuit 400, cut by the plane EE', according to some embodiments. Fig. 4L is a cross-sectional view of the integrated circuit 400, cut through the plane FF', according to some embodiments.

[0226] Components that are the same or similar to those in one or more of the Fig. 1, 2A to 2B, 3A to 3F, 4A to 4L, 5A to 5E and 6A to 6B are given the same reference numbers, so a detailed description is unnecessary.

[0227] The integrated circuit 400 is manufactured using the layout design 300. The integrated circuit 400 is cell 401. The structural relationships, including orientation, lengths and widths, as well as the features and layers of the integrated circuits 400 and 600, are derived from the structural relationships and features and layers of the layout design 300. Fig. 3A to 3F are similar, and a similarly detailed description is provided at least in the Fig. 4A to 4L are not discussed for brevity. In some embodiments, for example, at least one or more widths, lengths, or spacings of the layout design 300 are similar to the corresponding widths, lengths, or spacings of the integrated circuits 400 and 500, and a corresponding detailed description is omitted for brevity. In some embodiments, for example, at least the cell boundary 301a or 301b is similar to at least the corresponding cell boundary 401a or 401b of the integrated circuit 400, and a similarly detailed description is omitted for brevity.

[0228] The integrated circuit 400 comprises at least the set of active regions 402 and 404, the set of gates 406 and 408, the set of remote gate sections 440, the set of contacts 410, the set of contacts 412, the set of contacts 414, the set of conductors 416, the set of conductors 430, the set of conductors 432, the set of vias 420, the set of vias 422, the set of vias 424, the set of vias 426, a substrate 490, an insulating region 492 and a set of insulating regions 494.

[0229] The set of active regions 402 includes at least one or more active regions 402a, 402b, 402c.

[0230] The set of active regions 404 includes at least one or more active regions 404a, 404b, 404C.

[0231] The set of active regions 402 and 404 is embedded in a substrate 490. The substrate 490 has a front face 403a and a back face 403b, which is opposite the front face 403a. In some embodiments, at least the active regions 402 and 404, the gates 406 and 408, or the contacts 410, 412, or 414 are formed on the front face 403a of the substrate 490.

[0232] In some embodiments, at least the set of conductors 416, the set of vias 422 or the set of vias 426 are formed on the front side 403a of the substrate 490.

[0233] In some embodiments, the set of active regions 402 and 404 corresponds to the active regions of CFET transistors. In some embodiments, the set of active regions 402 comprises drain regions and source regions built up by an epitaxial growth process. In some embodiments, the set of active regions 402 comprises drain regions and source regions built up from an epitaxial material at the corresponding drain and source regions. In some embodiments, the active regions 402 and 404 correspond to the (unlabeled) nanosheet structures of nanosheet transistors.

[0234] Other transistor types fall within the scope of this disclosure. In some embodiments, for example, the set of active regions 402 corresponds to the nanowire structures (not shown) of nanowire transistors. In some embodiments, the set of active regions 402 corresponds to the planar structures (not shown) of planar transistors. In some embodiments, the set of active regions 402 corresponds to the fin structures (not shown) of finFETs.

[0235] In some embodiments, the active regions 402a, 402b and 402c correspond to the source and drain regions of NFET transistors of the integrated circuit 100, 200A, 200B, 400 or 500, and the active regions 404a, 404b and 404c correspond to the source and drain regions of PFET transistors of the integrated circuit 100, 200A, 200B, 400 or 500.

[0236] In some embodiments, the active regions 402a, 402b and 402c correspond to the source and drain regions of PFET transistors of the integrated circuit 100, 200A, 200B, 400 or 500, and the active regions 404a, 404b and 404c correspond to the source and drain regions of NFET transistors of the integrated circuit 100, 200A, 200B, 400 or 500.

[0237] In some embodiments, at least the active region 402a, 402b or 402c is an N-doped S / D region, and at least the active region 404a, 404b or 404c is a P-doped S / D region embedded in a dielectric of the substrate 490.

[0238] In some embodiments, the active region 404a comprises at least one of the active regions 404a1, 404a2 or 404a3.

[0239] In some embodiments, the active region 404a3 is the source / drain of the PFET transistor PU1.

[0240] In some embodiments, the active region 404a2 is the drain / source of the PFET transistor PU1.

[0241] In some embodiments, the active region 404a1 is the drain / source of the PFET transistor X1. In some embodiments, the active region 404a1 includes an insulating region 480a. In some embodiments, the active region 404a1 is a dummy active region that has been removed and replaced with the insulating region 480a.

[0242] In some embodiments, the active region 404b comprises at least one of the active regions 404b1, 404b2 or 404b3.

[0243] In some embodiments, the active region 404b3 is the source / drain of the PFET transistor PU2.

[0244] In some embodiments, the active region 404b2 is the drain / source of the PFET transistor PU2.

[0245] In some embodiments, the active region 404b1 is the drain / source of the PFET transistor X2. In some embodiments, the active region 404b1 includes an insulating region 480b. In some embodiments, the active region 404b1 is a dummy active region that has been removed and replaced with the insulating region 480b.

[0246] In some embodiments, at least one of the insulating regions 480a or 480b is a dielectric. In some embodiments, the dielectric comprises silicon dioxide, silicon oxide nitride, silicon nitride, or the like.

[0247] Other facilities, arrangements on other layout levels, or sets of structures in the set of active regions 402 or 404 fall within the scope of this disclosure.

[0248] Isolation Region 492 is set up to contain one or more elements of the

[0249] The set of active regions 402 and 404, the set of gates 406 and 408, the set of contacts 410, the set of contacts 412, the set of contacts 414, the set of conductors 416, the set of conductors 430, the set of conductors 432, the set of vias 420, the set of vias 422, the set of vias 424, or the set of vias 426 are electrically isolated from one another. In some embodiments, the insulating region 492 comprises several insulating regions, which are described in method 800 ( Fig. 8) are deposited at different times. In some embodiments, the insulating region 492 is a dielectric. In some embodiments, the dielectric comprises silicon dioxide, silicon oxide nitride, silicon nitride, or the like.

[0250] Other facilities, arrangements on other layout levels, or a different number of sections in isolation region 492 fall within the scope of this disclosure.

[0251] The Gates 406 set includes one or more Gates 406a or 406b.

[0252] The Gates 408 set includes one or more Gates 408a or 408b.

[0253] The set of gates 406 and 408 corresponds to one or more gates of transistors PD1, PU1, PD2, PU2, WPG1, WPG2, RPD1, RPD2, RPG1, RPG2, X1, X2 of integrated circuits 100, 200A, 200B, 400 or 500. In some embodiments, each of the gates in the group of gates 406 and 408 is in Fig. 4A to 4F with the designations “PD1, PU1, PD2, PU2, WPG1, WPG2, RPD1, RPD2, RPG1, RPG2, X1, X2” are shown, which are the corresponding transistors of the Fig. 2A to 2B with corresponding gates in Fig. 4A to 4L and 5, which are omitted for brevity.

[0254] Gate 406a includes one or more gates 406a1, 406a2 or 406a3.

[0255] Gate 406b comprises one or more gates 406b1 or 406b2.

[0256] Gate 408a comprises one or more gates 408a1, 408a2 or 408a3.

[0257] Gate 408b comprises one or more gates 408b1 or 408b2.

[0258] In some embodiments, gate 406a1 is a gate of the NFET transistor RPG1, gate 406a2 is a gate of the NFET transistor WPG2, gate 406a3 is a gate of the NFET transistor PD1, gate 406b1 is a gate of the NFET transistor RPD1 and a gate of the NFET transistor PD2, and gate 406b2 is a gate of the NFET transistor WPG1.

[0259] In some embodiments, gate 408a1 is a gate of PFET transistor RPG2, gate 408a2 is a gate of PFET transistor X2, gate 408a3 is a gate of PFET transistor PU1, gate 408b1 is a gate of PFET transistor RPD2 and a gate of PFET transistor PU2, and gate 408b2 is a gate of PFET transistor X1.

[0260] In some embodiments, the gate 406a1 and the gate 406a2 are separated from each other in the first direction X by the remote gate section 440c.

[0261] In some embodiments, the gate 406a2 and the gate 406a3 are separated from each other in the first direction X by the remote gate section 440b.

[0262] In some embodiments, the gate 406b1 and the gate 406b2 are separated from each other in the first direction X by the remote gate section 440b.

[0263] In some embodiments, the gate 408a1 and the gate 408a2 are separated from each other in the first direction X by the remote gate section 440c.

[0264] In some embodiments, the gate 408a2 and the gate 408a3 are separated from each other in the first direction X by the remote gate section 440b.

[0265] In some embodiments, the gate 408b1 and the gate 408b2 are separated from each other in the first direction X by the remote gate section 440b.

[0266] In some embodiments, at least one of gates 406a1, 406a2, or 406a3 has the same continuous structure. In some embodiments, at least one of gates 408a1, 408a2, or 408a3 has the same continuous structure. In some embodiments, at least one of gates 406b1 or 406b2 has the same continuous structure. In some embodiments, at least one of gates 408b1 or 408b2 has the same continuous structure.

[0267] In some embodiments, gate 406a1 and gate 408a1 are separated from each other in the third direction Z. In some embodiments, gate 406a1 and gate 408a1 are separated from each other in the third direction Z by an insulating region 494a of the set of insulating regions 494.

[0268] In some embodiments, gate 406a2 and gate 408a2 are coupled together. In some embodiments, gate 406a2 and gate 408a2 are part of the same continuous structure.

[0269] In some embodiments, gate 406a3 and gate 408a3 are coupled together. In some embodiments, gate 406a3 and gate 408a3 are part of the same continuous structure.

[0270] In some embodiments, gate 406b1 and gate 408b1 are coupled together. In some embodiments, gate 406b1 and gate 408b1 are part of the same continuous structure.

[0271] In some embodiments, gate 406b2 and gate 408b2 are coupled together. In some embodiments, gate 406b2 and gate 408b2 are part of the same continuous structure.

[0272] In some embodiments, the set of Gates 406 or 408 encapsulates the set of active regions 402 or 404.

[0273] Other facilities, arrangements on other layout levels, or sets of gates in the set of gates 406 and 408 fall within the scope of this disclosure.

[0274] The set of remote gate sections 440 comprises one or more remote gate sections 440a, 440b, 440c or 440d.

[0275] In some embodiments, one or more remote gate sections 440a, 440b, 440c or 440d comprise a corresponding insulating region (not labelled) similar to the set of insulating regions 494, and a similarly detailed description is therefore omitted.

[0276] In some embodiments, the remote gate section 440a separates the gate 406a3 and the gate 408a3 from a gate in an adjacent cell along the cell boundary 401c.

[0277] In some embodiments, the remote gate section 440d separates the gate 406b1 and the gate 408b1 from a gate in an adjacent cell along the cell boundary 401d.

[0278] In some embodiments, the one or more remote gate sections 440a, 440b, 440c or 440d are arranged such that the gates adjacent to the corresponding one or more remote gate sections 440a, 440b, 440c or 440d are electrically isolated.

[0279] Other facilities, arrangements on other layout levels, or sets of remote gate sections in the set of remote gate sections 440 fall within the scope of this disclosure.

[0280] The group of insulating regions 494 comprises at least one insulating region 494a. In some embodiments, the set of insulating regions 494 is also referred to as the set of gate insulating layers. In some embodiments, at least one of the insulating regions 494a is referred to as the gate insulating layer.

[0281] The set of insulating regions 494 is arranged to electrically isolate one or more gates of the set of gates 406 or 408 from another gate of the set of gates 406 or 408.

[0282] In some embodiments, the insulating region 494a is arranged to electrically isolate the gate 406a1 and the gate 408a1 from each other.

[0283] In some embodiments, the set of insulating regions 494a comprises a single insulating region which is deposited at a single time point in the process 800 ( Fig. 8) In some embodiments, the isolation region 494a comprises several isolation regions which are deposited at different times in the process 800 ( Fig. 8) In some embodiments, the insulating region 494 is a dielectric. In some embodiments, the dielectric comprises silicon dioxide, silicon oxide nitride, silicon nitride, or the like.

[0284] Other facilities, arrangements at other levels of arrangement, or a different number of sections in the set of isolation regions 494 fall within the scope of this disclosure.

[0285] The group of contacts 410 includes one or more contacts 410a, 410b, 410c, 410d, 410e or 410f.

[0286] The group of contacts 412 includes one or more contacts 412a, 412b, 412c, 412d, 412e or 412f.

[0287] Each contact of the set of contacts 410 or 412 corresponds to one or more drain or source terminals of the transistors PD1, PU1, PD2, PU2, WPG1, WPG2, RPD1, RPD2, RPG1, RPG2, X1, X2 of the integrated circuits 100, 200A, 200B, 400 or 500.

[0288] In some embodiments, one or more contacts of the set of contacts 410 overlap a pair of active regions of the set of active regions 402, thereby electrically coupling the pair of active regions of the set of active regions 402 and the source or drain of the corresponding transistors.

[0289] In some embodiments, one or more contacts of the set of contacts 412 overlap a pair of active regions of the set of active regions 404, thereby electrically coupling the pair of active regions of the set of active regions 404 and the source or drain of the corresponding transistors.

[0290] In some embodiments, the set of contacts 410 or 412 encapsulates the set of active regions 402 or 404.

[0291] In some embodiments, contact 410a is a source / drain terminal of the NFET transistor PD1.

[0292] In some embodiments, contact 410b is a source / drain terminal of the NFET transistor WPG1.

[0293] In some embodiments, contact 410c is a source / drain terminal of the NFET transistor WPG2.

[0294] In some embodiments, contact 410d is a source / drain terminal of the NFET transistor PD2.

[0295] In some embodiments, contact 410e is a source / drain terminal of the NFET transistor RPG1.

[0296] In some embodiments, contact 410f is a drain / source terminal of the NFET transistor RPG1 and a source / drain terminal of the NFET transistor RPD1.

[0297] In some embodiments, contact 412a is a source / drain terminal of the PFET transistor PU1.

[0298] In some embodiments, contact 412b is a source / drain terminal of the PFET transistor X1.

[0299] In some embodiments, contact 412c is a source / drain terminal of the PFET transistor X2.

[0300] In some embodiments, contact 412d is a source / drain terminal of the PFET transistor PU2.

[0301] In some embodiments, contact 412e is a source / drain terminal of the PFET transistor RPG2.

[0302] In some embodiments, contact 412f is a drain / source terminal of the PFET transistor RPG2 and a source / drain terminal of the PFET transistor RPD2.

[0303] The set of contacts 414 includes one or more contacts 414a, 414b or 414c.

[0304] In some embodiments, contact 414a is a drain / source terminal of the NFET transistor PD1, a drain / source terminal of the NFET WPG1, a drain / source terminal of the PFET transistor PU1, and a drain / source terminal of the PFET X1.

[0305] In some embodiments, contact 414a corresponds to node NDB from Fig. 2A to 2B, and a similarly detailed description is omitted for the sake of brevity.

[0306] In some embodiments, contact 414b is a drain / source terminal of the NFET transistor WPG2, a drain / source terminal of the NFET transistor PD2, a drain / source terminal of the PFET transistor X2, and a drain / source terminal of the PFET PU2.

[0307] In some embodiments, contact 414b corresponds to node ND from Fig. 2A to 2B, and a similarly detailed description is omitted for the sake of brevity.

[0308] In some embodiments, contact 414c is a drain / source terminal of the NFET transistor RPD1 and a drain / source terminal of the PFET transistor RPD2.

[0309] Other facilities, arrangements at other levels of arrangement, or sets of contacts in contact sets 410, 412, and 414 fall within the scope of this disclosure.

[0310] The set of conductors 416 comprises one or more conductors 416a or 416b.

[0311] In some embodiments, the conductor 416a is in direct contact with at least one of gate 408b1 or contact 414a.

[0312] In some embodiments, the conductor 416a couples the gate 408b1 to the contact 414a, thereby electrically coupling the gate terminals of transistors PU2 and RPD2 to the drain terminals of transistors PD1 and PU1 and transistors WPG1.

[0313] In some embodiments, conductor 416b is in direct contact with at least one of gate 408a3 or contact 414b. In some embodiments, conductor 416b couples gate 408a3 to contact 414b, thereby electrically coupling the gate terminals of transistors PD1 and PU1 to the drain terminals of transistors WPG2 and transistors PD2 and PU2.

[0314] In some embodiments, each of the conductors 416a or 416b comprises a corresponding via (on the same plane as the set of contacts 412) and a corresponding conductor embedded in the substrate 490.

[0315] Other facilities, arrangements on other layout levels, or sets of ladders in the set of ladders 416 fall within the scope of this disclosure.

[0316] The set of conductors 430 comprises one or more conductors 430a, 430b, 430c, 430d, 430e or 430f.

[0317] The set of conductors 432 comprises one or more conductors 432a, 432b, 432c, 432d or 432e.

[0318] The conductor set 430 consists of Mo guide tracks. The conductor set 432 consists of BMo guide tracks. In some embodiments, conductors 430 and 432 are conductors in different layers. In some embodiments, the conductor set 430 corresponds to 6 Mo guide tracks. In some embodiments, the conductor set 432 corresponds to 4 BMo guide tracks.

[0319] In some embodiments, conductor 430a is configured to provide the reference supply voltage VSS, conductor 430b is the write bit line WBLB, conductor 430c is the write bit line WBL, conductor 430d is configured to provide the reference supply voltage VSS, conductor 430e is the read bit line RBL and conductor 430f is the read bit line RWL.

[0320] In some embodiments, conductor 432a is the write word line WWL, conductor 432b is configured to provide the supply voltage VDD, conductor 432c is the write word line WWL, conductor 432d is configured to provide the supply voltage VDD, and conductor 432e is the read word line strip RWLB.

[0321] Other arrangements, arrangements at other levels of arrangement, or sets of conductors in sets of conductors 430 and 432 are possible within the scope of this disclosure.

[0322] The set of vias 420 comprises one or more vias 420a, 420b, 420c, 420d, 420e or 420f.

[0323] The set of vias 422 comprises one or more vias 422a, 422b or 422c.

[0324] The set of vias 424 comprises one or more vias 424a.

[0325] The set of vias 426 comprises one or more vias 426a, 426b or 426c.

[0326] The set of vias 420 is configured to electrically couple a corresponding source or drain region of the set of active regions 402 to the set of conductors 430 via the set of contacts 410 or 414, and vice versa. The via 420 is located between the contacts 410 or 414 and the conductors 430.

[0327] The set of vias 422 is configured to electrically couple a corresponding source or drain region of the set of active regions 404 to the set of conductors 432 via the set of contacts 412 or 414, and vice versa. The via 422 is located between the contacts 412 or 414 and the conductors 432.

[0328] The set of vias 424 is configured to electrically couple one or more gates of the set of gates 406 to the set of conductors 430 and vice versa. The vias 424 are located between the gates 406 and the conductors 430.

[0329] The set of vias 426 is configured to electrically couple one or more gates of the set of gates 408 to the set of conductors 432 and vice versa. The vias 426 are located between the gates 408 and the conductors 432.

[0330] Via 420a electrically couples conductor 430a and contact 410a. Via 420b electrically couples conductor 430b and contact 410b. Via 420c electrically couples conductor 430c and contact 410c. Via 420d electrically couples conductor 430d and contact 410d. Via 420e electrically couples conductor 430d and contact 410e. Via 420f electrically couples conductor 430e and contact 414c.

[0331] Through-hole 422a electrically couples conductor 432b and contact 412a. Through-hole 422b electrically couples conductor 432d and contact 412d. Through-hole 422c electrically couples conductor 432d and contact 412e.

[0332] Via 424a electrically couples conductor 430f and gate 406a1.

[0333] Via 426a electrically couples conductor 432a and gate 408b2. Via 426b electrically couples conductor 432c and gate 408a2. Via 426c electrically couples conductor 432e and gate 408a1.

[0334] Other facilities, arrangements on other layout levels, or sets of vias in the set of vias 420, 422, 424, and 426 are within the scope of this disclosure.

[0335] In some embodiments, at least one gate of the set of gates 406 or 408 is formed using doped or undoped polycrystalline silicon (or polysilicon). In some embodiments, at least one gate of the set of gates 406 or 408 comprises a metal such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0336] In some embodiments, at least one contact of the set (contacts 410, 412, or 414), or at least one conductor of the set (conductors 416, 430, or 432), or at least one via of the set (vias 420, 422, 424, or 426) comprises one or more layers of a conductive material, a metal, a metal compound, or a doped semiconductor. In some embodiments, the conductive material comprises tungsten, cobalt, ruthenium, copper, or the like, or combinations thereof. In some embodiments, a metal comprises at least Cu (copper), Co, W, Ru, Al, or the like. In some embodiments, a metal compound comprises at least AlCu, W-TiN, TiSix, NiSix, TiN, TaN, or the like. In some embodiments, a doped semiconductor comprises at least doped silicon or the like.

[0337] In some embodiments, the gate insulation layer 494a electrically isolates the gate 406a1 and the gate 408a1 from each other. In some embodiments, the memory cell 400 can be used as a multiport memory cell with at least one first port and one second port by electrically isolating the gate 406a1 and the gate 408a1 from each other, requiring less area than other approaches.

[0338] In some embodiments, by including the set of insulating regions 494 in the integrated circuit 400, the gates 406a1 and 408a1 are separated from each other by the insulating region 494a, allowing the NFET transistor RPG1 and the PFET transistor RPG2 to be used as separate transistors configured to operate independently of each other in a CMOS device of at least one read port of a multiport memory cell, resulting in an integrated circuit 400 that occupies less area than other approaches.

[0339] In some embodiments, the NFET transistor RPG1 and the PFET transistor RPG2 can be configured to be used as separate transistors and are configured to operate independently of each other in a CMOS device of at least one read port of a multiport memory cell, resulting in an integrated circuit 400 that has improved speed compared to other approaches.

[0340] Other features or arrangements of the integrated circuit 400 are within the scope of this disclosure.

[0341] Fig. Figures 5A to 5E are diagrams of an integrated circuit 500 according to some embodiments.

[0342] Fig. 5A to 5D are corresponding diagrams of the corresponding sections 500A to 500D of an integrated circuit 500, which have been simplified for better illustration.

[0343] Section 500A comprises one or more elements of the 500 integrated circuit at the OD level, the POLY level, the CPO level, the MD level, the MDLI level, the VG level, and the VD level. Section 500A is Section 400A. Section 500A is manufactured from Section 300A.

[0344] Section 500B comprises one or more elements of the 500 integrated circuit at the OD, POLY, CPO, BMD, MDLI, VDR, BVG, and BVD levels. Section 400B is manufactured according to a similar layout to Section 300B, and a similarly detailed description is omitted for brevity.

[0345] Section 500D comprises one or more elements of the BMo 500 integrated circuit. Section 500D is manufactured according to a similar scheme as Section 300D, and a similarly detailed description is omitted for brevity.

[0346] Section 500E comprises one or more elements of the 500 integrated circuit of the OD level, POLY level, CPO level, BMD level, MDLI level, VDR level, BVG level, BVD level, and BMo level. Section 500E is manufactured according to a similar scheme to Section 300F, and a similarly detailed description is omitted for brevity.

[0347] Fig. 5E is a cross-sectional view of the integrated circuit 500, which is cut by the plane GG', according to some embodiments.

[0348] In some embodiments, the integrated circuit 500 is a memory cell 200A or 200B.

[0349] The integrated circuit 500 is manufactured using a corresponding layout design similar to the integrated circuit 500.

[0350] In some embodiments, the integrated circuit 500 is manufactured by a layout design similar to that of the layout design 300, and a similarly detailed description is therefore omitted. The structural relationships, including orientation, lengths and widths, as well as the facilities and layers of the integrated circuit 500 are similar to the structural relationships, facilities, and layers of the integrated circuit 300. Fig. 3A to 3F, and a similarly detailed description is provided at least in the Fig. 5A to 5E, not discussed for the sake of brevity.

[0351] The integrated circuit 500 is cell 501.

[0352] The integrated circuit 500 is a variant of the integrated circuit 400. Fig. 4A to 4L, and a similarly detailed description is omitted for the sake of brevity.

[0353] Compared to the integrated circuit 400 from Fig. 4A to 4L, a set of vias 522 replaces the set of vias 422 of the integrated circuit 400, and a set of conductors 532 replaces the set of conductors 432 of the integrated circuit 400, and a similarly detailed description is omitted for brevity.

[0354] The integrated circuit 500 comprises at least the set of active regions 402 and 404, the set of gates 406 and 408, the set of remote gate sections 440, the set of contacts 410, the set of contacts 412, the set of contacts 414, the set of conductors 416, the set of conductors 430, the set of conductors 532, the set of vias 420, the set of vias 522, the set of vias 424, the set of vias 426, a substrate 490, an insulating region 492 and a set of insulating regions 494.

[0355] The set of conductors 532 includes at least one of the conductors 432a, 432b, 432c, 432d, 432e or 532f.

[0356] In comparison to the integrated circuit 400, conductor 532f of the set of conductors 532 is similar to one or more of the conductors 432a, 432b, 432c, 432d, 432e of the set of conductors 432, and a similarly detailed description is omitted for the sake of brevity.

[0357] The group of conductors 532 comprises the BMo guide tracks. In some embodiments, the conductors 532 are guide tracks in other layers. In some embodiments, the set of conductors 432 corresponds to 5 BMo guide tracks. Other BMo track assignments or numbers of BMo tracks are possible within the scope of this disclosure.

[0358] In some embodiments, conductor 532f is the read bit line RBL.

[0359] Other facilities, arrangements on other layout levels, or sets of ladders in the set of ladders 532 fall within the scope of this disclosure.

[0360] The set of vias 522 includes at least one of the vias 422a, 422b, 422c or 522d.

[0361] In comparison to the integrated circuit 400, the via 522d of the set of vias 522 is similar to one or more of the vias 422a, 422b or 422c of the set of vias 422, and a similarly detailed description is omitted for the sake of brevity.

[0362] The conductor 532f and contact 414c are electrically coupled via 522f.

[0363] In some embodiments, the read bit line RBL is placed on both the front side 403a of the integrated circuit 500 as conductor 430e and on the back side 403b of the integrated circuit 500 as conductor 532f by including conductor 532f, thereby improving the speed of the integrated circuit 500 compared to other approaches.

[0364] In some embodiments, the integrated circuit 500 achieves one or more of the advantages described here.

[0365] Other arrangements, configurations on other layout levels, or sets of elements in the integrated circuit 500 are within the scope of this disclosure.

[0366] Fig. 6A is a diagram of section 600A of a plan 600 of an integrated circuit according to some embodiments.

[0367] Fig. 6B is a diagram of section 600B of the plan 600 of the integrated circuit according to some embodiments.

[0368] In some embodiments, the floor plan 600 is a floor plan of the integrated circuit 400. Fig. 4A to 4L or the integrated circuit 500 in Fig. 5A to 5E.

[0369] In some embodiments, section 600A is a front face of the integrated circuit 600, according to some embodiments.

[0370] In some embodiments, section 600B is a reverse side of the integrated circuit 600, according to some embodiments.

[0371] The floor plan 600 has two rows that extend in a first direction X and are separated from each other in a second direction Y.

[0372] The floor plan 600 includes a cell 601a and a cell 601b.

[0373] Cell 601a is placed in row R1.

[0374] Cell 601b is located in row R2. Row R1 is adjacent to or near row R2.

[0375] A cell boundary 690 extends in the first direction X. The cell boundary 690 separates cell 601a and cell 601b.

[0376] Cell 601a comprises region 602.

[0377] Cell 601b comprises region 604.

[0378] In some embodiments, cell 601b is a mirror image of cell 601a with respect to cell boundary 690.

[0379] In some embodiments, region 602 corresponds to integrated circuit 400 from Fig. 4A to 4L or the integrated circuit 500 in Fig. 5A to 5E, and a similarly detailed description is omitted for the sake of brevity.

[0380] In some embodiments, region 602 corresponds to layout design 300 from Fig. 3A to 3F, and a similarly detailed description is omitted for the sake of brevity.

[0381] In some embodiments, region 604 is a mirror image of region 602 with respect to cell boundary 690.

[0382] Region 610a in row R1 includes the NFET transistors RPG1 and RPD1.

[0383] Region 612a in row R1 includes the NFET transistors RPG1 and RPD1. Region 612a is similar to region 610a, and a similarly detailed description is omitted for brevity.

[0384] In some embodiments, the NFET transistors RPG1 and RPD1 of region 612a are included in region 602 to improve the driving strength of the NFET transistors RPG1 and RPD1.

[0385] Region 610b in row R2 includes the NFET transistors RPG1 and RPD1.

[0386] Region 612b in row R2 includes the NFET transistors RPG1 and RPD1. Region 612b is similar to region 610b, and a similarly detailed description is omitted for brevity.

[0387] In some embodiments, the NFET transistors RPG1 and RPD1 of region 612a are included in region 602 to improve the driving strength of the NFET transistors RPG1 and RPD1.

[0388] Region 620a in row R1 includes the PFET transistors RPG2 and RPD2.

[0389] Region 622a in row R1 comprises the PFET transistors RPG2 and RPD2. Region 622a is similar to region 620a, and a similarly detailed description is omitted for brevity.

[0390] In some embodiments, the PFET transistors RPG2 and RPD2 of region 622a are included in region 602 to improve the driver strength of the PFET transistors RPG2 and RPD2.

[0391] Region 620b in row R2 includes the PFET transistors RPG2 and RPD2.

[0392] Region 622b in row R2 comprises the PFET transistors RPG2 and RPD2. Region 622b is similar to region 620b, and a similarly detailed description is omitted for brevity.

[0393] In some embodiments, the PFET transistors RPG2 and RPD2 of region 622a are included in region 602 to improve the driver strength of the PFET transistors RPG2 and RPD2.

[0394] In some embodiments, the 600-fold layout of the integrated circuit achieves Fig. 6A to 6B have one or more of the advantages described here.

[0395] Other arrangements, configurations on other layout levels, or quantities of elements in floor plan 600 are possible within the scope of this disclosure.

[0396] Fig. Figure 7 is a time diagram 700 of the waveforms of a memory cell 200A according to some embodiments.

[0397] In some embodiments Fig. 7 a corresponding time diagram 700 of the waveforms of the storage circuit 100 in Fig. 1, according to some embodiments.

[0398] In some embodiments, the timing diagram 700 comprises waveforms of signals during a "0" read operation and / or a "1" read operation of memory cell 200A. In some embodiments, the waveforms of the signals during a write operation of memory cell 200A are the same as the waveforms of the signals during a read operation of memory cell 200A and are shown as timing diagram 700.

[0399] In some embodiments Fig. 7 as a time diagram of the waveforms of memory cell 200B in Fig. 2B usable, in these embodiments the waveforms of the word lines and bit lines differ from the word lines and bit lines of memory cell 200A in Fig. 2A and memory cell 200B in Fig. 2B has been modified accordingly according to some embodiments.

[0400] The timing diagram 700 includes waveforms of the write word line WWL, the write bit line WBL, the write bit line bar WBLB, the read bit line RBL, the read word line RWL, the read word line bar RWLB or a signal from the storage node NDB.

[0401] Fig. Figure 7 is a time diagram of 700 waveforms from the 200A storage circuit. Fig. 2A according to some embodiments.

[0402] At time T0 in Fig. 7. The write word line signal WWL is logically low (e.g., reference voltage VSS or "Logic 0"), the write bit line bar WBLB is logically high (e.g., voltage VDD or "Logic 1"), the write bit line WBL is logically high, the memory node signal NDB is logically high, the read bit line RBL is preloaded to 0.5 * voltage VDD (e.g., VDD / 2), the read word line bar RWLB is logically high, and the read word line RWL is logically low.

[0403] In some embodiments, the pre-charge voltage of the read bit line RBL is equal to 0.5 * voltage VDD (e.g., VDD / 2). Other pre-charge voltages of the read bit line RBL are possible in some embodiments within the scope of this disclosure.

[0404] For example, at time To, the PFET transistor RPG2 is turned off in response to the read word line bar RWLB being logic high, and the NFET transistor RPG1 is turned on in response to the read word line RWL being logic low.

[0405] For example, at time To, the PFET transistors PU2 and RPD2 are switched off in response to the memory node NDB signal being logic high, and the NFET transistors PD2 and RPD1 are switched on in response to the memory node NDB signal being logic high.

[0406] At time T1 in Fig. 7 The read word line bar signal RWLB transitions from logic high to logic low, thereby turning on the PFET transistor RPG2.

[0407] At time T1 in Fig. 7 The read word line signal RWL transitions from logic low to logic high, thereby switching on the NFET transistor RPG1.

[0408] At time T1 in Fig. 7. The read bit line RBL changes from 0.5 * VDD to 0.4 * VDD when the PFET transistor RPG2 is turned on and the NFET transistor RPG1 is turned on.

[0409] At time T2 in Fig. At step 7, the RWLB signal transitions from logic low to logic high, thereby switching off the PFET transistor RPG2.

[0410] At time T2 in Fig. At step 7, the signal of the read word line RWL transitions from logic high to logic low, thereby switching off the NFET transistor RPG1.

[0411] At time T2 in Fig. 7. The read bit line RBL changes from 0.4 * VDD to 0.5 * VDD when the PFET transistor RPG2 switches off and the NFET transistor RPG1 switches off.

[0412] In some embodiments, a "0" read operation of memory cell 200A takes place between times T1 and T2.

[0413] In some embodiments, during a read operation of memory cell 200A, if the read bit line RBL is equal to 0.4 * VDD, a logical zero (“0”) or a read “0” from memory cell 200A is represented.

[0414] At time T3 in Fig. 7 The write word line signal WWL transitions from logic low to logic high, thereby switching on the NFET transistors WPG1 and WPG2.

[0415] At time T3 in Fig. 7. The write bitbar signal WBLB transitions from logic high to logic low, causing the memory node signal NDB to transition from logic high to logic low.

[0416] For example, at time T3, the PFET transistors PU2 and RPD2 are turned on in response to the signal from the memory node NDB transitioning from logic high to logic low, and the NFET transistors PD2 and RPD1 are turned off in response to the signal from the memory node NDB transitioning from logic high to logic low.

[0417] At time T4 in Fig. 7 The write word line signal WWL transitions from logic high to logic low, thereby switching off the NFET transistors WPG1 and WPG2.

[0418] At time T4 in Fig. 7. The write bitband signal WBLB transitions from logic low to logic high. In some embodiments, at time T4, the signal of node NDB does not change in response to the transition of the write bitband signal WBLB from logic low to logic high, because the signal of node ND is logic high, thus keeping the NFET transistor PD1 turned on and the PFET transistor PU1 turned off.

[0419] At time T5 in Fig. 7 The read word line bar signal RWLB transitions from logic high to logic low, thereby turning on the PFET transistor RPG2.

[0420] At time T5 in Fig. 7 The read word line signal RWL transitions from logic low to logic high, thereby switching on the NFET transistor RPG1.

[0421] At time T5 in Fig. 7. The read bit line RBL changes from 0.5 * VDD to 0.6 * VDD when the PFET transistor RPG2 switches off and the NFET transistor RPG1 switches off.

[0422] In some embodiments, a "1" read operation of memory cell 200A takes place between times T5 and T6.

[0423] In some embodiments, during a read operation of memory cell 200A, if the read bit line RBL is equal to 0.6 * VDD, a logical zero ("1") or a read "1" from memory cell 200A is represented.

[0424] At time T6, in Fig. 7. The write word line signal WWL is logically low, the write bit line bar WBLB is logically high, the write bit line WBL is logically high, the signal of the memory node NDB is logically low, the read bit line RBL is equal to 0.6 * voltage VDD, the read word line bar RWLB is logically low and the read word line RWL is logically high.

[0425] In some embodiments, the NFET transistor RPG1 and the PFET transistor RPG2 are configured to receive different corresponding signals (e.g., read word line bar RWLB and read word line RWL), thus using the NFET transistor RPG1 and the PFET transistor RPG2 as separate transistors configured to operate independently in a CMOS device of at least one read port of a multiport memory cell, resulting in an integrated circuit 400 or 500 or a memory cell 200A or 200B that occupies less area than other approaches.

[0426] In some embodiments, the NFET transistor RPG1 and the PFET transistor RPG2 are configured to be used as separate transistors and are configured to operate independently of each other in a CMOS device of at least one read port of a multiport memory cell, resulting in an integrated circuit 400 or 500 or a memory cell 200A or 200B with improved performance and speed compared to other approaches.

[0427] In some embodiments, at least one of the memory circuit 200A, the memory circuit 200B, the integrated circuit 400 or the integrated circuit 500 operates using the timing diagram 700 to achieve one or more of the advantages described herein, which include the details discussed herein.

[0428] Other features of the Time Diagram 700 fall within the scope of this revelation.

[0429] Fig. Figure 8 is a functional flowchart for a process 800 for manufacturing an IC device according to some embodiments. It should be understood that further processes before, during, and / or after the process 800 may occur. Fig. 8 can be executed, and that some other processes may only be briefly discussed here.

[0430] In some embodiments, a different sequence of operations in methods 800 to 1000 within the scope of this disclosure is possible. Methods 800 to 1000 comprise exemplary operations, which, however, are not necessarily performed in the sequence shown. According to the spirit and scope of the disclosed embodiments, operations may be added, exchanged, changed in order, and / or eliminated. In some embodiments, one or more of the operations of at least methods 800, 900, or 1000 are not performed.

[0431] In some embodiments, method 800 is an embodiment of process 904 of method 900. In some embodiments, methods 800 to 1000 can be used to produce or manufacture at least the integrated circuit 100, 200A, 200B, 400 or 500 or the layout 600 or an integrated circuit with similar features to at least the layout design 300.

[0432] In step 802 of method 800, a first set of transistors and a second set of transistors are fabricated on a front face 403a of a semiconductor wafer or substrate. In some embodiments, the first set of transistors or the second set of transistors of method 800 comprises one or more transistors in at least the set of active regions 402 or 404. In some embodiments, the first set of transistors or the second set of transistors of method 800 comprises one or more transistors described herein.

[0433] In some embodiments, process 802 comprises fabricating source and drain regions of the transistor set in a first well. In some embodiments, the first well comprises p-type dopants. In some embodiments, the p-type dopants comprise boron, aluminum, or other suitable p-type dopants. In some embodiments, the first well comprises an epilayer built up on a substrate. In some embodiments, the epilayer is doped by adding dopants during the epitaxy process. In some embodiments, the epilayer is doped by ion implantation after the epilayer has been formed. In some embodiments, the first well is formed by doping the substrate. In some embodiments, the doping is performed by ion implantation. In some embodiments, the first well has a dopant concentration between 1 × 10 12 atoms / cm² 3 and 1 × 1014 atoms / cm² 3 lies.

[0434] In some embodiments, the first well comprises n dopants. In some embodiments, the n dopants comprise phosphorus, arsenic, or other suitable n dopants. In some embodiments, the n dopant concentration ranges from about 1 × 10 12 atoms / cm² 3 up to about 1 × 10 14 atoms / cm² 3 ,

[0435] In some embodiments, the formation of the source / drain elements involves removing a section of the substrate to create cutouts at an edge of spacers, followed by a filling process to fill the cutouts in the substrate. In some embodiments, the wells are etched, for example, by wet or dry etching, after a cushion oxide layer or a sacrificial oxide layer has been removed. In some embodiments, the etching process is performed to remove an upper surface portion of the active region adjacent to an isolation region, such as an STI region. In some embodiments, the filling process is performed by an epitaxial or epitaxy process (epi-process). In some embodiments, the cutouts are filled by a growth process concurrent with an etching process, wherein the growth rate of the growth process is greater than the etching rate of the etching process.In some embodiments, the cutouts are filled by a combination of growth and etching processes. For example, a layer of material is built up in the well, and the built-up material is subsequently subjected to an etching process to remove a portion of the material. A further growth process is then performed on the etched material until a desired thickness of material is achieved in the cutout. In some embodiments, the growth process continues until the top surface of the material is above the top surface of the substrate. In some embodiments, the growth process continues until the top surface of the material is coplanar with the top surface of the substrate. In some embodiments, a portion of the first well is removed by an isotropic or anisotropic etching process. The etching process selectively etches the first well without etching any gate structure or spacers.In some embodiments, the etching process is performed by reactive ion etching (RIE), wet etching, or other suitable techniques. In some embodiments, a semiconductor material is deposited into the cutouts to form the source / drain elements. In some embodiments, an epi-process is performed to deposit the semiconductor material in the cutouts. In some embodiments, the epi-process includes a selective epitaxial growth (SEG) process, a continuous vapor deposition (CVD) process, molecular beam epitaxy (MBE), other suitable processes, and / or a combination thereof. The epi-process utilizes gaseous and / or liquid precursors that interact with a substrate composition. In some embodiments, the source / drain elements comprise epitaxially built silicon (epiSi), silicon carbide, or silicon germanium.Source / drain elements of the IC device associated with the Gates structure are, in some cases, doped or undoped in situ during the epi-process. If source / drain elements are undoped during the epi-process, they are, in some cases, doped during a subsequent process. This subsequent doping process is performed by ion implantation, plasma immersion ion implantation, gas and / or solid diffusion, other suitable methods, and / or combinations thereof. In some embodiments, the source / drain elements are subjected to further annealing processes after their formation and / or after the subsequent doping process.

[0436] In some embodiments, process 802 further comprises process 802a. In some embodiments, process 802a comprises forming a first gate region of the second set of transistors. In some embodiments, the first gate region of the second set of transistors of process 800 comprises the set of gates 408.

[0437] In some embodiments, process 802 further comprises process 802b. In some embodiments, process 802b comprises forming a first insulating material on a first gate structure of the second transistor set. In some embodiments, process 802b comprises forming a first insulating material over at least the first gate structure of the first gate regions of the second transistor set. In some embodiments, the first gate structure of the first gate regions of the second transistor set comprises at least one of the gates 408a1. In some embodiments, the first insulating material comprises the set of insulating regions 494. In some embodiments, the first insulating material comprises at least one of the insulating regions 494a.

[0438] In some embodiments, process 802 further comprises process 802c. In some embodiments, process 802c comprises forming a second gate region of the first set of transistors. In some embodiments, the second gate regions of the first transistor set of process 800 comprise the set of gates 406.

[0439] In some embodiments, the first and second gate regions are located between the drain region and the source region. In some embodiments, the first and second gate regions are located above the first well and the substrate. In some embodiments, fabricating the first and second gate regions of operations 802a and 802c includes performing one or more deposition processes to form one or more layers of dielectric material. In some embodiments, a deposition process includes chemical vapor deposition (CVD), plasma-enhanced electrochemical vapor deposition (PECVD), atomic layer deposition (ALD), or another method suitable for depositing one or more layers of material. In some embodiments, fabricating the first and second gate regions includes performing one or more deposition processes to form one or more layers of conductive material.In some embodiments, fabricating the first and second gate regions includes forming gate electrodes or dummy gate electrodes. In some embodiments, fabricating the gate regions includes depositing or building up at least one dielectric layer, e.g., a gate dielectric. In some embodiments, the gate regions are formed from doped or undoped polycrystalline silicon (or polysilicon). In some embodiments, the first and second gate regions comprise a metal, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0440] In some embodiments, forming the first insulating material on the first gate structure of the second set of transistors of process 802b comprises performing one or more deposition processes to form one or more dielectric and / or insulating material layers. In some embodiments, the one or more deposition processes for forming one or more dielectric and / or insulating material layers include CVD, PECVD, ALD, or other processes suitable for depositing one or more material layers. In some embodiments, forming the first insulating material on the first gate structure of the second set of transistors comprises performing one or more deposition processes to form one or more insulating material layers. In some embodiments, the first insulating material is a dielectric.In some embodiments, the dielectric comprises silicon dioxide, silicon nitride or the like.

[0441] In some embodiments, operations 802a, 802b, and 802c are replaced by forming the first gate regions of the second set of transistors and the second gate regions of the first set of transistors, removing a portion of the first gate regions of the second set of transistors and the second gate regions of the first set of transistors, and forming the first insulating material between the first gate structure of the second set of transistors and the second gate structure of the first set of transistors. In some embodiments, the gate removal process is a poly-cutting process that includes one or more etching processes. In some embodiments, the gate removal process includes one or more etching processes suitable for removing a portion of the gate structure. In some embodiments, a mask is used to specify the portions of the gate structure to be cut out or removed.In some embodiments, the mask is a hard mask. In some embodiments, the mask is a soft mask. In some embodiments, the etching corresponds to plasma etching, reactive ion etching, chemical etching, dry etching, wet etching, other suitable processes, a combination thereof, or the like.

[0442] In some embodiments, the gate removal process of operations 802a, 802b or 802c also includes the formation of the set of gates 406 or 408, and the cutting regions are formed by the set of cutting element structures 340. Fig. 3A to 3F.

[0443] In some embodiments, process 802 further comprises process 802d. In some embodiments, process 802d comprises depositing a first conductive material on a first level, a second level or a third level, thereby forming at least one corresponding first set of contacts, a second set of contacts or a third set of contacts.

[0444] In some embodiments, the first set of contacts, the second set of contacts, and the third set of contacts are sections of the first set of transistors and the second set of transistors.

[0445] In some embodiments, the first set of contacts comprises the set of contacts 410.

[0446] In some embodiments, the second set of contacts comprises the set of contacts 412.

[0447] In some embodiments, the third set of contacts comprises the set of contacts 414.

[0448] In step 804 of method 800, a first set of vias is formed on the front face 403a of the wafer or substrate at a VD layer or a VG layer (e.g., VD or VG). In some embodiments, the first set of vias of method 800 comprises one or more sections of at least the set of vias 420 or 424.

[0449] In some embodiments, process 804 comprises forming a first set of self-aligned contacts (SACs) in the insulating layer above the front face 403a of the wafer. In some embodiments, the first set of vias is electrically coupled to at least the first set of transistors or the second set of transistors.

[0450] In step 806 of process 800, a second conductive material is deposited on the front face 403a of the substrate on a first metal layer, thereby forming a first set of conductors on the front face 403a of the wafer or substrate on a first metal layer (e.g. Mo).

[0451] In some embodiments, process 808 comprises at least the deposition of a first set of conductive regions on the front face 403a of the integrated circuit. In some embodiments, the first set of conductors of process 800 comprises one or more sections of at least the set of conductors 430.

[0452] In some embodiments, the first set of conductors comprises a first read word line (RWL / 430f) and a first read bit line (RBL / 430e). In some embodiments, the first set of transistors is configured to receive a first read word line signal on the first read word line (RWL) and a first read bit line signal on the first read bit line (RBL) from the front face.

[0453] In step 808 of process 800, thinning is performed on the back side 403b of the wafer or substrate. In some embodiments, step 810 comprises a thinning process performed on the back side 403b of the semiconductor wafer or substrate. In some embodiments, the thinning process comprises a grinding process and a polishing process (such as chemical-mechanical polishing (CMP)) or other suitable processes. In some embodiments, a wet etching process is performed after the thinning process to remove the defects formed on the back side 403b of the semiconductor wafer or substrate.

[0454] In step 810 of process 800, a second set of conductors (VDR / 416) is fabricated on the back of the thinned wafer.

[0455] In some embodiments, the second set of conductors is located under one or more gates (e.g. set of gates 406 or 408) or active regions (e.g. set of active regions 402 or 404) of at least the first set of transistors or the second set of transistors.

[0456] In some embodiments, the second set of conductors is electrically coupled to at least the second set of transistors. In some embodiments, the second set of conductors is embedded in the thinned substrate.

[0457] In some embodiments, the second set of conductors of method 800 comprises one or more sections of at least the set of conductors 416.

[0458] In step 812 of method 800, a second set of vias is formed on the back side 403b of the thinned wafer or substrate at a BVD layer or a BVG layer (e.g., BVD or BVG). In some embodiments, the second set of vias of method 800 comprises one or more sections of at least the set of vias 422, 426, or 522.

[0459] In some embodiments, process 812 comprises forming a second set of self-aligned contacts (SACs) in the insulating layer above the back side 403b of the wafer. In some embodiments, the second set of vias is electrically coupled to at least the first set of transistors or the second set of transistors.

[0460] In step 814 of process 800, a third conductive material is deposited on the back side 403b of the substrate on a second metal layer, thereby forming a third set of conductors on the back side 403b of the wafer or substrate on the second metal layer (e.g. BM0).

[0461] In some embodiments, process 814 comprises at least the deposition of a second set of conductive regions on the back side 403b of the integrated circuit. In some embodiments, the third set of conductors of process 800 comprises one or more sections of at least the set of conductors 432 or 532.

[0462] In some embodiments, the third set of conductors is electrically coupled to at least the second set of transistors via the second set of vias. In some embodiments, the second set of conductors includes a second read word line (RWL / 432e). In some embodiments, the second set of transistors is configured to receive a second read word line signal on the second read word line.

[0463] In some embodiments, the second set of conductors further comprises a second read bit line (RBL / 532f). In some embodiments, the second set of transistors is further configured to receive the first read bit line signal on the second read bit line from the rear side.

[0464] In some embodiments, one or more of steps 802, 804, 806, 810, 812, or 814 of process 800 comprise the use of a combination of photolithography and material removal processes to form openings in an insulating layer (not shown) over the substrate. In some embodiments, the photolithography process comprises structuring a photoresist, such as a positive or negative photoresist. In some embodiments, the photolithography process comprises forming a hard mask, an antireflection structure, or another suitable photolithography structure. In some embodiments, the material removal process comprises a wet etching process, a dry etching process, an RIE process, laser drilling, or another suitable etching process. The openings are then filled with conductive material, such as copper, aluminum, titanium, nickel, tungsten, or another suitable conductive material.In some embodiments, the openings are filled by CVD, PVD, sputtering, ALD or another suitable formation process.

[0465] In some embodiments, at least one or more processes of method 800 are performed by system 1200. Fig. 12. In some embodiments, at least one process, such as the process 800 discussed above, is carried out wholly or partly by at least one manufacturing system, including system 1200. One or more of the operations of process 800 are carried out by IC-Fab 1240 ( Fig. 12) to manufacture the IC device 1260. In some embodiments, one or more of the operations of method 800 are carried out by manufacturing tools 1252 to manufacture the wafer 1242.

[0466] In some embodiments, the conductive material comprises copper, aluminum, titanium, nickel, tungsten, or another suitable conductive material. In some embodiments, the openings and the trench are filled by CVD, PVD, sputtering, ALD, or another suitable formation process. In some embodiments, the conductive material is planarized after deposition in one or more of operations 802d, 806, 808, or 814 to provide a flat surface for the subsequent steps.

[0467] In some embodiments, one or more of the operations of methods 800, 900 or 1000 are not performed.

[0468] One or more of the operations of methods 800 to 900 are performed by a processing device configured to execute instructions for manufacturing an integrated circuit, such as at least the integrated circuit 100, 200A, 200B, 400, or 500, or the plan 600. In some embodiments, one or more operations of methods 800 to 900 are performed by the same processing device used for one or more other operations of methods 800 to 900. In some embodiments, a different processing device is used to perform one or more operations of methods 800 to 900 than the one used to perform one or more other operations of methods 800 to 900. In some embodiments, a different sequence of operations of methods 800, 900, or 1000 is possible within the scope of this disclosure.Method 800, 900, or 1000 comprises exemplary operations, but these operations need not necessarily be performed in the sequence shown. The operations in Method 800, 900, or 1000 may be added, replaced, reordered, and / or eliminated according to the spirit and scope of the disclosed embodiments.

[0469] Fig. Figure 9 is a flowchart of a method 900 for forming or fabricating an integrated circuit according to some embodiments. It is to be understood that further processes may occur before, during, and / or after the method 900, as shown in Fig. 9 can be carried out as shown, and that some other processes may only be briefly described here. In some embodiments, the method 900 can be used to fabricate integrated circuits, such as at least the integrated circuits 100, 200A, 200B, 400, or 500. In some embodiments, the method 900 can be used to form integrated circuits with similar features and similar structural relationships as one or more of the layout design 300.

[0470] In step 902 of procedure 900, a layout design for an integrated circuit is created. Step 902 is performed by a processing device (e.g., processor 1102 ( Fig. 11)), which is configured to execute instructions for generating a layout design. In some embodiments, the layout design of Method 900 comprises one or more structures of at least Layout Design 300 or one or more elements similar to at least Integrated Circuit 100, 200A, 200B, 400 or 500 or Plan 600. In some embodiments, the layout design of this application is in a GDSII (Graphic Database System) file format. In some embodiments, Operation 902 corresponds to Method 1000 from Fig. 10.

[0471] In step 904 of method 900, the integrated circuit is fabricated based on the layout design. In some embodiments, step 904 of method 900 comprises fabricating at least one mask based on the layout design and fabricating the integrated circuit based on the at least one mask. In some embodiments, step 904 corresponds to method 800 from Fig. 8.

[0472] Fig. Figure 10 is a flowchart of a method 1000 for generating a layout design for an integrated circuit according to some embodiments. It is understood that further processes occur before, during, and / or after the process described in the figure. Fig. The procedures described in section 10 may be carried out in method 1000, and some other processes may only be briefly described here. In some embodiments, method 1000 is an embodiment of process 1002 of method 900. In some embodiments, method 1000 can be used to generate one or more layout structures of at least layout design 300, or one or more elements that are at least similar to integrated circuit 100, 200A, 200B, 400, or 500, or floor plan 600.

[0473] In some embodiments, the method 1000 can be used to generate one or more layout structures that have structural relationships, including orientation, lengths and widths, as well as facilities and layers of at least the layout design 300 or one or more elements that are at least similar to the integrated circuit 100, 200A, 200B, 400 or 500 or the floor plan 600, and a similarly detailed description is given in Fig. 10, not discussed for the sake of brevity.

[0474] In step 1002 of method 1000, a set of active region structures is created or placed on the layout design. In some embodiments, the active region structure set of method 1000 includes at least sections of one or more structures from the active region structure set 302 or 304. In some embodiments, the active region structure set of method 1000 includes one or more regions similar to the active region structure set 402 or 404. In some embodiments, the active region structure set of method 1000 includes one or more structures or similar structures in the OD layer.

[0475] In step 1004 of method 1000, a set of gate structures is created or placed on the layout design. In some embodiments, the set of cutting element structures of method 1000 comprises at least sections of one or more structures of the set of cutting element structures 306 or 308, or of the set of cutting element structures 340. In some embodiments, the set of active gate structures of method 1000 comprises one or more regions similar to the set of gates 406 or 408. In some embodiments, the set of gate structures of method 1000 comprises at least sections of one or more structures of the set of insulating structures 394. In some embodiments, the set of gate structures of method 1000 comprises one or more regions similar to the set of insulating regions 494. In some embodiments, the set of gate structures of method 1000 comprises one or more structures or similar structures in the POLY layer.

[0476] In step 1006 of method 1000, a first set of conductive structures is created or placed on the layout design. In some embodiments, the first set of conductive structures of method 1000 comprises at least sections of one or more structures of the set of contact structures 310. In some embodiments, the first set of conductive structures of method 1000 comprises one or more structures similar to the set of contacts 410. In some embodiments, the first set of conductive structures of method 1000 comprises one or more structures or similar structures in the MD layer.

[0477] In step 1008 of method 1000, a second set of conductive structures is created or placed on the layout design. In some embodiments, the second set of conductive structures of method 1000 comprises at least sections of one or more structures of the set of contact structures 312. In some embodiments, the second set of conductive structures of method 1000 comprises one or more structures similar to the set of contacts 412. In some embodiments, the second set of conductive structures of method 1000 comprises one or more structures or similar structures in the BMD layer.

[0478] In step 1010 of method 1000, a third set of conductive structures is created or placed on the layout design. In some embodiments, the third set of conductive structures of method 1000 comprises at least portions of one or more structures of the set of contact structures 314. In some embodiments, the third set of conductive structures of method 1000 comprises one or more structures similar to the set of contacts 414. In some embodiments, the third set of conductive structures of method 1000 comprises one or more structures or similar structures in the MDLI layer.

[0479] In step 1012 of method 1000, a fourth set of conductive structures is created or placed on the layout design. In some embodiments, the fourth set of conductive structures of method 1000 comprises at least sections of one or more structures of the set of conductive element structures 316. In some embodiments, the fourth set of conductive structures of method 1000 comprises one or more structures similar to the set of conductors 416. In some embodiments, the fourth set of conductive structures of method 1000 comprises one or more structures or similar structures in the VDR layer.

[0480] In step 1014 of method 1000, a first set of vias is created or placed on the layout design. In some embodiments, the first set of vias of method 1000 comprises at least portions of one or more structures of the set of vias 320 or 324. In some embodiments, the first set of vias of method 1000 comprises one or more vias that are at least similar to the set of vias 420 or 424. In some embodiments, the first set of vias of method 1000 comprises one or more structures or similar vias in the VG or VD layer.

[0481] In step 1016 of method 1000, a second set of vias is created or placed on the layout design. In some embodiments, the second set of vias of method 1000 includes at least portions of one or more structures of the set of vias 322 or 326. In some embodiments, the second set of vias of method 1000 includes one or more vias that are at least similar to the set of vias 422, 426, or 522. In some embodiments, the second set of vias of method 1000 includes one or more structures or similar vias in the BVG or BVD layer.

[0482] In step 1018 of method 1000, a fifth set of conductive structures is created or placed on the layout design. In some embodiments, the fifth set of conductive structures of method 1000 comprises at least sections of one or more structures of at least the set of conductive structures 330. In some embodiments, the fifth set of conductive structures of method 1000 comprises one or more conductive structures that are at least similar to the set of conductors 430. In some embodiments, the fifth set of conductive structures of method 1000 comprises one or more structures or similar conductors in the Mo layer.

[0483] In step 1020 of method 1000, a sixth set of conductive structures is created or placed on the layout design. In some embodiments, the sixth set of conductive structures of method 1000 comprises at least sections of one or more structures of at least the set of conductive structures 332. In some embodiments, the sixth set of conductive structures of method 1000 comprises one or more conductive structures that are at least similar to the set of conductors 432 or 532. In some embodiments, the sixth set of conductive structures of method 1000 comprises one or more structures or similar conductors in the BMo layer.

[0484] Fig. Figure 11 is a schematic view of a system 1100 for the design of an IC layout design and the fabrication of an IC circuit according to some embodiments.

[0485] In some embodiments, the System 1100 creates or places one or more of the IC layout designs described herein. The System 1100 comprises a hardware processor 1102 and a non-transitory, computer-readable storage medium 1104 (e.g., memory 1104) encoded with, i.e., storing, the computer program code 1106, i.e., a set of executable instructions 1106. The computer-readable storage medium 1104 is configured to be connected to manufacturing machines for fabricating the integrated circuit. The processor 1102 is electrically coupled to the computer-readable storage medium 1104 via a bus 1108. The processor 1102 is also electrically coupled to an I / O interface 1110 via the bus 1108. A network interface 1112 is also electrically connected to the processor 1102 via the bus 1108.Network interface 1112 is connected to a network 1114, enabling processor 1102 and computer-readable storage medium 1104 to connect to external elements via network 1114. Processor 1102 is configured to execute computer program code 1106, encoded in computer-readable storage medium 1104, to enable system 1100 to perform one or all of the operations described in procedures 900 to 1000.

[0486] In some embodiments, the 1102 processor is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC) and / or a suitable processing unit.

[0487] In some embodiments, the computer-readable storage medium 1104 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1104 comprises semiconductor or solid-state memory, magnetic tape, removable computer disk, random-access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or optical disk. In some embodiments that use optical disks, the computer-readable storage medium 1104 comprises a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disc (DVD).

[0488] In some embodiments, the storage medium 1104 stores the computer program code 1106, which is configured to cause the system 1100 to execute the process 900 to 1000. In some embodiments, the storage medium 1104 also stores information required for executing the process 900 to 1000, as well as information generated during the execution of the process 900 to 1000, such as the layout design 1116, user interface 1118, and manufacturing unit 1120, and / or a set of executable instructions for performing the operation of the process 900 to 1000. In some embodiments, the layout design 1116 comprises one or more of the layout structures of at least the layout design 300, or elements similar to at least the integrated circuit 100, 200A, 200B, 400, or 500, or the floor plan 600.

[0489] In some embodiments, the storage medium 1104 stores instructions (e.g., computer program code 1106) for communication with manufacturing machines. These instructions (e.g., computer program code 1106) enable the processor 1102 to generate manufacturing instructions that can be read by the manufacturing machines to effectively implement the process 900 to 1000 during a manufacturing process.

[0490] The System 1100 includes the I / O interface 1110. The I / O interface 1110 is coupled to an external circuit arrangement. In some embodiments, the I / O interface 1110 includes a keyboard, keypad, mouse, trackball, trackpad, and / or cursor direction keys for communicating information and commands to the processor 1102.

[0491] System 1100 also includes a network interface 1112, which is coupled to the processor 1102. The network interface 1112 allows System 1100 to communicate with the network 1114, to which one or more other computer systems are connected. The network interface 1112 includes wireless network interfaces such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or wired network interfaces such as Ethernet, USB, or IEEE-2094. In some embodiments, Method 900 to 1000 is implemented in two or more Systems 1100, and information such as layout design and user interface is exchanged between different Systems 1100 via the network 1114.

[0492] The System 1100 is configured to receive layout design information via the I / O interface 1110 or the network interface 1112. This information is transmitted via the bus 1108 to the processor 1102 to determine a layout design for manufacturing at least the integrated circuit 100, 200A, 200B, 400, or 500, or the floor plan 600. The layout design is then stored on the computer-readable medium 1104 as layout design 1116. The System 1100 is also configured to receive user interface information via the I / O interface 1110 or the network interface 1112. This information is stored on the computer-readable medium 1104 as user interface 1118. System 1100 is set up to receive information relating to a manufacturing unit 1120 via the I / O interface 1110 or the network interface 1112.The information is stored on the computer-readable medium 1104 as manufacturing unit 1120. In some embodiments, manufacturing unit 1120 includes manufacturing information used by system 1100. In some embodiments, manufacturing unit 1120 corresponds to mask manufacturing 1234. Fig. 12.

[0493] In some embodiments, Method 900 to 1000 is implemented as a standalone software application for execution by a processor. In some embodiments, Method 900 to 1000 is implemented as a software application that is part of an additional software application. In some embodiments, Method 900 to 1000 is implemented as a plug-in for a software application. In some embodiments, Method 900 to 1000 is implemented as a software application that is part of an EDA tool. In some embodiments, Method 900 to 1000 is implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to create a layout of the IC component. In some embodiments, the layout is stored on a non-transient, computer-readable medium. In some embodiments, the layout is created using a tool such as VIRTUOSO® from CADENCE DESIGN SYSTEMS, Inc.or another suitable layout generation tool. In some embodiments, the layout is generated based on a netlist created from a schematic design. In some embodiments, methods 900 to 1000 are implemented by a fabrication apparatus to produce an integrated circuit using a set of masks produced based on one or more layout designs generated by System 1100. In some embodiments, System 1100 is a fabrication apparatus configured to produce an integrated circuit using a set of masks produced based on one or more layout designs of this disclosure. In some embodiments, System 1100 can consist of... Fig. System 11 generates layout designs for an integrated circuit that are smaller than other approaches. In some embodiments, System 1100 generates from Fig. 11 layout designs for integrated circuits that take up less space and provide better routing resources than other approaches.

[0494] Fig. Figure 12 is a block diagram of a fabrication system for integrated circuits (IC) 1200 and an associated IC fabrication process according to at least one embodiment of this disclosure. In some embodiments, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of an integrated semiconductor circuit is fabricated using the fabrication system 1200 based on a layout diagram.

[0495] In Fig. 12 The IC manufacturing system 1200 (hereinafter “System 1200”) comprises units such as a design house 1220, a mask house 1230, and an IC manufacturer / fabricator (“Fab”) 1240, which interact with each other in the design, development, and manufacturing cycles and / or services related to the manufacture of an IC device 1260. The entities in System 1200 are connected by a communication network. In some embodiments, the communication network is a single network. In other embodiments, the communication network is a multitude of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities, providing services to and / or receiving services from one or more of the other entities.In some embodiments, one or more of the companies Design House 1220, Mask House 1230, and IC-Fab 1240 are owned by a single larger company. In some embodiments, one or more Design House 1220, Mask House 1230, and IC-Fab 1240 exist in a shared facility and utilize common resources.

[0496] Design House (or Design Team) 1220 creates an IC design layout 1222. The IC design layout 1222 comprises various geometric structures designed for an IC device 1260. These geometric structures correspond to structures made of metal, oxide, or semiconductor layers that represent the various components of the IC device 1260 to be manufactured. The different layers combine to form various IC elements. For example, a section of the IC design layout 1222 includes various IC elements, such as an active region, a gate electrode, a source electrode, and a drain electrode; metal traces or vias of an interlayer connection; and openings for bond pads formed in a semiconductor substrate (such as a silicon wafer); and various material layers placed on the semiconductor substrate.Design House 1220 implements a proper design procedure to create IC design layout 1222. The design procedure includes one or more logic design, physical design, or location and route. IC design layout 1222 is shown in one or more data files containing information about the geometric structures. For example, IC design layout 1222 can be expressed in a GDSII file format or a DFII file format.

[0497] The mask house 1230 comprises data preparation 1232 and mask production 1234. Mask house 1230 uses the IC design layout 1222 to produce one or more masks 1245, which are used to manufacture the various layers of the IC device 1260 according to the IC design layout 1222. Mask house 1230 performs mask data preparation 1232, in which the IC design layout 1222 is translated into a representative data file (RDF). Mask data preparation 1232 provides the RDF for mask production 1234. Mask production 1234 includes a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (reclined plate) 1245 or a semiconductor wafer 1242. The IC design layout 1222 is processed by the mask data preparation 1232 to meet the specific characteristics of the mask writer and / or the requirements of IC manufacturing 1240. Fig. Figure 12 illustrates mask data preparation 1232 and mask production 1234 as separate elements. In some embodiments, mask data preparation 1232 and mask production 1234 can be referred to collectively as mask data preparation.

[0498] In some embodiments, the mask data preparation 1232 includes optical proximity correction (OPC), which employs lithographic enhancement techniques to compensate for image defects that may arise from diffraction, interference, other process effects, and the like. OPC adapts the IC design layout 1222. In some embodiments, the mask data preparation 1232 includes further resolution enhancement (RET) techniques, such as off-axis illumination, subresolution auxiliary features, phase-shifted masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverted lithography technology (ILT) is also used, which OPC treats as an inverted imaging problem.

[0499] In some embodiments, the mask data preparation 1232 includes a mask rule checker (MRC) that checks the IC design layout processed in OPC against a set of mask creation rules that include certain geometric and / or connectivity constraints to ensure sufficient clearances, account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout to compensate for constraints encountered during mask manufacturing 1234, which may undo some of the modifications made by the OPC to satisfy the mask creation rules.

[0500] In some embodiments, the mask data preparation 1232 includes a lithography process check (LPC) that simulates the processing performed by the IC fab 1240 to manufacture the IC fixture 1260. The LPC simulates the processing based on the IC design layout 1222 to produce a simulated manufactured fixture, such as the IC fixture 1260. The processing parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools for manufacturing the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of field (DOF), mask error improvement factor (MEEF), other suitable factors, and the like, or combinations thereof.In some embodiments, after the simulated device has been generated by LPC, if the simulated device does not conform accurately enough in shape to meet the design rules, the OPC and / or MRC are repeated to further refine the IC design layout 1222.

[0501] It should be clear that the above description of the mask data preparation 1232 has been simplified for clarity. In some embodiments, the data preparation 1232 includes additional features such as a logic operation (LOP) for modifying the IC design layout according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1222 during the data preparation 1232 can be executed in a variety of different sequences.

[0502] Following mask data preparation 1232 and during mask fabrication 1234, a mask 1245 or a group of masks 1245 is produced based on the modified IC design layout 1222. In some embodiments, mask fabrication 1234 includes performing one or more lithographic exposures based on the IC design layout 1222. In some embodiments, an electron beam (E-beam) or a multi-E-beam mechanism is used to form a structure on a mask (photomask or reticle) 1245 based on the modified IC design layout 1222. The mask 1245 can be formed using various technologies. In some embodiments, the mask 1245 is fabricated using a binary process. In some embodiments, a mask structure comprises opaque regions and transparent regions.A radiation beam, such as an ultraviolet (UV) beam, used to expose the image-sensitive material layer (such as photoresist) with which the wafer is coated, is blocked by the opaque region and propagates through the transparent regions. In one example, a binary version of the mask 1245 comprises a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) deposited in the opaque regions of the binary mask. In another example, the mask 1245 is fabricated using a phase-shifting technique. In the phase-shifting mask (PSM) of the mask 1245, various elements in the structures formed on the mask are arranged to have a suitable phase difference to improve resolution and image quality. In various examples, the phase-shifting mask can be an equalized PSM or an alternating PSM.The mask(s) produced by the mask manufacturing process 1234 are used in various processes. For example, such a mask(s) are used in an ion implantation process to form different doped regions in the semiconductor wafer, in an etching process to form different etched regions in the semiconductor wafer, and / or in other suitable processes.

[0503] The IC-Fab 1240 is an IC manufacturing unit comprising one or more manufacturing facilities for producing various IC products. In some embodiments, the IC-Fab 1240 functions as a semiconductor foundry. For example, there may be one manufacturing facility for the front-end manufacturing of multiple IC products (front-end-of-line manufacturing (FEOL manufacturing)), while a second manufacturing facility handles the back-end manufacturing for interconnecting and packaging the IC products (back-end-of-line manufacturing (BEOL manufacturing)), and a third manufacturing facility provides other services to the foundry.

[0504] The IC Fab 1240 comprises wafer fabrication tools 1252 (hereinafter referred to as "fabrication tools 1252") configured to perform various fabrication operations on the semiconductor wafer 1242, such that the IC device 1260 is fabricated after the mask(s), e.g., the mask 1245. In various embodiments, the fabrication tools 1252 comprise one or more wafer steppers, an ion implanter, a photoresist coater, a process chamber, e.g., a CVD chamber or an LPCVD oven, a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes as discussed herein.

[0505] The IC-Fab 1240 uses the mask(s) 1245 manufactured by the mask-factory 1230 to manufacture the IC-device 1260. Thus, the IC-Fab 1240 uses the IC-design layout 1222, at least indirectly, to manufacture the IC-device 1260. In some embodiments, a semiconductor wafer 1242 is manufactured in the IC-Fab 1240 using mask(s) 1245 to create an IC-device 1260. In some embodiments, IC manufacturing includes performing one or more lithographic exposures, which are created, at least indirectly, based on the IC-design 1222. The semiconductor wafer 1242 comprises a silicon substrate or other ordinary substrate having layers of material formed on it. The semiconductor wafer 1242 further comprises one or more different doped regions, dielectric elements, multilayer interconnects and the like (formed in subsequent manufacturing steps).

[0506] System 1200 is shown to include the Design House 1220, the Mask House 1230, or the IC Fab 1240 as separate components or units. However, it is self-evident that one or more of the components—Design House 1220, Mask House 1230, or IC Fab 1240—are sections of the same component or unit.

[0507] Fig. Figures 13A to 13B are a flowchart of an operating procedure of a circuit according to some embodiments.

[0508] Fig. Figures 13A to 13B are a flowchart of method 1300 for operating a circuit according to some embodiments.

[0509] In some embodiments, Fig. 13A to 13B a ​​flowchart of procedure 1300 for operating at least one of the memory cells 200A from Fig. 2A or memory cell 200B from Fig. 2B. In some embodiments, for example Fig. 13A to 13B a ​​flowchart of procedure 1300 for performing at least one “0” read operation or one “1” read operation from at least one of the memory cells 200A Fig. 2A or memory cell 200B from Fig. 2B.

[0510] In some embodiments Fig. 13A to 13B a ​​flowchart of procedure 1300 for operating at least one from the storage circuit 100 Fig. 1, the integrated circuit 400 from Fig. 4A to 4L, the integrated circuit 500 from Fig. 5A to 5E or floor plan 600 from Fig. 6A to 6B.

[0511] In some embodiments Fig. 13A to 13B are a flowchart of procedure 1300 for operating a storage circuit, and procedure 1300 comprises the elements of timing diagram 700 from Fig. 7, and a similarly detailed description is omitted for the sake of brevity.

[0512] It is understood that additional processes may occur before, during and / or after the in Fig. The procedures shown in sections 13A to 13B can be carried out as follows: 1300, and some other processes can only be briefly described here. It is to be understood that the 1300 procedure uses elements from at least one of the storage circuit 100. Fig. 1, the 200A storage cell from Fig. 2A, the memory cell 200B from Fig. 2B, the layout design 300 from Fig. 3A to 3F, the integrated circuit 400 from Fig. 4A to 4L, the integrated circuit 500 from Fig. 5A to 5E, or floor plan 600 from Fig. 6A to 6B are used, and a similarly detailed description is omitted for the sake of brevity.

[0513] In some embodiments, other sequences of operations of Method 1300 are possible within the scope of this disclosure. Method 1300 includes exemplary operations, which, however, are not necessarily performed in the sequence shown. According to the spirit and scope of the disclosed embodiments, operations may be added, exchanged, reordered, and / or eliminated. In some embodiments, one or more of the operations from Method 1300 are not performed.

[0514] In some embodiments, common elements of method 1300 are not labelled in the description of each individual method 1300 for the sake of brevity.

[0515] In step 1302 of procedure 1300, a read bit line is pre-charged to a first pre-charge voltage.

[0516] In some embodiments, the initial pre-charge voltage is equal to 0.5 * VDD. Other pre-charge voltages are possible within the scope of this disclosure.

[0517] In some embodiments, the read bit line includes the read bit line RBL.

[0518] In step 1304 of procedure 1300, a read word line bar signal is caused to change from a first logical value (high) to a second logical value (low) on a read word line bar.

[0519] In some embodiments, the first logical value is a logical 1, and the second logical value is a logical 0.

[0520] In some embodiments, the read word guidance bar includes the read word guidance bar RWLB.

[0521] In some embodiments, at least one or more of the operations 1302 to 1336 are performed by at least one of the word line drivers 110ac or the LIO circuit 110BS.

[0522] In step 1306 of procedure 1300, a read word line signal is caused on a read word line to switch from the second logical value to the first logical value.

[0523] In some embodiments, the read word line includes the read word line RWL.

[0524] In step 1308 of procedure 1300, a first transistor and a second transistor are switched on in response to the bar signal of the read word line.

[0525] In some embodiments, the first transistor comprises the NFET transistor RPG1 and the second transistor comprises the PFET transistor RPG2.

[0526] In step 1310 of procedure 1300, a read bit line signal on a read bit line is caused to change from a first value to a second value in response to the switching on of at least the first transistor or the second transistor.

[0527] In some embodiments, the read bit line includes the read bit line RBL.

[0528] In some embodiments, the first value is equal to 0.5 * VDD.

[0529] In some embodiments, the second value is equal to 0.4 * VDD.

[0530] Other values ​​for the first value or the second value fall within the scope of this revelation.

[0531] In step 1312 of procedure 1300, the read word line bar signal on the read word line bar is caused to change from the second logical value to the first logical value.

[0532] In step 1314 of procedure 1300, the read word line signal is caused to change from the first logical value to the second logical value on the read word line.

[0533] In step 1316 of procedure 1300, the first transistor and the second transistor are switched off in response to the read word line signal and the read word line bar signal.

[0534] In step 1318 of procedure 1300, the read bit line is pre-charged to a second pre-charge voltage.

[0535] In some embodiments, the second pre-charge voltage is equal to 0.5 * VDD. Other pre-charge voltages are possible within the scope of this disclosure.

[0536] In step 1320 of procedure 1300, a write word line signal on a write word line is caused to change from the second logical value to the first logical value, thereby turning on a third transistor and a fourth transistor in response to the write word line signal.

[0537] In some embodiments, the third transistor includes the NFET transistor WPG1, and the fourth transistor includes the NFET transistor WPG2.

[0538] In some embodiments, the writing word line includes the writing word line WWL.

[0539] In step 1322 of procedure 1300, a write bit line strip signal is caused on a write bit line to switch from the first logical value to the second logical value.

[0540] In some embodiments, the write bit line includes the write bit line WBLB.

[0541] In step 1324 of procedure 1300, a signal from a first memory node of the memory cell is caused to change from the first logical value to the second logical value in response to the write bit line bar signal.

[0542] In some embodiments, the first storage node of the memory cell is the storage node NQB.

[0543] In step 1326 of procedure 1300, the write word line signal on the write word line is caused to change from the first logical value to the second logical value, thereby turning off the third transistor and the fourth transistor in response to the write word line signal.

[0544] In step 1328 of procedure 1300, the write bit line strip signal is caused to switch from the second logical value to the first logical value.

[0545] In process 1330 of procedure 1300, the read word line bar signal on the read word line bar is caused to change from the first logical value (high) to the second logical value (low).

[0546] In step 1332 of procedure 1300, the read word line signal on the read word line is caused to switch from the second logical value to the first logical value.

[0547] In step 1334 of procedure 1300, the first transistor and the second transistor are switched on in response to the read word line signal and the read word line bar signal.

[0548] In step 1336 of procedure 1300, the read bit line signal on the read bit line is caused to change from a third value to a fourth value in response to at least the first transistor or the second transistor being turned on.

[0549] In some embodiments, the third value is equal to 0.5 * VDD.

[0550] In some embodiments, the fourth value is equal to 0.6 * VDD.

[0551] Other values ​​for the third or fourth value fall within the scope of this revelation.

[0552] In operating procedure 1300, the circuit works in such a way that the advantages discussed here are achieved.

[0553] In some embodiments, one or more of the operations of Method 1300 are not performed. Furthermore, various PFET or NFET transistors shown in this disclosure are of a specific dopant type (e.g., N or P) and are for illustrative purposes only. The embodiments of the disclosure are not limited to a specific transistor type, and one or more of the PFET or NFET transistors shown in this disclosure may be replaced by a corresponding transistor of a different transistor / dopant type. Likewise, the low or high logic value of various signals used in the above description is for illustrative purposes only. Embodiments of the disclosure are not limited to a specific logic value when a signal is enabled and / or disabled. Selecting different logic values ​​is within the scope of various embodiments.The choice of a different number of transistors within the scope of this disclosure is within the scope of various embodiments.

[0554] One aspect of this description relates to a device. In some embodiments, the device is a multiport memory cell. In some embodiments, the device includes a cross-lock with a first memory node and a second memory node. In some embodiments, the device includes a first transistor of a first type, wherein the first transistor has a first gate extending in a first direction and located on a first plane. In some embodiments, the device includes a second transistor of a second type, which differs from the first type, and the second transistor includes a second gate on a second plane below the first plane. In some embodiments, the device includes a third transistor of a first type, which is coupled to the first memory node, wherein the third transistor includes a third gate on the first plane.In some embodiments, the device includes a fourth transistor of the second type coupled to the first memory node, the fourth transistor comprising a fourth gate on the second level. In some embodiments, the device includes a first read bit line extending in a second direction different from the first direction, the first read bit line being located on a first metal layer above a front face of a substrate and coupled to the third transistor and the fourth transistor. In some embodiments, the third transistor and the fourth transistor correspond to at least one first port of the device.

[0555] Another aspect of this description relates to a device. In some embodiments, the device is a multiport memory cell. In some embodiments, the device comprises a pair of inverters coupled to a first and a second memory node. In some embodiments, the device further comprises a first transistor stack on a substrate. In some embodiments, the first transistor stack comprises a first transistor of a first type, wherein the first transistor has a first gate extending in a first direction and located on a first plane. In some embodiments, the first transistor stack further comprises a second transistor of a second type, different from the first type, and the second transistor comprises a second gate extending in the first direction and located on a second plane below the first plane.In some embodiments, the device further comprises a second transistor stack on a substrate. In some embodiments, the second transistor stack comprises a third transistor of the first type coupled to the first memory node, the third transistor comprising a third gate extending in the first direction and located on the first plane. In some embodiments, the second transistor stack further comprises a fourth transistor of the second type coupled to the first memory node, the fourth transistor comprising a fourth gate extending in the first direction and located on the second plane.In some embodiments, the device further comprises a first conductor extending in a second direction different from the first direction, wherein the first conductor is located on a first metal layer above a front side of the substrate, is coupled to the third and fourth transistors, and is configured as a first read bit line. In some embodiments, the device further comprises a second conductor, configured as a second read bit line, extending in a second direction different from the first direction, wherein the second conductor is located on a second metal layer beneath a rear side of the substrate, is coupled to the third and fourth transistors, and wherein the second metal layer differs from the first metal layer.

[0556] Another aspect of this description relates to a method for fabricating a device. In some embodiments, the device is a multiport memory cell. In some embodiments, the method comprises fabricating a first set of transistors and a second set of transistors on a front face of a substrate, wherein the first set of transistors is stacked above the second set of transistors. In some embodiments, the method further comprises fabricating a first set of vias on the front face of the substrate, wherein the first set of vias is electrically coupled to at least the first set of transistors.In some embodiments, the method further comprises depositing a first conductive material on the front side of the substrate on a first metal plane, thereby forming a first set of conductors, wherein the first set of conductors is electrically coupled to at least the first set of transistors via the first set of vias, the first set of conductors comprising a first read word line and a first read bit line, the first set of transistors being configured to receive a first read word line signal on the first read word line and a first read bit line signal on the first read bit line from the front side. In some embodiments, the method further comprises performing the thinning on a rear side of the substrate opposite the front side.In some embodiments, the method further comprises fabricating a second set of conductors on the back side of the thinned substrate, wherein the second set of conductors is electrically coupled to at least the second set of transistors and embedded in the thinned substrate, located below the gates or active regions of at least the first set of transistors or the second set of transistors. In some embodiments, the method further comprises fabricating a second set of vias on the back side of the thinned substrate, wherein the second set of vias is electrically coupled to at least the second set of transistors.In some embodiments, the method further comprises depositing a second conductive material on the back side of the thinned substrate on a second metal plane, thereby forming a third set of conductors, wherein the third set of conductors is electrically coupled to at least the second set of transistors via the second set of vias, wherein the second set of conductors comprises a second read word line, and wherein the second set of transistors is configured to receive a second read word line signal on the second read word line.

[0557] The above describes elements of several embodiments so that those skilled in the field can better understand the aspects of this disclosure. Those skilled in the field should note that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as the embodiments introduced herein. They should also understand that such respective designs do not deviate from the spirit and scope of this disclosure and that they can make various changes, substitutions, and modifications to it without deviating from the spirit and scope of this disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 701,274

[0001]

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