Semiconductor module arrangement

Abstract

A semiconductor module arrangement comprises a housing with a first lateral side, a second lateral side opposite the first lateral side, a third lateral side perpendicular to the first lateral side and the second lateral side, and a fourth lateral side opposite the third lateral side, a first and a second substrate arranged in the housing such that the first substrate is located between the second substrate and the third lateral side, a first semiconductor element located on the first substrate, and a second semiconductor element located on the second substrate.The semiconductor module arrangement further comprises a first supply terminal, a second supply terminal and one or more output terminals arranged in a third section of the package located between the third lateral side and the fourth lateral side, wherein a distance between the third section of the package and the third lateral side is substantially equal to a distance between the third section of the package and the fourth lateral side.

Description

TECHNICAL AREA

[0001] This present disclosure relates to a semiconductor module arrangement. BACKGROUND

[0002] Document US 2020 / 0357711 A1 discloses a power semiconductor module arrangement comprising a first and a second switching element, each having a control terminal and a controllable load path between two load terminals, wherein the load paths are connected in series and operationally coupled between a first and a second supply node. The switching elements are interconnected via a first common node. An output node, configured for coupling to an output potential, is coupled to the first common node. The first supply node is formed by a plurality of first terminals, the second supply node by a plurality of second terminals, and the output node by a plurality of third terminals. The switching elements are arranged in a package.

[0003] The patent application US 2020 / 0388605A1 discloses a semiconductor substrate comprising a dielectric insulating layer and a structured metallization layer with at least five separate sections attached to the dielectric insulating layer, a first switching element with first emitter and collector terminals, a second switching element with second emitter and collector terminals, a first diode element with first anode and cathode terminals, and a second diode element with second anode and cathode terminals. The switching and diode elements are arranged on a first section of the metallization layer, with the collector and cathode terminals electrically connected to the first section. The first anode and emitter terminals are electrically connected to the second and third sections. The second anode and emitter are electrically connected to the fourth and fifth sections.The first section separates the second and fourth adjacent sections from the third and fifth adjacent sections.

[0004] German patent application DE 10 2023 110 888 A1 discloses a semiconductor module arrangement with a substrate having a metallization layer arranged on the surface of a dielectric insulating layer, wherein the metallization layer has a first, a second, a third, a fourth, a fifth, a sixth, and a seventh section. The semiconductor module arrangement also has a plurality of semiconductor bodies arranged on the metallization layer, forming a three-level neutral-point clamped type 1 (NPC1) converter or a three-level active-neutral-point clamped (ANPC) converter. The sections of the metallization layer are arranged and oriented on the dielectric insulating layer such that the semiconductor module arrangement is very compact and exhibits low leakage inductances and symmetrical currents.

[0005] Semiconductor module assemblies often contain at least one substrate housed in a package. A semiconductor assembly with multiple controllable semiconductor devices (e.g., two IGBTs in a half-bridge configuration) is mounted on each substrate of the at least one substrate. Each substrate typically has a substrate layer (e.g., a ceramic layer), a first metallization layer applied to one side of the substrate layer, and (optionally) a second metallization layer applied to the other side of the substrate layer. The controllable semiconductor devices are mounted, for example, on the first metallization layer. The second metallization layer may optionally be attached to a base plate. The controllable semiconductor devices are typically mounted on the substrate using soldering or sintering techniques.Electrical leads or connections are used to link different semiconductor devices within the semiconductor assembly. Furthermore, terminals are provided to connect the semiconductor assembly from outside the package. These terminals are typically electrically coupled to the first metallization layer at one end, while the other end protrudes from the package. The layout of the semiconductor module assembly, particularly the positioning of the terminals, can affect the switching characteristics, leakage inductance, and losses of the semiconductor assembly.

[0006] There is a need for a semiconductor module arrangement with improved switching characteristics and reduced stray inductance. OVERVIEW

[0007] A semiconductor module arrangement comprises a housing with a first lateral side, a second lateral side opposite the first lateral side, a third lateral side perpendicular to the first and second lateral sides, and a fourth lateral side opposite the third lateral side, a first substrate and a second substrate arranged in the housing such that the first substrate is located between the second substrate and the third lateral side, wherein each of the first and second substrates comprises a dielectric insulating layer and a first metallization layer arranged on a surface of the dielectric insulating layer, the first metallization layer comprising a first section and a second section, as well as a first semiconductor element arranged on the first substrate and a second semiconductor element arranged on the second substrate.wherein each of the first and second semiconductor elements comprises a first contact pad and a second contact pad, wherein the second contact pad of the first semiconductor element is electrically coupled to the first section of the first substrate and the second contact pad of the second semiconductor element is electrically coupled to the first section of the second substrate, the first contact pad of the first semiconductor element is electrically coupled to the second section of the first substrate and the first contact pad of the second semiconductor element is electrically coupled to the second section of the second substrate, wherein the semiconductor module arrangement further comprises a first supply terminal electrically coupled to the first section of the first substrate, a second supply terminal electrically coupled to the second section of the second substrate, and one or more output terminals,which are electrically coupled to the second section of the first substrate and the first section of the second substrate, wherein the first supply terminal, the second supply terminal and the one or more output terminals are arranged in a third section of the housing, which is located between the third lateral side and the fourth lateral side, wherein a distance between the third section of the housing and the third lateral side is substantially equal to a distance between the third section of the housing and the fourth lateral side.

[0008] The invention can be better understood with reference to the following drawings and description. The components in the figures are not necessarily to scale; rather, the focus is on illustrating the principles of the invention. Furthermore, the same reference numerals in the figures denote corresponding parts in the different views. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a cross-sectional view of a semiconductor module arrangement. Fig. Figure 2 schematically shows a circuit arrangement according to an example. Fig. Figure 3 schematically shows a top view of a semiconductor module arrangement according to embodiments of the disclosure. Fig. Figure 4 schematically shows a top view of a semiconductor module arrangement according to further embodiments of the disclosure. Fig. Figure 5 schematically shows a top view of a semiconductor module arrangement according to further embodiments of the disclosure. Fig. Figure 6 schematically shows a top view of a semiconductor module arrangement according to further embodiments of the disclosure. Fig. Figure 7 schematically shows a top view of a semiconductor module arrangement according to further embodiments of the disclosure. Fig. Figure 8 schematically shows a top view of a semiconductor module arrangement according to further embodiments of the disclosure. Fig. Figure 9 schematically shows a top view of a semiconductor module arrangement according to further embodiments of the disclosure. Fig. Figure 10 schematically shows a top view of a semiconductor module arrangement according to further embodiments of the disclosure. Fig. Figure 11 schematically shows a three-dimensional view of a housing of a semiconductor module arrangement according to embodiments of the disclosure. Fig. Figure 12 schematically shows a three-dimensional view of a housing of a semiconductor module arrangement according to further embodiments of the disclosure. Fig. Figure 13 schematically shows a three-dimensional view of a housing of a semiconductor module arrangement according to further embodiments of the disclosure. Fig. Figure 14 schematically shows a three-dimensional view of a housing of a semiconductor module arrangement according to further embodiments of the disclosure. Fig. Figure 15 schematically shows a three-dimensional view of a housing of a semiconductor module arrangement according to further embodiments of the disclosure. Fig. Figure 16 schematically shows a three-dimensional view of a housing of a semiconductor module arrangement according to further embodiments of the disclosure. Fig. Figure 17 schematically shows a three-dimensional view of a semiconductor module arrangement according to further embodiments of the disclosure. DETAILED DESCRIPTION

[0009] The following detailed description refers to the accompanying drawings. The drawings show specific examples in which the invention can be implemented. It is understood that the features and principles described in relation to the various examples can be combined with one another, unless expressly stated otherwise. In the description and in the claims, designations of certain elements as "first element," "second element," "third element," etc., are not to be understood as enumerative. Rather, such designations merely serve to name different "elements." That is to say, for example, that the presence of a "third element" does not require the presence of a "first element" and a "second element."An electrical conductor or electrical connection, as described here, can be a single electrically conductive element or at least two single electrically conductive elements connected in series and / or parallel. Electrical conductors and electrical connections can contain metal and / or semiconductor material and can be permanently electrically conductive (i.e., non-switchable). A semiconductor body, as described here, can be made of (doped) semiconductor material and can be a semiconductor chip or contained within a semiconductor chip. A semiconductor body has electrically connecting pads and contains at least one semiconductor element with electrodes.

[0010] Referring to Fig. Figure 1 is a schematic cross-sectional view of a semiconductor module arrangement 300. The semiconductor module arrangement 300 comprises a housing 37 and a substrate 310. The substrate 310 contains a dielectric insulating layer 311, a (structured) first metallization layer 3111 attached to the dielectric insulating layer 311, and a (structured) second metallization layer 3112 attached to the dielectric insulating layer 311. The dielectric insulating layer 311 is arranged between the first and second metallization layers 3111 and 3112.

[0011] Each of the first and second metallization layers 3111, 3112 can consist of or contain one of the following materials: copper, a copper alloy, aluminum, an aluminum alloy, or any other metal or alloy that remains solid during operation of the power semiconductor module assembly. The substrate 310 can be a ceramic substrate, that is, a substrate in which the dielectric insulating layer 311 is a ceramic, for example, a thin ceramic layer. The ceramic can consist of or contain one of the following materials: aluminum oxide, aluminum nitride, zirconium oxide, silicon nitride, boron nitride, or another dielectric ceramic. For example, the dielectric insulating layer 11 can consist of or contain one of the following materials: Al₂O₃, AlN, SiC, BeO, or Si₃N₄.The substrate 310 can be, for example, a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, or an active metal brazing (AMB) substrate. Furthermore, the substrate 310 can be an insulated metal substrate (IMS). An insulated metal substrate generally has a dielectric insulating layer 311, which comprises (filled) materials such as epoxy resin or polyimide. The material of the dielectric insulating layer 311 can, for example, be filled with ceramic particles. Such particles can be, for example, SiO2, Al2O3, AlN, or BN and can have a diameter between approximately 1 µm and approximately 50 µm. The substrate 310 can also be a conventional printed circuit board (PCB) with a non-ceramic dielectric insulating layer 311.For example, a non-ceramic dielectric insulating layer 311 may consist of or contain a cured resin.

[0012] The substrate 310 is arranged in a housing 37. In the Fig. In the example shown, the substrate 310 forms a base surface of the housing 37, while the housing 37 itself only has side walls and a cover. However, this is just one example. It is also possible that the housing 37 still has a base surface and the substrate 310 is arranged on the base surface and inside the housing 37. According to another example, the substrate 310 can be mounted on a base plate (not shown). In some semiconductor module assemblies 300, more than one substrate 310 is arranged on the base surface of a housing 37 or on a single base plate (not shown). The base plate can, for example, form a base surface of the housing 37.

[0013] One or more semiconductor bodies 320 can be arranged on the at least one substrate 310. Each of the semiconductor bodies 320 arranged on the at least one semiconductor substrate 310 can contain a diode, an IGBT (insulated-gate bipolar transistor), a MOSFET (metal-oxide-semiconductor field-effect transistor), a JFET (junction field-effect transistor), a HEMT (high-electron-mobility transistor), or another suitable controllable semiconductor element.

[0014] One or more semiconductor bodies 320 can form a semiconductor array on the substrate 310. In Fig. Figure 1 shows only two semiconductor bodies 320 as examples. The second metallization layer 3112 of the substrate 310 in Fig. 1 is a continuous layer. The first metallization layer 3111 is in the Fig. In the example shown, a structured layer is present. "Structured layer" means that the first metallization layer 3111 is not a continuous layer, but contains voids between different sections of the layer. Such voids are in Fig. Figure 1 is shown schematically. The first metallization layer 3111 in this example contains three different sections. However, this is only one example. In general, any other number of sections is possible. Different semiconductor bodies 320 can be mounted on the same or different sections of the first metallization layer 3111. Different sections of the first metallization layer 3111 may have no electrical connection or may be electrically connected to one or more other sections, for example, using bond wires 33. Electrical connections 33 may also include, for example, bond tapes, bonding plates, or busbars, to name just a few examples. The one or more semiconductor bodies 320 may be electrically and mechanically connected to the substrate 310 by an electrically conductive bonding layer 330.Such an electrically conductive bonding layer can be a solder layer, a layer of electrically conductive adhesive, or a layer of sintered metal powder, e.g., sintered silver powder.

[0015] According to other examples, it is also possible that the second metallization layer 3112 is a structured layer. It is also possible to omit the second metallization layer 3112 entirely.

[0016] The in Fig. The semiconductor module arrangement 300 shown in Figure 1 further includes terminal elements 34. The terminal elements 34 are electrically connected to the first metallization layer 3111 and establish an electrical connection between the interior and exterior of the housing 37. The terminal elements 34 can be electrically connected to the first metallization layer 3111 at a first end 341, while a second end 342 of the terminal elements 34 projects from the housing 37. The terminal elements 34 can be electrically contacted from the outside at their second end 342. A first portion of the terminal elements 34 can extend through the interior of the housing 37 in a substantially vertical direction y. The vertical direction y is a direction perpendicular to an upper surface of the substrate 310, the upper surface of the substrate 310 being a surface on which at least the semiconductor body 320 is mounted.The second ends 342 of the connecting elements 34 can be bent such that they extend in a first horizontal direction x, which runs parallel to the upper surface of the substrate 310. In this way, it may be easier to electrically contact the second ends 342 for some applications. The in . Fig. The connection elements 34 shown in Figure 1 are only examples. The connection elements 34 can be implemented in any other way and can be arranged at any location within the housing 37. For example, one or more connection elements 34 can be located near or adjacent to the side walls of the housing 37. It is also possible for the second ends 342 to extend completely in the vertical direction y instead of being bent in the first horizontal direction x. Any other suitable implementation is possible.

[0017] The semiconductor bodies 320 can each contain a chip pad metallization (not shown specifically), e.g., a source, drain, anode, cathode, or gate metallization. A chip pad metallization generally provides a contact surface for electrically connecting the semiconductor body 320. The chip pad metallization can, for example, electrically contact a compound layer 330, a terminal element 34, or an electrical connection 33. A chip pad metallization can, for example, consist of or contain a metal such as aluminum, copper, gold, or silver. The electrical connections 33 and the terminal elements 34 can, for example, also consist of or contain a metal such as copper, aluminum, gold, or silver.

[0018] Now referring to Fig. 2. The at least two semiconductor bodies 320 can, for example, be arranged in a half-bridge configuration. Fig. Figure 2 is a circuit diagram of an exemplary half-bridge arrangement. The half-bridge arrangement is designed to convert a DC voltage into an AC voltage. The AC voltage can, for example, be supplied to a load (not shown). The half-bridge arrangement is connected between a first supply node, which is configured to be operationally coupled to a first electrical potential DC+, and a second supply node, which is configured to be operationally coupled to a second electrical potential DC-. The first electrical potential DC+ can be a positive potential, and the second electrical potential DC- can be a negative potential, in order to supply a DC voltage via the first and second supply nodes. The first and second supply nodes form the inputs of the half-bridge arrangement.

[0019] The half-bridge can include a high-side switch S1 (first switch) and a low-side switch S2 (second switch) connected in series between the first and second supply nodes. The half-bridge configuration can be designed to drive a load (not specifically shown) at an output node of the half-bridge configuration. The load can be, for example, an inductive load. The output node is electrically connected to a common node between the high-side switch S1 and the low-side switch S2.

[0020] In the circuit arrangement of Fig. In Figure 2, each switch S1, S2 of the half-bridge arrangement is implemented as an IGBT (Insulated-Gate Bipolar Transistor). However, this is only one example. The switches S1, S2 could also be implemented, for example, as MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors), JFETs (Junction Field-Effect Transistors), HEMTs (High Electron Mobility Transistors), BJTs (Bipolar Junction Transistors), or any other type of controllable semiconductor device. Each of the switches S1, S2 can have an internal or external freewheeling diode D1, D2. According to another example, each of the switches S1, S2 has two or more separate switching elements that are electrically coupled in parallel (not shown specifically).

[0021] Each of the first switch S1 and the second switch S2 contains a control electrode and a controllable load path between a first load electrode and a second load electrode. The load paths of the first switch S1 and the second switch S2 are connected in series and coupled between the first supply node and the second supply node.

[0022] Several different connection ports can be provided to create the half-bridge arrangement according to the example of Fig. 2. To make electrical connections. For example, a first supply terminal 1 can be electrically connected to the first supply node, and a second supply terminal 4 can be electrically connected to the second supply node. A first control terminal 5 can be electrically connected to the control electrode of the first switch S1, and a second control terminal 6 can be electrically connected to the control electrode of the second switch S2. A first auxiliary emitter terminal 8 can be electrically connected to the second load electrode of the first switch S1, and a second auxiliary emitter terminal 10 can be electrically connected to the second load electrode of the second switch S1. A first collector terminal 7 can be electrically connected to the first load electrode of the first switch S1, and a second collector terminal 9 can be electrically connected to the first load electrode of the second switch S2.One or more output terminals 2, 3 can be electrically coupled to the output node of the half-bridge arrangement.

[0023] Auxiliary emitter terminals 8 and 10 can be provided, for example, to minimize potentially negative feedback effects on the gate-emitter voltage (gate-emitter voltage = voltage between the control electrode and the corresponding emitter terminal (second load electrode) of a switch S1 or S2). According to another example, the auxiliary emitter terminals 8 and 10 can be provided to detect an internal voltage drop between an emitter terminal and the respective auxiliary emitter terminals 8 and 10. A voltage drop might occur, for example, due to stray inductance at the moment the corresponding first or second switch S1 or S2 is turned on or off. The detected voltage drop can be used, for example, for fault detection.

[0024] Optionally, the arrangement can further include a temperature sensor, such as a negative temperature coefficient (NTC) thermistor, which has an input electrode and an output electrode. The temperature sensor can be configured to measure the temperature of the semiconductor module arrangement 300. The temperature sensor can be located at any suitable position in the arrangement. A first measuring terminal 11 can be electrically coupled to the input electrode, and a second measuring terminal 12 can be electrically coupled to the output electrode of the NTC.

[0025] In this way, multiple terminals can be provided to electrically contact a single half-bridge arrangement. In a semiconductor module arrangement 300, each of the individual terminals 1-10 or 1-12 can be implemented as a terminal element 34, as shown in relation to Fig. 1 described above. One or more terminals can be electrically coupled to the same section of the first metallization layer 311. For example, two or more terminals that are electrically coupled at the same electrical potential can be electrically coupled to the same section of the first metallization layer 311. However, this is only one example. It is also possible for two or more terminals that are electrically coupled at the same electrical potential to be electrically coupled to two or more different sections of the first metallization layer 311. Such sections can be electrically coupled to each other, for example, by means of bond wires, connecting plates, or busbars.

[0026] The layout of the semiconductor module arrangement, and in particular the position of the terminal elements 34 within the housing 37, can influence the switching behavior of the semiconductor arrangement. Therefore, the positions of the individual terminal elements 34 within the housing 37 can be selected to meet the creepage distance requirements and improve the switching behavior of the half-bridge arrangement.

[0027] Now, with reference to Fig. Figure 3 schematically illustrates a semiconductor module arrangement according to embodiments of the disclosure. The semiconductor module arrangement has a housing 37 comprising a first lateral side L1, a second lateral side L2 opposite the first lateral side L1, a third lateral side L3 perpendicular to the first lateral side L1 and to the second lateral side L2, and a fourth lateral side L4 opposite the third lateral side L3. Fig. The housing 37 is not specifically shown in Figure 3. The lateral sides L1, L2, L3, L4 are in Fig. 3 marked by arrows. The semiconductor module arrangement also includes a first substrate 310 A and a second substrate 310 B , which are arranged in the housing 37 such that the first substrate 310 A between the second substrate 310 B and the third lateral side L3 is arranged, wherein the first and second substrates 310 A , 310 B each a dielectric insulating layer 311 A , 311 B and one on a surface of the dielectric insulating layer 311 A , 311 B arranged first metallization layer 3111 A , 3111 B exhibits, wherein the first metallization layer is 3111 A , 3111 B a first section 3111 A1 , 3111 B1 , a second section 3111 A2 , 3111 B2and a third section 3111 A3 , 3111 B3 The semiconductor module arrangement further features a 310 on the first substrate. A first controllable semiconductor element arranged 22 A and one on the second substrate 310 B arranged second controllable semiconductor element 22 B on, wherein of the first and second controllable semiconductor element 22 A , 22 B Each has a first contact pad 2x1, a second contact pad and a third contact pad 2x3. The first controllable semiconductor element 22 A can form the first switch S1, as in Fig. 2 shown, and the second controllable semiconductor element 22 B can form the second switch S2. As described above, each of the first switch S1 and the second switch S2 can be formed by one or more controllable semiconductor elements 22 coupled in parallel to each other. Fig. Figure 3 schematically shows two controllable semiconductor elements 22 mounted on the first substrate 310 A are arranged and form the first switch S1, as well as two controllable semiconductor elements 22, which are located on the second substrate 310 B are arranged and form the second switch S2.

[0028] Further referring to Fig. 3 is the second contact pad of the first controllable semiconductor element 22 A with the first section 3111 A1 of the first substrate 310 A electrically coupled, and the second contact pad of the second controllable semiconductor element 22 B is with the first section 3111 B1 of the second substrate 310 B electrically coupled. The first contact pad 2 A1 of the first controllable semiconductor element 22 A is with the second section 3111 A2 of the first substrate 310 A electrically coupled, and the first contact pad 2 B1of the second controllable semiconductor element 22 B is with the second section 3111 B2 of the second substrate 310 B electrically coupled. The third contact pad 2 A3 of the first controllable semiconductor element 22 A is with the third section 3111 A3 of the first substrate 310 A electrically coupled, and the third contact pad 2 B3 of the second controllable semiconductor element 22 B is with the third section 3111 B3 of the second substrate 310 B electrically coupled.

[0029] At the in Fig. The arrangement shown in Figure 3 contains the controllable semiconductor elements 22. A , 22 B implemented as so-called vertical components, and the second contact pads of the two controllable semiconductor elements 22 A , 22 B are connected to the respective first sections 3111 by means of electrically conductive connecting layers A1 , 3111B1 electrically coupled and therefore in the top view of Fig. 3 not visible. Implementing the controllable semiconductor elements 22 A , 22 B However, vertical components are only one example. Instead, the components can also be implemented as so-called lateral components. In lateral components, all contact pads are arranged on a surface of the respective component that faces away from the respective substrate 310. If the controllable semiconductor elements 22 A , 22 B Implemented as lateral components, the second contact pads of the two controllable semiconductor elements 22 A , 22 B for example by means of one or more electrical connecting elements 33 (e.g. bond wires) with the respective first sections 3111 A1 , 3111 B1 be electrically coupled.

[0030] Still referring to Fig. 3 The semiconductor module arrangement 300 further has a first control terminal 5, which is connected to the third section 3111 A3 of the first substrate 310 A electrically coupled, a first auxiliary emitter connection 8, which is connected to the second section 3111 A2 of the first substrate 310 A electrically coupled, and a first collector connection 7, which is connected to the first section 3111 A1 of the first substrate 310 A electrically coupled, wherein the first control terminal 5, the first auxiliary emitter terminal 8, and the first collector terminal 7 are arranged in a first section of the housing 37 adjacent to the third lateral side L3. The first collector terminal 7 and the first auxiliary emitter terminal 8 can, for example, be located on additional sections of the first substrate 310 A be arranged. Electrical connections to the first section 3111 A1 and to the second section 3111 A2of the first substrate 310 A can be implemented, for example, by means of electrical connecting elements 33. However, other implementations are also possible. For example, the first collector terminal 7 and the first auxiliary emitter terminal 8 can be connected directly to the first section 3111. A1 or the second section 3111 A2 The semiconductor module arrangement 300 further comprises a second control terminal 6, which is connected to the third section 3111. B3 of the second substrate 310 B electrically coupled, a second auxiliary emitter connection 10, which is connected to the second section 3111 B2 of the second substrate 310 B electrically coupled, and a second collector connection 9, which is connected to the first section 3111 B1 of the second substrate 310 Belectrically coupled, wherein the second control terminal 6, the second auxiliary emitter terminal 10, and the second collector terminal 9 are arranged in a second section of the housing 37 adjacent to the fourth lateral side L4. The second collector terminal 9 and the second auxiliary emitter terminal 10 can, for example, be located on additional sections of the second substrate 310. B be arranged. Electrical connections to the first section 3111 B1 and the second section 3111 B2 of the second substrate 310 B can be implemented, for example, by means of electrical connecting elements 33. However, other implementations are also possible. For example, alternatively, the second collector terminal 9 and the second auxiliary emitter terminal 10 can be connected directly to the first section 3111. B1 or the second section 3111 B2The semiconductor module arrangement 300 further comprises a first supply connection 1, which is connected to the first section 3111. A1 of the first substrate 310 A electrically coupled, a second supply connection 4, which is connected to the second section 3111 B2 of the second substrate 310 B electrically coupled, and one or more output terminals 2 to 3, which are connected to the second section 3111 A2 of the first substrate 310 A and the first section 3111 B1 of the second substrate 310 B electrically coupled, wherein the first supply terminal 1, the second supply terminal 4 and the one or more output terminals 2, 3 are arranged in a third section of the housing 37, which is arranged between the first section and the second section.

[0031] That is, the main connections 1, 2, 3, 4 or power connections of both substrates 310 A, 310 B , which carry significant currents and voltages, are grouped together, all auxiliary and control connections 5, 7, 8 of the first substrate 310 A are grouped together, and all auxiliary and control ports 6, 9, 10 of the second substrate 310 B are grouped together, with the main connections 1, 2, 3, 4 between the auxiliary and control connections 5, 7, 8 of the first substrate 310 A and the auxiliary and control connections 6, 9, 10 of the second substrate 310 B are arranged.

[0032] This is also in Fig. Figure 9, which shows a schematic top view of a housing 37 of a semiconductor module arrangement 300, with the second ends of the terminals 1-10 protruding from the housing 37. In the arrangement of Fig. Figure 9 also shows the second ends of a first measuring connection 11 and a second measuring connection 12. The first and second measuring connections 11, 12 can, for example, be connected to the auxiliary and control connections 6, 9, 10 of the second substrate 310. B or with the auxiliary and control connections 5, 7, 8 of the first substrate 310 A be grouped.

[0033] According to some embodiments and as exemplified in Fig. As shown in Figure 9, the first control terminal 5 (e.g., at least the second end of the first control terminal 5), the first auxiliary emitter terminal 8 (e.g., at least the second end of the first auxiliary emitter terminal 8), and the first collector terminal 7 (e.g., at least the second end of the first collector terminal 7) can be arranged in a row and parallel to the third lateral side L3. Similarly, the second control terminal 6 (e.g., at least the second end of the second control terminal 6), the second auxiliary emitter terminal 10 (e.g., at least the second end of the second auxiliary emitter terminal 10), and the second collector terminal 9 (e.g., at least the second end of the second collector terminal 9) can be arranged in a row and parallel to the fourth lateral side L4.

[0034] According to alternative embodiments, the first control terminal 5 (e.g., at least the second end of the first control terminal 5), the first auxiliary emitter terminal 8 (e.g., at least the second end of the first auxiliary emitter terminal 8), and the first collector terminal 7 (e.g., at least the second end of the first collector terminal 7) can be arranged in a row and parallel to the first lateral side L1. Similarly, the second control terminal 6 (e.g., at least the second end of the second control terminal 6), the second auxiliary emitter terminal 10 (e.g., at least the second end of the second auxiliary emitter terminal 10), and the second collector terminal 9 (e.g., at least the second end of the second collector terminal 9) can be arranged in a row and parallel to the first lateral side L1. According to some embodiments, it is even possible for the first control terminal 5 (e.g.,at least the second end of the first control terminal 5), the first auxiliary emitter terminal 8 (e.g. at least the second end of the first auxiliary emitter terminal 8), the first collector terminal 7 (e.g. at least the second end of the first collector terminal 7), the second control terminal 6 (e.g. at least the second end of the second control terminal 6), the second auxiliary emitter terminal 10 (e.g. at least the second end of the second auxiliary emitter terminal 10) and the second collector terminal 9 (e.g. at least the second end of the second collector terminal 9) are all in the same row and parallel to, for example, the third lateral side L3 (see e.g. . Fig. 15) arranged. In general, the respective terminals can be arranged in any way with the respective section of the housing 37.

[0035] According to some embodiments and as in Fig. As shown schematically in Figure 9, the semiconductor module arrangement 300 has two output terminals 2, 3, wherein a second end of the first supply terminal 1, which is arranged outside the housing 37, and a second end of the second supply terminal 4, which is arranged outside the housing 37, are arranged in a row and parallel to the third and fourth lateral sides L3, L4, wherein the second ends of the two output terminals 2, 3 arranged outside the housing 37 are arranged in a row and parallel to the third and fourth lateral sides L3, L4, and the second end of the first supply terminal 1 and the second end of the second supply terminal 4 are arranged between the second ends of the two output terminals 2, 3 and the fourth lateral side L4.Alternatively, the second end of the first supply connection 1 and the second end of the second supply connection 4 can, for example, be arranged between the second ends of the two output connections 2, 3 and the third lateral side L3.

[0036] According to an alternative embodiment, the semiconductor module arrangement 300 has only one output terminal 2, wherein a second end of the first supply terminal 1, which is located outside the housing 37, a second end of the second supply terminal 4, which is located outside the housing 37, and a second end of the output terminal 2, which is located outside the housing 37, are arranged in a row and parallel to the first and second lateral sides L1, L2. This is shown in the Fig. 12, Fig. 13 and Fig. 14 schematically represented.

[0037] According to some embodiments, the second end of the second supply terminal 4 can be arranged between the second end of the output terminal 2 and the second end of the first supply terminal 1 (see e.g. Fig. 12). According to alternative embodiments, the second end of the first supply terminal 1 can be arranged between the second end of the second supply terminal 4 and the second end of the output terminal 2 (see, for example, Fig. 13). According to further alternative embodiments, the second end of the output terminal 2 can be arranged between the second end of the first supply terminal 1 and the second end of the second supply terminal 4 (see, e.g., Fig. 14).

[0038] The semiconductor module arrangement can have a single half-bridge, as for example in the Fig. 3 and Fig. 9 shown schematically. However, it is also possible that the semiconductor module arrangement has two or even more than two half-bridges. That is, according to some embodiments and as shown in Fig. As shown schematically in Figure 4, the semiconductor module arrangement 300 can also accommodate a third substrate 310. C and a fourth substrate 310 D , which are arranged in the housing 37 such that the third substrate 310 C between the fourth substrate 310 D and the third lateral side L3 and between the first substrate 310 A and the first lateral side L1 is arranged, and the fourth substrate 310 D between the second substrate 310 B and the first lateral side L1 is arranged, exhibiting the third and fourth substrates 310 C , 310 D each a dielectric insulating layer 311 C , 311 D and one on a surface of the dielectric insulating layer 311C , 311 D arranged first metallization layer 3111 C , 3111 D exhibits, wherein the first metallization layer is 3111 C , 3111 D a first section 3111 C1 , 3111 D1 , a second section 3111 C2 , 3111 D2 and a third section 3111 C3 , 3111 D3 The semiconductor module arrangement can further include a third controllable semiconductor element 22. C , which is on the third substrate 310 C is arranged, and a fourth controllable semiconductor element 22 D , which is on the fourth substrate 310 D is arranged, having, of the third and fourth controllable semiconductor element 22 C , 22 D Each has a first contact pad 2x1, a second contact pad and a third contact pad 2x3.

[0039] The second contact pad of the third controllable semiconductor element 22 Cis with the first section 3111 C1 of the third substrate 310 C electrically coupled, and the second contact pad of the fourth controllable semiconductor element 22 D is with the first section 3111 D1 of the fourth substrate 310 D electrically coupled. The first contact pad 2 C1 of the third controllable semiconductor element 22 C is with the second section 3111 C2 of the third substrate 310 C electrically coupled, and the first contact pad 2 D1 of the fourth controllable semiconductor element 22 D is with the second section 3111 D2 of the fourth substrate 310 D electrically coupled.

[0040] The semiconductor module arrangement 300 further includes an additional first supply terminal 1, which is connected to the first section 3111 C1 of the third substrate 310 Celectrically coupled, an additional second supply connection 4, which is connected to the second section 3111 D2 of the fourth substrate 310 D electrically coupled, and one or more additional output terminals 2, 3, which are connected to the second section 3111 C2 of the third substrate 310 C and the first section 3111 D1 of the fourth substrate 310 D electrically coupled, wherein the additional first supply terminal 1, the additional second supply terminal 4 and the one or more additional output terminals 2, 3 are arranged in the third section of the housing 37 and between the first lateral side L1 and the first supply terminal 1, the second supply terminal 4 and the one or more output terminals 2, 3.

[0041] That is, the first and second sections 3111 C1 , 3111 D1 , 3111 C2 , 3111 D2of the third and fourth substrates 310 C , 310 D are electrically contacted via individual connections. An electrical connection can be formed outside the housing 37 by electrically coupling the first supply terminal 1 with the additional first supply terminal 1, the second supply terminal 4 with the additional second supply terminal 4, or one or more output terminals 2, 3 with one or more additional output terminals 2, 3. There is no internal connection (e.g., by means of bond wires 33) between, for example, the first section 3111 A1 of the first substrate 310 A and the first section 3111 C1 of the third substrate 310 C or between the second section 3111 A2 of the first substrate 310 A and the second section 3111 C2 of the third substrate 310 CSimilarly, there is no internal connection (e.g., via bond wires 33) between, for example, the first section 3111 B1 of the second substrate 310 B and the first section 3111 D1 of the fourth substrate 310 D or between the second section 3111 B2 of the second substrate 310 B and the second section 3111 D2 of the fourth substrate 310 D Similarly, there are no additional electrical connections (e.g., bond wires) between the first substrate 310 A and the second substrate 310 B required. All electrical connections between the first substrate 310 A and the second substrate 310 B are provided via the first supply connection 1, the second supply connection 4, and one or more output connections 2, 3. The same applies to the third substrate 310. C and the fourth substrate 310 D .

[0042] At the in Fig. The 4 illustrated examples show the third substrate 310 C and the fourth substrate 310 D There are no separate auxiliary and control connections. The third contact pad 2 C3 of the third controllable semiconductor element 22 C can be done, for example, with the third section 3111 A3 of the first substrate 310 A be electrically coupled, and the third contact pad 2 D3 of the fourth controllable semiconductor element 22 D can be used with the third section 3111 B3 of the second substrate 310 B be electrically coupled. That is, internal connections (e.g. by means of bond wires 33) may be provided to connect the third 310 C and the fourth substrate 310 D with the respective auxiliary and control connections located on the first substrate 310 A or the second substrate 310 B are intended to be electrically coupled. In Fig. 4 are electrical connections that make up the third 310 C and the fourth substrate 310 D with the auxiliary connections 7, 8, 9, 10 on the first substrate 310 A or the second substrate 310 B Electrical coupling is not explicitly shown for clarity. (Referring to) Fig. However, alternatively, it is possible that the third substrate is 310. C and the fourth substrate 310 D They have separate control connections as well as separate auxiliary connections. That is to say, the third substrate 310 C can be (essentially) identical to the first substrate 310 A be, and the fourth substrate 310 D can be (essentially) identical to the second substrate 310 B be. This is also the case, for example, in Fig. 16 schematically represented.

[0043] For example, in the Fig. The half-bridge arrangements shown in Figures 2, 3 to 5, and 7 to 9 are, however, only a few of several examples. According to alternative embodiments, passive semiconductor elements such as diodes can be used instead of controllable semiconductor elements. This is shown schematically in Figure 2. Fig. Figure 6 illustrates this. That is, according to some embodiments, a semiconductor module arrangement 300 has a housing 37 having a first lateral side L1, a second lateral side L2 opposite the first lateral side L1, a third lateral side L3 perpendicular to the first lateral side L1 and the second lateral side L2, and a fourth lateral side L4 opposite the third lateral side L3. The semiconductor module arrangement 300 further comprises a first substrate 310 A and a second substrate 310 B , which are arranged in the housing 37 such that the first substrate 310 A between the second substrate 310 Band the third lateral side L3 is arranged, wherein the first and second substrates 310 A , 310 B each a dielectric insulating layer 311 A 311 B and one on a surface of the dielectric insulating layer 311 A , 311 B arranged first metallization layer 3111 A , 3111 B exhibits, wherein the first metallization layer is 3111 A , 3111 B a first section 3111 A1 , 3111 B1 and a second section 3111 A2 , 3111 B2 The semiconductor module arrangement 300 further comprises a first semiconductor element 22. A , which is on the first substrate 310 A is arranged, and a second semiconductor element 22 B , which is on the second substrate 310 B is arranged, on, wherein of the first and second semiconductor element 22 A , 22 BEach has a first contact pad 2x1 and a second contact pad. The second contact pad of the first semiconductor element 22 A is with the first section 3111 A1 of the first substrate 310 A electrically coupled, and the second contact pad of the second semiconductor element 22 B is with the first section 3111 B1 of the second substrate 310 B electrically coupled. The first contact pad 2 A1 of the first semiconductor element 22 A is with the second section 3111 A2 of the first substrate 310 A electrically coupled, and the first contact pad 2 B1 of the second semiconductor element 22 B is with the second section 3111 B2 of the second substrate 310 B electrically coupled. The semiconductor module arrangement 300 further comprises a first supply connection 1, which is connected to the first section 3111 A1 of the first substrate 310 Aelectrically coupled, a second supply connection 4, which is connected to the second section 3111 B2 of the second substrate 310 B electrically coupled, and one or more output terminals 2, 3, which are connected to the second section 3111 A2 of the first substrate 310 A and the first section 3111 B1 of the second substrate 310 B electrically coupled, wherein the first supply terminal 1, the second supply terminal 4 and the one or more output terminals 2, 3 are arranged in a third section of the housing 37, which is arranged between the third lateral side L3 and the fourth lateral side L4, wherein a distance between the third section of the housing 37 and the third lateral side L3 is substantially equal to a distance between the third section of the housing 37 and the fourth lateral side (L4).

[0044] When passive semiconductor elements, such as diodes, are used instead of controllable semiconductor elements, auxiliary terminals are generally not required. Therefore, in such cases, an arrangement may only have the main terminals. A semiconductor substrate 310 need not necessarily have a third section 31113 of the first metallization layer 3111 in this case. However, it is generally also possible for the substrates 310 to be implemented in the same way regardless of whether passive semiconductor components or controllable semiconductor elements are arranged on them. For example, if a passive semiconductor component is arranged on a substrate 310 that has a third section 31113, the third section 31113 may simply not be electrically contacted. Similarly, other sections, elements, or terminals may not be electrically contacted, even if they are provided as a standard feature on a substrate 310.For example, it is generally possible to have one or more arrangements, such as those relating to . Fig. 3 are described, with one or more arrangements as described in relation to Fig. 6 are described, to be combined in a single housing 37.

[0045] The in the Fig. 3 and Fig. The arrangements shown in the 6 diagrams are highly symmetrical. In these examples, the first substrate is 310 A and the second substrate 310 B , in particular the first and second sections 3111 A1 , 3111 A2 , 3111 B1 , 3111 B2 the respective first metallization layers are implemented in an (almost) symmetrical manner. The specific shape and arrangement of the first and second sections 3111 A1 , 3111 A2 , 3111 B1 , 3111 B2 , as in the Fig. 3 and Fig. Figure 6, however, is only one of several possible implementations. Referring to Fig. 7 is another possible implementation of the first and second sections 3111 A1 , 3111 A2 , 3111 B1 , 3111 B2 schematically represented. It is noted that a section of the first metallization layer 3111 x It can be formed by a single continuous section. This is the case, for example, in the Fig. 3, Fig. 4, Fig. 5 and Fig. 6 examples shown for the first and second sections 3111 A1 , 3111 B1 , 3111 A2 , 3111 B2 That is the case. However, it is also possible that a section of the first metallization layer 3111 x formed by two or more separate sections, which are electrically coupled to each other by means of one or more electrical connecting elements such as bond wires, bond strips, connecting plates or busbars. This is the case, for example, in the Fig. 7 shown example for the second sections 3111 A2 , 3111 B2 This is the case. Generally, many other different implementations (e.g., shapes, arrangements, etc.) are possible. In the case of the Fig. 3, Fig. 6 and Fig. The first substrate 310 is shown in the 7 examples. A and the second substrate 310 B to a high degree identical. According to some examples, the first substrate can be 310 A and the second substrate 310 B essentially symmetrical with respect to an axis of symmetry that extends between the first substrate 310 A and the second substrate 310 B and extends parallel to the third and fourth long sides L3, L4.

[0046] However, it is not absolutely necessary that the first substrate be 310 A and the second substrate 310 B are symmetrical to each other. Referring to Fig. 8. It is also possible that the first substrate is 310. A and the second substrate 310 B are implemented in different ways. For example, in the Fig. In the embodiment shown in section 8, the first substrate 310 A according to the example of Fig. 3 implemented, while the second substrate 310 B according to the example of Fig. 7 is implemented. From the first substrate 310 A and the second substrate 310 B However, each can also be implemented in any other suitable way.

[0047] According to some embodiments, at least one section of the first section may be 3111 A1 and of the second section 3111 A2 of the first substrate 310 A along one side of the first substrate 310 A , which corresponds to the second substrate 310 B is facing, extend. Similarly, at least one section of the first section 3111 may B1and of the second section 3111 B2 of the second substrate 310 B along one side of the second substrate 310 B , which corresponds to the first substrate 310 A This allows the first supply connection 1, the second supply connection 4 and one or more output connections 2, 3 to be arranged centrally between the third longitudinal side L3 and the fourth longitudinal side L4.

[0048] Now, with reference to Fig. Figure 10 schematically shows a top view of a semiconductor module arrangement according to further embodiments of the disclosure. In this example, the semiconductor module arrangement has the first, second, third, and fourth substrates as described above, as well as additional fifth and sixth substrates. The first metallization layers and the (controllable) semiconductor elements are not shown in detail in the figure for the sake of clarity. Electrical connections between the different substrates (e.g., for electrically connecting the different substrates to the auxiliary and control terminals provided on the first substrate and the second substrate, respectively) are shown in Fig. Figure 10 is shown schematically only. As described above, no electrical connections are provided between the different substrates with respect to the main terminals. That is, for each pair of substrates, individual first supply terminals (1), second supply terminals (4), and output terminals (2, 3) are provided. As described above, the first and second substrates form a pair, and the third and fourth substrates form a pair. Similarly, the fifth and sixth substrates form a pair.

[0049] Fig. Figure 11 schematically shows a three-dimensional view of a housing 37 of a semiconductor module arrangement according to some embodiments of the disclosure. As described above and in Fig. As shown schematically in Figure 11, the semiconductor module arrangement can have two output terminals 2, 3, wherein a second end of the first supply terminal 1, which is arranged outside the housing 37, and a second end of the second supply terminal 4, which is arranged outside the housing 37, are arranged in a row and parallel to the third and fourth lateral sides L3, L4, wherein the second ends of the two arranged output terminals 2, 3, which are arranged outside the housing 37, are arranged in a row and parallel to the third and fourth lateral sides L3, L4, and the second end of the first supply terminal 1 and the second end of the second supply terminal 4 are arranged between the second ends of the two output terminals 2, 3 and the fourth lateral side L4.This arrangement of the second ends of the respective main terminals can be the same for each pair of substrates included in the semiconductor module arrangement.

[0050] As mentioned above, according to alternative embodiments, the semiconductor module arrangement can have only one output terminal 2, wherein a second end of the first supply terminal 1, which is located outside the housing 37, a second end of the second supply terminal 4, which is located outside the housing 37, and a second end of the output terminal 2, which is located outside the housing 37, are arranged in a row and parallel to the first and second lateral sides L1, L2.

[0051] Fig. Figure 12 schematically shows a three-dimensional view of a housing for a semiconductor module assembly according to further embodiments of the disclosure. In this embodiment, the second end of the second supply terminal 4 can be arranged between the second end of the output terminal 2 and the second end of the first supply terminal 1. This arrangement of the second ends of the respective main terminals can be the same for each pair of substrates contained in the semiconductor module assembly. Fig. Figure 13 schematically shows a three-dimensional view of a housing for a semiconductor module assembly according to further embodiments of the disclosure. In this embodiment, the second end of the first supply terminal 1 can be arranged between the second end of the second supply terminal 4 and the second end of the output terminal 2. This arrangement of the second ends of the respective main terminals can be the same for each pair of substrates contained in the semiconductor module assembly. Fig. Figure 14 schematically shows a three-dimensional view of a housing for a semiconductor module assembly according to further embodiments of the disclosure. In this embodiment, the second end of the output terminal 2 can be arranged between the second end of the first supply terminal 1 and the second end of the second supply terminal 4. This arrangement of the second ends of the respective main terminals can be the same for each pair of substrates contained in the semiconductor module assembly.

[0052] Fig. Figure 15 schematically shows a three-dimensional view of a housing 37 of a semiconductor module arrangement according to yet another embodiment of the disclosure. In this embodiment, all auxiliary connections are arranged in one and the same row along the third longitudinal side L3 of the housing 37. Fig. Figure 16 schematically shows a three-dimensional view of a housing 37 of a semiconductor module arrangement according to yet another embodiment of the disclosure. In this embodiment, auxiliary connections are provided for each pair of substrates, similar to what is described in relation to Fig. 5 was described.

[0053] Fig. Figure 17 schematically shows a three-dimensional view of a semiconductor module arrangement according to further embodiments of the disclosure. In this example, possible implementations of the various connections are schematically represented. The different substrates, as well as the different sections of the respective first metallization layers and the controllable semiconductor elements, are shown in Fig. 17 are visible. For clarity, in Fig. 17 no bond wires or other internal electrical connections shown.

[0054] The semiconductor module arrangements according to the various embodiments described here fulfill several different requirements. For example, the semiconductor module arrangement according to the various examples described here exhibits a comparatively low leakage inductance. For instance, the leakage inductance is reduced by arranging one or more output terminals 2, 3, as well as the first supply terminal 1 and the second supply terminal 2, centrally between the third longitudinal side L3 and the fourth longitudinal side L4. Furthermore, a highly symmetrical switching behavior between the low-side and high-side can be achieved using the semiconductor module arrangements described here. The total losses in the semiconductor module arrangement described here are also comparatively low.

Claims

[1] Semiconductor module arrangement (300) comprising: a housing (37) having a first lateral side (L1), a second lateral side (L2) opposite the first lateral side (L1), a third lateral side (L3) perpendicular to the first lateral side (L1) and the second lateral side (L2), and a fourth lateral side (L4) opposite the third lateral side (L3), a first substrate (310 A ) and a second substrate (310 B ), which are arranged in the housing (37) such that the first substrate (310 A ) between the second substrate (310 B ) and the third lateral side (L3), wherein the first and second substrates (310 A , 310 B ) each a dielectric insulating layer (311 A , 311 B ) and one on a surface of the dielectric insulating layer (311 A , 311 B ) arranged first metallization layer (3111 A, 3111 B ) exhibits, wherein the first metallization layer (3111 A , 3111 B ) a first section (3111 A1 , 3111 B1 ) and a second section (3111 A2 , 3111 B2 ) exhibits, and a first semiconductor element (22 A ), which is on the first substrate (310 A ) is arranged, and a second semiconductor element (22 B ), which is on the second substrate (310 B ) is arranged, wherein the first and second semiconductor elements (22 A , 22 B ) each has a first contact pad (2x1) and a second contact pad, wherein the second contact pad of the first semiconductor element (22 A ) with the first section (3111 A1 ) of the first substrate (310 A ) is electrically coupled and the second contact pad of the second semiconductor element (22 B ) with the first section (3111 B1 ) of the second substrate (310B ) is electrically coupled, the first contact pad (2 A1 ) of the first semiconductor element (22 A ) with the second section (3111 A2 ) of the first substrate (310 A ) is electrically coupled and the first contact pad (2 B1 ) of the second semiconductor element (22 B ) with the second section (3111 B2 ) of the second substrate (310 B ) is electrically coupled, the semiconductor module arrangement (300) further a first supply connection (1) which is connected to the first section (3111 A1 ) of the first substrate (310 A ) is electrically coupled, a second supply connection (4) which is connected to the second section (3111 B2 ) of the second substrate (310 B ) is electrically coupled, and one or more output terminals (2, 3) connected to the second section (3111 A2 ) of the first substrate (310 A ) and the first section (3111B1 ) of the second substrate (310 B ) are electrically coupled, wherein the first supply terminal (1), the second supply terminal (4) and the one or more output terminals (2, 3) are arranged in a third section of the housing (37) which is located between the third lateral side (L3) and the fourth lateral side (L4), wherein a distance between the third section of the housing (37) and the third lateral side (L3) is substantially equal to a distance between the third section of the housing (37) and the fourth lateral side (L4). [2] Semiconductor module arrangement (300) according to claim 1, wherein the first metallization layer (3111 A , 3111 B ) of each of the first substrate (310 A ) and the second substrate (310 B ) further a third section (3111 A3 , 3111 B3 ) exhibits; the first semiconductor element (22A ) is a controllable semiconductor element and also a third contact pad (2 A3 ) exhibits; the second semiconductor element (22 B ) is a controllable semiconductor element and also a third contact pad (2 B3 ) exhibits; the third contact pad (2 A3 ) of the first controllable semiconductor element (22 A ) with the third section (3111 A3 ) of the first substrate (310 A ) is electrically coupled and the third contact pad (2 B3 ) of the second controllable semiconductor element (22 B ) with the third section (3111 B3 ) of the second substrate (310 B ) is electrically coupled; and the semiconductor module arrangement (300) continues to have: a first control connection (5) which is connected to the third section (3111 A3 ) of the first substrate (310 A) is electrically coupled, a first auxiliary emitter connection (8) which is connected to the second section (3111 A2 ) of the first substrate (310 A ) is electrically coupled, and a first collector connection (7) connected to the first section (3111 A1 ) of the first substrate (310 A ) is electrically coupled, wherein the first control terminal (5), the first auxiliary emitter terminal (8) and the first collector terminal (7) are arranged in a first section of the housing (37) between the third section and the third lateral side (L3), a second control terminal (6) connected to the third section (3111 B3 ) of the second substrate (310 B ) is electrically coupled, a second auxiliary emitter connection (10) which is connected to the second section (3111 B2 ) of the second substrate (310 B ) is electrically coupled, and a second collector connection (9) which is connected to the first section (3111 B1) of the second substrate (310 B ) is electrically coupled, wherein the second control terminal (6), the second auxiliary emitter terminal (10) and the second collector terminal (9) are arranged in the first section of the housing (37) or in a second section of the housing (37) between the third section and the fourth lateral side (L4). [3] Semiconductor module arrangement (300) according to claim 2, wherein the first control terminal (5), the first auxiliary emitter terminal (8) and the first collector terminal (7) are arranged in a series and parallel to the third lateral side (L3). [4] Semiconductor module arrangement (300) according to claim 2 or 3, wherein the second control terminal (6), the second auxiliary emitter terminal (10) and the second collector terminal (9) are arranged in a row and parallel to the fourth lateral side (L4). [5] Semiconductor module arrangement (300) according to one of claims 1 to 4, comprising two output terminals (2, 3), wherein a second end of the first supply terminal (1), which is arranged outside the housing (37), and a second end of the second supply terminal (4), which is arranged outside the housing (37), are arranged in a row and parallel to the third and fourth lateral sides (L3, L4), second ends of the two output terminals (2, 3), which are located outside the housing (37), are arranged in a row and parallel to the third and fourth lateral sides (L3, L4), and the second end of the first supply connection (1) and the second end of the second supply connection (4) are arranged between the second ends of the two output connections (2, 3) and the fourth lateral side (L4). [6] Semiconductor module arrangement (300) according to any one of claims 1 to 4, comprising an output terminal (2), wherein a second end of the first supply terminal (1) which is arranged outside the housing (37), a second end of the second supply terminal (4) which is arranged outside the housing (37), and a second end of the output terminal (2) which is arranged outside the housing (37) are arranged in a row and parallel to the first and second lateral side (L1, L2). [7] Semiconductor module arrangement (300) according to claim 6, wherein the second end of the second supply terminal (4) is arranged between the second end of the output terminal (2) and the second end of the first supply terminal (1). [8] Semiconductor module arrangement (300) according to claim 6, wherein the second end of the first supply terminal (1) is arranged between the second end of the second supply terminal (4) and the second end of the output terminal (2). [9] Semiconductor module arrangement (300) according to claim 6, wherein the second end of the output terminal (2) is arranged between the second end of the first supply terminal (1) and the second end of the second supply terminal (4). [10] Semiconductor module arrangement (300) according to one of the preceding claims, further comprising a third substrate (310 C ) and a fourth substrate (310 D ), which are arranged in the housing (37) such that the third substrate (310 C ) between the fourth substrate (310 D ) and the third lateral side (L3) and between the first substrate (310 A) and the first lateral side (L1) and the fourth substrate (310 D ) between the second substrate (310 B ) and the first lateral side (L1), with the third and fourth substrates (310 C , 310 D ) each a dielectric insulating layer (311 C , 311 D ) and one on a surface of the dielectric insulating layer (311 C , 311 D ) arranged first metallization layer (3111 C , 3111 D ) exhibits, wherein the first metallization layer (3111 C , 3111 D ) a first section (3111 C1 , 3111 D1 ) and a second section (3111 C2 , 3111 D2 ) exhibits, and a third semiconductor element (22 C ), which is based on the third substrate (310 C ) is arranged, and a fourth semiconductor element (22 D ), which is based on the fourth substrate (310 D) is arranged, wherein the third and fourth controllable semiconductor elements (22 C , 22 D ) each has a first contact pad (2x1) and a second contact pad, wherein the second contact pad of the third semiconductor element (22 C ) with the first section (3111 C1 ) of the third substrate (310 C ) is electrically coupled and the second contact pad of the fourth semiconductor element (22 D ) with the first section (3111 D1 ) of the fourth substrate (310 D ) is electrically coupled, the first contact pad (2 C1 ) of the third semiconductor element (22 C ) with the second section (3111 C2 ) of the third substrate (310 C ) is electrically coupled and the first contact pad (2 D1 ) of the fourth semiconductor element (22 D ) with the second section (3111 D2 ) of the fourth substrate (310 D ) is electrically coupled, the semiconductor module arrangement (300) further an additional first supply connection (1) connected to the first section (3111 C1 ) of the third substrate (310 C ) is electrically coupled, an additional second supply connection (4) which is connected to the second section (3111 D2 ) of the fourth substrate (310 D ) is electrically coupled, and one or more additional output terminals (2, 3) connected to the second section (3111 C2 ) of the third substrate (310 C ) and the first section (3111 D1 ) of the fourth substrate (310 D) are coupled, wherein the additional first supply terminal (1), the additional electrical second supply terminal (4) and the one or more additional output terminals (2, 3) are arranged in the third section of the housing (37) and between the first lateral side (L1) and the first supply terminal (1), the second supply terminal (4) and the one or more output terminals (2, 3). [11] Semiconductor module arrangement (300) according to claim 10, wherein the third semiconductor element (22 C ) is a controllable semiconductor element and also a third contact pad (2 C3 ) exhibits; the fourth semiconductor element (22 D ) is a controllable semiconductor element and also a third contact pad (2 D3 ) exhibits; and the third contact pad (2 C3 ) of the third controllable semiconductor element (22 C ) with the third section (3111 A3) of the first substrate (310 A ) is electrically coupled and the third contact pad (2 D3 ) of the fourth controllable semiconductor element (22 D ) with the third section (3111 B3 ) of the second substrate (310 B ) is electrically coupled. [12] Semiconductor module arrangement (300) according to one of the preceding claims, wherein the first and second semiconductor element (22) A , 22 B ) each has at least one diode, at least one IGBT, at least one MOSFET, at least one JFET or at least one HEMT.

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