Circuit for converting an analog signal into spike trains, computing unit with a neuromorphic chip and vehicle

Abstract

The invention relates to a circuit (1) for converting an analog signal (2) into spike trains (3) for processing by a pulsed neural network (SNN), comprising a signal input (4) for receiving the analog signal (2) and a signal output (6) subdivided into at least two output lines (5) for outputting the spike trains (3), characterized by the following components: - a comparator layer (7) comprising at least two comparators (8), each comparator (8) being configured to read the analog signal (2) and compare it with a comparator-specific threshold (9) and output a signal if the analog signal (2) exceeds the respective threshold (9); and - a logic gate layer (10) comprising an arrangement of gate elements for reading and combining the output signals of the comparators (8) such that the output signals of the comparators (8) are distributed to the output lines (5) of the signal output (6) to form the spike trains (3) such that each output line (5) is assigned a specific amplitude range (11) of the analog signal (2).

Description

[0001] The invention relates to a circuit for converting an analog signal into spike trains of the type defined in more detail in the preamble of claim 1, a computing unit with such a circuit and a vehicle with such a circuit or computing unit.

[0002] Pulsed neural networks, also known as "spiking neural networks" (SSNs), are a type of artificial neural network whose operating principle is modeled on the workings of a biological brain. Information is propagated through the network in the form of so-called spike trains. The neurons in a pulsed neural network exhibit a membrane potential that increases in response to incoming impulses, or "spikes." Once the membrane potential exceeds a defined threshold, the respective neuron fires its own impulse. This impulse is then passed on through the network to downstream neurons.

[0003] Neurons can fire at any time, regularly, or in bursts. The best-known strategies for encoding information are frequency coding, time coding, interspike interval coding, and population coding. Various mechanisms exist for controlling neuronal firing. The integrate-and-fire model, the leaky integrate-and-fire model, the Izhikevich model, and the spike response model have proven particularly effective. In the integrate-and-fire model, a neuron collects input signals and integrates them over time. As soon as the membrane potential reaches a defined threshold, the neuron fires, thus emitting the aforementioned impulse or spike. Afterward, the membrane potential returns to a resting value. In the leaky integrate-and-fire model, however, the membrane potential decays over time if no new impulses are received.One possible way to implement this concept is so-called voltage thresholding. In this process, an electrical input signal in the form of a voltage is converted into discrete spikes.

[0004] The processing of vehicle sensor data using artificial intelligence is already well-established. Various sensor systems output analog signals, i.e., continuous-time signals. Measures are required to enable the processing of these analog signals by a pulsed neural network. This involves converting the corresponding continuous-time signals into discrete spike trains. This presents a complex technical challenge.

[0005] An analog signal is continuous and variable, while spike trains consist of temporally discrete events. The challenge lies in developing suitable mechanisms that allow the analog signal to be precisely discretized and transformed into a form optimally suited for downstream neuromorphic processing. It is essential to ensure that the vital information content of the original signal is preserved, as an insufficient or faulty transformation can lead to information loss or distortion.

[0006] A key challenge is preserving information content during discretization. The conversion process must be designed to adequately represent important details of the continuous signal in the spike trains. An insufficiently optimized spike train can lead to the inadequate capture of essential signal characteristics, impairing the efficiency and accuracy of subsequent processing steps. Furthermore, directly converting a continuous signal without dynamic adjustment often results in uneven firing rates in the resulting spike trains. In analog neural circuits, there is a risk that individual neurons will be over- or under-activated, leading to an uneven distribution of spikes. This asymmetry can reduce the efficiency of signal processing and disrupt the flow of information within neuromorphic systems.

[0007] Another problem arises from the dynamic nature of many analog input signals. Such signals exhibit time-varying amplitudes and frequencies, which often renders static thresholds insufficient to adequately capture the full range of signal variability. Without adaptive mechanisms to adjust the thresholds, there is a risk that parts of the signal will be either overrepresented or underrepresented, leading to distortion in the spike train.

[0008] The real-time requirements of signal conversion are also a critical factor. In many applications, the conversion of analog signals to spike trains must occur in real time, placing high demands on the speed and responsiveness of the conversion process. Any delay or lack of adaptability during this phase can negatively impact overall system performance.

[0009] WO 2024 / 023111 A1 discloses a system and method for efficient feature-centric analog-to-spike encoders. The publication describes a signal processing circuit capable of converting an analog signal into a spike train. Before the analog signal is converted into the spike train, it is modulated, which is then converted into an error signal, and finally into an output signal. The modulated signal represents one or more features contained in the analog signal. The modulated signal is compared to a reference signal, with the error signal representing a deviation between the modulated signal and the reference signal. Depending on the presence of one or more features in the modulated signal, the output signal is generated using a locked-loop circuit. The analog signal can be represented by a voltage value.The signal processing circuit can include other common components such as amplifiers, filters, and the like. A feedback loop can also be implemented in the circuit. The characteristics detected in the analog signal can be based on delay, frequency, and phase.

[0010] Furthermore, US Patent 2022 / 0216879 A1 describes a system and associated method for analog-to-digital signal conversion, comprising an analog-to-digital converter, a digital-to-analog converter, and an amplifier. Analog input signals are read by the analog-to-digital converter, reference signals are generated by a digital-to-analog converter, and an error signal containing the difference between the analog input signal and the reference signal is amplified by the amplifier. Additionally, the system includes a level-transition-based sampling circuit comprising a first comparator that compares the error signal to a first reference level and a second comparator that compares the error signal to a second reference level, thereby generating event-based reset signals corresponding to a multitude of samples to reset the digital-to-analog converter.In addition, the system has a trigger circuit configured to generate reset signals asynchronously to the event-based reset signals.

[0011] The present invention aims to provide means for the efficient encoding and processing of information while maximizing the information content of spike trains for pulsed neural networks. A further objective of the invention is to provide means for the efficient and reliable processing of sensor data in a vehicle.

[0012] According to the invention, this problem is solved by a circuit for converting an analog signal into spike trains with the features of claim 1, a computing unit with such a circuit, and a vehicle with such a circuit or computing unit. Advantageous embodiments and further developments are described in the dependent claims.

[0013] A generic circuit for converting an analog signal into spike trains for processing by a pulsed neural network, comprising a signal input for receiving the analog signal and a signal output subdivided into at least two output lines for outputting the spike trains, according to the invention has the following components: - a comparator layer comprising at least two comparators, each comparator being configured to read the analog signal and compare it with a comparator-specific threshold and output a signal if the analog signal exceeds the respective threshold; and - a logic gate layer comprising an arrangement of gate elements for reading and combining the output signals of the comparators, such that the output signals of the comparators are distributed to the output lines of the signal output to form the spike trains, such that each output line is assigned a specific amplitude range of the analog signal.

[0014] The circuit according to the invention thus represents a hardware component that encodes the different amplitude ranges of the analog signal into multiple spike trains based on population coding. The circuit according to the invention can be implemented as an electrical or electronic circuit, as an integrated circuit, or as a system-on-a-chip, and can be integrated into an embedded system, also referred to as an "embedded system".

[0015] The analog signal is a continuous-time signal and can be efficiently and effectively discretized into spike trains using the circuit according to the invention. In particular, the analog signal can have a value from 0 to 1. The amplitude can therefore fluctuate in the range of 0 to 1. Any desired amplitude value can be scaled using suitable upstream circuit elements, such as operational amplifiers, voltage dividers, microcontrollers, or the like. Thus, an amplitude range of, for example, -15 to 64 can be mapped to 0 to 1. In particular, the analog signal is a voltage signal.

[0016] The circuit comprises at least two comparators. Each comparator has its own threshold value. Therefore, the same threshold value is not applied to multiple comparators simultaneously. As soon as the analog signal reaches a certain level, those comparators whose threshold values ​​are exceeded output a signal. For example, if there are three comparators with threshold values ​​of 0.2, 0.4, and 0.9, and the analog signal is currently at 0.5, the first and second comparators will each output their respective signals, while the third comparator will not. The reverse scenario is also conceivable: the output signal is triggered when the signal falls below the threshold value. However, for consistency, the rest of this document will always refer to "exceeding" the threshold.The expert understands that the amplitude ranges of the analog signal can be seamlessly subdivided by the respective threshold values ​​of neighboring comparators.

[0017] The circuit according to the invention is characterized by n comparators or n output lines. "n" corresponds to any natural number equal to or greater than two. The analog signal can thus be subdivided into n amplitude ranges. These amplitude ranges can be of equal or different amplitudes, their size being determined by the respective comparator-specific threshold. Depending on the perspective, the upper or lower limit of the assigned amplitude range of the analog signal is thus determined by the comparator's own threshold and the threshold of the adjacent comparator.

[0018] Each comparator has an assigned output line. The input neurons of a downstream SNN can be connected to these output lines. The logic gate layer ensures that, with a relatively high analog signal, a spike is not output on all output lines, but only on the output line where the analog signal's amplitude falls within the range specified by the comparator-specific thresholds. The point at which a spike is generated is the point at which the analog signal reaches or crosses the threshold between two adjacent comparators. Referring back to the previous example, a spike would therefore be output via the output line assigned to the second comparator if the output signal, rising from the range between 0.2 and 0.4, reaches or exceeds the value 0.4.

[0019] Preferably, the comparator thresholds are chosen such that the entire amplitude range of the analog signal is covered. It is therefore possible to consider only parts of the analog signal, or its entire range.

[0020] The threshold values ​​are particularly preferably distributed equidistantly.

[0021] A further advantageous embodiment of the circuit according to the invention provides that the comparator-specific thresholds can be dynamically adjusted depending on the number of spikes in the spike train generated by the specific comparator. By adjusting the comparator thresholds, the firing rate of the neurons, and thus the distribution of spikes in the respective spike trains, can be influenced. This can be used to achieve a particularly uniform firing of the neurons. This allows for particularly efficient encoding of the analog signal. The uniform firing rate maximizes the information content of the spike train, since all neurons are active with equal frequency and optimally utilize their potential.

[0022] This leads to optimal signal representation and improves the performance of downstream neuromorphic processing stages.

[0023] Signal processing in hardware is performed in parallel, enabling the circuit according to the invention to operate with constant time complexity. The duration of individual operations is independent of the size of the input data or the number of neurons. In particular, the fundamental operations—signal comparison, logic operations, integration, and threshold adjustment—exhibit a constant time complexity of O(1). These properties ensure a fast and efficient conversion of continuous-time signals into optimized spike trains with minimal latency.

[0024] According to an advantageous embodiment of the circuit according to the invention, a respective threshold can be raised if the number of spikes in the spike train generated by the specific comparator exceeds a defined threshold, and lowered if the number of spikes falls below the defined threshold. The number of spikes in a given spike train is a measure of the respective neuronal activity. Since spikes are output over time, the term "number" in this context can also be understood as "density," i.e., as number / time window. This allows both over- and under-excited neurons to be identified and their respective thresholds to be adjusted. This ensures uniform neuronal activity, as described above.Dynamic threshold adjustment is performed, enabling the circuit according to the invention to react in real time to changes in the analog signal or internal imbalances. This increases the information flow. The influence of prior manual calibration, i.e., manually setting the initial threshold values ​​of the comparators, can be reduced. The circuit according to the invention can thus calibrate itself depending on the incoming analog signal.

[0025] An advantageous embodiment of the circuit according to the invention is further characterized by a feedback layer for implementing the dynamic adaptability of the comparator-specific thresholds, comprising the following components connected in series in a feedback loop for each output line: optionally an inductor, a parallel circuit consisting of an operational amplifier and a capacitor, a comparator, and optionally a resistor, wherein the input of the feedback loop is connected to one of the outputs of the logic gate layer and the output of the feedback loop is connected to an input of the comparator associated with the respective logic gate layer. Thus, a specific hardware embodiment for realizing the mechanisms described above is specified.

[0026] Each neuron A iEach output line is connected to an integrator that sums the number of triggered spikes. An operational amplifier acts as the integrator and transfers a fixed charge to a feedback capacitor with each spike. The resulting voltage V int,i The voltage increases proportionally to the number of spikes. This voltage is continuously compared to a fixed reference value to dynamically adjust the associated threshold Ti. If V exceeds the threshold, the voltage must be adjusted accordingly. int,i The reference value is increased; if V int,i Below this level, Ti is reduced. In this way, the closed feedback loop regulates the firing rates of the neurons so that they fire evenly on average.

[0027] According to a further advantageous embodiment of the circuit according to the invention, it is further provided that the dynamic adaptability of the comparator-specific thresholds can be activated and deactivated as required. The option to be able to temporarily activate and deactivate the threshold adjustment allows the circuit according to the invention to initially run in a calibration mode in which the thresholds T i The system is stabilized and optimally adjusted. After the calibration period is complete, the feedback can be switched off, allowing the circuit to operate in an inference mode where the determined thresholds are kept constant. This flexibility allows switching between phases of automatic threshold adjustment and phases of stable inference. This is particularly advantageous for applications where periodic recalibration is required and otherwise stable operating conditions are preferred.

[0028] A generic computing unit comprising a neuromorphic chip for executing a pulsed neural network is characterized, according to the invention, by a circuit described above, wherein each output line of the circuit is connected to at least one individual input neuron of the pulsed neural network implemented in the neuromorphic chip. The information transmission of the split analog signal, discretized into spike trains, to the neuromorphic chip is thus based on the so-called 1-n principle. This allows a single neuron to influence multiple functions simultaneously. This promotes robust and flexible information distribution within the pulsed neural network.

[0029] The circuit according to the invention can be implemented separately from the neuromorphic chip or integrated into it. The SNN and the circuit are then arranged on the same die.

[0030] A vehicle according to the invention comprises a circuit or a computing unit described above. The vehicle according to the invention can thus efficiently and reliably convert analog signals into spike trains for processing by pulsed neural networks.

[0031] The vehicle in question can be any road vehicle such as a car, truck, van, bus, or similar. Generally, it can also be a rail vehicle, watercraft, or aircraft.

[0032] A vehicle sensor is particularly preferably connected to the signal input of the circuit to provide the analog signal. The circuit or computing unit according to the invention can thus be used to process sensor data in a vehicle using pulsed neural networks. All common sensor types can be used, such as temperature sensors, pressure sensors, position sensors like potentiometers, Hall sensors, suspension travel sensors, or the like, volumetric flow sensors, mass flow sensors, light sensors, microphones, IMUs, and the like.

[0033] Further advantageous embodiments of the circuit, the computing unit and the vehicle according to the invention also result from the exemplary embodiments which are described in more detail below with reference to the figures.

[0034] This shows: Fig. 1 a schematic representation of a circuit according to the invention; Fig. 2 a schematic representation of the conversion of an analog signal into spike trains using the circuit according to the invention in two embodiments; and Fig. 3 a schematic representation of a circuit according to the invention integrated with a neuromorphic chip into a common computing unit.

[0035] Fig. Figure 1 schematically shows a circuit 1 according to the invention. This circuit comprises various strands, which can be considered neurons, since each strand is assigned an input neuron of an SNN. First, a signal input 4 is used to input a signal into Fig. The analog signal 2 shown is fed to a comparator layer 7. The number of comparators 8 implemented in comparator layer 7 can be arbitrarily determined by the manufacturer, taking into account the required operating conditions, and is at least two. Each comparator 8 is configured to read the analog signal 2 and process it with a comparator-specific signal, also shown in the diagram. Fig. The respective comparator 8 outputs a signal when the analog signal 2 exceeds its respective threshold 9.

[0036] Downstream of the comparator layer 7 is a logic gate layer 10. The logic gate layer 10 comprises an arrangement of gate elements for reading and combining the output signals of the comparators 8. In the embodiment shown, the logic gate layer 10 comprises a NOT gate and an AND gate for each pair of adjacent comparators 8.

[0037] The depicted wiring configuration results in the output signals of the comparators 8 being distributed to the output lines 5 of a signal output 6 of the circuit 1 for the formation of the spike trains 3 in such a way that each output line 5 is a specific and also in Fig. The amplitude range 11 shown in Figure 2 is assigned to the analog signal 2.

[0038] Optionally, the circuit 1 according to the invention can further comprise a feedback layer 12 for each strand. This comprises a feedback strand 13. In each feedback strand 13, the following elements are arranged in series: an optional inductor 14, a parallel circuit consisting of an operational amplifier 15 and a capacitor 16, a comparator 17, and optionally a resistor 18.

[0039] The operational amplifier 15 acts as an integrator, summing the number of spikes received by the logic gate layer 10. With each received spike, a fixed charge is transferred to the capacitor 16, which thus functions as a feedback capacitor. The resulting voltage V int,i The voltage increases proportionally to the number of spikes. This voltage is continuously compared to a fixed reference value in order to dynamically adjust the corresponding threshold 9 of the associated compensator 8. If V exceeds the threshold, the voltage is reduced by a certain amount of pressure.int,i The reference value is increased to 9, and otherwise, if V int,i below that, it decreases.

[0040] Fig. Figure 2 shows in subfigures 2A and 2B two different embodiments of a division of the analog signal 2 into different amplitude ranges 11 using two comparators 8 ( Fig. 2A) or four comparators 8 ( Fig. 2B). In the Fig. In the embodiment shown in Figure 2A, the entire amplitude range of the analog signal 2 is distributed unevenly between the two comparators 8. In the embodiment shown in Figure 2A, the entire amplitude range of the analog signal 2 is distributed unevenly between the two comparators 8. Fig. In the embodiment shown in 2B, however, each comparator 8 is assigned an equally large amplitude range 11. The respective comparator-specific threshold values ​​9 are thus, in the case of the embodiment shown in Fig. The embodiment shown in 2B is distributed equidistantly.

[0041] In Fig. 2A and Fig. 2B shows on the far left how the analog signal 2 is divided among the respective amplitude ranges 11 and the neurons A1 to A2 or A4.

[0042] In the center of each diagram is a graph showing the analog signal 2 versus time t and the respective comparator-specific thresholds 9. These thresholds 9 are labeled T1, T2, T3, and T4. The respective times t0 to t8 at which the analog signal 2 crosses a given threshold 9 are marked in the diagrams.

[0043] In the Fig. 2A and Fig. Figure 2B, on the far right, shows the spike trains 3 that result on the respective output lines 5. As can be seen, a spike or pulse is generated precisely when the analog signal 2 crosses a respective threshold value 9. By analogy, this can be understood as the respective neuron A ifires. It is conceivable that, moreover, at the beginning of the measurement period, neuron A fires. i fires, in whose amplitude range 11 the analog signal 2 starts.

[0044] Circuit 1 can also be designed such that the respective spikes in the spike trains 3 are not only output directly when a respective threshold value 9 is crossed, but are repeatedly output at a fixed and optionally variably adjustable frequency as long as the analog signal 2 is within a respective amplitude range 11 (in Fig. 2 not shown). It is also conceivable to take into account the directional dependence of the analog signal 2, so that respective spikes are only generated if the analog signal passes through or reaches a respective threshold value 9 exclusively from below or from above (in Fig. 2 not shown). Circuit 1 can include further components in logic gate layer 10, such as flip-flops.

[0045] With the aid of the circuit 1 according to the invention, analog signals s(t) can be processed at extremely high sampling rates, such as 10 GHz or more. Such a high sampling cycle requires a fast and efficient conversion into discrete spike trains 3 in order to adequately prepare the analog output for use in Fig. To make the neuromorphic chips 20 shown in the 3 shown usable. By means of the circuit 1 according to the invention, the analog signal 2 in the form of s(t) is directly and in real time compared with a series of comparators 8, which continuously compare the signal amplitude against the predetermined threshold values ​​T1, T2, ..., T nCheck. Since the signal processing is performed in parallel in hardware, circuit 1 enables an immediate response to changes in the analog signal 2, regardless of the high sampling rate. The firing rates of the neurons are regulated by the subsequent dynamic adjustment of the thresholds 9 in the feedback loop. The conversion of the analog signal 2 into spike trains 3 is precise, maximizing the information density by utilizing all neurons equally.

[0046] Fig. Figure 3 shows a computing unit 19 according to the invention, in which the circuit 1 according to the invention is integrated together with said neuromorphic chip 20. As shown, each output line 5 of the circuit 1 is assigned to one or more individual input neurons 21 of a pulsed neural network (SNN) implemented in the neuromorphic chip 20. There is said to be an analogy between the input neurons 21 and the neurons A nParticularly preferably, the circuit 1 or the computing unit 19 is integrated into a vehicle 23. In particular, the analog signal 2 is output by a sensor 22 of the vehicle.

[0047] It is conceivable that the pulsed neural network SNN has inputs for more than one sensor 22 or more than one circuit 1, thus enabling parallel data processing of multiple sensors 22. In this way, dependencies between the sensor behavior of multiple sensors 22 can be directly taken into account by the pulsed neural network SNN without explicitly modeling or otherwise representing these dependencies.

Claims

[1] Circuit (1) for converting an analog signal (2) into spike trains (3) for processing by a pulsed neural network (SNN), comprising a signal input (4) for receiving the analog signal (2) and a signal output (6) subdivided into at least two output lines (5) for outputting the spike trains (3), characterized by the following components: - a comparator layer (7) comprising at least two comparators (8), each comparator (8) being configured to read the analog signal (2) and compare it with a comparator-specific threshold (9) and output a signal if the analog signal (2) exceeds the respective threshold (9); and - a logic gate layer (10) comprising an arrangement of gate elements for reading and combining the output signals of the comparators (8) such that the output signals of the comparators (8) are distributed to the output lines (5) of the signal output (6) to form the spike trains (3) such that each output line (5) is assigned a specific amplitude range (11) of the analog signal (2). [2] Circuit (1) according to claim 1, characterized by , that the threshold values ​​(9) of the comparators (8) are chosen such that the entire amplitude range of the analog signal (2) is covered. [3] Circuit (1) according to claim 1 or 2, characterized by , that the threshold values ​​(9) are equidistantly distributed. [4] Circuit (1) according to any one of claims 1 to 3, characterized by, that the comparator-specific thresholds (9) can be dynamically adjusted depending on the number of spikes in the spike train (3) that can be generated by the specific comparator (8). [5] Circuit (1) according to claim 4, characterized by , that a respective threshold (9) can be raised if the number of spikes in the spike train (3) generated by the specific comparator (8) exceeds a specified number threshold and can be lowered if the number of spikes falls below the specified number threshold. [6] Circuit (1) according to claim 4 or 5, characterized bya feedback layer (12) for implementing the dynamic adaptability of the comparator-specific thresholds (9), comprising for each output line (5) the following components connected in series in a feedback loop (13): optionally an inductor (14), a parallel circuit consisting of an operational amplifier (15) and a capacitor (16), a comparator (17) and optionally a resistor (18), wherein the input of the feedback loop (13) is connected to one of the outputs of the logic gate layer (10) and the output of the feedback loop (13) is connected to an input of the comparator (8) associated with the respective logic gate layer (10). [7] Circuit (1) according to any one of claims 4 to 6, characterized by , that the dynamic adjustability of the comparator-specific thresholds (9) can be activated and deactivated as required. [8] Computing unit (19) comprising a neuromorphic chip (20) for executing a pulsed neural network (SNN), characterized by a circuit (1) according to one of claims 1 to 7, wherein each output line (5) of the circuit (1) is connected to at least one individual input neuron (21) of the pulsed neural network (SNN) implemented in the neuromorphic chip (20). [9] vehicle, characterized by a circuit (1) according to one of claims 1 to 7 or a computing unit (19) according to claim 8. [10] Vehicle according to claim 9, characterized by , that a vehicle sensor is connected to the signal input (4) of the circuit (1) to provide the analog signal (1).

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