Pulse Amplitude Modulation Transition Density Trigger in a Test and Measuring Device

Abstract

A test and measurement instrument comprises an input for receiving a pulse-amplitude modulated n-level signal (PAMn), an analog-to-digital converter (ADC) coupled to the input to digitize the PAMn signal, a capture memory coupled to the ADC and configured to store at least a portion of the digitized PAMn signal as a waveform, a trigger circuit coupled to the ADC and the capture memory to generate a trigger signal to cause the test and measurement instrument to initiate waveform acquisition, a PAMn clock and data recovery (CDR) circuit configured to decode bits from the PAMn signal, and a transition detection logic circuit coupled to the PAMn CDR circuit and the trigger circuit to detect symbol transitions based on the decoded bits and to initiate the trigger circuit.The trigger signal is designed to generate a response to the detection of a specific symbol transition.

Description

CROSS REFERENCE TO RELATED APPLICATIONSThis application claims priority to U.S. Provisional Patent Application No. 63 / 677,362, filed July 30, 2024, the contents of which are hereby incorporated by reference into this application.FIELD OF TECHNOLOGYThis disclosure relates to test and measurement instruments, and more particularly to trigger technology for a test and measurement instrument, such as an oscilloscope.BACKGROUNDPulse amplitude modulation (PAM) is used more and more. Multi-stage PAM3, PAM4, PAM8 and PAM30 signals are all part of important standards. Visualization or measurement of the signal integrity of these signals is substantially more complicated than with conventional NRZ (non-return-to-zero) signals. In conventional oscilloscope triggers, the display of the waveform is biased to a subset of the possible transitions. PAM4 has twelve different transitions. PAM8 has fifty-six different transitions. Conventional oscilloscope trigger systems, both analog and digital, can use runt triggers to trigger some of these transition types, but not the majority. And triggering only one transition at a time does not provide a good visual representation of signal integrity. Embodiments of this disclosure overcome these and other shortcomings of conventional oscilloscope trigger technology.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a functional block diagram of a test and measurement instrument according to embodiments of the disclosure. FIG. 2 is a functional block diagram of a test and measurement instrument according to embodiments of the disclosure. FIG. 3 is a functional block diagram of a test and measurement instrument according to embodiments of the disclosure. FIG. 4 is an example of displaying an eye diagram of a PAM4 signal.DETAILED DESCRIPTIONFIG. 4 shows an example of an eye diagram representation 400 of a PAM4 signal. The eye diagram shown in Figure 4 illustrates the twelve different possible transitions between the four different signal amplitude levels and the corresponding four symbols (S0, S1, S2, S3) in a PAM4 signal. The example signal shown in FIG. 4 uses gray coding such that symbol S0or 0 corresponds to bits 00, symbol S1or 1 corresponds to bits 01, symbol S2or 2 corresponds to bits 11, and symbol S3or 3 corresponds to bits 10. As mentioned above, conventional analog and digital oscilloscope triggering systems can use runt triggering to trigger some of the twelve different transitions between symbols, but not the majority. And triggering at only one transition at a time does not provide a good visual representation of signal integrity. For example, if the user always triggers at the transition from 0 to 1 with the PAM4 signal shown in FIG. 4 and there are significant issues with signal integrity at the transition from 3 to 1, the user may never recognize the issue.Users often trigger on a waveform and activate display persistence to indicate the noise and jitter of a signal. However, this persistence may not indicate problematic transitions at the current trigger. If the display is provided with a grey scale for persistence, the most frequently triggered transition is emphasized even more and problems with other transitions are obscured. Users may attempt to bypass this through longer detections, but this does not solve the problem, as some detections are still dominated by a few transition types and large deviations occur between the individual passes.Current oscilloscopes also have high speed serial pattern triggers. These allow triggering at a particular transition or series of transitions. This also does not solve the problem, as persistence continues to indicate only a portion of the pattern and is likely not to represent all transitions, particularly as the order of the PAMn signals increases.The first problem to be solved is the detection of certain transitions. This could be done with a conventional analog or digital trigger system using multiple threshold / edge detectors and timers. Depending on the baud rate of the signaling in relation to the sampling rate of the oscilloscope, a digital trigger may require interpolation of the data in front of the trigger system. In the event of considerable channel losses in the system under test, it may also be necessary to equalize the signal upstream of the trigger device. This is a possible implementation, but is so complicated that it is impractical.Another method for detecting transitions involves using dedicated transceiver circuitry to receive and decode the serial data in parallel for analog detection. This topology is frequently used today in oscilloscopes to enable triggering on fast serial data, but currently only for NRZ signals. In order to detect transitions, this topology has to be extended to PAM signals in an ASIC or FPGA. To detect certain transitions, custom circuitry would be used after the transceiver.FIG. 1 shows a functional block diagram of a test and measurement device 100, such as an oscilloscope, in accordance with some embodiments of this disclosure. The test and measurement device 100 comprises an input 102 for receiving a PAMn signal, wherein n is greater than or equal to three, for example PAM3, PAM4, PAM8, etc. The received analog PAMn signal is forwarded from the input 102 to an analog front end circuit in order to condition the received input signal. The front end circuit may include a preamplifier 104. Preamplifier 104 amplifies and / or attenuates the input signal and outputs the signal to both an analog-to-digital converter (ADC) 106 and a PAMn clock and data recovery circuit (CDR) 112. The ADC 106 digitizes the input signal and passes the digitized signal to both a sense memory 108 and a trigger circuit 110. The acquisition memory 108 is configured to store at least a portion of the digitized PAMn signal as a waveform. In parallel, the PAMn-CDR circuit decodes 112 bits from the analog PAMn signal according to known CDR methods. In some embodiments, the PAMn-CDR circuit 112 may be implemented in, for example, an FPGA or an ASIC. The decoded bits are passed to a transition detection logic circuit 114. Transition detection logic 114 uses the decoded bits from CDR 112 and compares them with the decoded bits of the previous clock cycle to detect all possible PAM transitions. For example, in the example of the PAM4 signal of CDR 112 discussed above and shown in FIG. 4, if bits 01 were decoded for the current clock cycle and the decoded bits of the previous clock cycle were 10, transition detection logic 114 detects a transition from symbol 3 to symbol 1, which may also be referred to as 3->1.Transition detection logic 114 communicates with trigger circuit 110 to configure trigger circuit 110 to generate a trigger signal in response to detecting a particular signal transition. The trigger signal causes the test and measurement device to trigger a detection of the waveform when a particular transition is detected. The particular transition, e.g., from symbol 3 to symbol 1, may be configurable by the user. In some embodiments, trigger circuit 110 includes a digital trigger, but in other embodiments, an analog trigger circuit may be used.Another technique for detecting the transitions according to some embodiments of the disclosure is illustrated in a test and measurement device 200 shown in FIG. 2. The apparatus 200 uses clock and data recovery based on the sampled data instead of the analog input signal. This technique is similar to the technique used in the test and measurement device 100 shown in FIG. 1, but does not rely on existing analog CDR techniques implemented in an ASIC or FPGA. This digital CDR would rely on the sampled data and allow triggering according to more recent standards that may not be supported in existing IPs.FIG. 2 shows a functional block diagram of a test and measurement device 200, such as an oscilloscope, in accordance with some embodiments of the present disclosure. The test and measurement device 200 includes an input 102, a front end circuit, which may include a preamplifier 104, an ADC 106, a sense memory 108, and a trigger circuit 110, each of which substantially corresponds to the identically numbered blocks in the test and measurement device 100 of FIG. 1. However, as shown in FIG. 2, in the test and measurement device 200, the digitized PAMn signal is output from the ADC 106 to the sense memory 108, the trigger circuit 110, and to a digital PAMn CDR circuit 212. Thus, the CDR in the test and measurement device 200 is based on sampled data and not an analog copy that is sent to a separate receiver circuit. Optionally, the digitized PAMn signal may also pass through an interpolation block 202 and / or a continuous time linear equalizer (CTLE) block 204 before the digital CDR. Interpolator 202 and CTLE 204 may be required depending on the speed of the input signal and the type of channel. Like the analog PAMn CDR 112 in FIG. 1, the digital PAMn CDR 212 decodes bits from the digitized PAMn signal and passes the decoded bits to the transition detection logic 114, which compares them with the decoded bits from the previous clock cycle and then communicates with the trigger circuit 110 to trigger them at certain symbol transitions.According to some embodiments of this disclosure, once the various transitions are detected, a random or round robin trigger may be used to effect a persistent display that overlays the display of all transitions in equal sets. This can also be done with grey levels. This round robin or random transition selection may be implemented in the trigger circuit 110.For analysis applications, it would be ideal if the detected waveform had an equal number of each transition type. Most patterns, however, do not allow for a perfectly uniform distribution. One solution according to some embodiments of this disclosure includes providing counters for each transition type that are incremented each time a particular transition is detected, as shown in the example of FIG. 3.FIG. 3 is a functional block diagram of a test and measurement device 300 that includes counters for tracking the number of each detected transition type, in accordance with some embodiments of this disclosure. As shown in FIG. 3, the test and measurement device 300 includes an input 102, a front end circuit that includes a preamplifier 104, an ADC 106, a sense memory 108, a trigger circuit 110, a PAMn analog CDR 112, and a transition detection logic circuit 114 that each substantially correspond to the identically numbered blocks in the test and measurement device 100 in FIG. 1. In addition, the test and measurement device 300 also includes a symbol transition count circuit such as a transition memory controller 302, a number m of symbol transition counters 304 a, 304 b,..., 304 m, a number m of count threshold blocks 306 a 306 b,..., 306 m, a logic gate 310, and a peak tracker block 308.The transition memory controller 302 is coupled to the transition detection logic 114. Each transition counter 304 is coupled to the transition memory controller 302 and to the transition detection logic 114. Each transition counter 306 is coupled to one of the transition counters 304.The total amount m of transition counters 304 and count thresholds 306 corresponds to the number of different symbol transitions for the PAMn signal. For example, for a PAM4 signal, there are twelve different symbol transitions, such that m is equal to twelve. For a PAM8 signal, m is equal to 56. Thus, each of the m different symbol transitions 304 and each of the m different symbol transitions 306 are associated. The symbol transition counter circuit is configured such that each time a particular symbol transition is detected, the count of the associated transition counter is incremented. The count value may then be compared to an adjustable threshold in the count threshold 306. The logical result of this comparison is then passed to logic gate 310, which combines the outputs of all m counter thresholds and, based on the combined outputs, sends a signal to the trigger circuit, e.g., when all counter thresholds have been reached.The peak tracker 308 is coupled to each of the transition counters 304 a, 304 b,..., 304 m, and to each of the counter thresholds 306 a, 306 b,..., 306 m. The peak tracker 308 is configured to track the highest count of all possible m transitions, and may be further configured such that all other transitions must satisfy a certain percentage of the transition with the highest count. For example, if transition 0 -> 2 occurs most frequently in the PAMn signal, say 1000 edge occurrences, then all other transitions must have a user-configurable percentage thereof. According to some embodiments, the peak tracker 308 may automatically form the count thresholds for the other transitions to a percentage of the count for the most dense transition, i.e., the peak count. The peak tracker 308 may be advantageous for PAMn signals where it cannot be predicted which transition will be the closest.According to some embodiments, the transition events may be stored in a capture memory 108 adjacent to the captured samples before or at the edge. The event would be stored only once, regardless of how many samples are on the edge. It is not so important that the event be stored with an accurate sample. This is only used to track the number of each type of transition. Since the data in the circular buffer acquisition memory is overwritten, each transition type in the overwritten sample is decremented by the associated counter. In this way, the symbol transition count circuit reflects the number of transitions in the current sense memory. For higher order PAM signaling, the transition data may be encoded with the captured samples prior to storage, such that PAM4 does not need to store 12 bits in parallel with 8 or 16 bit data samples. This would consume a memory bandwidth corresponding to that of the stored data, but could be encoded to 4 bits. This would be even more important for PAM8 or PAM16.Once counters are present that reflect the number of each type of transition, a trigger may be built on the counters. The trigger could be configured by the user to provide a minimum number for each transition. For example, a user setting a minimum number of 3000 transitions of each type could perform statistically significant jitter computations based on each transition type. The number of transitions required for the user depends on the standard and the value to be measured and can therefore be formed.Another possibility would be for the user to require an approximately uniform distribution of the transitions. To do this, it would be necessary to track which of the transition types has the highest number, and the peak tracker 308 would have to set a threshold for all transition types other than the user-configurable percentage of that number. This could be enabled by the peak tracker 308.In this way, embodiments of the disclosure may provide the possibility that a test and measurement device responds to the "density", i.e., frequency of occurrence, of a particular symbol transition type or a combination of particular symbol transition types present in a PAMn input signal. This greatly increases the usefulness of test and measurement equipment for the analysis and error correction of modern communication systems using multi-stage PAM standards such as PAM4, PAM8, PAM16, etc.Aspects of the disclosure may be executed on specially developed hardware, firmware, digital signal processors, or on a specially programmed general purpose computer including a processor operating in accordance with programmed instructions. The terms "controller" or "processor" as used herein are intended to include microprocessors, microcomputers, application specific integrated circuits (ASICs), and dedicated hardware controllers. One or more aspects of the disclosure may be embodied in computer-executable data and instructions, such as one or more program modules executed by one or more computers (including monitoring modules) or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types when executed by a processor in a computer or other device. The computer-executable instructions may be stored on a non-transitory computer-readable medium, such as a hard disk, an optical disk, a removable medium, a solid state memory, a random access memory (RAM), etc. As is known to one of ordinary skill in the art, the functionality of the program modules may be combined or distributed in various aspects as desired. Moreover, the functionality may be embodied in whole or in part in firmware or hardware equivalents such as integrated circuits, FPGA, and the like. Certain data structures may be used to more effectively implement one or more aspects of the disclosure, and such data structures are provided within the scope of the computer-executable instructions and computer-usable data described herein.The disclosed aspects may be implemented in hardware, firmware, software, or any combination thereof in some cases. The disclosed aspects may also be implemented as instructions transmitted or stored by one or more non-transitory computer readable media and readable and executed by one or more processors. Such instructions may be referred to herein as a "computer program product.". Computer-readable media within the meaning of this description are all media to which computer access is possible. Computer readable media may include, for example, but is not limited to, computer storage media and communication media.Computer storage media is any media that can be used to store computer readable information. Examples of computer storage media include RAM, ROM, electrically erasable programmable read only memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital video disc (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, as well as any other volatile or non-volatile, removable or non-removable media implemented in any technology. Computer storage media excludes signals per se and transient forms of signal transmission.Communication media is any media that can be used to transmit computer readable information. Examples of communication media include coaxial cables, fiber optic cables, air, or other media suitable for the transmission of electrical, optical, radio frequency (RF), infrared, acoustic, or other signals.In addition, certain features are referred to in this written description. It is understood that the disclosure in this specification encompasses all possible combinations of these particular features. For example, if a particular feature is disclosed in the context of a particular aspect, that feature may also be used in the context of other aspects as long as possible.When reference is made in this application to a method having two or more defined steps or acts, the defined steps or acts may be performed in any order or simultaneously, unless the context excludes these possibilities.Although certain aspects of the disclosure have been illustrated and described for purposes of illustration, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure.References included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Patent Literature citedUS 63 / 677,362

[0001]

Claims

A test and measurement device comprising: an input for receiving a pulse amplitude modulated n-level signal (PAMn), where n is greater than or equal to three; an analog-to-digital converter (ADC) coupled to the input for digitizing the PAMn signal; a sense memory coupled to the ADC and configured to store at least a portion of the digitized PAMn signal as a waveform; a trigger circuit coupled to the ADC and the sense memory and configured to generate a trigger signal for causing the test and measurement device to trigger a detection of the waveform; A PAMn clock and data recovery (PAMn-CDR) circuit configured to decode bits from the PAMn signal; and a transition detection logic circuit coupled to the PAMn-CDR circuit and the trigger circuit configured to detect transitions of the symbols based on the decoded bits and to cause the trigger circuit to generate the trigger signal in response to detecting a particular transition of the symbols.The test and measurement device of claim 1, further comprising an amplifier coupled to the input to amplify the PAMn signal; wherein the PAMn CDR circuit is coupled to the amplifier, and wherein the PAMn CDR circuit comprises an analog PAMn CDR circuit structured to decode bits from the amplified PAMn signal from the amplifier.The test and measurement device of claim 1 or 2, wherein the PAMn-CDR circuit is coupled to the ADC and wherein the PAMn-CDR circuit comprises a digital PAMn-CDR circuit structured to decode bits from the digitized PAMn signal from the ADC.The test and measurement device of claim 3, further comprising an interpolator coupled between the ADC and the PAMn-CDR circuit.The test and measurement device of claim 3 or 4, further comprising a continuous linear equalizer (CTLE) coupled between the ADC and the PAMn-CDR circuit.The test and measurement device according to any one of claims 1 to 5, wherein the PAMn-CDR circuit is implemented in an FPGA or an ASIC.The test and measurement device of any of claims 1 to 6, wherein the trigger circuit is further configured to generate trigger signals for each of the m-symbol transitions, where m is equal to the number of different symbol transitions for the PAMn signal.The test and measurement device of claim 7, wherein the trigger circuit is further configured to generate trigger signals for each of the m symbol transitions in a round robin or random manner such that trigger signals are generated for a substantially equal number of each of the m symbol transitions.The test and measurement device of any of claims 1 to 8, further comprising a symbol transition counter circuit configured to track the number of detected symbol transitions, each count value associated with a respective one of the m different symbol transitions for the PAMn signal.The test and measurement device of claim 9, wherein the symbol transition count circuit comprises: a transition memory controller coupled to the transition detection logic circuit; m transition counters, each transition counter associated with a respective one of the m different symbol transitions for the PAMn signal; and wherein each transition counter is coupled to the transition detection logic circuit and to the transition memory control circuit; m transition count thresholds, each coupled to one of the m transition counters; and a logic gate configured to combine the outputs of the m transition count thresholds and to send a signal to the trigger circuit based on the combined outputs.The test and measurement device of claim 10, further comprising a peak tracker configured to determine a peak count number of counts and to set the counter thresholds as a selectable percentage of the peak count.The test and measurement device of any of claims 9 to 11, wherein the symbol transition counter circuit is configured to increment a count value each time the associated symbol transition is detected.The test and measurement device of any of claims 9 to 12, wherein the symbol transition count circuit is configured to count down when overwriting the portion of the PAMn signal stored in the acquisition memory and including the associated symbol transition.The test and measurement device of any of claims 9 to 13, wherein the trigger circuit is further configured to generate a trigger signal based on a selectable combination of count values.A method of operating a test and measurement device for triggering symbol transitions of a pulse amplitude modulated n-level (PAMn) signal, the method comprising: receiving a PAMn signal at an input, wherein n is greater than or equal to three; digitizing the PAMn signal; storing at least a portion of the digitized PAMn signal in a capture memory; decoding bits of the PAMn signal using a clock and data recovery (CDR) circuit to determine a current symbol and a previous symbol; capturing a symbol transition between the previous symbol and the current symbol; forming a trigger circuit to generate a trigger signal in response to detecting a particular transition of a symbol.The method of claim 15, further comprising: amplifying the PAMn signal prior to digitizing the PAMn signal; and wherein decoding bits of the PAMn signal comprises decoding bits of the amplified PAMn signal using an analog PAMn-CDR circuit.The method of claim 15 or 16, further comprising storing an indication of a detected particular symbol transition in the acquisition memory along with the digitized PAMn signal.The method of any of claims 15 to 17, further comprising: configuring the trigger circuit to generate trigger signals for each of the m-symbol transitions in a round-robin or random manner such that trigger signals are generated for a substantially equal number of each of the m-symbol transitions, where m is equal to the number of different m-symbol transitions for the PAMn signal.The method of any of claims 15 to 18, further comprising: incrementing and decrementing count values for each of the m different symbol transitions for the PAMn signal to reflect the number of each symbol transition present in the digitized PAMn signal stored in the acquisition memory.The method of claim 19, further comprising: determining a peak count of the counts; setting counter thresholds to a selectable percentage of the peak count; and configuring the trigger circuit to generate trigger signals until all counter thresholds are reached.

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