SAVING ENERGY IN STANDBY

Abstract

A device or system comprising one or more devices is provided. In an example, a device includes one or more circuits that enable the device to determine that a communication link between a first communication node and a second communication node is in a linking idle state. Furthermore, in response to the determination that the communication link is in a linking idle state, the device can transmit a disable command to the first communication node and / or the second communication node, the disable command causing a receiver thereof to disable part of an encoding process for the communication link.

Description

AREA OF REVELATION

[0001] The present disclosure relates generally to networks and in particular to network devices and methods for improving their power consumption. BACKGROUND

[0002] Switches and similar network devices are a core component of many communication, security, and computing networks. Switches are frequently used to connect multiple devices, device types, networks, and network types.

[0003] Devices, including but not limited to personal computers, servers, or other types of computing equipment, can be interconnected via network devices such as switches. Such interconnected entities form a network that enables data communication and resource sharing between nodes. Although a given switch may be capable of handling large amounts of data, switches often do not operate at full capacity, and communication links between nodes can fluctuate between periods of low traffic. As a result, conventional switches and nodes consume amounts of power that can be unnecessarily high, especially during periods of low traffic. SUMMARY

[0004] The invention is defined by the claims. To illustrate the invention, aspects and embodiments are described herein that may or may not fall within the scope of the claims.

[0005] The amount of data that computers need to manage and process has increased dramatically. Social media, artificial intelligence, and the Internet of Things have created a need for storage capacity and fast processing of large data sets.

[0006] The trend in modern data processing is moving towards the use of high-performance, massively parallel processing systems that divide large computational tasks into many smaller tasks that can be executed simultaneously. Since such parallel processing architectures have now become widespread, there is a need for large-capacity, high-performance, and low-latency main memory that can store large amounts of data and enable rapid access for parallel processors.

[0007] Even though the RAM capacity of modern systems may seem relatively generous, some massively parallel processing systems are now reaching the limits of their memory capacity. System RAM capacity is generally limited by the maximum address space of the CPU(s) used. For example, many modern CPUs cannot access more than about three terabytes (TB). This capacity (three million bytes) may sound large, but it may not be sufficient for certain massively parallel GPU operations such as deep learning, data analysis, medical imaging, and graphics processing.

[0008] Data centers and other computing environments, such as those employing AI (artificial intelligence) training systems, utilize a network infrastructure known as a fabric, which provides interconnectivity between various components. This facilitates rapid data transfer and communication for handling large datasets and computationally intensive tasks. Such computing environments may employ a fabric of processing devices, such as GPUs and switches, to provide computing capacity to host devices like PCs and servers.

[0009] In such computing environments, there can be periods when parts of the fabric are idle or partially idle with respect to traffic. For example, switches might be used in bursts to provide interconnectivity to GPUs and may remain idle or partially idle while the GPUs perform computational functions. Traditionally, a significant amount of power is wasted in such scenarios.

[0010] Several power-saving features have been developed to conserve power when the communication link between two nodes is inactive for extended periods. These features are achieved by supplying power to the PHY components of the partner nodes connected to the communication link. Such power-saving approaches are referred to as L1 power-saving approaches. While L1 power saving is significant, it suffers from long entry and exit latencies. Embodiments of the present disclosure aim to improve the power efficiency of devices in a network (e.g., switches, nodes, computing devices, etc.) such that entry and exit latencies are minimized.For example, the power-saving approaches presented and described here can offer power savings for devices with entry and exit latencies on the order of 1 µs or less, compared to previous power-saving approaches that could exhibit entry and exit latencies on the order of 100 µs.

[0011] The present disclosure describes a system and a method by which a device, for example, a switch or other computing system, can improve its power consumption (e.g., the power consumption associated with devices in a data center or similar) by disabling the encoder / decoder logic (e.g., a forward error correction (FEC) encoder and / or FEC decoder). During a link idle period (e.g., when no packets are being transmitted), the demands associated with communication linking are reduced. For example, the importance of maintaining a secure communication link is lower when no packets are being transmitted over the communication link. Based on this assumption, embodiments of the present disclosure aim to save power by disabling the FEC encoder and / or FEC decoder functionality of the linking partners (e.g.,The communication link (connected to the nodes) is deactivated. To achieve this power saving, a process is defined to synchronize both linking partners and prevent false error messages.

[0012] According to at least some embodiments of the present disclosure, a controller can be equipped with the ability to decide when a communication link should enter a sleep state (e.g., an L0 IDLE state). Once the communication link has entered the sleep state, the partner nodes associated with the communication link can be instructed to perform power-saving measures. For example, the partner nodes can be instructed to have their internal controllers implement one or more power-saving functions. Embodiments of the present disclosure provide for instructing one or both partner nodes of a communication link to synchronize with each other and save power by disabling some or all of their respective encoder and decoder functions.In some embodiments, the partner nodes can be instructed to save power to the FEC (Forward Error Correction) encoder and the FEC decoder while simultaneously synchronizing the size of the communication link that is in a link idle state.

[0013] In some embodiments, the flow over the communication link (e.g., between partner nodes) can be unidirectional. In such a situation, the entity that coordinates the power consumption of the partner nodes associated with the communication link can instruct the sending node to enter an IDLE state. Upon receiving such an instruction, the sending node can verify that all pending traffic has been sent (e.g., ensure that the communication link is empty and no additional packets are passing through it). Once it has determined that the communication link is empty, the sending node can send a command to the other partner node (e.g., the receiving node) that causes the receiving node to disable its FEC decoder functionality.In some embodiments, the command transmitted from the sending node to the receiving node may include a specification of the number of FEC blocks that the receiving node should consume before disabling its FEC decoder. Simultaneously (e.g., after transmitting the command to the receiving node), the sending node may disable its own FEC encoder. When both partner nodes have disabled their respective FEC encoder and FEC decoder functionality, the communication link can be considered to have entered an L0-IDLE state.

[0014] If one of the partner nodes wants to exit the L0 IDLE state, that node can send a command to its partner node. In a scenario with a unidirectional communication link, the sending node can send a command to the receiving node indicating that the sending node wants to exit the L0 IDLE state and that the receiving node should activate its FEC decoder functionality within a predetermined number of FEC blocks. After receiving the command from the sending node, the receiving node can count the number of blocks received from the sending node via the communication link until the predetermined number of FEC blocks (e.g., "X" blocks) has been received, at which point the receiving node can activate its FEC decoder. Simultaneously (e.g., after the sending node has sent the command to exit the L0 IDLE state), the sending node can activate its own FEC encoder functionality.

[0015] Once both partner nodes have activated their respective FEC encoder and FEC decoder functionality, traffic on the communication link is protected again and packets can be sent securely over the communication link.

[0016] To support the sharing of control information between the two linking partners, a predefined header (e.g., a vendor-specific header) can be used for communication over the communication link, even if the FEC encoder and FEC decoder functionality of the linking partners has been disabled. The vendor-specific header can remain protected even if it is not encoded by the sender node. This security feature provided by the vendor-specific header can be achieved by enabling the encoder / decoder only for the control information that consumes a negligible portion of the encoder and decoder current.

[0017] In an illustrative example, a device is disclosed comprising one or more circuits for: determining that a communication link between a first communication node and a second communication node is in a linking idle state; and transmitting, in response to the determination that the communication link is in a linking idle state, a disable command to the first communication node and / or the second communication node, wherein the disable command causes a receiver of the same to disable part of an encoding operation for the communication link.

[0018] According to at least some aspects, in response to receiving a status update from a power management controller, it is determined that the communication link is in a linking idle state.

[0019] According to at least some aspects, the first communication node comprises a sender node, the second communication node comprises a receiver node, and communication between the first communication node and the second communication node is unidirectional.

[0020] According to at least some aspects, the sending node transmits the deactivation command to the receiving node after the sending node has determined that the communication link is in a linking idle state.

[0021] According to at least some aspects, the one or more circuits also serve to: determine that all pending traffic between the first communication node and the second communication node has been transmitted, so that the communication link is empty, and transmit, after determining that the communication link is idle and empty, the deactivation command from the sending node to the receiving node.

[0022] According to at least some aspects, this part of the encoding process includes error correction decoding.

[0023] According to at least some aspects, the encoding process includes FEC (Forward Error Correction) encoding and FEC decoding.

[0024] According to at least some aspects, this part of the encoding process includes error correction encoding.

[0025] According to at least some aspects, the one or more circuits further serve to: detect that the communication link is exiting the linking sleep state, and transmit, in response to the detection that the communication link is exiting the linking sleep state, an activation command to the first communication node and / or the second communication node, the activation command causing the receiver of the same to activate the part of the encoding process for the communication link that was interrupted in response to the receipt of the deactivation command.

[0026] According to at least some aspects, the activation command specifies a number of blocks to be transmitted before the encoding process is activated for communication linking.

[0027] According to at least some aspects, the communication link remains in an active state even when the part of the encoding process is deactivated.

[0028] According to at least some aspects, the deactivation command is contained in an in-band communication between both sides of the communication link.

[0029] According to at least some aspects, the communication link is maintained as an error-free link while it is in the linking dormant state.

[0030] According to at least some embodiments, a communication node is provided comprising: a port facilitating interconnectivity with a communication network; and one or more circuits for: establishing a communication link with a receiving node via the port; detecting that the communication link is in a link-quiet state; and transmitting, in response to the detection that the communication link is in a link-quiet state, a disable command to the receiving node, the disable command causing the receiving node to disable a decoding operation for the communication link.

[0031] According to at least some aspects, in response to receiving a status update from a power management controller, it is determined that the communication link is in a linking idle state.

[0032] According to at least some aspects, the one or more circuits also serve to: determine that all pending traffic for the receiving node has been transmitted, so that the communication link is empty; and transmit, after determining that the communication link is in the linking idle state and empty, the deactivation command to the receiving node.

[0033] According to at least some aspects, the decoding process includes error correction decoding.

[0034] According to at least some aspects, the one or more circuits also serve to: detect that the communication link is exiting the linking sleep state, and transmit, in response to the detection that the communication link is exiting the linking sleep state, an activation command to the receiving node, which causes the receiving node to activate the decoding process.

[0035] According to at least some aspects, the activation command specifies a number of blocks to be transmitted before an encoding process is activated for communication linking.

[0036] According to at least some embodiments, a communication node is provided comprising: a port facilitating interconnectivity with a communication network; and one or more circuits for: establishing a communication link with a sender node via the port; receiving, via the port, a disable command indicating that the communication link is in a linking idle state; and disabling, in response to receiving the disable command, a decoding operation for the communication link.

[0037] According to at least some aspects, the communication link remains in an active state even when the decoding process is disabled, and the communication link is unidirectional.

[0038] Each feature of an aspect or embodiment can be applied to other aspects or embodiments in any suitable combination. In particular, each feature of a process aspect or embodiment can be applied to a device aspect or embodiment, and vice versa.

[0039] Further features and advantages are described herein and will become apparent from the following detailed description and the figures. Brief description of the multiple views of the drawings

[0040] The present revelation is described in conjunction with the accompanying figures, which are not necessarily drawn to scale: Fig. Figure 1 is a block diagram representing an illustrative configuration of a network according to at least some embodiments of the present disclosure; Fig. 2 is a block diagram representing an illustrative configuration of a device according to at least some embodiments of the present disclosure; Fig. Figure 3 is a block diagram representing an illustrative configuration of routing circuitry according to at least some embodiments of the present disclosure; Fig. 4 is a block diagram representing the contents of working memory according to at least some embodiments of the present disclosure; Fig. 5 is a flowchart representing a first method according to at least some embodiments of the present disclosure; Fig. Figure 6 is a flowchart representing a second method according to at least some embodiments of the present disclosure; Fig. Figure 7 is a flowchart representing a third method according to at least some embodiments of the present disclosure; Fig. Figure 8 is a state diagram illustrating possible states of a transmitter node according to at least some embodiments of the present disclosure.

[0041] The same reference numbers and designations in the different drawings refer to the same elements. DETAILED DESCRIPTION

[0042] The following description contains only embodiments and is not intended to limit the scope, applicability, or configuration of the claims. Rather, the following description is intended to provide guidance to those skilled in the art for implementing the described embodiments. It is understood that various modifications to the function and arrangement of the elements can be made without deviating from the essence and scope of the attached claims.

[0043] From the following description and for reasons of computational efficiency, it becomes clear that the components of the system can be placed at any suitable location within a distributed network of components without affecting the operation of the system.

[0044] Furthermore, it is understood that the various links connecting the elements can be wired, conductive, or wireless links, or any suitable combination thereof, or any other suitable element known or subsequently developed that can supply and / or transmit data to and from the connected elements. Transmission media used as links can, for example, be any suitable carrier for electrical signals, including coaxial cable, copper wire and optical fibers, electrical conductive traces on a PCB (printed circuit board), or the like.

[0045] The term "automatic" and variations thereof, as used herein, refers to any suitable process or operation that is carried out without substantial human input when the process or operation is carried out. However, a process or operation may be automatic even if the execution of the process or operation requires substantial or non-substantial human input, provided that the input is received prior to the execution of the process or operation. Human input is considered substantial if that input affects the execution of the process or operation. Human input that merely approves the execution of the process or operation is not considered substantial.

[0046] The terms "determine", "calculate" and "calculate" as well as their variations are used interchangeably here and include any suitable type of methodology, process, procedure or technique.

[0047] Various aspects of the present disclosure are described here with reference to drawings that are schematic representations of idealized configurations. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by an average person skilled in the field to which this disclosure belongs. It is further understood that terms as defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the relevant prior art and this disclosure.

[0048] With reference to Fig. In sections 1-8, various systems and methods for implementing a power-saving process are described. According to at least some embodiments of the present disclosure, power saving can be achieved by disabling at least part of the encoding and / or decoding functionality of a node when the node is associated with a communication link that is in a link sleep state. While the encoding and / or decoding functionality is disabled, a process can be used to synchronize both link partners associated with the communication link and thus prevent false error indications.

[0049] First, with reference to Fig. 1. A computing environment as described herein may be a network of devices that may be directly (e.g., by a cable) or indirectly (e.g., by a fabric) interconnected. A fabric as described herein may include one or more interconnect devices and / or one or more processing devices. The computing environment may include interconnect devices, computing devices, client devices, switches, servers, CPUs, GPUs, communication nodes, or the like. By way of illustration and without limitation, the computing environment may include one or more devices in a data center. For example, the computing environment may include a plurality (N) of GPUs that communicate with each other via a high-performance, high-bandwidth interconnect fabric, such as NVIDIA's NVLINK™. Other systems may provide a single GPU connected via NVLINK™.

[0050] The NVLINK™ interconnect fabric (comprising communication links 109, nodes 103 and 106, connection management devices 100, and other devices) can provide multiple high-speed links connecting nodes 103 and 106 in the form of GPUs. In the example shown, each node in the compute environment can be connected to at least one other node via one or more high-speed communication links 109. Thus, a first node 103 can be connected to a second node 106 via a first communication link 109 and to other nodes and the connection management device 100 via other communication links. It should be understood that some GPUs can be directly connected to other GPUs without being connected via the connection management device 100.

[0051] In the exemplary embodiment shown, each node 103, 106 can use high-speed links 109 and / or the link management device 100 to communicate with the memory provided by one or all of the other nodes. For example, there may be cases and applications where nodes are provided in the form of a GPU, and each GPU requires more memory than is provided by its own locally attached memory. Some non-restrictive use cases include situations where the system 100, when performing deep learning training of large models using network activation offload, big data analysis (e.g., RAPIDS (ETL) analysis, in-memory database analysis, graph analysis, etc.), computational pathology using deep learning, medical imaging, graphics rendering, or the like, requires more memory than is available as part of each GPU.

[0052] As one possible solution, each GPU can use links 109 and other devices (e.g., a switch) to access local memory on any other GPU as if it were its own local memory. Thus, each GPU can have its own locally linked memory that it can access without initiating transactions across the interconnect fabric, but it can also use the interconnect fabric to address / access individual words of the local memory of other GPUs connected to the fabric.In some non-restrictive embodiments, each GPU can use MMU hardware-accelerated atomic functions to access such local memory of other GPUs, which read a memory location, modify the read value, and write the results back to the memory location without requiring instructions to load into a register and to store from a register (see above).

[0053] Such access by one GPU to the local memory of another GPU can be, from the perspective of an application running on the GPU initiating the access, “the same” (though not quite as fast) as if the GPU were accessing its own locally connected memory. Hardware within each GPU and hardware within a switch performs the necessary address translations to map virtual addresses used by the running application to physical memory addresses of the GPU’s local memory and the local memory of one or more other GPUs. As explained herein, such peer-to-peer access extends the memory connected to the fabric without incurring the additional cost of more compute-capable GPUs.

[0054] Nodes 103, 106, and other nodes can correspond to computing devices, communication devices, connection devices, or the like. The connection management device(s) 110 can also correspond to a computing device, communication device, or connection device. In some embodiments, nodes 103 and 106 can communicate directly with each other via a communication link 109. In some embodiments, a communication link between the first node 103 and the second node 106 can correspond to an indirect communication link, meaning that the communication link is routed through one or more connection devices. In both scenarios, the connection management device 100 can be configured to monitor the status of the communication link established between the first node 103 and the second node 106.If the first node 103 and the second node 106 communicate with each other via a communication link, the first node 103 and the second node 106 can be considered linking partners or partner nodes.

[0055] The one or more connection devices and the connection management device(s) 100 can be connected either directly or indirectly to nodes 103 and 106. Such a network of computing devices can be useful in various environments, from data centers and cloud computing infrastructures to AI systems.

[0056] As mentioned above, the first node 103 and / or the second node 106 can be computing units, such as personal computers, servers, or other computing devices, and are responsible for running applications and performing data processing tasks. The nodes 103 and 106 described herein can range from servers in a data center to desktop computers in a network or devices such as IoT (Internet of Things) sensors and smart devices. Nodes can also include processing devices, which may contain one or more processing circuits, such as GPUs, CPUs (Central Processing Units), ASICs (Application-Specific Integrated Circuits), FPGAs (Field Programmable Gate Arrays), or other circuits capable of performing computations, as well as memory and storage resources to run software applications, handle data processing, and perform specific tasks as needed.In some implementations, nodes 103 and 106 may also or alternatively include hardware such as GPUs to handle intensive tasks for machine learning, AI (artificial intelligence) workloads, or other complex processes.

[0057] For example, nodes 103 and 106 can be operated as a high-performance computing (HPC) cluster. A cluster of nodes 103 and 106, deployed as multiple processing units, can comprise numerous interconnected servers, each equipped with powerful CPUs and / or GPUs. These processing units can provide computing power to, for example, train large-scale AI models or run complex scientific simulations. For AI and machine learning tasks, the processing units can include one or more GPUs or other processing circuits capable of handling the parallel processing requirements of neural networks and other applications.

[0058] Connection devices and connection management devices 100 can enable communication between nodes 103 and 106, either directly or indirectly. A connection device or connection management device 100 can be, for example, a switch, a NIC (Network Interface Controller), or another device capable of receiving and sending data, and can act as a central node in the network. Connection devices can be wired in a topology that includes spine switches and top-of-rack switches. Connection devices can be capable of receiving, processing, and forwarding data, such as packets, to appropriate destinations within the network, such as nodes 103 and 106.In some implementations, a connection device or connection management device as described herein may be contained in a switch enclosure, platform or housing, which may contain one or more connection devices 100 as well as one or more power supply devices.

[0059] In some implementations, each node 103, 106 can be connected via network cable or wirelessly to one or more ports of one or more connection devices. Processes executed by nodes 103, 106, such as applications, can involve transferring data to other nodes in the network, such as other processing devices and / or client devices. Data can flow through the network of nodes and connection devices using one or more protocols, such as TCP (Transmission Control Protocol), UDP (User Datagram Protocol), or IP (Internet Protocol). Upon receiving data from a node 103, 106, or another connection management device 100, each connection device or connection management device 100 can examine the data to identify a destination and route it through the network.

[0060] Client devices as described herein can be computing devices that perform, for example, AI-related, research-related, and other processor-intensive tasks, utilizing processing devices to handle the computational loads and data throughput required by such intensive applications. Client devices can include, for example, workstations and personal computers used by researchers, data scientists, and professionals for developing, testing, and running AI models and research simulations. Client devices may include one or more CPUs and / or GPUs, but may require additional computing power for complex tasks.

[0061] By interacting with processing devices, client devices can be enabled to perform functions such as training machine learning models, performing data processing, running simulations, analyzing large datasets, and performing complex data processing tasks such as data mining, pattern recognition, and predictive modeling.

[0062] As described herein, the connection management device 100 and / or nodes 103 and 106 may be equipped with functionality that enables nodes 103 and 106 to apply power-saving protocols when the communication link between nodes 103 and 106 is detected as being in a linking quiescent state. The detection that the communication link is about to enter, or has entered, such a state may be made by the connection management device 100, the first node 103, and / or the second node 106. Following such a detection regarding the communication link, nodes 103 and 106 may be synchronized with each other to disable at least some of their encoding and / or decoding functionality. Nodes 103 and 106 may remain in such a state until the communication link exists or begins to exit the linking quiescent state.

[0063] The functionality responsible for managing the flow of nodes 103 and 106 can be provided in the connection management device 100, in the first node 103, in the second node 106, or in a combination of devices 100, 103, and 106. With reference to Fig. 2. Additional details of a device 200 according to at least some embodiments of the present disclosure are now described. The device 200 can correspond to the connection management device 100, the first node 103, or the second node 106. In other words, the device described in Fig. The components of the device 200 shown in the illustration can be integrated into the connection management device 100, the first node 103 or the second node 106 without deviating from the present disclosure.

[0064] As shown, the device 200 comprises several ports 203, a routing circuit 206, a processing circuit 209, and a working memory 212. The ports 203 of the device 200 can enable the transmission of data packets or unpackaged data to, from, or through the device 200. Such ports 203 can serve as interface points to which network cables can be connected to connect the device 200 with other devices 200 (e.g., connection management device(s) 100, nodes 103, 106, and other nodes).

[0065] Each port 203 can be capable of receiving incoming data packets from other devices and / or transmitting outgoing data packets to other devices. In some implementations, ports 203 can be configured to operate either as dedicated input or output ports 203, or they can be configured to operate in a dual-purpose mode, capable of performing both input and output functions. For example, an output port 203 can be used exclusively for sending data from device 200, and an input port 203 can be used exclusively for receiving incoming data into device 200.

[0066] As mentioned above, using a system or procedure described herein, links can be opened when traffic is expected, and the associated power consumption can be managed when the links enter a sleep state. Routing circuit 206 of the device 200 can process a received packet by determining an output port 203b from which the packet should be sent and forwarding the packet from that determined output port 203b. Using a system or procedure as described herein, routing circuit 206 can be able to dynamically enter and / or exit ports 203. As a result, routing circuit 206 can be able to reduce the overall power consumption of the device 200 without significantly increasing the latency.

[0067] The routing circuit 206 of the device 200 can comprise one or more input circuits 215 and output circuits 218, as described in more detail below. Each input port 203a can be associated with one or more input circuits 215, and each output port 203b can be associated with one or more output circuits 218. In some implementations, a single port 203 can function as both an input port 203a and an output port 203b. In such implementations, the port 203 can be associated with one or more input circuits 215 and one or more output circuits 218. Each input circuit 215 can be associated with an input port 203a, and each output circuit 218 can be associated with an output port 203b.

[0068] To support the functionality of the routing circuit 206, the processing circuit 209 can be configured to control aspects of the power consumption of the device 200. In some embodiments, the power-saving functions of the device 200 can be facilitated by the processing circuit 209, which executes one or more instructions stored in the working memory 212 as power management instructions 230. When executed by the processing circuit 209, the power management instructions 230 can configure the processing circuit 209 to implement certain power-saving functions, particularly in response to the detection that a communication link is in a link sleep state. The power management instructions 230 can enable the device 200 to identify when a communication link has entered, or is about to enter, a link sleep state.The power management commands 230 can alternatively or additionally notify other devices 200 that a communication link is entering, or about to enter, a link sleep state. Alternatively or additionally, the power management commands 230 can cause the device 200 to disable at least part of its encoding and / or decoding functionality (e.g., disable part of an encoding operation) in response to the detection that a communication link with which the device 200 is associated has entered, or is about to enter, a link sleep state. Alternatively or additionally, the power management commands 230 can cause the device 200 to coordinate with other partner nodes while the communication link is in a sleep state.While the power management instructions 230 are shown as being stored in the working memory 212, it is understood that the processing circuit 209 may include one or more hardware elements that implement some or all of the power management functions. In other words, the power management functionality of the device 200 may be implemented using power management instructions 230 executed by the processing circuit 209, or the power management functionality of the device 200 may be implemented by a specially configured processing circuit 209. In some embodiments, the processing circuit 209 may include a CPU, an ASIC, and / or other circuitry capable of handling the computations, decision-making, and management functions required for the operation of the device 200.

[0069] The processing circuit 209 can be configured to handle level management and control functions of the device 200, such as setting up routing tables, configuring ports, and otherwise managing the operation of the device 200. The processing circuit 209 can run software and / or firmware to configure and manage the device 200, such as an operating system and management tools.

[0070] Routing circuit 206 may comprise one or more circuits and components, such as input circuits 215, output circuits 218, queueing circuits 221, shared buffer circuits 224, and / or other circuits and components that can be used to process and forward packets received by the device 200. Each of these examples, and others, may be selectively enabled and disabled, in whole or in part, based on the status of a communication link with which the device 200 is associated, as described in more detail below.

[0071] The memory 212 of a device 200 described herein can comprise one or more memory elements capable of storing configuration settings, application data, operating system data, and other data. Such memory elements can include, for example, RAM (Random Access Memory), DRAM (Dynamic RAM), Flash memory, NVRAM (Non-Volatile RAM), TCAM (Ternary Content-Addressable Memory), SRAM (Static RAM), and / or memory elements of other formats.

[0072] The main memory 212 can store one or more caches 227. Each cache 227 can contain a number of entries and be associated with a specific port 203 of the device 200. As described below, each cache 227 can store data that identifies one or more output ports 203 from which data is transmitted that is received at the port 203 associated with the cache 227.

[0073] Fig. Figure 3 shows elements of routing circuit 206 of a device 200 according to one or more implementations of the present disclosure. One or more input ports 203a can, after receiving data, transmit the data to one or more input circuits 215. In some implementations, each input port 203a can be associated with a dedicated input circuit 215, while in other implementations, several input ports 203b can share one input circuit 215.

[0074] Each input circuit 215 can include one or more forward error correction (FEC) circuits 306, decryption circuits 309, control planes 312, and / or other circuits and components capable of handling input packets and / or unpacked input data. An FEC circuit 306 as described herein can be used to perform error detection and correction on packets received from an input port 203a before the packets are forwarded to an output port 203b. The FEC circuit 306 can receive input data from an input port 203a and, after performing FEC, output the received input data or a processed version of the input data to a decryption circuit 309.

[0075] A decryption circuit 309 as described herein can be used to decrypt all or part of the received packets so that the device 200 can determine an output port 203b from which each packet should be sent. The decryption circuit 309 can ensure that sensitive data remains protected from unauthorized access while the data passes through the device 200. The decryption circuit 309 can output received packets or data associated with received packets to one or more shared buffer circuits 224, as described below. The decryption circuit 309 can also output data associated with received packets to the control plane 312.

[0076] A control plane 312 as described herein can be used to manage how received data packets are forwarded and handled within the device 200. The control plane 312 can receive data associated with a received packet from the decryption circuit 309 and, based on the data associated with the received packet, write commands to one or more queue circuits 221, as described below.

[0077] A control plane 312 can include one or more components, such as one or more RAM circuits, ASICs, FPGAs, flash memory, NICs (Network Interface Cards), CAM (Content Addressable Memory) circuits, port logic circuits, SerDes (Serializer / Deserializer) circuits, and clock tree circuits. Each component of the control plane 312 can be selectively enabled and / or disabled based on packets received by the Device 200. The control plane 312 can be referred to here as the input control plane. Different packets handled by the Device 200 may require different sets or subsets of components of the control plane 312 to be forwarded. As described herein, a controller or control circuit can be used to determine which components are required for a received packet and to ensure that the required components are enabled.

[0078] The FEC circuit 306, decryption circuit 309, control plane 312, and / or other circuits and components of the input circuits 215 may each comprise one or more ASICs, FPGAs, DSPs (Digital Signal Processors), network processors, accelerators, hardware security modules, CPUs, and / or other components and circuits capable of performing input processing. As can be understood, each input circuit 215 of a device 200 may comprise one or more additional circuits and components in addition to, or instead of, the FEC circuit 306, decryption circuit 309, and control plane 312 described above.

[0079] Each of the input circuits 215 of the device 200 can be activated to write data to a shared buffer circuit 224 and a queue circuit 221. Packets to be output from the device 200 can be stored in the shared buffer circuit 224. Data that can be used by output circuits 218 to route packets to output ports 203b can be written to the queue circuits 221. Once a queue circuit 221 assigns a specific packet to a specific output port 203b, packet data stored in the shared buffer circuit 224 can be read by an output circuit 218 associated with that specific output port 203b.

[0080] Data to be sent by the device 200 can be processed by one or more output circuits 218. In some implementations, each output port 203b can be associated with a dedicated output circuit 218. In other implementations, multiple output ports 203b can share one or more output circuits 218.

[0081] An output circuit 218 may include a packet modifier 321, an FEC 318, and an encryption circuit 315, but should not be considered limited to these. The FEC 318 and the encryption circuit 315 may be configured to each perform FEC encoding and encryption functions, respectively. As explained herein, the functionality of the FEC decoder 306 and / or the FEC encoder 318 may be selectively enabled and / or disabled based on the state of a communication link with which the device 200 is associated.

[0082] A packet modifier 321 as described herein may include circuitry such as one or more RAM circuits, ASICs, FPGAs, flash memory, NICs, CAM circuits, port logic circuits, SerDes circuits, clock tree circuits, or other components that can adjust packets before the packets are transmitted by the linking device. Such adjustments may include, for example, adding or removing tags, modifying settings and packet header data, and other modifications.

[0083] Each component of the packet modifier 321 can be selectively enabled and / or disabled based on the packets received by the device 200. The packet modifier 321 can be referred to here as the output control plane. Different packets handled by the device 200 may require different sets or subsets of components of the packet modifier 321 to be forwarded.

[0084] An encryption circuit 315 and / or an FEC encoder 318 as described herein may include circuitry such as an ASIC, an FPGA, or other components capable of encrypting and encoding packets before the packets are transmitted by the device 200. Such encryption may, for example, involve the use of encryption algorithms such as AES (Advanced Encryption Standard), RSA, or other algorithms.

[0085] After processing by an output circuit 218, a packet can be transmitted from the device 200 via an output port 203b. The output port 203b can be directly connected to the final destination of the packet or it can be connected to another device 200 that can forward the packet to the final destination.

[0086] The reduction of the overall power consumption of the device 200 can be achieved by selectively activating and deactivating components of the input circuits 215 and output circuits 218. For example, the FEC decoder 306 and / or the FEC encoder 318 can be selectively deactivated in response to the detection that a communication link with which the device 200 is associated has entered, or is about to enter, a link sleep state.

[0087] When data is forwarded from the device 200, the processing circuit 209 can identify the input port 203a, where the data was received, and the output port 203b, from which the data was sent. The processing circuit 209 can write data identifying the output port 203b to a cache 227 associated with input port 203a in memory 212. In this way, each cache 227 can maintain a log of the most recently used output ports 203b from an input port 203a associated with that cache 227.

[0088] Fig. Figure 4 is a representation of the main memory 212, which stores a number of caches 227a-c. A first cache 227a is represented as associated with input port 1, a second cache 227b is represented as associated with input port 2, and an nth cache 227c is represented as associated with input port n. While the caches 227a-c of Fig. Since each of the four ports is represented as being associated with a single input port 203a, it should be understood that other arrangements may be used in some implementations. For example, a cache 227 may be associated with a group of ports 203.

[0089] Each cache 227a-c can store identifications 403a-i of output ports 203b. In the Fig. In the example shown, cache 227a, associated with input port 1, contains identifications 403a-c of output ports 1, 2, and 4; cache 227b, associated with input port 2, contains identifications 403d-f of output ports 1, 3, and 5; and cache 227c, associated with input port n, contains identifications 403g-i of output ports 3, 4, and 6. The specific numbers of the output ports 203b identified in each cache 227a-c should be considered for illustrative purposes only and are in no way intended to be restrictive.

[0090] Output ports 203b can be represented in the caches 227 in different implementations in various ways. For example, each port 203b can be represented by a port number or by a bit of a binary number. When processing circuitry detects that an input port 203a has received data transmitted by a particular output port 203b, the processing circuitry can edit the cache 227 associated with the input port to include an identification of the output port 203b.

[0091] With reference to Fig. Sections 5-7 now describe various methods according to at least some embodiments of the present disclosure. The various methods can be executed by one, some, or all components of a computing network. In some embodiments, steps of a method can be executed in the sequence shown or in another sequence. In some embodiments, steps of one method can be combined with steps of another method. Furthermore, steps of a method can be executed by a single device (e.g., a connection management device 100, a node 103, 106, and / or a device 200). Thus, embodiments of the present disclosure provide that a method can be executed on a single device of the computing network or by several devices.

[0092] With reference to Fig. Section 5 first describes a first method 500 according to at least some embodiments of the present disclosure. The method 500 can be implemented by a device 200, such as a connection management device 100, a first node 103 and / or a second node 106, to support the power-saving functionality of the device(s).

[0093] Method 500 begins with a device 200 monitoring a communication link between a first node 103 and a second node 106 (step 504). In some embodiments, the communication link to be monitored may be a direct communication link 109 between the first node 103 and the second node 106. In other embodiments, the communication link to be monitored may be a communication link that passes through a linking device (e.g., a switch) to support communication between the first node 103 and the second node 106. The communication link may be monitored by a link management device 100, the first node 103, and / or the second node 106.In some embodiments, the communication link can be monitored by the linking device used to connect the first node 103 and the second node 106. In some embodiments, the linking management device 100 can determine the state of the communication link by monitoring the communication link, while the first node 103 and / or the second node 106 determine the state of the communication link based on receiving a state update from the linking management device 100.

[0094] Procedure 500 continues by determining that the communication link has entered, or is about to enter, a linking quiescent state (step 508). The determination in step 508 can be made by the same device that monitors the communication link in step 504. The determination that a communication link has entered, or is about to enter, a linking quiescent state can be based on the finding that no packets are passing through the communication link or that the buffer(s) 224 or cache(s) 227 associated with the communication link is / are empty or is / are about to become empty.

[0095] In response to the detection that the communication link has entered, or is about to enter, the linking sleep state, procedure 500 continues by synchronizing the linking partners associated with the communication link (e.g., the first node 103 and the second node 106) to ensure that false error indications are prevented (step 512). In some embodiments, the first node 103 and the second node 106 can synchronize their power-saving functions with each other while the communication link is in the linking sleep state. Synchronizing the power-saving functions of nodes 103 and 106 helps ensure that the communication link does not remain in an unsafe state when data-containing packets are transmitted over the communication link.

[0096] The first node 103 can correspond to a sending node, and the second node 106 can correspond to a receiving node. In such an embodiment, the communication link can be a unidirectional communication link that supports packet transmissions from the first node 103 to the second node 106. Synchronization between the first node 103 and the second node 106 can be supported by the first node 103 sending one or more disable commands to the second node 106, before or simultaneously with the first node 103 disabling at least part of its FEC encoding functionality. The disable command(s) transmitted from the first node 103 to the second node 106 can instruct the second node 106 to disable at least part of its FEC decoding functionality.The deactivation command(s) transmitted between nodes 103 and 106 can be transmitted via in-band communication. Using in-band communication can support the transmission of such commands even when the communication link is in a sleep state. As explained in more detail below, the timing of the deactivation command(s) transmission can support the synchronization of nodes 103 and 106.

[0097] Procedure 500 can be continued by disabling at least part of an encoding operation for the linking partners while the communication link is at rest (step 516). As explained herein, disabling at least part of an encoding operation can include disabling at least some FEC encoding and / or FEC decoding functions of the first node 103 and / or the second node 106.

[0098] Procedure 500 can be continued by synchronizing the linking partners while the communication link remains in linking sleep mode (step 520). Synchronizing the linking partners can be performed to prevent false error messages while the communication link is in linking sleep mode. Synchronization can refer to both linking partners agreeing to disable at least some of their FEC encoding and / or decoding functionality while the communication link is in linking sleep mode.

[0099] With reference to Fig. Section 6 now describes a second method 600 according to at least some embodiments of the present disclosure. Method 600 may comprise one or more steps to support the synchronization of the linking partners while the communication link is in a linking quiescent state. Method 600 begins by determining that a communication link is in a linking quiescent state (step 604). The communication link may support communication between linking partners, which may include the first node 103 and the second node 106. In some embodiments, the communication link may correspond to a unidirectional communication link. The determination in step 604 may be similar to or identical with the determination in step 508.

[0100] Procedure 600 can continue by determining that pending traffic between the first node and the second node 106 has terminated (step 608). In particular, but without limitation, the first node 103 (e.g., the sending node) can determine that its buffer 224 or cache 227, used to transfer data to the second node 106, is about to become empty or is empty. Such a determination can also be equivalent to a determination (or conclusion) that the communication link is empty or about to become empty.

[0101] In response to the detection that all pending traffic between the first node 103 and the second node 106 has been transmitted, the first node 103 can transmit a disable command to the second node 106 (step 612). The disable command can be included in in-band communication established between the first node 103 and the second node 106. The disable command can cause the second node 106 (e.g., the receiving node) to disable a decoding operation for the communication link (step 616). In some embodiments, the first node 103 can synchronize the disabling of its encoding operation to match the disabling of the decoding operation by the second node 106.

[0102] Procedure 600 can be continued in response to the detection that the communication link is exiting the linking idle state (step 620). In some embodiments, the detection of step 620 can be made by the linking management device 100. In some embodiments, the detection of step 620 can be made by the first node 103 in response to the receipt of new data or packets to be transmitted to the second node 106.

[0103] In response to the detection that the communication link is exiting the link sleep state, an activation command can be transmitted to the first node 103 and / or the second node 106 (step 624). In some embodiments, the activation command can cause a receiver to activate the portion of the encoding process that was previously interrupted as part of the implementation of the power-saving functions described herein. In some embodiments, the activation command can be transmitted from the link management device 100 to both the first node 103 and the second node 106. In some embodiments, the activation command can be transmitted from the first node 103 to the second node 106.In some embodiments, the activation command can be transmitted from the link management device 100 to the first node 103, whereupon the first node 103 can transmit a second activation command to the second node 106. The activation command can specify a number of blocks to be transmitted by the first node 103 before the first node activates the one or more encoding operations for data transmission over the communication link. Synchronization between nodes 103 and 106 can be possible because the communication link can remain in an activated but inactive state even if some of the encoding operations for the communication link are disabled. In some embodiments, the activation command is transmitted from the first node 103 to the second node 106. In some embodiments, the activation command is transmitted from the link management device 100 to the second node 106.In some embodiments, the activation command is transmitted by the link management device 100 to both the first node 103 and the second node 106. In some embodiments, the link management device 100 transmits an activation command to the first node 103, which causes the first node 103 to transmit another activation command to the second node 106.

[0104] With reference to Fig. In section 7, details of a further method 700 according to at least some embodiments of the present disclosure are now described. The method 700 can commence when a communication link is established between a first node 103 and a second node 106 (step 704). The communication link can connect the first node 103 and the second node 106 directly or via one or more connection devices or connection management devices 100. The communication link can be bidirectional or unidirectional.

[0105] Procedure 700 continues by receiving a disable command at a port 203 supporting the communication link, indicating that the communication link is in a sleep state or is about to enter a sleep state (step 708). In some embodiments, the disable command can be received at a receiving node (e.g., a second node 106).

[0106] Procedure 700 can be continued by the receiver of the disable command disabling a decoding operation for the communication link (step 712). In some embodiments, the receiver of the disable command can disable its FEC decoder for communications relating to the communication link while the communication link is in a sleep state.

[0107] The communication link can remain in an active state even when the decoding process for the communication link is disabled (step 716). Additionally, the communication link can be maintained as a healthy link while it is in the idle state (step 720). In some embodiments, the decoding process can be disabled for as long as the communication link is in the idle state.

[0108] The present disclosure includes processes with fewer than all of those in Fig. 5 to 7 identified steps (and the corresponding descriptions of procedures 500, 600 and 700) as well as procedures that include additional steps beyond those in Fig. The present disclosure includes steps 5 to 7 identified herein (and the corresponding descriptions of processes 500, 600 and 700). It also includes processes that comprise one or more steps from the processes described herein and one or more steps from another process described herein.

[0109] With reference to Fig. Section 8 now describes additional details regarding the possible states of a node 103, 106 according to at least some embodiments of the present disclosure. The Fig.The eight depicted states can include states associated with a sender node. A first state 804 can correspond to a linking state in which the sender node is connected to a receiver node via a communication link, and at least some data is transmitted between the nodes via the communication link. The sender node can remain in the first state 804 unless and until it is determined that the communication link has entered or is about to enter a rest state (e.g., an L0 rest state).

[0110] In response to the communication link entering a sleep state, the sending node can enter a second state, 808. In this second state, the sending node can stop transmitting packets or data traffic over the communication link. From the second state, 808, the sending node can return to the first state, 804, if the communication link is no longer in a sleep state. While the sending node is in the second state, 808, the receiving node can remain in a normal operating state.

[0111] The sending node can also transition from the second state 808 to a third state 812 if the communication has become empty (e.g., if no additional blocks or data are being transmitted over the communication link). In the third state 812, the sending node can send a command to the receiving node indicating a wish to disable encoding / decoding operations for the communication link. The command may include a disable command described herein, which contains a countdown for the devices to synchronize when their respective encoding / decoding functions are disabled.

[0112] The sending node can transition from the third state 812 to the fourth state 816 when the countdown associated with the synchronization counter has expired. In the fourth state 816, the sending node no longer transmits any data or packets to the receiving node via the communication link, and the encoding / decoding operations associated with the communication link have been deactivated.

[0113] The sending node can then enter a fifth state 820 in response to a sleep timer reaching its maximum value (e.g., or shutting down). Alternatively or additionally, the sending node can enter the fifth state 820 in response to a detection that data should be transmitted via the communication link. The fifth state 820 can correspond to a wake-up state, in which the sending node begins the process of waking up and reactivating the encoding / decoding functionality for the communication link. In this wake-up state, the sending node can send an activation command to the receiving node, specifying a number of blocks to be transmitted before the communication link encoding process is activated. The activation command can cause the receiving node to activate its decoding operations after the specified number of blocks has been received from the sending node.

[0114] The transmitting node can then enter a sixth state, 824, after the specified number of blocks have been transmitted. In the sixth state, 824, a complete link is established between the transmitting and receiving nodes, and the encoding / decoding processes for the communication link are resumed.

[0115] Specific details were provided in the description to facilitate a thorough understanding of the embodiments. However, it will be clear to the average person skilled in the art that the embodiments can also be implemented without these specific details. In other cases, known circuits, processes, algorithms, structures, and techniques can be presented without unnecessary details so as not to obscure the embodiments.

[0116] While illustrative embodiments of the disclosure have been described in detail here, it is understood that the inventive concepts may be embodied and used in other ways, and that the appended claims are to be interpreted as including such variations, provided they are not limited by the prior art. It is understood that each feature described herein may be claimed in combination with one or more other features described herein, irrespective of whether the features originate from the same described embodiment.

[0117] It is understood that the aspects and embodiments described above are only exemplary and that changes can be made in detail within the scope of the claims.

[0118] Each device, method and feature disclosed in the description and (if applicable) in the claims and drawings can be provided independently or in any suitable combination.

[0119] Reference numerals contained in the claims serve only for illustration and do not have a limiting effect on the scope of the claims.

Claims

[1] Device comprising one or more circuits for: Determine that a communication link between a first communication node and a second communication node is in a link resting state; and Transmitted, in response to the finding that the communication link is in a linking idle state, a disable command to the first communication node and / or the second communication node, wherein the disable command causes a receiver of the same to disable part of an encoding operation for the communication link. [2] Device according to claim 1, wherein, in response to the receipt of a state update from a power management controller, it is determined that the communication link is in the linking idle state. [3] Device according to claim 1 or 2, wherein the first communication node comprises a transmitter node, wherein the second communication node comprises a receiver node and wherein communication between the first communication node and the second communication node is unidirectional. [4] Device according to claim 3, wherein the transmitting node transmits the deactivation command to the receiving node in response to the finding that the communication link is in a sleep state. [5] Device according to claim 4, wherein the one or more circuits further serve to: Determine that all pending traffic between the first communication node and the second communication node has been transferred, so that the communication link is empty; and After determining that the communication link is in a linking idle state and empty, the deactivation command is transmitted from the sending node to the receiving node. [6] Device according to a previous claim, wherein the part of the encoding process includes error correction decoding. [7] Device according to a previous claim, wherein the encoding process comprises FEC (Forward Error Correction) encoding and / or FEC decoding. [8] Device according to a previous claim, wherein the part of the encoding process includes error correction encoding. [9] Device according to a previous claim, wherein the one or more circuits further serve to: Determine that the communication link is exiting its inactive state; and Transmitted, in response to the detection that the communication link is exiting the linking sleep state, an activation command is sent to the first communication node and / or the second communication node, the activation command causing the receiver of the same to activate the portion of the communication link encoding process that was interrupted in response to the receipt of the deactivation command. [10] Device according to claim 9, wherein the activation command specifies a number of blocks to be transmitted prior to the activation of the encoding process for communication linking. [11] Device according to a previous claim, wherein the communication link remains in an active state even when the part of the encoding process is deactivated. [12] Device according to a previous claim, wherein the deactivation command is contained in an in-band communication between both sides of the communication link. [13] Device according to a previous claim, wherein the communication link is maintained as an error-free link in the linking rest state. [14] Communication node comprising the following: a port that facilitates interconnectivity with a communications network; and one or more circuits for: Establishing a communication link with a receiver node via the port; Determine that the communication link is in a linking dormant state; and Transferred, in response to the finding that the Communication linking in linking quiescent state is a disable command to the receiver node, where the disable command causes the receiver node to disable a decoding operation for the communication linking. [15] Communication node according to claim 14, wherein, in response to receiving a state update from a power management controller, it is determined that the communication link is in the linking idle state. [16] Communication node according to claim 14 or 15, wherein the one or more circuits further serve to: Determine that all pending traffic has been transferred to the receiving node, so the communication link is empty; and After determining that the communication link is in a linking idle state and empty, the deactivation command is transmitted to the receiver node. [17] Communication node according to claim 14, 15 or 16, wherein the decoding process includes error correction decoding. [18] Communication node according to one of claims 14-17, wherein the one or more circuits further serve to: Determine that the communication link is exiting its inactive state; and In response to the detection that the communication link is exiting the linking sleep state, an activation command is sent to the receiver node, causing the receiver node to activate the decoding process. [19] Communication node according to claim 18, wherein the activation command specifies a number of blocks to be transmitted prior to the activation of an encoding process for communication linking. [20] Communication node comprising the following: a port that facilitates interconnectivity with a communications network; and one or more circuits for: Establishing a communication link with a sender node via the port; Received, via the port, a disable command indicating that the communication link is in a linking idle state; and Disable, in response to receiving the disable command, a decoding process for the communication link. [21] Communication node according to claim 20, wherein the communication link remains in an active state even when the decoding process is deactivated, wherein the communication link is unidirectional.

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