PHASE-CHANGING MATERIAL DEVICE AND METHOD FOR ITS FORMATION

Abstract

A phase-change storage device can be provided by: forming a bottom electrode, a layer of dielectric material, and a via opening that extends through the layer of dielectric material such that a top segment of the bottom electrode is exposed below the via opening; forming a tubular dielectric spacer in a peripheral region of the via opening; depositing a continuous layer stack comprising a heater lining layer, a phase-change material layer including a phase-change material, and a material layer for the top electrode above the layer of dielectric material and the tubular dielectric spacer; and structuring the continuous layer stack into a layer stack comprising a heater lining, a phase-change material section, and a top electrode.

Description

RELATED REGISTRATIONS

[0001] This application claims priority over the preliminary US application No. 63 / 711,791 entitled “Phase Change Memory Device and Methods for Manufacturing the Same”, which was filed on October 25, 2024, and the entire contents of which are hereby incorporated by reference into the present text for all purposes. BACKGROUND

[0002] Phase change material (PCM) devices can be used for memory-based computing applications due to their scalability and non-volatility. However, the manufacturing process sequence for PCM devices requires many processing steps. One of the time-consuming and costly processing steps involves the formation of bottom electrodes and heating elements using a chemical-mechanical polishing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood with reference to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. The dimensions of the various structural elements may be enlarged or reduced as necessary for the sake of clarity in this discussion. Fig. Figure 1 is a vertical cross-sectional view of an intermediate structure of a first embodiment after the formation of field-effect transistors, metal interconnect structures and layers of dielectric material according to an embodiment of the present disclosure. Fig. Figure 2 is a vertical cross-sectional view of the intermediate structure of the first embodiment after the formation of via openings through a layer of dielectric material according to an embodiment of the present disclosure. Fig. Figure 3 is a vertical cross-sectional view of the intermediate structure of the first embodiment after the formation of a layer of dielectric spacer material according to an embodiment of the present disclosure. Fig. Figure 4 is a vertical cross-sectional view of the intermediate structure of the first embodiment after the formation of tubular dielectric spacers according to an embodiment of the present disclosure. Fig. Figure 5 is a vertical cross-sectional view of the intermediate structure of the first embodiment after the formation of a continuous layer stack comprising a heating lining layer, a phase change material layer and a material layer for the upper electrode according to an embodiment of the present disclosure. Fig. Figure 6 is a vertical cross-sectional view of the intermediate structure of the first embodiment after structuring the continuous layer stack into layer stacks in progress, each comprising a heating lining in progress, a phase change material section in progress and an upper electrode in progress according to an embodiment of the present disclosure. Fig. Figure 7 is a vertical cross-sectional view of the intermediate structure of the first embodiment after the formation of a side wall lining layer according to an embodiment of the present disclosure. Fig. Figure 8 is a vertical cross-sectional view of the intermediate structure of the first embodiment after the formation of side wall linings in progress according to an embodiment of the present disclosure. Fig. Figure 9 is a vertical cross-sectional view of the intermediate structure of the first embodiment after structuring the layer stacks under construction into layer stacks, each comprising a heating lining, a phase change material section and an upper electrode, and structuring the side wall linings under construction into side wall linings according to an embodiment of the present disclosure. Fig. Figure 10 is a vertical cross-sectional view of the structure of the first embodiment after removal of a structured etching mask layer according to an embodiment of the present disclosure. Fig. Figures 11A-11C illustrate successive top views of a region of a first device of the structure of the first embodiment during the processing steps of Fig. 8 - 10. Fig. Figures 12A-12C illustrate successive top views of a region of a second device of the structure of the embodiment during the processing steps of Fig. 8 - 10. Fig. Figures 13A-13C illustrate successive top views of a region of a third device of the structure of the embodiment during the processing steps of Fig. 8 - 10. Fig. Figure 14 illustrates a top view of a region of a fourth device of the structure of the embodiment after the processing steps of Fig. 8. Fig. Figure 15 is a vertical cross-sectional view of the structure of the first embodiment after the formation of a dielectric encapsulation layer and additional metal interconnect structures according to an embodiment of the present disclosure. Fig. 16A - 16D are different arrangements of a phase-change memory cell in different programmed resistance states according to an embodiment of the present disclosure. Fig. Figure 17 is a vertical cross-sectional view of an intermediate structure of a second embodiment after the deposition of a heating lining layer according to an embodiment of the present disclosure. Fig. Figure 18 is a vertical cross-sectional view of the intermediate structure of the second embodiment after the vertical recession of the heating lining layer according to an embodiment of the present disclosure. Fig. Figure 19 is a vertical cross-sectional view of the intermediate structure of the second embodiment after the deposition of a phase change material layer and a material layer for the upper electrode according to an embodiment of the present disclosure. Fig. Figure 20 is a vertical cross-sectional view of the intermediate structure of the second embodiment after the formation of layer stacks in progress, each comprising a heating lining in progress, a phase change material section in progress and an upper electrode in progress according to an embodiment of the present disclosure. Fig. Figure 21 is a vertical cross-sectional view of the structure of the second embodiment after the formation of the dielectric encapsulation layer and the additional metal interconnect structures according to an embodiment of the present disclosure. Fig. Figure 22 is a vertical cross-sectional view of an intermediate structure of a third embodiment after the deposition of a heating lining layer according to an embodiment of the present disclosure. Fig. Figure 23 is a vertical cross-sectional view of the intermediate structure of the third embodiment after the deposition of a phase change material layer and a material layer for the upper electrode according to an embodiment of the present disclosure. Fig. Figure 24 is a vertical cross-sectional view of the intermediate structure of the third embodiment after the formation of layer stacks in progress, each comprising a heating lining in progress, a phase change material section in progress and an upper electrode in progress according to an embodiment of the present disclosure. Fig. Figure 25 is a vertical cross-sectional view of the structure of the third embodiment after the formation of the dielectric encapsulation layer and the additional metal interconnect structures according to an embodiment of the present disclosure. Fig. Figure 26 is a first flowchart illustrating general processing steps for manufacturing a device structure according to embodiments of the present disclosure. Fig. Figure 27 is a second flowchart illustrating general processing steps for manufacturing a device structure according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to illustrate the present disclosure. These are merely examples and not limitations. The drawings are not drawn to scale. Elements with the same reference numerals refer to the same element, and it is assumed that they have the same material composition and thickness range unless expressly stated otherwise. It is assumed that all features of an original embodiment are present in every derived embodiment unless expressly stated otherwise.Thus, features described in the drawings and / or description with reference to related embodiments serve to support features in an embodiment. Embodiments in which multiple instances of a described element are repeated are expressly considered unless expressly stated otherwise. Embodiments in which non-essential elements are omitted are expressly considered, even if such embodiments are not expressly disclosed but are known in the prior art.

[0005] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, can be used in this text to simplify the description and to describe geometric features between elements, as illustrated in the figures. A first physical element is "embedded" in a second physical element if the entire volume of the first element is contained within a hypothetical volume defined by a set of hypothetical surfaces that have the smallest total surface area among all sets of hypothetical surfaces containing the entirety of the exterior surfaces of the second element and that are topologically homeomorphic to the surface of a sphere. Such a set of hypothetical surfaces covers any opening, if any, in the exterior surfaces with a surface segment of the smallest possible area among all possible opening-free surface segments.The spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text can be interpreted accordingly. Unless explicitly stated otherwise, it is assumed that each element with the same reference number has the same material composition and a thickness within the same thickness range.

[0006] Phase change memory (PCM) devices can be used in various applications due to their scalability and non-volatility. However, the complexity of the PCM manufacturing process can present challenges. For example, heating elements are typically manufactured using a chemical-mechanical polishing (CMP) process. The CMP process not only requires expensive equipment and consumables but also demands strict process controls, which can lead to longer production times and / or reduced production yield.

[0007] Various embodiments of the present disclosure provide sequences of manufacturing steps for producing phase-change storage devices (PCM devices) while simultaneously reducing complexity and processing costs. More specifically, the disclosed sequences of manufacturing steps provide methods for producing PCM devices without using a CMP process. More precisely, a heating liner contacting a bottom surface of a phase-change material section is used to provide a dual function as a heating element and a heating liner for the phase-change material section.The heater lining can be formed by: providing a narrow via opening in a layer of dielectric material, by filling all or a peripheral region of the via opening with a heater lining layer, and by subsequently structuring the heater lining layer. A phase-change material layer and a top electrode material layer can be deposited over the heater material layer, and the heater lining layer, the phase-change material layer, and the top electrode material layer can be structured using the same masking structure. The heater lining comprises a vertically extending section formed within the via opening and a horizontally extending section that lies above the layer of dielectric material.A sidewall lining can be formed on each layer stack of a heating lining, a phase change material section, and a top electrode to provide a phase change storage cell. Thus, the phase change storage cell can be manufactured without the use of a costly CMP process.

[0008] Prior to the formation of the heater lining, a tubular dielectric spacer can be formed in the via hole. In one embodiment, a void in the tubular dielectric spacer can be so narrow that it is completely filled during the deposition of the heater lining layer. In another embodiment, the void in the tubular dielectric spacer can be wider than twice the target thickness of a horizontally extending section of a subsequently formed heater lining, and a combination of overdeposition and indentation etching can be used to provide the target thickness for the horizontally extending section of the heater lining while the void in the via hole is being filled.In a further embodiment, the void in the tubular dielectric spacer can be wider than twice the nominal thickness of a heating element lining, and a remaining portion of the void can be filled with a vertically extending section of the phase-change material. The various embodiments of the present disclosure are now described with reference to the accompanying drawings.

[0009] With reference to Fig. Figure 1 illustrates a first embodiment according to the present disclosure. The first embodiment comprises a substrate 8, which may be a semiconductor substrate, such as a commercially available silicon substrate. The substrate 8 may have a semiconductor material layer 9, at least in its upper section. The semiconductor material layer 9 may be a surface section of a bulk semiconductor substrate or may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 contains a single-crystal semiconductor material, such as single-crystal silicon. In another embodiment, the substrate 8 may be a single-crystal silicon substrate containing a single-crystal silicon material.

[0010] Flat trench insulation structures 720, containing a dielectric material such as silicon oxide, can be formed in an upper section of the semiconductor material layer 9. Suitable doped semiconductor wells, such as p-wells and n-wells, can be formed within any region laterally enclosed by a section of the flat trench insulation structures 720.

[0011] Semiconductor devices 700 can be formed on the semiconductor material layer 9. The semiconductor devices 700 can comprise complementary metal-oxide-semiconductor transistors (CMOS transistors) and optionally additional semiconductor devices (such as resistors, diodes, capacitor structures, etc.). The semiconductor devices 700 can include programming transistors 701 formed in a memory array region 100 and peripheral transistors 702 formed in a boundary region 300. Each field-effect transistor (701, 702) can comprise a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. In one embodiment, the channel region can comprise a portion of the semiconductor material layer 9 and can include a single-crystal semiconductor material.Each of the 701 programming transistors can be configured to provide a set of programming pulses for a specific phase-change memory cell to be subsequently created. The 702 peripheral transistors can be configured as components of a peripheral circuit that controls the operation of the 701 programming transistors and is connected to an input / output (I / O) circuit (not illustrated).

[0012] In one embodiment, the substrate 8 can comprise a substrate of single-crystal silicon, and the field-effect transistors (701, 702) can each have a section of the single-crystal silicon substrate as a semiconducting channel. For the purposes of this text, a “semiconducting” element refers to an element with an electrical conductivity in the range of 1.0 × 10⁻⁶. -6 S / cm up to 1.0 × 10 5S / cm. For the purposes of this text, a "semiconductor material" refers to a material with an electrical conductivity in the range of 1.0 × 10 -6 S / cm up to 1.0 × 10 5 S / cm in the absence of electrical dopants in the material and is able to create a doped material with an electrical conductivity in the range of 1.0 S / cm to 1.0 × 10 5 S / cm can be produced with suitable doping using an electrical dopant.

[0013] Various metal interconnect structures formed within layers of dielectric material can subsequently be formed over the substrate 8 and the semiconductor devices. In an illustrative example, the layers of dielectric material can, for instance, include: a first layer 601 of dielectric material, which can be a layer surrounding the contact structure connected to the source and drains (sometimes referred to as a contact-level dielectric layer 601); a first interconnect-level dielectric layer 610; a second interconnect-level dielectric layer 620; a third interconnect-level dielectric layer 630; and a fourth interconnect-level dielectric layer 640. The metal interconnect structures can include: device contact via structures 612,which are formed in the first layer 601 from dielectric material and contact a respective component of the semiconductor devices 700, first metal conductor structures 618 formed in the first layer 610 from dielectric material at the interconnect level, first metal via structures 622 formed in a lower section of the second layer 620 from dielectric material at the interconnect level, second metal conductor structures 628 formed in an upper section of the second layer 620 from dielectric material at the interconnect level, second metal via structures 632 formed in a lower section of the third layer 630 from dielectric material at the interconnect level, and third metal conductor structures 638 formed in an upper section of the third layer 630 from dielectric material at the interconnect level. An additional layer of dielectric material,The layer 641, referred to in the present text as a lower fourth layer of dielectric material at the interconnect level, can be formed above the third layer 630 of dielectric material at the interconnect level.

[0014] Each of the dielectric material layers (601, 610, 620, 630, 641) can contain a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (612, 618, 622, 628, 632, 638) can contain at least one conductive material, which may be a combination of a metallic lining layer (such as a metallic nitride or a metallic carbide) and a metallic filler material. Each metallic lining layer can contain TiN, TaN, WN, TiC, TaC, and WC, and each metallic filler material can contain W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof.In one embodiment, the first metal via structures 622 and the second metal conductor structures 628 can be formed as integrated conductor and via structures by a dual damascening process. In general, any connected set of a metal conductor structure (628, 638) and at least one underlying metal via structure (622, 632) can be formed as an integrated conductor and via structure.

[0015] In general, semiconductor devices (such as field-effect transistors (701, 702)) can be formed on a substrate 8, and metal interconnect structures (612, 618, 622, 628, 632, 638) and layers (601, 610, 620, 630, 641) of dielectric material can be formed over the semiconductor devices. The metal interconnect structures (612, 618, 622, 628, 632, 638) can be formed in the layers (601, 610, 620, 630, 641) of dielectric material and can be electrically connected to the semiconductor devices.

[0016] A subset of the metal interconnect structures (612, 618, 622, 628, 632, 638) located within a layer of dielectric material beneath a topmost dielectric layer can comprise lower electrodes 38 (formed as a section of the metal interconnect structure 638) of subsequent phase-change memory cells. In an illustrative example, a subset of the third metal interconnect structures 638 can comprise a two-dimensional array of lower electrodes 38 for the array of subsequent phase-change memory cells. The lower electrodes 38 can be formed within a layer of dielectric material (such as a third layer 630 of dielectric material at the interconnect level) located beneath a topmost layer of dielectric material (such as a lower fourth layer 641 of dielectric material at the interconnect level).The lower electrodes 38 comprise at least one metal with high electrical conductivity. For example, the lower electrodes 38 may include a metal component containing copper, aluminum, or tungsten. Optionally, the lower electrodes 38 may include a metallic barrier lining containing a metallic barrier material such as TiN, TaN, WN, and / or MoN.

[0017] In summary, programming transistors 701 can be formed on a substrate 8. Metal interconnect structures (612, 618, 622, 628, 632, 638), formed within layers (601, 610, 620, 630, 641) of dielectric material at the interconnect level, can be formed over the programming transistors 701. The metal interconnect structures (612, 618, 622, 628, 632, 638) can be configured to be electrically connected to heating elements of subsequently formed phase-change memory cells.

[0018] According to one aspect of the present disclosure, the programming transistors 701 can be configured to program each of the phase-change memory cells into at least two different resistance states, and preferably into at least three different resistance states, and particularly preferably into at least four different resistance states. The programming of each phase-change memory cell into different resistance states can be accomplished by selecting a pulse pattern from a set of pre-programmed pulse patterns that each programming transistor 701 can apply. The pulse patterns can differ from one another with respect to the duration of a pulse pattern and the peak voltage of the pulse pattern.In one embodiment, the total number of resistance states into which a phase-change memory cell can be programmed may be in a range of 2 to 64, such as 3 to 16 and / or 4 to 8, although a larger number of resistance states may be programmed as required by changing the pulse pattern generated by each programming transistor 701.

[0019] With reference to Fig. 2. Via holes 41 can be formed through the top layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level). Each via hole 41 can be formed over one of the underlying metal interconnect structures (such as a subset of the third metal conductor structures 638), so that top-side segments of the underlying metal interconnect structures are physically exposed. The layer of dielectric material through which the via holes 41 are formed comprises a heat-resistant dielectric material, such as undoped silicate glass or doped silicate glass. The thickness of the dielectric material layer can be in the range of 200 nm to 1,000 nm, although smaller or larger thicknesses can also be used.The lateral dimension (such as the diameter) of the lower section of each via hole 41 can be in a range of 50 nm to 400 nm, although smaller or larger lateral dimensions can also be used.

[0020] In general, the lower electrodes 38, a layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level) and the via openings 41 extending through the layer of dielectric material can be formed such that a top segment of each lower electrode 38 is exposed below each via opening 41.

[0021] With reference to Fig. 3. A dielectric spacer material can be conformally deposited in the edge regions of the vias 41 and above the layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level) that surrounds the vias 41 and forms a layer 42L of dielectric spacer material. The dielectric spacer material of layer 42L can have a thermal conductivity of less than 40 W / m·K. For example, the dielectric spacer material of layer 42L can comprise silicon oxide, silicon nitride, aluminum oxide, silicon carbide nitride, or a combination thereof. In one embodiment, the dielectric spacer material of layer 42L can consist essentially of silicon oxide having a thermal conductivity in the range of 1.1 W / m·K to 1.4 W / m·K.In general, the dielectric spacer layer 42L can have the same material composition as, or a different material composition than, the dielectric layer through which the vias 41 extend vertically. The dielectric spacer layer 42L can be deposited by a conformal deposition process, such as a chemical vapor deposition process. The top surface of the dielectric spacer layer 42L can include annular convex surface segments that form around the upper edges of the vias 41 due to the isotropic nature of the deposition process that forms the dielectric spacer layer 42L.

[0022] According to one aspect of the present disclosure, the thickness of the layer 42L of dielectric spacer material is selected such that the difference between the width of the lower section of each via opening 41 and twice the thickness of the layer 42L of dielectric spacer material is within a target range for the width of the lower section of each vertically extending section of a subsequently formed heater lining layer.In an illustrative example, in cases where the width of the lower section of each via opening 41 is in a range of 50 nm to 400 nm, and if the desired range for the width of the lower section of each vertically extending section of a subsequently formed heating lining layer is in a range of 20 nm to 100 nm, the thickness of the layer 42L of dielectric spacer material can be in a range of 15 nm to 150 nm, such as 30 nm to 80 nm, although smaller or larger thicknesses can also be used.

[0023] With reference to Fig. 4. An anisotropic etching process can be performed to anisotropically etch horizontally extending sections of the layer 42L of dielectric spacer material. Each remaining vertically extending section of the layer 42L of dielectric spacer material, which remains in a marginal region of a respective via opening 41, forms a tubular dielectric spacer 42 with a tubular arrangement. According to one aspect of the present disclosure, a central section of the top-end segment of an underlying lower electrode 38 can be exposed under each vacancy that is laterally surrounded by a respective tubular dielectric spacer 42.

[0024] Each tubular dielectric spacer 42 may comprise an outer cylindrical side wall having an outer cone angle in a range of 0 degrees to 15 degrees, such as 1 degree to 5 degrees, with respect to the vertical direction. For the purposes of this text, a “cylindrical side wall” refers to any side wall that has a closed perimeter in a horizontal cross-sectional view and extends vertically with or without a cone angle with respect to a vertical direction. Each tubular dielectric spacer 42 may also comprise an inner cylindrical side wall having an inner cone angle in a range of 0 degrees to 15 degrees, such as 1 degree to 5 degrees, with respect to the vertical direction. The inner cone angle may be the same as, or approximately the same as, the outer cone angle.In one embodiment, each tubular dielectric spacer 42 comprises an annular convex surface segment bordering an upper circumference of the inner cylindrical side wall of the via openings 41.

[0025] With reference to Fig. 5 A metallic heating material can be deposited in the vacancies laterally surrounded by the tubular dielectric spacers 42 and above the layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level) through which the via openings 41 extend vertically. The deposited metallic heating material forms a heating lining layer 52L, which is a lining layer containing the metallic heating material. The metallic heating material has a higher electrical conductivity than the metallic material of the lower electrodes 38. In one embodiment, the heating lining layer 52L comprises a first metallic nitride material, which can be a stoichiometric or near-stoichiometric metallic nitride material. For example, the heating lining layer 52L can comprise TaN, TiN, WN, and / or MoN.In one embodiment, the electrical conductivity of the metallic material of the heating lining layer 52L can be in a range of 1.0 × 10. 3 S / cm up to 1.0 × 10 5 The metallic heating material can be deposited by chemical or physical vapor deposition. In one embodiment, the metallic heating material can comprise a stoichiometric or near-stoichiometric metallic nitride material, such as stoichiometric or near-stoichiometric TiN, TaN, WN and / or MoN.

[0026] In one embodiment, a conformal deposition process, such as a chemical vapor deposition process, can be used to deposit the metallic heating material of the heating lining layer 52L. According to one aspect of the present disclosure, the duration of the deposition process depositing the heating lining layer 52L can be selected such that a predominant fraction and / or all of the volume of each vacancy within the via openings 41 is filled with the deposited material of the heating lining layer 52L. The thickness of the horizontally extending section of the heating lining layer 52L is selected such that structured sections of the heating lining layer 52L can provide electrical resistance to subsequently formed phase storage cells during operation.The thickness of the horizontally extending section of the heating lining layer 52L, which is deposited above the top of the layer of dielectric material through which the via openings 41 extend vertically, can be in a range of 10 nm to 80 nm, such as 20 nm to 50 nm, although smaller or larger thicknesses can also be used.

[0027] In general, the heater lining layer 52L can be deposited within a fraction of the volume of each via hole 41 through a layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level) and over the horizontal top surface of the dielectric material layer. After deposition of the heater lining layer 52L, the heater lining layer 52L comprises a planar horizontal surface segment PHSS that lies above the dielectric material layer and further comprises annular convex surface segments ACSS that border the perimeter of a respective hole in the planar horizontal surface segment PHSS and lie above each of the via holes 41.The formation of the ring-shaped convex surface segments ACSS is due to the isotropic nature of the deposition process used to deposit the heating lining layer 52L.

[0028] The heater lining layer 52L comprises vertically extending sections deposited in the vacancies within the tubular dielectric spacers 42 and a horizontally extending section deposited above the top surface of the dielectric material layer (such as the lower fourth layer 641 of dielectric material at the interconnect level). The heater lining layer 52L at least partially fills each vacancy within the via openings 41. In one embodiment, the maximum width (such as the width in the horizontal plane, including the top surface of the dielectric material layer) of each vacancy can be less than half the thickness of the heater lining layer 52L, measured along the horizontally extending section of the heater lining layer 52L that lies above the dielectric material layer.In one embodiment, a vertically extending seam S is formed in the center of each void, which is filled with a respective vertically extending section of the heating lining layer 52L. Each vertically extending seam S can be formed in the center of a respective vertically extending section of the heating lining layer 52L. In one embodiment, the heating lining layer 52L is deposited on each physically exposed central section of the top surface segments of the lower electrodes 38.

[0029] A phase-change material layer 54L can be deposited on all physically exposed surfaces of the heating lining layer 52L. Thus, the phase-change material layer 54L is deposited directly on the planar horizontal surface segment PHSS of the heating lining layer 52L, which lies above a horizontal plane that includes a top surface of the layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level), and directly on each annular convex surface segment ACSS of the heating lining layer 52L.

[0030] The phase change material layer 54L comprises, and / or consists essentially of, a phase change material. For the purposes of this text, "phase change material" refers to a material that has at least two distinct phases, each providing different resistivities. A phase change material (PCM) can be used to store information as a state of resistivity of a material that can exist in different resistivity states corresponding to the different phases of the material. The different phases can include an amorphous state with high resistivity and a crystalline state with low resistivity (that is, a lower resistivity than in the amorphous state).The transition between the amorphous and crystalline states can be induced by controlling the cooling rate after applying an electrical pulse that renders the phase-change material amorphous in the first part of a programming process. The second part of the programming process involves controlling the cooling rate of the phase-change material. In embodiments where rapid quenching occurs, the phase-change material can cool to an amorphous state with high resistivity. In embodiments where slow cooling occurs, the phase-change material can cool to a crystalline state with low resistivity.

[0031] Examples of phase-change materials include germanium-antimony-telluride compounds (GST compounds) such as Ge₂Sb₂Te₅ or GeSb₂Te₄, germanium-antimony compounds, indium-germanium-telluride compounds, aluminum-selenium-telluride compounds, indium-selenium-telluride compounds, and aluminum-indium-selenium-telluride compounds. In one embodiment, the phase-change material of the phase-change material layer 54L can comprise a doped GST compound such as N-doped GST, Si-doped GST, C-doped GST, Ge-doped GST, Ru-doped GST, or Al-doped GST, or a doped GeTe compound such as N-doped GeTe, Si-doped GeTe, C-doped GeTe, or Ge-doped GeTe. The phase change material layer 54L can be deposited by physical vapor deposition.The thickness of the phase-change material layer 54L can be in a range of 30 nm to 200 nm, for example from 50 nm to 90 nm, although smaller or larger thicknesses can also be used. In one embodiment, the phase-change material of the phase-change material layer can be selected such that the electrical conductivity of the amorphous phase of the phase-change material is in a range of 1.0 × 10⁻⁶. -8 S / cm up to 1.0 × 10 -3 S / cm, while the electrical conductivity of the crystalline phase of the phase change material is in the range of 1.0 × 10 -1 S / cm up to 1.0 × 10 3 S / cm lies.

[0032] The 56L material layer for the upper electrode comprises a metallic material such as tungsten, tantalum, titanium, molybdenum, tungsten, tungsten, or molybdenum. The 56L material layer for the upper electrode can have a thickness ranging from 100 nm to 200 nm, although thinner or thicker layers are also possible. The 56L material layer for the upper electrode can be deposited by chemical or physical vapor deposition.

[0033] In general, a continuous layer stack (52L, 54L, 56L) comprising a heater lining layer 52L, a phase-change material layer 54L including a phase-change material, and a material layer 56L for the upper electrode can be deposited over the layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level) and the tubular dielectric spacers 42. The heater lining layer 52L can be deposited directly onto the layer of dielectric material through which the vias 41 extend vertically, and directly onto the tubular dielectric spacers 42 located in the edge regions of the vias 41.

[0034] With reference to Fig. 6. A first structuring process can be performed to structure the continuous layer stack (52L, 54L, 56L) into layer stacks (52', 54', 56') under construction. More precisely, a first structured etch mask layer 77 can be formed over the continuous layer stack (52L, 54L, 56L). For example, the first structured etch mask layer 77 can be formed by depositing a photoresist layer over the continuous layer stack (52L, 54L, 56L) and lithographically structuring the photoresist layer into an array of discrete structured photoresist material sections. In one embodiment, the first structured etch mask layer 77 can comprise a two-dimensional array, such as a two-dimensional rectangular periodic array, of structured photoresist material sections located in the memory array region 100.In one embodiment, each structured photoresist material section can have a rectangular horizontal cross-sectional shape. In another embodiment, the lateral dimensions of each structured photoresist material section can be selected such that at least two phase-change memory cells are structured in subsequent processing steps. Alternatively, the lateral dimensions of each structured photoresist material section can be selected such that a single phase-change memory cell is structured in subsequent processing steps.

[0035] A first anisotropic etching process can be performed to etch sections of the continuous layer stack (52L, 54L, 56L) that are not masked by the first structured etch mask layer 77. The first anisotropic etching process features an etching chemistry that selectively etches the materials of the continuous layer stack (52L, 54L, 56L) to the material of the dielectric layer (such as the lower fourth layer 641 of dielectric material at the interconnect level) that embeds the tubular dielectric spacers 42. The continuous layer stack (52L, 54L, 56L) is structured into layer stacks in progress (52', 54', 56'), each comprising a heating lining in progress 52', a phase change material section in progress 54' and an upper electrode in progress 56'.For the purposes of this text, an "element under processing" refers to an element that is modified in its structure and / or composition in a subsequent processing step. Each heating lining 52' under processing can be a structured section of the heating lining layer 52L. Each phase change material section 54' under processing can be a structured section of the phase change material layer 54L. Each upper electrode 56' under processing can be a structured section of the upper electrode material layer 56L.For each layer stack under processing (52', 54', 56'), the side walls of the heating lining 52' under processing can be vertically congruent with the side walls of the phase-change material section 54' under processing, and can be vertically congruent with the side walls of the upper electrode 56' under processing. For the purposes of this text, a first surface is "vertically congruent" with a second surface, wherein the second surface lies above or below the first surface, and wherein the first surface and the second surface are within the same vertical plane, which may be planar or curved in a horizontal cross-sectional view. The first structured etch mask layer 77 can subsequently be removed, for example, by ashenation.

[0036] With reference to Fig. 7 and according to one aspect of the present disclosure, a sidewall lining layer 58L can be deposited on the physically exposed surfaces of the layer stacks (52', 54', 56') under construction and on the physically exposed top surface of the layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level) that embeds the lower electrodes 38 and the tubular dielectric spacers 42. In one embodiment, the sidewall lining layer 58L can comprise a metallic nitride material layer deposited by a conformal deposition process, such as a chemical vapor deposition process. In another embodiment, the sidewall lining layer 58L can comprise a second metallic nitride material that may comprise and / or substantially consist of TiN, TaN, WN and / or MoN.The thickness of the sidewall lining layer 58L can be in a range of 1 nm to 20 nm, such as 2 nm to 4 nm, although smaller or larger thicknesses can also be used.

[0037] According to one aspect of the present disclosure, the electrical conductivity of the second metallic nitride material can be reduced by incorporating carbon or nitrogen atoms into the metallic nitride material layer by in-situ or ex-situ doping of carbon or nitrogen atoms, that is, by incorporating the carbon or nitrogen atoms during or after the deposition of the sidewall lining layer 58L. For example, the carbon or nitrogen atoms can be provided by a reactive carbon-containing gas (such as acetylene or ethylene) or a reactive nitrogen-containing gas (such as ammonia) during a chemical evaporation process that deposits the sidewall lining layer 58L.Alternatively, after the deposition process, the sidewall lining layer 58L can be exposed to an environment containing reactive carbon-containing or reactive nitrogen-containing species at an elevated temperature. As a further alternative, an ion implantation or plasma doping process can be performed after the deposition process.

[0038] The carbon atoms or the nitrogen atoms can be incorporated into the second metallic nitride material of the sidewall lining layer 58L at such an atomic concentration that the electrical conductivity of the doped metallic nitride material of the sidewall lining layer 58L after incorporation of the carbon atoms or the nitrogen atoms is less than 1 / 3 of the electrical conductivity of the second metallic nitride material before incorporation of the carbon atoms or the nitrogen atoms. In an illustrative example, the electrical conductivity of the sidewall lining layer 58L after incorporation of the carbon atoms or the nitrogen atoms can be in the range of 1.0 × 10 1 S / cm up to 1.0 × 10 5 S / cm lie.

[0039] In general, the ratio of metal atoms to nitrogen atoms in a stoichiometric metal compound MN, where M is Ta, Ti, Mo, or W, is 1:1. In embodiments where nitrogen doping is used, when doping a stoichiometric metal compound with nitrogen atoms to form the sidewall lining layer 58L of the present disclosure, the ratio of metal atoms to nitrogen atoms in the sidewall lining layer 58L can be in the range of 1:1.02 to 1:1.05. In embodiments where carbon doping is used, when doping a stoichiometric metal compound with carbon atoms to form the sidewall lining layer 58L of the present disclosure, the ratio of metal atoms to nitrogen atoms to carbon atoms in the sidewall lining layer 58L can be in the range of 1:1:0.02 to 1:1:0.05.In general, the atomic concentration of the additional nitrogen atoms in a nitrogen-doped metallic nitride material can range from 0.02 to 0.05 times the atomic concentration of the metal atoms. Similarly, the atomic concentration of the carbon atoms in a carbon-doped metallic nitride material can range from 0.02 to 0.05 times the atomic concentration of the metal atoms.

[0040] In one embodiment, the second metallic nitride material of the sidewall lining layer 58L, after the doping process, can have an electrical conductivity that is less than 1 / 3 and preferably less than 1 / 10 of the electrical conductivity of the first metallic nitride material of the heating linings 52' under construction. In other words, the heating linings 52' under construction comprise a material with an electrical conductivity that is at least three times and preferably at least ten times the electrical conductivity of the sidewall lining material of the sidewall lining layer 58L.

[0041] In general, the first metallic nitride material of the heater lining layer 52L (and of the heater linings 52' under construction) and the second metallic nitride material (which is a doped metallic nitride material) of the sidewall lining layer 58L can be selected such that the resistance of a heater lining to be structured from a heater lining 52' under construction and the resistance of a sidewall lining to be structured from the sidewall lining layer 58L dominate the resistance of high-resistance states of phase-change material cells, including the high-resistance state and initial resistance states with relatively high resistance values. In this embodiment, the resistance of the amorphous volume of a phase-change material section does not determine the resistance of high-resistance states of a phase-change storage cell.Thus, the phase change storage cell can be operated without impairment due to resistance drift of a phase change material.

[0042] With reference to Fig. 8. An anisotropic etching process can be performed to remove horizontally extending sections of the sidewall lining layer 58L. The anisotropic etching process can be selective for the material of the dielectric layer (such as the lower fourth layer 641 of dielectric material at the interconnect level) that embeds the tubular dielectric spacers 42. Each remaining vertically extending section of the sidewall lining layer 58L forms a sidewall lining 58' in progress, which laterally surrounds a respective layer stack (52', 54', 56') in progress.Each sidewall lining 58' under construction contacts each sidewall of the heater lining 52' under construction, the phase-change material section 54' under construction, and the top electrode 56' under construction of each layer stack (52', 54', 56') under construction. In one embodiment, a top-side segment of each sidewall of the top electrodes 56' under construction may be physically exposed. Generally, a sidewall lining 58' under construction can be formed around each layer stack (52', 54', 56') under construction by conformally depositing and anisotropically etching a layer of the sidewall lining material.

[0043] With reference to Fig. 9 A second structuring process can be carried out to structure the layer stacks (52', 54', 56') and the sidewall linings 58' that are in progress. A second structured etch mask layer 79 can be formed over the layer stacks (52', 54', 56') and the sidewall linings 58' that are in progress in such a way that it covers the first areas of the layer stacks (52', 54', 56') and the sidewall linings 58' that are in progress without covering the second areas of the layer stacks (52', 54', 56') and the sidewall linings 58' that are in progress.For example, a photoresist layer (not shown) can be applied over the layer stacks (52', 54', 56') and the sidewall linings 58' under construction and can be lithographically structured into a two-dimensional array, such as a rectangular array, of structured photoresist material sections. In one embodiment, the second structured etch mask layer 79 can cover at least two discrete regions of each layer stack (52', 54', 56') under construction that are not connected to each other, that is, separated by a gap that is not covered by the second structured etch mask layer 79.

[0044] A second anisotropic etching process can be performed to etch unmasked sections of the layer stacks (52', 54', 56') and the sidewall linings 58' under construction, that is, to etch the sections of the layer stacks (52', 54', 56') and the sidewall linings 58' under construction that are not masked by the second structured etch mask layer 79. The second anisotropic etching process features an etching chemistry that selectively etches the materials of the layer stacks (52', 54', 56') and the sidewall linings 58' under construction for the material of the dielectric layer (such as the lower fourth layer 641 of dielectric material at the interconnect level) that embeds the tubular dielectric spacers 42.

[0045] In one embodiment, the second structuring process can structure any connected combination of a layer stack (52', 54', 56') under construction and a sidewall lining 58' under construction into several discrete material sections that are not interconnected. In one embodiment, each structured section of a layer stack (52', 54', 56') under construction comprises a layer stack having a heating lining 52, a phase-change material section 54, and an upper electrode 56. Each structured section of a sidewall lining 58' under construction forms a sidewall lining 58 according to one embodiment of the present disclosure. A layer stack (52', 54', 56') under construction can be structured into several layer stacks (52, 54, 56).A sidewall lining 58' under construction can be structured into multiple sidewall linings 58. For each layer stack (52, 54, 56), the lateral distance between a sidewall of the layer stack (52, 54, 56) and a proximal sidewall of an underlying heating element 52 can be in a range of 30 nm to 200 nm, such as 50 nm to 150 nm, although smaller or larger lateral distances can also be used.

[0046] In general, at least one sidewall lining 58 can be formed on a sidewall of each layer stack (52, 54, 56), which is a structured section of the continuous layer stack (52L, 54L, 56L), by depositing and structuring a sidewall lining material. The sidewall lining material of the at least one sidewall lining 58 comprises a material with an electrical conductivity higher than that of an amorphous phase of the phase-change material. The sidewall lining material can comprise a metallic nitride material formed by incorporating carbon or nitrogen atoms such that the metallic nitride material has a lower electrical conductivity than a stoichiometric metallic nitride material.Thus, in embodiments where an amorphous phase section of a phase-change material and a sidewall lining 58 provide two parallel electrically conductive paths, the sidewall lining 58 provides a path with lower resistance and predominantly determines the total resistance of the two parallel electrically conductive paths during operation of the phase-change memory cell of the present disclosure. This aspect is particularly useful for operating the phase-change memory cell for computation-in-memory (CIM) applications because the resistance drift effect of the phase-change material during operation of the phase-change memory cell is suppressed.

[0047] With reference to Fig. 10 The second structured etch mask layer 79 can be removed, for example, by ashenation. Each connected combination of a lower electrode 38, a heating liner 52, a phase-change material section 54, an upper electrode 56, and at least one side wall liner 58 forms a phase-change storage cell 50. The vertically extending section of the heating liner 52 acts as a heating element for the phase-change storage cell 50 and provides various types of thermal pulses required to program the phase-change material section 54 to a desired resistance state when a suitable programming pulse, i.e., a pulse of electric current, is applied between the lower electrode 38 and the upper electrode 56.

[0048] In one embodiment, each phase-change memory cell 50 comprises: a tubular dielectric spacer 42 located within a via opening 41 in a layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level); a heater liner 52 comprising a vertically extending section laterally surrounded by the tubular dielectric spacer 42 and a horizontally extending section extending over a top-side segment of the layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level); a phase-change material section 54 comprising a phase-change material contacting a top-side of the heater liner layer 52L; and a top electrode 56 contacting a top-side of the phase-change material section 54.

[0049] In one embodiment, the heating lining 52 comprises a planar horizontal surface segment PHSS that lies above the layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level), and further comprises an annular convex surface segment ACSS that borders a circumferential edge of an opening in the planar horizontal surface segment PHSS and lies above the via opening 41; and the phase change material section 54 contacts the annular convex surface segment ACSS.

[0050] In one embodiment, the vertically extending section of the heater liner 52 comprises a vertically extending seam S; and an upper surface of the heater liner 52 comprises an annular convex surface segment ACSS having a lower apex adjacent to an upper end of the vertically extending seam S. In one embodiment, the phase-change material section 54 comprises a vertically extending section located within a central region of the via opening 41; and the vertically extending section of the heater liner 52 comprises a cylindrical inner sidewall contacting the vertically extending section of the phase-change material section 54.

[0051] In one embodiment, the phase change storage cell 50 comprises at least one side wall lining 58 which is located on at least one side wall of the phase change material section 54, contacts a side wall of the horizontally extending section of the heating lining 52, and comprises a material with an electrical conductivity that is higher than an electrical conductivity of an amorphous phase of the phase change material.

[0052] In general, the reference to Fig. 8 described first structuring process and the one with reference to Fig. 11 described second structuring process uses different combinations of structures to provide an array of phase-change memory cells 50 that has different facilities. Fig. Figures 11A-11C illustrate successive top views of a region of a first device of the structure of an embodiment during the processing steps of Fig. 8 - 10. Fig. Figures 12A-12C illustrate successive top views of a region of a second device of the structure of the embodiment during the processing steps of Fig. 8-10. Fig. Figures 13A-13C illustrate successive top views of a region of a third device of the structure of the embodiment during the processing steps of Fig. 8 - 10. Fig. Figure 14 illustrates a top view of a region of a fourth device of the structure of the embodiment after the processing steps of Fig. 8. The in Fig. The various facilities illustrated in 11A - 14 are merely illustrations describing specific facilities and do not limit the scope of protection of the present disclosure.

[0053] With reference to Fig. 11A is a region of a first device of the structure of an embodiment comprising a layer stack (52', 54', 56') in progress and a side wall lining 58' in progress, in a processing step of Fig. Figure 8 illustrates this. The layer stack under construction (52', 54', 56') can include first side walls parallel to a first horizontal direction hd1 and second side walls parallel to a second horizontal direction hd2. The second horizontal direction hd2 can be perpendicular to the first horizontal direction hd1.

[0054] With reference to Fig. Figure 11B illustrates the region of the first setup of the structure of an embodiment after the formation of the second structured etch mask layer 79 and before the second anisotropic etching process. The second structured etch mask layer 79 can comprise a two-dimensional array, such as a 2 × N array, of structured discrete etch mask material segments (such as structured photoresist material segments) covering 2N segments of the first sidewalls of the layer stack under construction (52', 54', 56'). In the illustrated example, the integer N is 4. In general, the integer N can be any positive integer. As discussed above, the layer stack under construction (52', 54', 56') comprises first sidewalls extending laterally along the first horizontal direction hd1 and second sidewalls extending laterally along the second horizontal direction hd2.The masking material sections of the second structured etching mask layer 79 extend laterally along the second horizontal direction hd2 and can be spaced apart laterally from each other along the first horizontal direction hd1.

[0055] With reference to Fig. 11C can be the second anisotropic etching process as described in reference to Fig. 9 described. The second anisotropic etching process removes unmasked sections of the layer stack in progress (52', 54', 56') that are not covered by the second structured etch mask layer 79. Each structured section of the layer stack in progress (52', 54', 56') comprises a layer stack (52, 54, 56) that has a respective heater lining 52, a respective phase-change material section 54, and a respective top electrode 56. In general, the multiple structured sections of each layer stack in progress (52', 54', 56') can comprise at least one series of structured sections arranged along the first horizontal direction hd1. In the Fig. The first setup illustrated in Figure 11C can comprise at least one series of structured sections, two series of structured sections of the layer stack in progress (52', 54', 56'), that is, two series of layer stacks (52, 54, 56) forming a 2 x N array of layer stacks (52, 54, 56). In general, a P x Q array of layer stacks in progress (52', 54', 56') can be used, and a 2P x QN array of phase-change memory cells 50 can be constructed using the methods shown in Figure 11C. Fig. 11A - 11C illustrated the first facility to be formed.

[0056] In general, the at least one sidewall lining 58 can be formed on each layer stack (52, 54, 56) within each phase-change storage cell 50. In the first setup, the at least one sidewall lining 58 within each phase-change storage cell 50 can consist of a single sidewall lining 58 formed directly on a sidewall of the layer stack (52, 54, 56) of the phase-change storage cell 50, which is a structured section of the continuous layer stack (52L, 54L, 56L).

[0057] With reference to Fig. 12A is a region of a second device of the structure of an embodiment comprising two layer stacks (52', 54', 56') in progress and two side wall linings 58' in progress, in a processing step of Fig. Figure 8 illustrates this. Each layer stack in progress (52', 54', 56') can include first side walls parallel to a first horizontal direction hd1 and second side walls parallel to a second horizontal direction hd2. The second horizontal direction hd2 can be perpendicular to the first horizontal direction hd1.

[0058] With reference to Fig. Figure 12B illustrates the region of the second setup of the structure of an embodiment after the formation of the second structured etch mask layer 79 and before the second anisotropic etching process. The second structured etch mask layer 79 can comprise a 1 × N array of structured discrete etch mask material sections (such as structured photoresist material sections) covering 2N segments of the first sidewalls of each layer stack (52', 54', 56') under construction. Each structured discrete etch mask material section can include a photoresist material strip extending laterally along the second horizontal direction hd2 and having a uniform width along the first horizontal direction hd1. In the illustrated example, the integer N is 4. In general, the integer N can be any positive integer.As discussed above, each layer stack in progress (52', 54', 56') comprises first sidewalls extending laterally along the first horizontal direction hd1 and second sidewalls extending laterally along the second horizontal direction hd2. The masking material sections of the second structured etch mask layer 79 extend laterally along the second horizontal direction hd2 and may be laterally spaced from each other along the first horizontal direction hd1.

[0059] With reference to Fig. 12C can be the second anisotropic etching process as described in reference to Fig. 9 described. The second anisotropic etching process removes unmasked sections of the layer stack in progress (52', 54', 56') that are not covered by the second structured etch mask layer 79. Each structured section of the layer stack in progress (52', 54', 56') comprises a layer stack (52, 54, 56) that has a respective heater lining 52, a respective phase-change material section 54, and a respective top electrode 56. In general, the multiple structured sections of each layer stack in progress (52', 54', 56') can comprise at least one series of structured sections arranged along the first horizontal direction hd1. In the Fig. In the second setup illustrated in Figure 12C, the at least one set of structured sections can comprise a set of structured sections of the layer stack in progress (52', 54', 56'), that is, a set of layer stacks (52, 54, 56) forming a 1 x N array of layer stacks (52, 54, 56). In general, a P x Q array of layer stacks in progress (52', 54', 56') can be used, and a P x QN array of phase-change memory cells 50 can be used with the aid shown in Fig. 12A - 12C illustrated the second facility being formed.

[0060] In general, the at least one sidewall lining 58 can be formed on each layer stack (52, 54, 56) within each phase-change storage cell 50. In the second arrangement, the at least one sidewall lining 58 within each phase-change storage cell 50 can comprise two sidewall linings 58 formed directly on a pair of sidewalls of the layer stack (52, 54, 56) of the phase-change storage cell 50, which is a structured section of the continuous layer stack (52L, 54L, 56L). The pair of sidewalls can be parallel to each other, and the two sidewall linings 58 are laterally spaced apart in a horizontal direction, such as the second horizontal direction hd2.

[0061] With reference to Fig. 13A is a region of a third feature of the structure of an embodiment comprising the layer stack under processing (52', 54', 56') and the side wall linings under processing 58', in a processing step of Fig. Figure 10 illustrates this. Each layer stack in progress (52', 54', 56') can include first sidewalls parallel to a first horizontal direction hd1 and second sidewalls parallel to a second horizontal direction hd2. The second horizontal direction hd2 can be perpendicular to the first horizontal direction hd1.

[0062] With reference to Fig. Figure 13B illustrates the region of the third feature of the structure of an embodiment after the formation of the second structured etch mask layer 79 and before the second anisotropic etching process. The second structured etch mask layer 79 can comprise a pair of structured discrete etch mask material sections (such as structured photoresist material sections) that cover all second sidewalls of the layer stacks under construction (52', 54', 56') and segments of each first sidewall adjacent to a respective second sidewall of the layer stacks under construction (52', 54', 56'). Each first sidewall of the layer stacks under construction (52', 54', 56') includes a central segment that is not covered by the second structured etch mask layer 79.As discussed above, each layer stack in progress (52', 54', 56') comprises first sidewalls extending laterally along the first horizontal direction hd1 and second sidewalls extending laterally along the second horizontal direction hd2. The two masking material sections of the second structured etch mask layer 79 extend laterally along the second horizontal direction hd2 and may be laterally spaced apart from each other along the first horizontal direction hd1 such that the middle segments of each first sidewall of the layer stacks in progress (52', 54', 56') are not covered by the second structured etch mask layer 79.

[0063] With reference to Fig. 13C can be the second anisotropic etching process as described in reference to Fig. 9 described. The second anisotropic etching process removes unmasked sections of the layer stacks (52', 54', 56') under construction that are not covered by the second structured etch mask layer 79. Each structured section of the layer stacks under construction (52', 54', 56') comprises a layer stack (52, 54, 56) that has a respective heater lining 52, a respective phase-change material section 54, and a respective top electrode 56. In general, the multiple structured sections of each layer stack under construction (52', 54', 56') can comprise at least one series of structured sections arranged along the first horizontal direction hd1. In the Fig. In the third arrangement illustrated in Figure 13C, the at least one series of structured sections can comprise a series having two structured sections of the layer stack in progress (52', 54', 56'), that is, a series of layer stacks (52, 54, 56) forming a 1 x 2 array of layer stacks (52, 54, 56). In general, a P x Q array of layer stacks in progress (52', 54', 56') can be used, and a P x 2Q array of phase-change memory cells 50 can be used using the Fig. 13A - 13C illustrated the third facility being formed.

[0064] In general, the at least one sidewall lining 58 can be formed on each layer stack (52, 54, 56) within each phase-change storage cell 50. In the third arrangement, the at least one sidewall lining 58 within each phase-change storage cell 50 can consist of a single sidewall lining 58 formed directly on three sidewalls of the layer stack (52, 54, 56) of the phase-change storage cell 50, which is a structured section of the continuous layer stack (52L, 54L, 56L).

[0065] With reference to Fig. 14 is a fourth arrangement of the structure of an embodiment according to the processing steps of Fig. Figure 8 illustrates the masking structure of the first structured etching mask layer 77, which is used in the processing steps of Fig. 8 is used, modified such that the structure of the first structured etch mask layer 77 is the same as the target structure for an array of layer stacks (52, 54, 56) for an array of phase-change memory cells 50. In this embodiment, the structure is defined with reference to Fig. The first anisotropic etching process described in section 6 directly converts the continuous layer stack (52L, 54L, 56L) into the array of layer stacks (52, 54, 56). Furthermore, when performing the process described in section 6, the following can be achieved: Fig. 7 and Fig. The processing steps described in section 8 allow the sidewall lining layer 58L to be structured directly into the sidewall linings 58. Therefore, the following can be carried out with reference to Fig. 9 and Fig. The processing steps described in section 10 may be omitted if the fourth feature of the structure of an embodiment is used.

[0066] In general, the at least one sidewall lining 58 can be formed on each layer stack (52, 54, 56) within each phase-change storage cell 50. In the fourth configuration, the at least one sidewall lining 58 within each phase-change storage cell 50 can comprise a ring-shaped configuration. In other words, the at least one sidewall lining 58 within each phase-change storage cell 50 can consist of a single sidewall lining 58 that is topologically homeomorphic to a torus, meaning it can be continuously deformed into a torus without forming a new hole or removing an existing one. The single sidewall lining 58 can be formed directly on each sidewall of a respective layer stack (52, 54, 56), which is a structured section of the continuous layer stack (52L, 54L, 56L).

[0067] With reference to Fig. 15. A dielectric encapsulation layer 643 and additional metal interconnect structures (62, 642, 648) can be formed over the phase-change memory cells 50. The dielectric encapsulation layer 643 comprises at least one dielectric interlayer material such as silicon oxide, silicon nitride, and / or silicon carbide nitride. The dielectric encapsulation layer 643 forms an upper fourth layer of dielectric material at the interconnect level. The combination of the lower fourth layer 641 of dielectric material at the interconnect level and the dielectric encapsulation layer 643 forms a fourth layer 640 of dielectric material at the interconnect level.The additional metal interconnect structures (62, 642, 648) can be upper-contact via structures 62, which contact a top surface of one of the respective upper electrodes 56; third-contact via structures 642, which are formed through a lower section of the fourth layer 640 of dielectric material at the interconnect level; and fourth-contact via structures 648, which are formed on the upper-contact via structures 62 and the third-contact via structures 642 in a top section of the fourth layer 640 of dielectric material at the interconnect level. Top surfaces of the fourth-contact via structures 648 can be coplanar with the horizontal top surface of the dielectric encapsulation layer 643.If required, additional layers of dielectric material (not shown) and additional metal interconnect structures can be formed to provide electrical connections between the upper electrodes 56 of the phase-change memory cells 50 and the various semiconductor devices 700 located beneath the layers (601, 610, 620, 630, 640) of dielectric material.

[0068] In general, programming transistors 701 can be provided on a substrate 8. Metal interconnect structures (612, 618, 622, 628, 632, 638) embedded in layers (601, 610, 620, 630, 641) of dielectric material at the interconnect level can be formed over the programming transistors 701. Lower electrodes 38 and tubular dielectric spacers 42 can be formed within a layer of dielectric material, such as a lower fourth layer 641 of dielectric material at the interconnect level. Each heater liner 52 can be electrically connected to an electrical node, such as an output node, of a respective programming transistor 701.A continuous layer stack (52L, 54L, 56L) comprising a heater lining layer 52L, a phase change material layer 54L including a phase change material, and a material layer 56L for the top electrode can be deposited and structured to form layer stacks (52, 54, 56) of a heater lining 52, a phase change material section 54, and a top electrode 56. A sidewall lining layer 58L can be formed and structured to form sidewall linings 58. At least one sidewall lining 58 can be formed on at least one sidewall of each layer stack (52, 54, 56).

[0069] Each sidewall lining 58 comprises a material with an electrical conductivity higher than that of an amorphous phase of the phase-change material of the phase-change material sections 54. For each phase-change storage cell 50, a dielectric encapsulation layer 643 can be deposited directly on at least one sidewall of the layer stack (52, 54, 56) (which is a structured section of the continuous layer stack (52L, 54L, 56L)), directly on an outer wall of each of the at least one sidewall lining 58, and directly on a top surface of the layer stack (52, 54, 56). Thus, for each phase-change storage cell 50, the dielectric encapsulation layer 643 is in contact with at least one sidewall of the layer stack, an outer wall of each of the at least one sidewall lining 58, and a top surface of the layer stack (52, 54, 56).

[0070] For each phase-change memory cell 50 that is electrically connected to a programming transistor 701, the programming transistor 701 is configured to program the phase-change memory cell 50 into at least three different resistance states by applying at least three different programming pulse patterns to the heating lining 52. Fig. 16A - 16D are different arrangements of a phase-change material section 54 in different programmed resistance states according to an embodiment of the present disclosure.

[0071] With reference to Fig. Figure 16A illustrates a phase-change storage cell 50 in a low-resistance state. In this embodiment, at least 99% of the total volume of the phase-change material section 54 is in a polycrystalline phase. In one embodiment, the entire phase-change material section 54 can be a crystalline phase-change material section 54C containing a polycrystalline phase-change material. The electrical conductivity of the crystalline phase-change material is higher than the electrical conductivity of the materials of the heater lining 52 and the at least one side wall lining 58. Thus, the primary electrically conductive path extends vertically between the heater lining 52 and the upper electrode 56.

[0072] With reference to Fig. Figure 16B illustrates a phase-change storage cell 50 in a first intermediate state. In this embodiment, the phase-change material section 54 comprises a first volume containing the amorphous phase and a second volume containing the crystalline phase. The first volume comprises an amorphous phase-change material section 54A, and the second volume comprises a crystalline phase-change material section 54C. The first volume is not in direct contact with the at least one side wall lining 58. The electrical conductivity of the amorphous phase-change material is lower than the electrical conductivity of the materials of the heating lining 52 and the at least one side wall lining 58.Thus, the primary electrically conductive path extends laterally within the heating lining 52 below the amorphous phase change material section 54A and extends through the crystalline phase change material section 54C between a circumferential section of the heating lining 52 and the upper electrode 56 at an angle relative to the vertical direction.

[0073] With reference to Fig. Figure 16C illustrates a phase-change storage cell 50 in a second intermediate state, which provides a higher resistance than the first intermediate state. In this embodiment, the phase-change material section 54 comprises a first volume containing the amorphous phase and a second volume containing the crystalline phase. The first volume comprises an amorphous phase-change material section 54A, and the second volume comprises a crystalline phase-change material section 54C. The first volume is in direct contact with the at least one side wall lining 58 and does not contact the upper electrode 56. The electrical conductivity of the amorphous phase-change material is lower than the electrical conductivity of the materials of the heating lining 52 and the at least one side wall lining 58.Thus, the primary electrically conductive path extends laterally within the heating lining 52 below the amorphous phase-change material section 54A, extends vertically through a lower section of each side wall lining 58, and extends through the crystalline phase-change material section 54C between a middle section of each side wall lining 58 and the upper electrode 56 at an angle relative to the vertical direction.

[0074] With reference to Fig. Figure 16D illustrates a phase-change memory cell 50 in a high-resistance state. In this embodiment, at least 99% of the total volume of the phase-change material section 54 is in an amorphous phase.

[0075] Although in Fig. Figures 16A-16D illustrate four resistance states of a phase-change memory cell 50. The pulse pattern of the programming pulse can be pre-programmed by the programming transistor 701 to be selected from several programming pulse patterns stored in a programming circuit for the phase-change memory cells 50. The total number of pre-programmed pulse patterns can be in the range of 2 to 210, such as 3 to 28 and / or 4 to 26. The total number of resistance states that can be programmed in each phase-change memory cell 50 can be the same as the total number of pre-programmed pulse patterns. In one embodiment, each programming transistor 701 can be configured to apply at least four different programming pulse patterns to a respective heater lining 52.The programming pulses can have a specific duration and / or voltage decay rate to provide a controlled cooling rate of a molten region of a phase-change material section 54. The duration of the programming pulses can range from 10 nanoseconds to 500 nanoseconds, with the longer programming pulses generally corresponding to the formation of large crystallized regions of the phase-change material section 54.

[0076] With reference to Fig. Figure 17 illustrates a structure of a second embodiment according to an embodiment of the present disclosure. The structure of the second embodiment can be distinguished from that in Fig. The structure of the first embodiment, as illustrated in 1, can be derived by: forming the through-holes 41 with a larger lateral dimension, and carrying out the modifications in relation to Fig. 3 and Fig. 4 described processing steps, and deposition of a heating lining layer 52L, which has a greater thickness than that described in relation to Fig. 5 described heating lining layer 52L has.

[0077] For example, the lateral dimension (such as the diameter) of the lower section of each via opening 41 can be determined in a processing step corresponding to the processing step of Fig. 2 formed, in a range of 80 nm to 400 nm, although smaller or larger lateral dimensions can also be used. The thickness of layer 42L of dielectric spacer material, as in a processing step corresponding to the processing step of Fig. The thickness of the layer 42L of dielectric spacer material is chosen such that the difference between the width of the lower portion of each via hole 41 and twice the thickness of the layer 42L of dielectric spacer material is greater than a desired range for the width of the lower portion of each vertically extending section of a subsequently formed heater lining layer. In an illustrative example, if the width of the lower portion of each via hole 41 is in the range of 80 nm to 400 nm, and if the desired range for the width of the lower portion of each vertically extending section of the heater lining layer 52L is in the range of 20 nm to 100 nm, the thickness of the layer 42L of dielectric spacer material can be in the range of 15 nm to 150 nm, such as 30 nm to 80 nm, although smaller or larger thicknesses can also be used.Thus, the lateral distance between the inner cylindrical side wall and an outer cylindrical side wall of each tubular dielectric spacer 42 can be approximately in a range of 15 nm to 150 nm, such as 30 nm to 80 nm, although smaller or larger lateral distances can also be used.

[0078] The heater lining layer 52L can be deposited with a sufficient thickness to fill a predominant fraction and / or all of the volume of each vacancy within the via holes 41 with the deposited material of the heater lining layer 52L. The thickness of the horizontally extending portion of the heater lining layer 52L, which is formed above the top surface of the layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level), can be in a range of 25 nm to 120 nm, such as 50 nm to 80 nm, although smaller or larger thicknesses can also be used.

[0079] As in the structure of the first embodiment, a vertically extending seam S can be formed within each vertically extending section of the heating lining layer 52L, which is deposited within a fraction of the volume of a respective via opening 41. Another fraction of the volume of the respective via opening 41 can be occupied by a tubular dielectric spacer 42.As in the structure of the first embodiment, the heating lining layer 52L is formed with a planar horizontal surface segment PHSS that lies above the layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level) and annular convex surface segments ACSS, each bordering a circumferential edge of a respective opening in the planar horizontal surface segment PHSS and each comprising a respective lower tip point that borders an upper end of the vertically extending seam S.

[0080] With reference to Fig. 18. The heating lining layer 52L can be vertically recessed by performing a back-etching process, which is a recession etching process that etches the material of the heating lining layer 52L. The back-etching process vertically recesses the horizontally extending section of the heating lining layer 52L. The back-etching process simultaneously recesses the annular convex surface segments ACSS of the heating lining layer 52L while vertically recessing the horizontally extending section of the heating lining layer 52L. In other words, the back-etching process simultaneously etches the annular convex surface segments ACSS and the planar horizontal surface segment PHSS of the heating lining layer 52L.

[0081] The re-etching process can comprise a wet etching process or a reactive ion etching process. The duration of the re-etching process can be selected such that the thinned, horizontally extending section of the heating lining layer 52L has a thickness within a target thickness range, which may be in the range of 1 nm to 50 nm, such as 3 nm to 20 nm, although smaller or larger thicknesses can also be used. In general, the thickness of the horizontally extending section of the heating lining layer 52L, which is formed by the process described above, can be determined by the thickness of the thinned, horizontally extending section of the heating lining layer 52L. Fig. 17 and Fig. The processing steps described in section 18 are formed, and the thickness of the horizontally extending section of the heating lining layer 52L within the structure of the first embodiment is less than the thickness of the horizontally extending section of the heating lining layer 52L within the structure of the first embodiment, and the horizontally extending section of the heating lining layer 52L of the structure of the second embodiment can provide a higher electrical resistance relative to the horizontally extending section of the heating lining layer 52L of the first embodiment.

[0082] With reference to Fig. 19 can be a subset of those with reference to Fig. The processing steps described in 5 are carried out to deposit a phase change material layer 54L and a material layer 56L for the upper electrode over the horizontally extending section of the heating lining layer 52L.

[0083] With reference to Fig. 20 can refer to Fig. The 6 described processing steps are carried out to structure the continuous layer stack (52L, 54L, 56L) into a two-dimensional array of layer stacks in progress (52', 54', 56').

[0084] With reference to Fig. 21 can refer to Fig. The processing steps described in Sections 7-15 are performed to form a two-dimensional array of phase-change memory devices 50. Each phase-change memory cell 50 of the structure of the second embodiment can have a larger lower width for the vertically extending section of a heating lining 52 and / or a smaller thickness for the horizontally extending section of the heating lining 52, which can be advantageously used to provide improved resistance distribution characteristics for the different programmed states of the phase-change memory cell 50.

[0085] With reference to Fig. Figure 22 illustrates a third embodiment according to an embodiment of the present disclosure after the formation of a heating lining layer 52L. The structure of the third embodiment can be compared to that shown in Fig. The structure of the first embodiment, as illustrated in 1, can be derived by: forming the through-holes 41 with a larger lateral dimension, and carrying out the modifications in relation to Fig. 3 and Fig. 4 described processing steps, and deposition of a heating lining layer 52L, which has the same thickness range as that described in relation to Fig. The heating lining layer 52L described in section 5 is present. The heating lining layer 52L can be deposited by a conformal deposition process.

[0086] As described above, a void can exist within each volume laterally surrounded by a tubular dielectric spacer 42. In the structure of the third embodiment, the maximum width of each void within the volumes of the vias 41 is greater than half the thickness of the heater lining layer 52L. Thus, the voids in the volumes of the vias 41 are not completely filled by the heater lining layer 52L. In other words, after the formation of the heater lining layer 52L, an unfilled portion of a void can remain in each volume of the vias 41.In one embodiment, an inner cylindrical side wall of a tubular section of the heating lining layer 52L and a top segment of a horizontally extending section of the heating lining layer 52L, which contacts a respective underlying lower electrode 38, can be physically exposed to any unfilled void that is present within the volume of a respective via opening 41 through the layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level).

[0087] As in the structure of the first embodiment, the heating lining layer 52L is formed with a planar horizontal surface segment PHSS that lies above the layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level) and annular convex surface segments ACSS, each bordering a circumferential edge of a respective opening in the planar horizontal surface segment PHSS and each comprising a respective lower tip point that borders an upper end of the vertically extending seam S.

[0088] With reference to Fig. 23 can be a subset of those with reference to Fig. The processing steps described in section 5 are performed to deposit a phase-change material layer 54L and the material layer 56L for the upper electrode. In the structure of the third embodiment, the phase-change material layer 54L comprises vertically extending sections, each having a cylindrical side wall that contacts a respective inner cylindrical side wall of the tubular dielectric spacer 42 within the volume of a respective via opening 41, which extends vertically through the layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level). Each vertically extending section of the phase-change material layer 54L can be deposited within the unfilled section of a respective vacancy, which is laterally surrounded by a respective tubular section of the heater lining layer 52L.The material layer 56L for the upper electrode is then deposited over the phase change material layer 54L.

[0089] With reference to Fig. 24 can refer to Fig. The 6 described processing steps are carried out to structure the continuous layer stack (52L, 54L, 56L) into a two-dimensional array of layer stacks in progress (52', 54', 56').

[0090] With reference to Fig. 25 can refer to Fig. The processing steps described in Sections 7-15 are performed to form a two-dimensional array of phase-change storage devices 50. Each phase-change storage cell 50 of the structure of the third embodiment can have vertically extending tubular sections of a heating lining 52. In one embodiment, the lateral thickness of the vertically extending tubular sections of the heating lining 52 (measured between a cylindrical inner wall and a cylindrical outer wall) and the vertical thickness of the horizontally extending section of the heating lining 52, which lies above the layer of dielectric material through which the vias 41 extend vertically, can be equal.

[0091] With common reference to Fig. 1-25, and according to various embodiments of the present disclosure, an apparatus structure is provided comprising: a tubular dielectric spacer 42 located within a via opening 41 in a layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level); a heater lining 52 comprising a vertically extending section laterally surrounded by the tubular dielectric spacer 42 and a horizontally extending section that lies above a top-side segment of the layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level); a phase-change material section 54 comprising a phase-change material that contacts a top-side of the heater lining layer 52L;and an upper electrode 56 that contacts a top side of the phase-change material section 54.;

[0092] In one embodiment, the heating lining 52 comprises a planar horizontal surface segment PHSS that lies above the layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level), and further comprises an annular convex surface segment ACSS that borders a circumferential edge of an opening in the planar horizontal surface segment PHSS and lies above the via opening 41; and the phase change material section 54 contacts the annular convex surface segment ACSS.

[0093] In one embodiment, the vertically extending section of the heating lining 52 comprises a vertically extending seam S; and an upper surface of the heating lining 52 comprises an annular convex surface segment ACSS having a lower apex adjacent to an upper end of the vertically extending seam S.

[0094] In one embodiment, the phase change material section 54 comprises a vertically extending section located within a central region of the via opening 41; and the vertically extending section of the heater lining 52 comprises a cylindrical inner side wall that contacts the vertically extending section of the phase change material section 54.

[0095] In one embodiment, the device structure comprises at least one side wall lining 58, which is located on at least one side wall of the phase change material section 54, contacts a side wall of the horizontally extending section of the heating lining 52, and comprises a material with an electrical conductivity that is higher than an electrical conductivity of an amorphous phase of the phase change material.

[0096] Fig. Figure 26 is a first flowchart illustrating general processing steps for manufacturing a device structure according to embodiments of the present disclosure.

[0097] Referring to step 2610 and Fig. 1 - 2, 17 and 22 can be formed by a lower electrode 38, a layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level) and a via opening 41 extending through the layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level) such that a top segment of the lower electrode 38 is exposed below the via opening 41.

[0098] Referring to step 2620 and Fig. 3, Fig. 4, Fig. 17 and Fig. 22 a tubular dielectric spacer 42 can be formed in an edge region of the via opening 41 such that a middle section of the top segment is exposed under a void which is laterally surrounded by the tubular dielectric spacer 42.

[0099] Referring to step 2630 and Fig. 5, Fig. 17 and Fig. 16, and Fig. 22 and Fig. 23 a continuous layer stack (52L, 54L, 56L) comprising a heating lining layer 52L, a phase change material layer 54L comprising a phase change material, and a material layer 56L for the upper electrode, can be formed above the layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level) and the tubular dielectric spacer 42.

[0100] Referring to step 2640 and Fig. 6 - 16D, 19 - 21, and 24 and 25 the continuous layer stack (52L, 54L, 56L) can be structured into a layer stack (52, 54, 56) comprising a heating lining 52, a phase change material section 54 and an upper electrode 56.

[0101] Fig. Figure 27 is a second flowchart illustrating general processing steps for manufacturing a device structure according to embodiments of the present disclosure.

[0102] Referring to step 2710 and Fig. 1, Fig. 2 and Fig. 17 a lower electrode 38, a layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level) and a via opening 41 extending through the layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level) can be formed such that a top segment of the lower electrode 38 is exposed below the via opening 41.

[0103] Referring to step 2720 and Fig. 3-5 and 17, a heating lining layer 52L can be deposited within a fraction of a volume of the via opening 41 and above the layer of dielectric material (such as the lower fourth layer 641 of dielectric material at the interconnect level).

[0104] Referring to step 2730 and Fig. 18. A horizontally extending section of the heating lining layer 52L can be vertically omitted.

[0105] Referring to step 2740 and Fig. 19 A phase change material layer 54L, comprising a phase change material, and a material layer 56L for the upper electrode can be deposited over the horizontally extending section of the heating lining layer 52L.

[0106] Referring to step 2750 and Fig.6 - 16D, 20 and 21 the material layer 56L for the upper electrode, the phase change material layer 54L and the heating lining layer 52L can be structured into a layer stack (52, 54, 56) comprising a heating lining 52, a phase change material section 54 and an upper electrode 56.

[0107] Within each phase-change storage cell, the heating liner 52 and the side wall liner 58 are used to adjust the resistance levels of high-resistance states of the phase-change storage cell. The combination of heating liner 52 and side wall liner 58 suppresses the effect of resistance drift of the phase-change material section 54, reduces the power consumption of the phase-change storage cell, reduces the failure rate during operation of the phase-change storage cell, and allows for a reduction in the cell size of the phase-change storage cell.In general, the thickness of the heating element lining 52 and the thickness of the side wall lining 58 can be optimized to provide a wide variation in the resistance of different resistance states of the phase-change memory cell and to enable efficient multi-level cell (MLC) operation, that is, cell operation in which the cell is programmed to three or more resistance states. Thus, a large programming window can be provided for the use of phase-change memory cells 50 for MLC operation.

[0108] Embodiments of the present disclosure provide advances in processing technology for manufacturing phase-change storage devices by eliminating the need for a chemical-mechanical polishing (CMP) process during the formation of heating elements comprising vertically extending sections of the heating liners 52. In one embodiment, each heating liner 52 is formed within a via opening 41 and is laterally surrounded by a tubular dielectric spacer 42. A horizontally extending section of the heating liner 52 lies above a layer of dielectric material through which the via openings 41 extend vertically. A phase-change material section 54 is arranged above the heating liner 52, and an upper electrode 56 contacts the top surface of the phase-change material section 54.The sequence of processing steps used to form the phase-change memory cells 50 reduces manufacturing complexity while simultaneously improving thermal efficiency and cost-effectiveness. The phase-change memory cells 50 of this disclosure minimize heat loss by using a material with low thermal conductivity for the tubular dielectric spacers 42, which laterally surround the vertically extending sections of the heating liners 52 that act as heating elements. Improved thermal insulation for the heating elements can enhance device performance for computation-in-memory (CIM) applications.

[0109] The above outlines features of various embodiments so that the person skilled in the art can better understand the aspects of the present disclosure. Every embodiment described using the term "comprises" also inherently discloses that the term "comprises" may be replaced by "consists substantially of" or by the term "consists of," unless expressly disclosed otherwise in the present text. Whenever two or more elements are listed as alternatives in the same paragraph or in different paragraphs, a Markush group containing a list of the two or more elements may also be implicitly disclosed.Whenever the auxiliary verb "can" is used in this disclosure to describe the formation of an element or the performance of a processing step, an embodiment in which such an element or processing step is not performed is expressly considered, provided that the resulting device is capable of producing an equivalent result. Therefore, when applied to the formation of an element or the performance of a processing step, the auxiliary verb "can" is also to be interpreted as "could" or "could, but need not" whenever omitting the formation of such an element or processing step is capable of producing the same result or equivalent results, the equivalent results including somewhat better and somewhat worse results.It is clear to the person skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as in the embodiments presented in this text. It should also be clear to the person skilled in the art that such equivalent designs do not depart from the essence and scope of protection of the present disclosure, and that they can make various changes, substitutions, and modifications to the present invention without departing from the essence and scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 711,791

[0001]

Claims

[1] Method for forming a device structure, comprising: Forming a lower electrode, a layer of dielectric material and a via opening that extends through the layer of dielectric material such that a top segment of the lower electrode is exposed below the via opening; Forming a tubular dielectric spacer in a peripheral region of the via opening such that a central section of the top segment is exposed under a void that is laterally surrounded by the tubular dielectric spacer; Deposition of a continuous stack of layers comprising a heating lining layer, a phase change material layer including a phase change material, and a material layer for the top electrode, over the layer of dielectric material and the tubular dielectric spacer; and Structuring the continuous layer stack into a layer stack comprising a heating lining, a phase change material section, and an upper electrode. [2] Method according to claim 1, wherein the heating lining layer comprises a vertically extending section deposited in a void within the tubular dielectric spacer and a horizontally extending section deposited over a top surface of the layer of dielectric material. [3] Method according to claim 1 or 2, wherein a vertically extending seam is formed in the middle of the vertically extending section of the heating lining layer. [4] Method according to claim 2 or 3, wherein the phase change material layer comprises a vertically extending section having a cylindrical side wall that contacts an inner cylindrical side wall of the tubular dielectric spacer. [5] Method according to any one of claims 1 to 4, further comprising: Deposition of a layer of dielectric spacer material in the edge region of the via opening and above the layer of dielectric material; and anisotropic etching of the layer of dielectric spacer material, wherein a remaining vertically extending section of the layer of dielectric spacer material filling the edge region of the via aperture forms the tubular dielectric spacer. [6] Method according to any one of claims 1 to 5, wherein: the heating element lining layer is deposited on the middle section of the top segment of the lower electrode; and the phase change material layer is deposited on a planar horizontal surface segment of the heating lining layer, which lies above a horizontal plane that has a top surface of dielectric material. [7] Method according to any one of claims 1 to 6, wherein: the heating lining layer, after deposition of the heating lining layer, comprises a planar horizontal surface segment that lies above the layer of dielectric material, and further comprises an annular convex surface segment that borders a circumferential edge of an opening in the planar horizontal surface segment and lies above the via opening; and The phase change material layer is deposited directly onto the ring-shaped convex surface segment. [8] Method according to claim 7, wherein: the heating system lining layer is deposited through a conformal deposition process; a maximum width of the void is less than half the thickness of the heating system lining layer; and A vertically extending seam is formed in the center of the void, which is filled with a vertically extending section of the heating lining layer. [9] Method according to claim 7, wherein: the heating system lining layer is deposited through a conformal deposition process; a maximum width of the void is greater than half the thickness of the heating system lining layer; an unfilled section of the vacancy exists after the formation of the heating element lining layer within a volume of the via opening; and a vertically extending section of the phase change material layer is deposited within the unfilled section of the vacancy. [10] Method according to any one of claims 1 to 9, further comprising forming at least one sidewall lining by depositing and structuring a sidewall lining material, wherein the at least one sidewall lining is formed on at least one sidewall of the layer stack, wherein the at least one sidewall lining comprises a material having an electrical conductivity that is higher than an electrical conductivity of an amorphous phase of the phase change material. [11] Method for forming a device structure, comprising: Forming a lower electrode, a layer of dielectric material and a via opening that extends through the layer of dielectric material such that a top segment of the lower electrode is exposed below the via opening; Deposition of a heating element lining layer within a fraction of the volume of the via opening and above the layer of dielectric material; vertical recession of a horizontally extending section of the heating element lining layer; Deposition of a phase change material layer comprising a phase change material and a material layer for the upper electrode over the horizontally extending section of the heating element lining layer; and Structuring the upper electrode material layer, the phase change material layer, and the heating lining layer into a layer stack comprising a heating lining, a phase change material section, and an upper electrode. [12] Method according to claim 11, further comprising forming a tubular dielectric spacer in a peripheral region of the via opening such that a central section of the top segment is exposed under a void which is laterally surrounded by the tubular dielectric spacer, wherein the fraction of the volume of the via opening comprises a volume of a void within the tubular dielectric spacer. [13] Method according to claim 11 or 12, wherein the vertical recession of the horizontally extending section of the heating lining layer comprises carrying out a back-etching process that etches a material of the heating lining layer. [14] Method according to any one of claims 11 to 13, wherein a vertically extending seam is formed within a vertically extending section of the heating lining layer which is deposited within the fraction of the volume of the via opening. [15] Method according to claim 14, wherein: the heating lining layer is formed with a planar horizontal surface segment lying above the layer of dielectric material and an annular convex surface segment bordering a circumferential edge of an opening in the planar horizontal surface segment and comprising a lower apex bordering an upper end of the vertically extending seam; and The vertical recession of the horizontally extending section of the heating lining layer involves performing a back-etching process that simultaneously recesses the annular convex surface segment of the heating lining layer vertically while the horizontally extending section of the heating lining layer is recessed vertically. [16] Device structure, comprising: a tubular dielectric spacer located within a via opening in a layer of dielectric material; a heating lining comprising a vertically extending section surrounded laterally by the tubular dielectric spacer and a horizontally extending section lying over a top segment of the layer of dielectric material; a phase change material section comprising a phase change material that contacts a top side of the heating liner; and an upper electrode that contacts a top side of the phase change material section. [17] Device structure according to claim 16, wherein: the heating element lining comprises a planar horizontal surface segment that lies above the layer of dielectric material, and further comprises an annular convex surface segment that borders a circumferential edge of an opening in the planar horizontal surface segment and lies above the via opening; and The phase change material section contacts the ring-shaped convex surface segment. [18] Device structure according to claim 16 or 17, wherein: the vertically extending section of the heating system lining includes a vertically extending seam; and The upper surface of the heating lining comprises an annular convex surface segment that has a lower apex adjacent to an upper end of the vertically extending seam. [19] Device structure according to one of claims 16 to 18, wherein: the phase-change material section comprises a vertically extending section located within a central region of the via opening; and The vertically extending section of the heating lining comprises a cylindrical inner wall that contacts the vertically extending section of the phase change material section. [20] Device structure according to one of claims 16 to 19, further comprising at least one side wall lining which is located on at least one side wall of the phase change material section, contacts a side wall of the horizontally extending section of the heating lining, and comprises a material having an electrical conductivity which is higher than an electrical conductivity of an amorphous phase of the phase change material.

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