DISPLAY DEVICE

Abstract

Display device (100) comprising: an active layer (ACT), a gate insulating layer (640) arranged on the active layer (ACT) and having a first opening (H1); a first electrode (E1) electrically connected to at least one section of the first area (CT1) in the first opening (H1); a second electrode (E2) arranged on the gate insulating layer (640); a protective layer (630) arranged on the first electrode (E1) and the second electrode (E2) and having a second opening (H2); and a pixel electrode (PE) arranged on the protective layer (630) and electrically connected to the first electrode (E1) in the second opening (H2).

Description

BACKGROUND TECHNICAL AREA

[0001] Embodiments of the present disclosure relate to a display device. DISCUSSION OF THE RELATED TECHNOLOGY

[0002] A display device can have at least one driver transistor and one storage capacitor for each sub-pixel. The display device can have sub-pixels with varying aperture ratios, depending on the structure of the different sub-pixels, whereby the image quality or resolution of the display panel varies based on the aperture ratio of the sub-pixel. As the resolution in display devices increases, it becomes advantageous to increase the aperture ratio of each sub-pixel.

[0003] However, since the number or type of elements (e.g. transistors, storage capacitors, light-emitting device) included in each sub-pixel is limited, it can be difficult to optimize the sub-pixel structure to increase the aperture ratio. EXPLANATION OF THE REVELATION

[0004] Embodiments of the present disclosure can provide a display device that is able to reduce the size of the sub-pixel circuit section provided in each sub-pixel by structural optimization.

[0005] Such embodiments can also provide a display device capable of reducing the size of the sub-pixel circuit through structural optimization, thereby increasing the size of the aperture within each sub-pixel, improving light extraction efficiency, and reducing power consumption.

[0006] In addition, embodiments of the present disclosure can provide a display device that is able to simplify the structure of a sub-pixel circuit and reduce the size of a sub-pixel circuit by applying an overlap structure of an opening in a protective layer and an opening in a gate insulating layer to a sub-pixel circuit.

[0007] Such embodiments can also provide a display device capable of simplifying the structure of a sub-pixel circuit and reducing the size of a sub-pixel circuit by applying a non-overlapping structure of an opening of a protective layer and a storage capacitor to the sub-pixel circuit.

[0008] Additional embodiments can provide a display device in which a pixel electrode is electrically connected to an active layer, with an electrode of a drive transistor positioned between them to form a current path within a sub-pixel circuit, thereby reducing contact resistance compared to a direct connection between the pixel electrode and the active layer. Display devices according to the independent claims are provided according to aspects of the present disclosure. Further embodiments are described in the dependent claims.

[0009] Further embodiments of the present disclosure can provide a display device comprising a substrate, an active layer arranged on the substrate (the active layer having a channel region), a first region arranged on one side of the channel region, and a second region arranged on the other side of the channel region. A gate insulating layer can be arranged on the active layer and can have a first opening. A first electrode can be electrically connected to at least one section of the first region in the first opening, and a second electrode can be arranged on the gate insulating layer and overlap the channel region.

[0010] A protective layer can be arranged on the first and second electrodes, can overlap at least a section of the first electrode, and can have a second opening that overlaps at least a section of the first opening. Furthermore, a pixel electrode can be arranged on the protective layer and electrically connected to the first electrode in the second opening.

[0011] Further embodiments of the present disclosure can provide a display device with a substrate and a driver transistor arranged on the substrate, the driver transistor having an active layer, a first electrode, a second electrode, and a third electrode. A light-emitting device can include a pixel electrode electrically connected to the first electrode, a common electrode facing the pixel electrode, and a storage capacitor arranged on the driver transistor and overlapping a channel region of the driver transistor's active layer.

[0012] As described herein, it is possible to provide a display device capable of reducing the size of the sub-pixel circuit section provided in each sub-pixel through structural optimization.

[0013] It is also possible to provide a display device that is able to reduce the size of the sub-pixel circuit through structural optimization, thereby increasing the size of the aperture within each sub-pixel, improving the light extraction efficiency, and reducing power consumption.

[0014] It is further possible to provide a display device that is able to simplify the structure of a sub-pixel circuit and reduce the size of a sub-pixel circuit by applying an overlap structure of an opening in a protective layer and an opening in a gate insulating layer to a sub-pixel circuit.

[0015] Thus, it is possible to provide a display device that is able to simplify the structure of a sub-pixel circuit and reduce the size of a sub-pixel circuit by applying a non-overlapping structure of an opening of a protective layer and a storage capacitor to the sub-pixel circuit.

[0016] It is also possible to provide a display device in which a pixel electrode is electrically connected to an active layer, with an electrode of a drive transistor placed in between to form a current path within a sub-pixel circuit, thereby reducing contact resistance compared to a direct connection structure between the pixel electrode and the active layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objectives, features / characteristics and advantages of the present disclosure will become clearer to a person skilled in the art by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which: Fig. 1 is a representation that depicts a display device according to embodiments of the present disclosure; Fig. 2 and Fig. 3. Provide an example of a sub-pixel arranged in a display device according to embodiments of the present disclosure; Fig. 4 represents a further example of a sub-pixel of a display device according to embodiments of the present disclosure; Fig. 5 and Fig. 6. An implementation example of a sub-pixel according to embodiments of the present disclosure; Fig. 7 and Fig. 8. A further implementation example of a sub-pixel according to embodiments of the present disclosure; and Fig. 9 and Fig. 10 represents a further implementation example of a sub-pixel according to embodiments of the present disclosure. DETAILED DESCRIPTION OF THE EXECUTION FORMS

[0018] In the following disclosure, reference is made to the accompanying drawings, which show specific examples or embodiments that can be implemented for illustrative purposes, and in which the same reference numerals and symbols can be used to denote the same or similar components, even if they are shown in different accompanying drawings. Furthermore, in the following description of examples or embodiments of the present disclosure, detailed descriptions of various related functions and components contained herein are omitted where it is determined that such descriptions may render the subject matter rather unclear in some embodiments of the present disclosure.

[0019] Terms such as "identifying," "having," "containing," "forming," "educating," and "educated" used herein are generally intended to allow the addition of other components, unless the terms are used with the term "only." As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise.

[0020] In addition, the features of different embodiments of the present disclosure can be partially or completely coupled or combined with one another and can interact and be operated in technically different ways, and the embodiments can be implemented independently of one another or in association with one another. Furthermore, the term "can" used herein encompasses all meanings and definitions of the term "may / may".

[0021] Additionally, terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used herein to describe elements of the present revelation. Each of these terms is not used to define the essence, order, sequence, or number of elements, etc., but is used merely to distinguish the corresponding element from other elements.

[0022] When it is mentioned that a first element is "connected," "coupled," "contacted," "overlapped," etc., with a second element, it should be interpreted that not only can the first element be "directly connected or coupled" with the second element, or the second element "directly contacted or overlapped," but a third element can also be "arranged" between the first and second elements, or the first and second elements can be "connected," "coupled," "contacted," "overlapped," etc., via a fourth element. Here, the second element can be contained within at least one of two or more elements that are "connected," "coupled," "contacted," "overlapped," etc., with each other.

[0023] When time-related terms such as "after", "subsequent", "next", "before", and the like are used to describe processes or operations of elements or configurations or sequences or steps in operating, processing, or manufacturing procedures, these terms may be used to describe non-consecutive or non-sequential processes or operations unless the term "direct" or "immediate" is used together.

[0024] Additionally, whenever any dimensions, relative sizes, etc., are mentioned, it should be noted that numerical values ​​for elements or features, or corresponding information (e.g., level, range, etc.), have a tolerance or error range that can be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if a relevant description is not specified. Furthermore, the term "may / can" fully encompasses all meanings of the term "can."

[0025] Various embodiments of the disclosure are described in detail below with reference to the accompanying drawings.

[0026] In particular, Fig. 1 a representation that depicts a display device 100 according to embodiments of the present disclosure.

[0027] With reference to Fig. 1 The display device 100 can have a display panel 110 and a control circuit for controlling the display panel 110.

[0028] As shown, the control circuit can comprise a data control circuit 120, a gate control circuit 130 and a control device 140 for controlling the data control circuit 120 and the gate control circuit 130.

[0029] Additionally, the display panel 110 can have a substrate SUB, a plurality of data lines DL, and a plurality of gate lines GL arranged on the substrate SUB. The display panel 110 can also have a plurality of sub-pixels SP connected to the data lines DL and the gate lines GL.

[0030] The display panel 110 can have a display area DA, in which an image is displayed, and a non-display area NDA, in which no image is displayed. The sub-pixels SP for displaying an image are arranged in the display area DA of the display panel 110. In the non-display area NDA, the data drive circuit 120, the gate drive circuit 130, and the control device 140 can be electrically connected, or alternatively, one or more of the data drive circuit 120, the gate drive circuit 130, and the control device 140 can be mounted, and a pad section to which an integrated circuit or a printed circuit can be connected can be arranged.

[0031] Furthermore, the data control circuit 120 serves to control the data lines DL and can supply data signals to the data lines DL. The gate control circuit 130 can be a circuit for controlling the gate lines GL and can supply a gate signal to the gate lines GL. The control device 140 can supply a data control signal DCS to the data control circuit 120 to control the operating timing of the data control circuit 120, can supply image data DATA to the data control circuit 120, and can supply a gate control signal GCS to the gate control circuit 130 to control the operating timing of the gate control circuit 130.

[0032] Furthermore, the control device 140 can receive input image data from an external source (e.g., host system 150), sample the received input image data according to the timing implemented in each frame of the received input image data, convert the externally input received input image data into a data signal format used by the data control circuit 120, supply image data DATA to the data control circuit 120, and control the data control at a suitable time according to the sampling of the received input image data.

[0033] Furthermore, the control device can output 140 different gate control signals GCS, which include a gate start pulse (GSP), a gate shift clock (GSC) and a gate output enable signal (GOE) to control the gate drive circuit 130.

[0034] Additionally, the control device can output 140 different data control signals DCS, which include a source start pulse (SSP), a source sample clock (SSC) and a source output enable signal (SOE) to control the data control circuit 120.

[0035] The control device 140 can be implemented as a component separate from the data control circuit 120, or it can be implemented as an integrated circuit by being integrated with the data control circuit 120.

[0036] Furthermore, the data control circuit 120 can receive image data DATA from the control device 140 and supply data voltages to a plurality of data lines DL, thereby controlling the data lines DL. Here, the data control circuit 120 can also be referred to as a source control circuit.

[0037] Additionally, the data control circuit 120 can include at least one integrated source driver circuit (SDIC). For example, each integrated source driver circuit (SDIC) can be connected to the display panel 110 in a tape-automated bonding (TAB) manner, can be connected to a bonding pad of the display panel 110 in a chip-on-glass (COG) or chip-on-panel (COP) manner, or can be implemented in a chip-on-film (COF) manner and connected to the display panel 110.

[0038] Furthermore, the gate drive circuit 130 can output a gate signal of a turn-on voltage level or a gate signal of a turn-off voltage level according to the control of the control device 140. The gate drive circuit 130 can also sequentially drive a plurality of gate lines GL by sequentially supplying gate signals of a turn-on voltage level to a plurality of gate lines GL.

[0039] The gate driver circuit 130 can be connected to the display panel 110 in a tape-automated bonding (TAB) manner, to a bonding pad of the display panel 110 in a chip-on-glass (COG) or chip-on-panel (COP) manner, or to the display panel 110 in a chip-on-film (COF) manner. Alternatively, the gate driver circuit 130 can be configured as a gate-in-panel (GIP) type within a non-display area (NDA) of the display panel 110. Additionally, the gate driver circuit 130 can be located on or connected to the substrate SUB. If the gate driver circuit 130 is a GIP type device, it can be located within the non-display area (NDA) of the substrate SUB. The gate control circuit 130 can also be connected to the substrate SUB if it is a chip-on-glass (COG) type or a chip-on-film (COF) type.

[0040] Additionally, at least one of the data control circuit 120 and the gate control circuit 130 can be located in the display area DA. For example, at least one of the data control circuit 120 and the gate control circuit 130 can be located such that it does not overlap with the sub-pixels SP, or it can be located such that it partially or completely overlaps with the sub-pixels SP.

[0041] Furthermore, the data control circuit 120 can convert the image data DATA received by the control device 140 into an analog data voltage for each specific gate line GL controlled by the gate control circuit 130 and supply the converted image data to a plurality of data lines DL to activate individual sub-pixels SP with a specific color and intensity. The data control circuit 120 can be connected to one side (e.g., the top or the bottom) of the display panel 110. Depending on the control method and the panel design, the data control circuit 120 can be connected to both sides (e.g., the top and the bottom) of the display panel 110 or to two or more of the four sides of the display panel 110.

[0042] Furthermore, the gate control circuit 130 can be connected to one side (e.g., the left side or the right side) of the display panel 110. Depending on the gate control method and the panel design method, the gate control circuit 130 can be connected to both sides (e.g., the left side and the right side) of the display panel 110, or it can be connected to two or more of the four sides of the display panel 110.

[0043] Furthermore, the display control device 140 can be a timing control device used in related examples of display technology, can be a control device capable of performing other control functions, including timing control, can be a control device other than timing control, or can be a circuit within a control device. The control device 140 can be implemented with various circuits or electronic components, such as an integrated circuit (IC), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or a processor.

[0044] Furthermore, the control device 140 can be mounted on a printed circuit board, a flexible printed circuit, etc. The control device 140 can also be electrically connected to the data control circuit 120 and the gate control circuit 130 via the printed circuit board, flexible printed circuit, etc.

[0045] Furthermore, the display device 100 can be a display having a backlight unit, such as a liquid crystal display, or it can be a self-illuminating display, such as an organic light-emitting diode (OLED) display, a quantum dot display, a micro-light-emitting diode (LED) display, etc. If the display device 100 is an organic light-emitting diode (OLED) display, each sub-pixel SP can have an OLED capable of emitting light itself. If the display device 100 is a quantum dot display, each sub-pixel SP can have a light-emitting device made from a quantum dot, which is a semiconductor crystal that emits light itself.If the display device 100 is a micro-LED display, each sub-pixel SP can have a micro-LED capable of emitting light itself and is made of an inorganic material as a light-emitting device.

[0046] The display panel 110 can have a top-emission structure or a bottom-emission structure and in some cases can have a double-sided emission structure.

[0047] Next, we will... Fig. 2 and Fig. Figure 3 represents an example of a sub-pixel SP arranged in a display device 100. In particular, it represents Fig. 2 an example of an equivalent circuit of a sub-pixel SP according to embodiments of the present disclosure, and Fig. Figure 3 is a representation to further explain the equivalent circuit of the sub-pixel SP, which is in Fig. 2 is shown.

[0048] With reference to Fig. 2 Each sub-pixel SP can have a light-emitting device ED and a sub-pixel circuit section SPC configured to drive the light-emitting device ED.

[0049] As in Fig. As shown in Figure 2, the sub-pixel circuit SPC can include a drive transistor DT for driving a light-emitting device ED, a scan transistor SCT for transmitting a data voltage VDATA to a first node N1 of the drive transistor DT, and a storage capacitor Cst between the first node N1 and a second node N2 to maintain a constant voltage for a frame.

[0050] The light-emitting device ED can have a pixel electrode PE and a common electrode CE and an emission layer EL arranged between the pixel electrode PE and the common electrode CE.

[0051] Furthermore, the pixel electrode PE of the light-emitting device ED can be an electrode arranged for each sub-pixel SP, and the common electrode CE can be an electrode arranged for all sub-pixels SP. Here, the pixel electrode PE can be an anode electrode, and the common electrode CE can be a cathode electrode. Alternatively, the pixel electrode PE can be a cathode electrode, and the common electrode CE can be an anode electrode.

[0052] Furthermore, the common electrode CE of the light-emitting device ED can be connected to a low-potential voltage line VSSL, which applies a low-potential voltage EVSS.

[0053] The light-emitting device ED can be, for example, an organic light-emitting diode (OLED), a light-emitting diode (LED), or a quantum dot light-emitting device.

[0054] Additionally, the control transistor DT serves to control the light-emitting device ED and can have the first node N1, the second node N2, a third node N3 and the like.

[0055] The first node N1 of the control transistor DT can be a source node or a drain node of the control transistor DT and can be electrically connected to the pixel electrode PE of the light-emitting device ED.

[0056] The second node N2 of the control transistor DT can be the gate node of the control transistor DT and can be electrically connected to the source node or drain node of the scan transistor SCT.

[0057] The third node N3 of the control transistor DT can be the drain node or source node of the control transistor DT and can be electrically connected to a high-potential voltage line VDDL that provides a high-potential power supply voltage EVDD.

[0058] Additionally, the driver transistor DT can have unique properties, such as threshold voltage and mobility. If the unique properties of the driver transistor DT change, the current drive capability (e.g., current supply power) of the driver transistor DT changes, and the emission characteristics of the corresponding sub-pixel SP may also change.

[0059] The device characteristics (e.g., threshold voltage, mobility, etc.) of the control transistor DT can change as the control time of the control transistor DT elapses. Additionally, if light is shone onto the control transistor DT, particularly if light is shone onto the channel area of ​​the control transistor DT, the device characteristics (e.g., threshold voltage, mobility, etc.) of the control transistor DT can change.

[0060] Therefore, as in Fig. Figure 2 shows that a shielding structure LS is formed near the driver transistor DT to reduce changes in the device properties (e.g., threshold voltage changes, mobility changes, etc.) of the driver transistor DT. For example, the shielding structure LS can be formed under the active layer of the driver transistor DT.

[0061] In addition to the light-blocking role, the shielding structure LS can be formed under the channel area of ​​the drive transistor DT and can serve as a functional part of the drive transistor DT.

[0062] As a result, the shielding structure LS can shield the drive transistor DT from light, e.g. reducing the reflection of external light if the display panel 110 is a bottom-emission structure, but can also influence the electric field of a channel area of ​​the drive transistor DT if the shielding structure LS is electrically connected to the first node N1 of the drive transistor DT.

[0063] Additionally, the scan transistor SCT can be controlled by means of a scan-gate signal SCAN, which is a type of gate signal, and can be connected between the second node N2 of the control transistor DT and the data line DL.

[0064] As a result, the scan transistor SCT can be turned on or off according to the scan-gate signal SCAN, which is supplied by a scan-gate line SCL, which is a type of gate line GL, in order to control the connection between the data line DL and the second node N2 of the drive transistor DT.

[0065] Additionally, the scan transistor SCT can be switched on by means of a scan-gate signal SCAN, which has a switch-on voltage, and can transmit the data voltage VDATA, which is supplied by the data line DL, to the second node N2 of the control transistor DT.

[0066] If the scan transistor SCT is an n-type transistor, the turn-on voltage of the scan gate signal SCAN can be a high-level voltage. If the scan transistor SCT is a p-type transistor, the turn-on voltage of the scan gate signal SCAN can be a low-level voltage.

[0067] Furthermore, the storage capacitor Cst can be connected between the first node N1 and the second node N2 of the control transistor DT. The storage capacitor Cst can also be charged with an amount corresponding to the voltage difference between its two terminals and can maintain this voltage difference for a set frame time. Accordingly, the corresponding sub-pixel SP can emit light during a given frame time.

[0068] With reference to Fig. 2 and Fig. 3. A sub-pixel SP can have: an emission region (i.e., an aperture, EA) in which a light-emitting device ED is arranged, and a sub-pixel circuit SPC in which a drive transistor DT and a scan transistor SCT are arranged. Here, the sub-pixel circuit SPC can have: a scan transistor region SCTA in which a scan transistor SCT is arranged, and a drive transistor region DTA in which a drive transistor DT is arranged.

[0069] As shown, a first electrode E1, a second electrode E2 and a third electrode E3 of the control transistor DT can be arranged in the control transistor area DTA.

[0070] For example, the first electrode E1 can be a source electrode or a drain electrode of the control transistor DT, the second electrode E2 can be a gate electrode of the control transistor DT, and the third electrode E3 can be a drain electrode or a source electrode of the control transistor DT.

[0071] With reference to Fig. 3 The third electrode E3, which is located in the control transistor area DTA, can overlap with a high potential voltage line VDDL, and the third electrode E3 can be electrically connected to the high potential voltage line VDDL at a position that overlaps with the high potential voltage line VDDL.

[0072] Accordingly, the third electrode E3 can be arranged on the high-potential voltage line VDDL and can be electrically connected to the high-potential voltage line VDDL.

[0073] With reference to Fig. 2 and Fig. 3. The light-emitting device ED, located in the emission region EA, can have a pixel electrode PE, an emission layer EL, and a common electrode CE. Here, the pixel electrode PE can extend from the emission region EA in the direction of the control transistor region DTA and overlap with the first electrode E1 and the second electrode E2 of the control transistor DT.

[0074] Additionally, the driver transistor area (DTA) can be designed with an opening overlap structure in which the opening of the protection layer and the opening of the gate insulating layer overlap, thereby simplifying the structure of the sub-pixel circuit SPC and reducing the size of the sub-pixel circuit SPC.

[0075] An opening-overlap structure applied to the sub-pixel circuit SPC will be described later with reference to Fig. 5 to Fig. 10 specifically described.

[0076] For reference Fig. 5 and Fig. Figure 6 presents an implementation example of a sub-pixel SP, Fig. 7 and Fig. Figure 8 represents another implementation example of a sub-pixel SP, and Fig. 9 and Fig. Figure 10 represents another implementation example of a sub-pixel SP. However, the embodiments of the present disclosure are not limited to this, and the configurations described below with reference to Fig. 5 to Fig. The 10 described can also be applied as a single implementation example of a sub-pixel SP.

[0077] Next, [the text] presents Fig. Figure 4 shows another example of a sub-pixel SP of a display device 100.

[0078] In particular, Fig. Figure 4 presents another example of an equivalent circuit of a sub-pixel SP according to embodiments of the present disclosure. As in Fig. As shown in Figure 4, each of a plurality of sub-pixels SP arranged on a display panel 110 of a display device 100 can further include a sensing transistor SENT.

[0079] Additionally, the sensing transistor SENT can be controlled by a sensing gate signal SENSE, which is a type of gate signal, and can be connected between the first node N1 of a drive transistor DT and a reference voltage line RVL. In other words, the sensing transistor SENT can be switched on or off according to the sensing gate signal SENSE, which is supplied by the sensing gate line SENL, which is a different type of gate line GL, in order to control the connection between the reference voltage line RVL and the first node N1 of the drive transistor DT.

[0080] The sensing transistor SENT can also be switched on by means of a sensing gate signal SENSE, which has the switch-on level voltage, and can transmit a reference voltage Vref, supplied by the reference voltage line RVL, to the first node N1 of the control transistor DT.

[0081] Additionally, the sensing transistor SENT can be switched on by means of the sensing gate signal SENSE, which has the switch-on level voltage, and can transmit the voltage of the first node N1 of the control transistor DT to the reference voltage line RVL.

[0082] If the sensing transistor SENT is an n-type transistor, the turn-on voltage of the sensing gate signal SENSE can be a high-level voltage. If the sensing transistor SENT is a p-type transistor, the turn-on voltage of the sensing gate signal SENSE can be a low-level voltage.

[0083] The function of the sensing transistor SENT, which transmits the voltage of the first node N1 of the drive transistor DT to the reference voltage line RVL, can be used during drive operation to detect the characteristic value of the sub-pixel SP. In this situation, the voltage transmitted to the reference voltage line RVL can be a voltage used to calculate the characteristic value of the sub-pixel SP or a voltage in which the characteristic value of the sub-pixel SP is reflected.

[0084] Furthermore, each of the drive transistor DT, the scan transistor SCT, and the sensing transistor SENT can be an n-type or a p-type transistor. In the embodiments of the present disclosure, for the sake of simplicity, each of the drive transistor DT, the scan transistor SCT, and the sensing transistor SENT of the present example is an n-type transistor.

[0085] Additionally, the storage capacitor Cst can be an external capacitor that is intentionally designed to be outside the drive transistor DT, rather than a parasitic capacitor, such as an internal capacitor that exists between the gate node and the source node (Cgs) of the drive transistor DT, and an internal capacitor that exists between the gate node and the drain node (Cgd) of the drive transistor DT.

[0086] Additionally, the scan gate line SCL and the capture gate line SENL can be different gate lines GL. In this situation, the scan gate signal SCAN and the capture gate signal SENSE can be separate gate signals, and the on-off timing of the scan transistor SCT and the on-off timing of the capture transistor SENT in a sub-pixel SP can be independent. The on-off timing of the scan transistor SCT and the on-off timing of the capture transistor SENT in a sub-pixel SP can be the same or different.

[0087] Alternatively, the scan gate line SCL and the capture gate line SENL can be the same gate line GL, and a gate node of the scan transistor SCT and a gate node of the capture transistor SENT in a sub-pixel SP can be connected to a single gate line GL. In this situation, the scan gate signal SCAN and the capture gate signal SENSE can be the same gate signal, and the on-off timing of the scan transistor SCT in a sub-pixel SP and the on-off timing of the capture transistor SENT in a sub-pixel SP can be the same.

[0088] The structure of the sub-pixel SP, which is in Fig. 2 and Fig. Figure 4 is just an example and can be modified in various ways to include one or more transistors or one or more capacitors.

[0089] Next are Fig. 5 and Fig. 6 illustrations that represent another implementation example of a sub-pixel SP.

[0090] In particular, Fig. Figure 5 shows a top view according to an implementation example of a drive transistor area DTA provided in a sub-pixel SP, and Fig. Figure 6 shows a cross-sectional view of the control transistor area DTA along the line AA', which is shown in the top view of Fig. 5 is shown.

[0091] With reference to Fig. 5 and Fig. 6 An exemplary sub-pixel SP can have a substrate 610, a shielding structure LS arranged on the substrate 610, a buffer layer 620 arranged on the substrate 610 and the shielding structure LS, and an active layer ACT arranged on the buffer layer 620.

[0092] The sub-pixel SP can further comprise a gate insulating layer 640 arranged on the active layer ACT, a first electrode E1, a second electrode E2 arranged to overlap with at least one section of the gate insulating layer 640, a protective layer 630 arranged on the first electrode E1 and the second electrode E2, and a pixel electrode PE of a light-emitting device ED arranged on the protective layer 630.

[0093] In addition, the sub-pixel SP can also have a coating layer 650, which is arranged on the protective layer 630.

[0094] The active layer ACT can have a channel area CH, a first area CT1 located on one side of the channel area CH, and a second area CT2 located on the other side of the channel area CH.

[0095] The active layer ACT can be implemented as a single-layer structure, and in this situation the active layer ACT can comprise at least one material of indium gallium zinc oxide (IGZO) and indium zinc oxide (IZO), but the embodiments of the present disclosure are not limited thereto.

[0096] Furthermore, the sub-pixel SP can also have an auxiliary electrode located between the active layer ACT and the first electrode E1, and the auxiliary electrode can have a transparent conductive oxide.

[0097] For example, the transparent conductive oxide may contain at least one of the following: indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), antimony tin oxide (ATO), and fluorine-doped transparent oxides (FTO).

[0098] As a further example, if an auxiliary electrode is arranged between the active layer ACT and the first electrode E1, one of the active layer ACT and the auxiliary electrode may comprise an indium gallium zinc oxide (IGZO) material, and the other may comprise an indium zinc oxide (IZO) material. However, the embodiments of the present disclosure are not limited thereto.

[0099] If the auxiliary electrode is not arranged, the active layer ACT can be an active layer in which at least one section of the active layer ACT is conductive. For example, the active layer ACT can be conductive in at least one section of the remaining area, with the exception of an area that overlaps with the channel area CH, but the embodiments of the present disclosure are not limited thereto.

[0100] Furthermore, the gate insulating layer 640 can have a first opening H1, and the first electrode E1 can be electrically connected to at least one section of the first region CT1 of the active layer ACT in the first opening H1.

[0101] Accordingly, the first opening H1 of the gate insulating layer 640 can have a second connecting section CA2 in which the first electrode E1 and the first area CT1 of the active layer ACT are electrically connected.

[0102] Additionally, the first electrode E1 can be positioned so that it is electrically connected to the first region CT1 and can be positioned so that it overlaps a section of the gate insulating layer 640. For example, the first electrode E1 can be a source electrode or a drain electrode of the driver transistor DT. The second electrode E2 can be positioned on the gate insulating layer 640 and can overlap with the channel region CH. Thus, the second electrode E2 can be a gate electrode of the driver transistor DT.

[0103] The protective layer 630 can have a second opening H2 that overlaps at least a section of the first electrode E1 and overlaps at least a section of the first opening H1.

[0104] Furthermore, the pixel electrode PE can be electrically connected to the first electrode E1 at the second opening H2, and can be electrically connected to the shielding structure LS at the second opening H2.

[0105] Accordingly, the second opening H2 can have a first connecting section CA1, through which the pixel electrode PE and the first electrode E1 are electrically connected, and a third connecting section CA3, through which the pixel electrode PE and the shielding structure LS are electrically connected.

[0106] Furthermore, in a single opening of the protective layer 630 (e.g. in the second opening H2) the pixel electrode PE can be electrically connected to the first electrode E1 and the shielding structure LS simultaneously.

[0107] Since at least one section of the first opening H1 and at least one section of the second opening H2 overlap, and at least one section of the first connecting section CA1 and at least one section of the second connecting section CA2 can also overlap.

[0108] Through the first connection section CA1, the second connection section CA2 and the third connection section CA3, the pixel electrode PE, the first electrode E1, the first area CT1 of the active layer ACT and the shielding structure LS can be electrically connected to each other in such a way that they form a node, i.e. the first node N1.

[0109] For example, a node formed by a pixel electrode PE, a first electrode E1, a first area CT1 of an active layer ACT and a shielding structure LS can be a source node of a drive transistor DT, but the embodiments of the present disclosure are not limited thereto.

[0110] It is possible that the second opening H2 does not overlap a storage capacitor Cst, which is arranged in each of a plurality of sub-pixels SP, and it is possible that a node formed by a pixel electrode PE, a first electrode E1, a first area CT1 of an active layer ACT and a shielding structure LS does not overlap a storage capacitor Cst.

[0111] With reference to Fig. 5 and Fig. 6. The storage capacitor Cst can overlap a channel area CH, which may have a gate node (i.e., the second node N2) of the drive transistor DT.

[0112] The second electrode E2 can be any of the capacitor electrodes that form the storage capacitor Cst, and the pixel electrode PE can be another of the capacitor electrodes that form the storage capacitor Cst.

[0113] In particular, the storage capacitor Cst can have the second electrode E2 as a first capacitor electrode, and the pixel electrode PE adjacent to the second electrode E2 as a second capacitor electrode. Additionally, the protective layer 630, which is provided between the first and second capacitor electrodes, can be included as an insulator of the storage capacitor Cst.

[0114] With reference to Fig. 5 and Fig. 6. The active layer ACT can have a circumferential region comprising a first connection section CA1, provided in the second opening H2, and a second connection section CA2, also provided in the first opening H1. Additionally, a current path (C / P) can be formed in the active layer ACT within this circumferential region.

[0115] Accordingly, it is possible that the vertically overlapping pixel electrode PE and the active layer ACT are not directly connected, but can be connected via the first electrode E1, thus forming a current path (C / P) of the active layer ACT around the first opening H1 and the second opening H2. This allows for a reduction in the size of the sub-pixel circuit SPC and prevents a drive error due to high contact resistance, which occurs when the pixel electrode PE and the active layer ACT are directly connected.

[0116] With reference to Fig. 5. The second electrode E2, which overlaps with the channel region CH of the active layer ACT, can extend to a region that does not overlap with the active layer ACT and can be electrically connected to the source electrode or the drain electrode ACT_SC of the scan transistor SCT. For the sake of simplicity, the reference symbol 'ACT_SC' can be described as the source electrode of the scan transistor SCT.

[0117] The SP sub-pixel from Fig. 5 may further comprise a third electrode E3 which extends to an area in which the second area CT2 of the active layer ACT and the high-potential voltage line VDDL are formed, and which overlaps with the high-potential voltage line VDDL and the second area CT2.

[0118] The third electrode E3 can be electrically connected to at least one section of the high-potential voltage line VDDL and to at least one section of the second region CT2 of the active layer ACT via the high-potential voltage line VDDL. Accordingly, a high-potential power supply voltage EVDD can be applied to the second region CT2 via the high-potential voltage line VDDL. The third electrode E3 can be a drain electrode or a source electrode of a driver transistor. If an auxiliary electrode is arranged between the active layer ACT and the first electrode E1, an auxiliary electrode can also be arranged between the active layer ACT and the third electrode E3.

[0119] According to the example from Fig. 5. The high-potential voltage line VDDL and the data line DL can be made of the same material as the shielding structure LS.

[0120] Additionally, the scan-gate line SCL and the first electrode E1, the second electrode E2, and the third electrode (E3) of the control transistor DT can be made of the same material. Furthermore, the active layer ACT of the control transistor DT and the source electrode ACT_SC of the scan transistor SCT can be made of the same material.

[0121] Next are Fig. 7 and Fig. 8 illustrations showing other implementation examples of a sub-pixel SP.

[0122] In particular, Fig. Figure 7 shows a top view according to a further embodiment of a drive transistor region DTA provided in a sub-pixel SP, and shows an enlarged view of a first electrode E1 and a second electrode E2 section of the drive transistor DT compared to Fig. 5 dar, and Fig. Figure 8 shows a cross-sectional view of the control transistor area DTA along line BB', which is shown in the top view of Fig. 7 is shown.

[0123] As in Fig. 7 and Fig. As shown in Figure 8, an exemplary sub-pixel SP can have a substrate 610, a shielding structure LS arranged on the substrate 610, a buffer layer 620 arranged on the substrate 610 and the shielding structure LS, and an active layer ACT arranged on the buffer layer 620.

[0124] The sub-pixel SP can comprise a gate insulating layer 640 arranged on the active layer ACT and having a first opening H1, a first electrode E1 arranged to overlap with at least one section of the gate insulating layer 640, a protective layer 630 arranged on the first electrode E1, and a pixel electrode PE of a light-emitting device ED arranged on the protective layer 630.

[0125] Additionally, the sub-pixel SP can further comprise a coating layer 650 arranged on the protective layer 630. The sub-pixel SP can further comprise an auxiliary electrode 800 arranged between the active layer ACT and the first electrode E1, and the auxiliary electrode 800 can comprise a transparent conductive oxide.

[0126] For example, the transparent conductive oxide can comprise at least one of the following: indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), antimony tin oxide (ATO), and fluorine-doped transparent oxides (FTO). Additionally, one of the active layer (ACT) and the auxiliary electrode can comprise an indium gallium zinc oxide (IGZO) material, and the other can comprise an indium zinc oxide (IZO) material, but the embodiments of the present disclosure are not limited thereto.

[0127] The active layer ACT can also have a channel region CH, a first region CT1 located on one side of the channel region CH, and a second region CT2 located on the other side of the channel region CH. The first electrode E1 can be electrically connected to at least one section of the first region CT1 of the active layer ACT in the first opening H1.

[0128] In other words, the first electrode E1 can be electrically connected to the auxiliary electrode 800 and the active layer ACT in the first opening H1. Accordingly, the first opening H1 of the gate insulating layer 640 can have a second connecting section CA2 through which the first electrode E1 and the first region CT1 of the active layer ACT are electrically connected.

[0129] Furthermore, the first electrode E1 can be a source electrode or a drain electrode of the control transistor DT.

[0130] The protective layer 630 is arranged on the first electrode E1 and can have a second opening H2 which overlaps at least a section of the first electrode E1 and overlaps at least a section of the first opening H1.

[0131] The pixel electrode PE can be electrically connected to the first electrode E1 at the second opening H2, and can be electrically connected to the shielding structure LS at the second opening H2.

[0132] The second opening H2 can have a first connection section CA1, in which the pixel electrode PE and the first electrode E1 are electrically connected, and a third connection section CA3, in which the pixel electrode PE and the shielding structure LS are electrically connected.

[0133] Accordingly, the pixel electrode PE can be electrically connected to the first electrode E1 and the shielding structure LS simultaneously in a single opening of the protective layer 630, i.e. at the second opening H2.

[0134] Through the first connection section CA1, the second connection section CA2 and the third connection section CA3, the pixel electrode PE, the first electrode E1, the first area CT1 of the active layer ACT and the shielding structure LS can be electrically connected to each other in such a way that they form a node, i.e. the first node N1.

[0135] For example, the node formed by the pixel electrode PE, the first electrode E1, the first area CT1 of the active layer ACT and the shielding structure LS can be a source node of the drive transistor DT, but the embodiments of the present disclosure are not limited thereto.

[0136] It is possible that the node formed by the pixel electrode PE, the first electrode E1, the first area CT1 of the active layer ACT and the shielding structure LS does not overlap the storage capacitor Cst, which is arranged in each of the sub-pixels SP formed on the substrate.

[0137] As a variation of the in Fig. In the device shown in Figure 6, the first electrode E1 can be omitted to allow the pixel electrode PE to directly contact the first region CT1 of the active layer ACT. The removal of the first electrode E1 can also be carried out in the following embodiments. In various other embodiments, a layer used to create the pixel electrode PE can be structured such that it also provides an electrode that directly contacts the third region CT3 of the active layer ACT.

[0138] With reference to Fig. 7. The storage capacitor Cst can overlap with the channel area CH, which in the present situation has the second node N2 as a gate node of the control transistor DT.

[0139] With reference to Fig. 7 and Fig. 8 The current path C / P of the active layer ACT can be formed in a region that passes through the second connection section CA2, where the first electrode E1 and the first region CT1 of the active layer ACT are electrically connected.

[0140] In other words, the embodiments of the present disclosure can form a current path C / P of the active layer ACT in a lower region of the first electrode E1 by connecting the pixel electrode PE and the active layer ACT, which are vertically overlapping, through the first electrode E1 and the auxiliary electrode 800, without directly connecting the pixel electrode PE and the active layer ACT, thereby reducing the size of the sub-pixel circuit SPC and preventing a control error caused by a high contact resistance that occurs when the pixel electrode PE and the active layer ACT are directly connected.

[0141] Furthermore, parts of the buffer layer 620, the protective layer 630, the gate insulating layer 640, the first electrode E1 and the active layer ACT may not overlap with the shielding structure LS, and each of the buffer layer 620, the protective layer 630, the gate insulating layer 640, the first electrode E1 and the active layer ACT may have a step in the area that does not overlap with the shielding structure LS.

[0142] In other words, the sub-pixel SP can be implemented as a PAD-free structure in which the shielding structure LS is not located under at least some areas of the second connection section CA2.

[0143] Next are Fig. 9 and Fig. 10 illustrations that represent another implementation example of the sub-pixel SP.

[0144] In particular, Fig. 9 a top view according to a further embodiment of a drive transistor area DTA provided in a sub-pixel SP, and is a drawing which, in comparison to the top view of Fig. 7 turned to the left and right, and Fig. Figure 10 is a cross-sectional view of the control transistor area DTA along the line C-C', which is shown in the top view from Fig. 9 is shown.

[0145] With reference to Fig. 9 and Fig. 10. A sub-pixel SP according to embodiments of the present disclosure can comprise a substrate 610, a shielding structure LS arranged on the substrate 610, a buffer layer 620 arranged on the substrate 610 and the shielding structure LS, and an active layer ACT arranged on the buffer layer 620.

[0146] Additionally, the sub-pixel SP can have a gate insulating layer 640 arranged on an active layer ACT, a first electrode E1 and a second electrode E2 arranged to overlap with at least one section of the gate insulating layer 640, a protective layer 630 arranged on the first electrode E1 and the second electrode E2, and a pixel electrode PE of a light-emitting device ED arranged on the protective layer 630.

[0147] Furthermore, the sub-pixel SP can also have a coating layer 650 arranged on the protective layer 630.

[0148] The sub-pixel SP can further include an auxiliary electrode 800 located between the active layer ACT and the first electrode E1, and the auxiliary electrode 800 can have a transparent conductive oxide.

[0149] For example, the transparent conductive oxide can comprise at least one of the following: indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), antimony tin oxide (ATO), and fluorine-doped transparent oxides (FTO). Additionally, the auxiliary electrode can comprise an indium gallium zinc oxide (IGZO) material, and the other can comprise an indium zinc oxide (IZO) material, but the embodiments of the present disclosure are not limited thereto.

[0150] Additionally, the active layer ACT can have a channel area CH, a first area CT1 located on one side of the channel area CH, and a second area CT2 located on the other side of the channel area CH.

[0151] The gate insulating layer 640 can have a first opening H1, and the first electrode E1 can be electrically connected to the first area CT1 in the first opening H1, and can be electrically connected to the shielding structure LS.

[0152] In other words, the first opening H1 of the gate insulating layer 640 can have a second connection section CA2, in which the first electrode E1 and the first area CT1 of the active layer ACT are electrically connected, and a fourth connection section CA4, in which the first electrode E1 is electrically connected to the shielding structure LS.

[0153] The first electrode E1 can be arranged to be electrically connected to the first region CT1, and can be arranged to overlap a section of the gate insulating layer 640. For example, the first electrode E1 can be a source electrode or a drain electrode of the drive transistor DT.

[0154] With reference to Fig. 9 and Fig. 10 The second electrode E2 can be arranged to overlap with the channel area CH on the gate insulating layer 640, and the second electrode E2 can extend to an area that does not overlap with the active layer ACT.

[0155] For example, the second electrode E2 can be a gate electrode of a control transistor DT.

[0156] The protective layer 630 can have a second opening H2 which overlaps with at least one section of the first electrode E1 and which overlaps with at least one section of the first opening H1.

[0157] The pixel electrode PE can be electrically connected to the first electrode E1 in the second opening H2. Furthermore, the second opening H2 can have a first connection section CA1 in which the pixel electrode PE and the first electrode E1 are electrically connected, and the second opening H2 can further have a second connection section CA2 and a fourth connection section CA4.

[0158] Accordingly, in a single opening of the protective layer 630 (i.e., the second opening H2), the pixel electrode PE can be electrically connected simultaneously with the first electrode E1, the first area CT1 of the active layer ACT, and the shielding structure LS.

[0159] At least part of the first opening H1 and at least part of the second opening H2 can overlap. At least part of the first connecting section CA1 and at least part of the second connecting section CA2 can overlap. At least part of the first connecting section CA1 and at least part of the fourth connecting section CA4 can overlap.

[0160] Through the first connection section CA1, the second connection section CA2 and the fourth connection section CA4, the pixel electrode PE, the first electrode E1, the first area CT1 of the active layer ACT and the shielding structure LS can be electrically connected to each other in such a way that they form a node, i.e. the first node N1.

[0161] For example, a node formed by a pixel electrode PE, a first electrode E1, a first region CT1 of an active layer ACT, and a shielding structure LS can be a source node of a drive transistor DT, but the embodiments of the present disclosure are not limited thereto. It is possible that a node formed by a pixel electrode PE, a first electrode E1, a first region CT1 of an active layer ACT, and a shielding structure LS does not overlap with a storage capacitor Cst arranged in each of a plurality of sub-pixels SP.

[0162] Additionally, the storage capacitor Cst can overlap with a channel area CH. In other words, the storage capacitor Cst, located in a sub-pixel SP, can overlap a gate node of a drive transistor DT, i.e., the second node N2.

[0163] The second electrode E2 can be one of the capacitor electrodes that form the storage capacitor Cst, and the pixel electrode PE can be another of the capacitor electrodes that form the storage capacitor Cst.

[0164] For example, the storage capacitor Cst can have the second electrode E2 as a first capacitor electrode, the pixel electrode PE adjacent to the second electrode E2 as a second capacitor electrode, and can have at least a section of a protective layer 630 provided between the first capacitor electrode and the second capacitor electrode, which is included as an insulator of the storage capacitor Cst.

[0165] With reference to Fig. 9 and Fig.10. The current path C / P of the active layer ACT can be formed in a region passing through the second connection section CA2, where the first electrode E1 and the first region CT1 of the active layer ACT are electrically connected.

[0166] Accordingly, a current path (C / P) of the active layer ACT can be formed in a lower region of the first electrode E1 by connecting the pixel electrode PE and the active layer ACT, which are vertically overlapping, through the first electrode E1 and the auxiliary electrode 800, thereby reducing the size of the sub-pixel circuit SPC and preventing a drive error caused by a high contact resistance that occurs when the pixel electrode PE and the active layer ACT are directly connected.

[0167] It is possible that some areas of the buffer layer 620, the protective layer 630, the gate insulating layer 640, the first electrode E1 and the active layer ACT do not overlap with the shielding structure LS, and each of the buffer layer 620, the protective layer 630, the gate insulating layer 640, the first electrode E1 and the active layer ACT may have a step in the area that does not overlap with the shielding structure LS.

[0168] Accordingly, the sub-pixel SP can be implemented as a PAD-free structure in which at least some areas of the second connection section CA2 are not provided with the shielding structure LS underneath.

[0169] Embodiments of the present disclosure described above are briefly described below. A display device according to embodiments of the present disclosure may comprise: a substrate, an active layer arranged on the substrate and comprising a channel region, a first region arranged on one side of the channel region, and a second region arranged on the other side of the channel region, a gate insulating layer arranged on the active layer and comprising a first opening, a first electrode electrically connected to at least one section of the first region in the first opening, a second electrode arranged on the gate insulating layer and overlapping the channel region, and a protective layer arranged on the first electrode and the second electrode, overlapping at least one section of the first electrode and comprising a second opening.The display device comprises a first electrode that overlaps at least a portion of the first opening, and a pixel electrode arranged on the protective layer and electrically connected to the first electrode in the second opening. The display device may further comprise a shielding structure arranged on the substrate and a buffer layer arranged on the substrate and the shielding structure. The shielding structure may be electrically connected to the pixel electrode at the second opening. The pixel electrode, the first electrode, the active layer, and the shielding structure may be electrically connected to each other. The display device may further comprise a storage capacitor arranged on the substrate, comprising a plurality of capacitor electrodes. The storage capacitor may not overlap the second opening. One of the capacitor electrodes may be the second electrode.and the other of the capacitor electrodes can be the pixel electrode. The second electrode can extend to an area that does not overlap with the channel area.

[0170] The active layer can have a circumferential region comprising a first connection section where the pixel electrode and the first electrode are electrically connected, and a second connection section where the first electrode and the first region are electrically connected. A current path in the active layer can be formed in the circumferential region. The display device can further comprise an auxiliary electrode arranged between the active layer and the first electrode. The auxiliary electrode can have a transparent conductive oxide.

[0171] A current path in the active layer can be formed in a region that passes through a second connection section where the first electrode and the first region are electrically connected. The first electrode can be electrically connected to the shielding structure at the second opening. It is possible that at least one section of the second connection section, where the first electrode and the first region are electrically connected, does not overlap with the shielding structure.

[0172] The display device according to embodiments of the present disclosure may further comprise a light-emitting device and a control transistor for controlling the light-emitting device. The first electrode may be a source electrode or a drain electrode of the control transistor, and the second electrode may be a gate electrode of the control transistor. The first electrode and the second electrode may be made of the same material. The display device may further comprise a high-potential voltage line to which a high-potential voltage is applied; and a third electrode electrically connected between the second electrode and the high-potential voltage line. The first electrode, the second electrode, and the third electrode may be made of the same material.

[0173] A display device according to embodiments of the present disclosure can comprise a substrate, a driver transistor arranged on the substrate and comprising an active layer, a first electrode, a second electrode, and a third electrode. The display device can further comprise a light-emitting device comprising a pixel electrode electrically connected to the first electrode, a common electrode facing the pixel electrode, and a storage capacitor arranged on the driver transistor. The storage capacitor can overlap a channel region of the active layer of the driver transistor.

[0174] The display device according to embodiments of the present disclosure may further comprise: a gate insulating layer arranged on the active layer and having a first opening, and a protective layer arranged on the first electrode and the second electrode, wherein the protective layer overlaps with at least a portion of the first electrode and has a second opening that overlaps with at least a portion of the first opening. The display device may further comprise: a pixel electrode arranged on the protective layer and connected in the second opening to the first electrode, which is electrically connected to at least a portion of the active layer through the first opening.

Claims

[1] Display device (100) comprising: a substrate (SUB, 610); a transistor on the substrate (SUB, 610) wherein the transistor has an active layer (ACT) wherein the active layer (ACT) has a channel region (CH), a first region (CT1) located on one side of the channel region (CH) and a second region (CT2) located on the other side of the channel region (CH); a gate insulating layer (640) that is arranged on the active layer (ACT) and that has a first opening (H1); a first electrode (E1) that is electrically connected to at least one section of the first region (CT1) of the active layer (ACT) in the first opening (H1); a second electrode (E2) which is located on the gate insulating layer (640) and overlaps with the channel area (CH); a protective layer (630) arranged on the first electrode (E1) and the second electrode (E2), wherein the protective layer (630) overlaps with at least one section of the first electrode (E1) and has a second opening (H2) that overlaps with at least one section of the first opening (H1); and a pixel electrode (PE) which is arranged on the protective layer (630) and is electrically connected to the first electrode (E1) in the second opening (H2). [2] Display device (100) according to claim 1, further comprising: a shielding structure (LS) arranged on the substrate (SUB, 610); and a buffer layer (620) arranged on the substrate (SUB, 610) and the shielding structure (LS). [3] Display device (100) according to claim 2, wherein the shielding structure (LS) is electrically connected to the pixel electrode (PE) at the second opening (H2). [4] Display device (100) according to claim 2 or 3, wherein the pixel electrode (PE), the first electrode (E1), the active layer (ACT) and the shielding structure (LS) are electrically connected to each other. [5] Display device (100) according to any one of claims 1 to 4, further comprising a storage capacitor (Cst) arranged on the substrate (SUB, 610) and comprising a plurality of capacitor electrodes (E2, PE), wherein the storage capacitor (Cst) does not overlap with the second opening (H2). [6] Display device (100) according to claim 5, wherein one of the plurality of capacitor electrodes (E2, PE) is the second electrode (E2). [7] Display device (100) according to claim 6, wherein the other of the plurality of capacitor electrodes (E2, PE) is the pixel electrode (PE). [8] Display device (100) according to any one of claims 5 to 7, wherein the second electrode (E2) extends to an area that does not overlap with the channel area (CH). [9] Display device (100) according to any one of claims 1 to 8, wherein the active layer (ACT) has a circumferential region comprising a first connection section (CA1) where the pixel electrode (PE) and the first electrode (E1) are electrically connected, and a second connection section (CA2) where the first electrode (E1) and the first region (CT1) are electrically connected, and wherein a current path (C / P) is formed in the active layer (ACT) in the circumferential region. [10] Display device (100) according to any one of claims 1 to 8, further comprising an auxiliary electrode (800) arranged between the active layer (ACT) and the first electrode (E1), wherein the auxiliary electrode (800) comprises a transparent conductive oxide. [11] Display device (100) according to claim 10, wherein a current path (C / P) is formed in the active layer (ACT) in a region passing through a second connecting section (CA2) where the first electrode (E1) and the first region (CT1) are electrically connected. [12] Display device (100) according to claim 2 or any of claims 3 to 11 which refers directly or indirectly back to claim 2, wherein the first electrode (E1) is electrically connected to the shielding structure (LS) at the second opening (H2). [13] Display device (100) according to claim 2 or any of claims 3 to 12 which refers directly or indirectly back to claim 2, wherein the first electrode (E1) and the first area (CT1) are electrically connected at a second connection section, and wherein at least one section of the second connection section where the first electrode (E1) and the first area (CT1) are electrically connected does not overlap with the shielding structure (LS). [14] Display device (100) according to any one of claims 1 to 13, wherein the transistor is a control transistor (DT) for controlling a light-emitting device (ED), where the first electrode (E1) is a source electrode or a drain electrode of the control transistor (DT) and the second electrode (E2) is a gate electrode of the control transistor (DT), and where the first electrode (E1) and the second electrode (E2) are made of the same material. [15] Display device (100) according to any one of claims 1 to 14, further comprising: a high-potential voltage line (VDDL) to which a high-potential voltage (EVDD) is applied; and a third electrode (E3) which is electrically connected between the second area (CT2) and the high potential voltage line (VDDL). [16] Display device (100) according to claim 15, wherein the first electrode (E1), the second electrode (E2) and the third electrode (E3) are made of the same material. [17] Display device (100) comprising: a substrate (SUB, 610); a control transistor (DT) which is arranged on the substrate (SUB, 610) and which has an active layer (ACT), a first electrode (E1), a second electrode (E2) and a third electrode (E3); a light-emitting device (ED) comprising a pixel electrode (PE) electrically connected to the first electrode (E1) and a common electrode (CE) facing the pixel electrode (PE); and a storage capacitor (Cst) that is located on the control transistor (DT) and overlaps with a channel area (CH) of the active layer (ACT) of the control transistor (DT). [18] Display device (100) according to claim 17, further comprising: a gate insulating layer (640) that is arranged on the active layer (ACT) and that has a first opening (H1); a protective layer (630) arranged on the first electrode (E1) and the second electrode (E2), overlapping with at least one section of the first electrode (E1), and having a second opening (H2) that overlaps with at least one section of the first opening (H1); and a pixel electrode (PE) which is arranged on the protective layer (630) and which is connected in the second opening (H2) to the first electrode (E1) which is electrically connected to at least one section of the active layer (ACT) through the first opening (H1). [19] Display device (100) comprising: a substrate (SUB, 610); a light shield (LS) arranged on the substrate (SUB, 610); a transistor (DT) arranged in top view on and overlapping the light shield (LS), wherein the transistor (DT) has an active layer (ACT) comprising a channel region (CH) overlapping the light shield (LS), a first region (CT1) located on one side of the channel region (CH), and a second region (CT2) located on the other side of the channel region (CH); a first electrode (E1) electrically connected to the first area (CT1), a second electrode (E2) overlapping the channel area (CH), and a third electrode (E3) electrically connected to the second area (CT2); and a light-emitting device (ED) comprising a common electrode (CE) connected to a first power-voltage line (VSSL) which applies a first power voltage, a pixel electrode (PE) and a light-emitting element arranged between the common electrode (CE) and the pixel electrode (PE), wherein the pixel electrode (PE) has an integrally formed section that overlaps the second electrode (E2) to form a storage capacitor (Cst), directly contacts the first electrode (E1) and overlaps the common electrode (CE) and the light-emitting element in top view. [20] Display device (100) according to claim 19, further comprising: an insulating layer (620) between the light shield (LS) and the channel area (CH); a gate insulating layer (640) between the second electrode (E2) and the active layer (ACT), which has a first hole (H1); and an insulating layer (630) between the pixel electrode (PE) and the second electrode (E2) which has a second hole (H2) that overlaps the first hole (H1) in top view, where the first hole (H1) and the second hole (H2) overlap at a point directly above the light shield (LS).

Images