TWO-STAGE OXIDE GRID SILICON CARBIDE MOSFET

Abstract

Semiconductor devices and processes for manufacturing semiconductors are described. A semiconductor device can include a drift region formed on a silicon carbide substrate. The semiconductor device can include a trench that penetrates a source region and a channel and reaches the drift region. The semiconductor device can include an oxide region lining the trench. The oxide region can have a bottom section, a bottom section, and a top section. The thickness of the bottom section and the bottom section can be greater than the thickness of the top section. The semiconductor device can include a gate electrode formed in the trench lined with the oxide region. The semiconductor device can include a shielding region in contact with a bottom section of the trench. The width of the semiconductor region can be less than or equal to the width of the trench.

Description

BACKGROUND

[0001] The present disclosure relates generally to semiconductor devices, in particular a silicon carbide device (SiC device) comprising a two-stage oxide trench.

[0002] A metal-oxide-semiconductor field-effect transistor (MOSFET) cell can be a planar MOSFET or a trench MOSFET. Compared to planar MOSFETs, the trench structure in a trench MOSFET contributes to more efficient control of the depletion region. By vertically etching a trench into the substrate and lining it with gate oxide and a conductive material (typically polysilicon), the trench MOSFET can also achieve a higher packing density and reduce the on-resistance compared to planar MOSFETs. The trench structure also helps to minimize parasitic capacitances and improve thermal management. In one aspect, when silicon carbide (SiC) is used to form the trench MOSFET, the breakdown voltage is increased compared to silicon trench MOSFETs (Si-trench MOSFETs) because SiC has a larger band gap than silicon (Si). SUMMARY

[0003] In one embodiment, a semiconductor device can be described generally. The semiconductor device can include a semiconductor substrate of a first conductivity type. The semiconductor substrate can be formed by silicon carbide (SiC). The semiconductor device can further include a drift region of the first conductivity type formed on the semiconductor substrate. The semiconductor device can further include a channel of a second conductivity type opposite to the first conductivity type formed on the drift region. The semiconductor device can further include a source region of the first conductivity type formed on the channel. The semiconductor device can further include a trench that penetrates the source region and the channel layer and reaches the drift region. The semiconductor device can further include an oxide region that lines the trench.The oxide region can include a bottom section, a bottom section, and a top section. The thickness of the bottom section can be greater than the thickness of the top section. The thickness of the bottom section can be greater than the thickness of the top section. A gate electrode can be formed within the trench lined by the oxide region. The semiconductor device can further include a second-type conductivity shield in contact with the bottom section of the trench, and the width of the shield can be less than or equal to the width of the trench.

[0004] In one embodiment, a semiconductor device can be described generally. The semiconductor device can include a semiconductor substrate of a first conductivity type. The semiconductor substrate can be formed by silicon carbide (SiC). The semiconductor device can further include a drift region of the first conductivity type formed on the semiconductor substrate. The semiconductor device can further include a channel of a second conductivity type opposite to the first conductivity type formed on the drift region. The semiconductor device can further include a source region of the first conductivity type formed on the channel. The semiconductor device can further include a trench that penetrates the source region and the channel layer and reaches the drift region. The semiconductor device can further include an oxide region that lines the trench.The oxide region can include a bottom section, a bottom section, and a top section. The thickness of the bottom section can be greater than the thickness of the top section. The thickness of the bottom section can be greater than the thickness of the top section. At least one gate electrode can be formed in the trench lined with the oxide region. The semiconductor device can further include a second-type conductivity shield in contact with the bottom section of the trench, and the width of the shield can be less than or equal to the width of the trench.

[0005] In one embodiment, a method for fabricating a semiconductor device is generally described. The method may include forming a first oxide layer of a first thickness to line a trench formed in a silicon carbide (SiC) substrate. The method may further include forming a conductive material on a bottom section of the trench lined with the first oxide layer. The method may further include forming a nitride layer over the conductive material and along sidewalls of the trench. The method may further include etching the conductive material using the nitride layer as a hard mask. The method may further include performing a first oxidation process on a remaining section of the conductive material to form a bottom section and a lower side section of an oxide region within the trench.The process may further include removing the nitride layer and cleaning exposed trench sidewalls. The process may further include performing a second oxidation process on the exposed trench sidewalls to form an upper side section of the oxide region. The process may further include forming a gate electrode in the trench lined with the oxide region.

[0006] The foregoing summary is for illustrative purposes only and is not intended to be restrictive in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent with reference to the drawings and the following detailed description. In the drawings, identical reference numerals denote identical or functionally similar elements. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates an example of a section of a two-stage oxide-pit silicon carbide MOSFET in one embodiment. Fig. Figure 2 illustrates an example of a two-stage oxide-pit silicon carbide MOSFET in one embodiment. Fig. Figure 3 illustrates an example of an oxide region in a two-stage oxide trench silicon carbide MOSFET in one embodiment. Fig. Figure 4A illustrates a step in a manufacturing process of a two-stage oxide-pit silicon carbide MOSFET in one embodiment. Fig. Figure 4B illustrates a further step in a manufacturing process of a two-stage oxide-pit silicon carbide MOSFET in one embodiment. Fig. Figure 5A illustrates a further step in a manufacturing process of a two-stage oxide-pit silicon carbide MOSFET in one embodiment. Fig. Figure 5B illustrates a further step in a manufacturing process of a two-stage oxide-pit silicon carbide MOSFET in one embodiment. Fig. Figure 6A illustrates a further step in a manufacturing process of a two-stage oxide-pit silicon carbide MOSFET in one embodiment. Fig. Figure 6B illustrates a further step in a manufacturing process of a two-stage oxide-pit silicon carbide MOSFET in one embodiment. Fig. Figure 7A illustrates a further step in a manufacturing process of a two-stage oxide-pit silicon carbide MOSFET in one embodiment. Fig. Figure 7B illustrates a further step in a manufacturing process of a two-stage oxide-pit silicon carbide MOSFET in one embodiment. Fig. Figure 8A illustrates a further step in a manufacturing process of a two-stage oxide-pit silicon carbide MOSFET in one embodiment. Fig. Figure 8B illustrates a further step in a manufacturing process of a two-stage oxide-pit silicon carbide MOSFET in one embodiment. Fig. Figure 8C illustrates a further step in a manufacturing process of a two-stage oxide-pit silicon carbide MOSFET in one embodiment. Fig. Figure 9A illustrates another example of a two-stage oxide-pit silicon carbide MOSFET in one embodiment. Fig. Figure 9B illustrates a further step in a manufacturing process of a two-stage oxide-pit silicon carbide MOSFET in one embodiment. Fig. Figure 9C illustrates a further step in a manufacturing process of a two-stage oxide-pit silicon carbide MOSFET in one embodiment. Fig. Figure 9D illustrates a further step in a manufacturing process of a two-stage oxide-pit silicon carbide MOSFET in one embodiment. Fig. Figure 9E illustrates a further step in a manufacturing process of a two-stage oxide-pit silicon carbide MOSFET in one embodiment. Fig. Figure 10 is a flowchart illustrating a process for manufacturing a two-stage oxide-trough silicon carbide MOSFET in one embodiment. DETAILED DESCRIPTION

[0007] The following description sets out numerous specific details, such as certain structures, components, materials, dimensions, processing steps, and techniques, to provide an understanding of the various embodiments of the present application. However, the person skilled in the art will recognize that the various embodiments of the present application can be carried out without these specific details. In other cases, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0008] It is understood that when an element is described as a layer, region, or substrate being "on" or "above" another element, it may be located directly on top of the other element, or there may be intermediate elements. In contrast, when an element is described as being "directly on" or "directly above" another element, there are no intermediate elements. It is also understood that when an element is described as being "beneath" or "under" another element, it may be located directly beneath or below the other element, or there may be intermediate elements. In contrast, when an element is described as being "directly beneath" or "directly below" another element, there are no intermediate elements.

[0009] A trench-gate metal-oxide-semiconductor field-effect transistor (MOSFET) can handle considerable power and provide high-power drive capability by conducting current vertically from an upper surface to a lower surface of a semiconductor die. The trench-gate MOSFET, within its active region, can contain a large number of parallel-connected active trench-gate MOSFET cells, each containing a trench formed in the semiconductor die. Each active trench has surrounding source regions and oppositely doped body regions, and the trenches can be deep enough to traverse the body regions to a drift region below the upper surface of the semiconductor die. Each active trench-gate cell has a gate buried within the trench, which may include a gate electrode containing doped polysilicon and a gate dielectric.The gate electrodes, when appropriately biased, can control the current flow in the body area and allow the MOSFET cells to be switched on, thus enabling current to flow from top to bottom between the source and the drain.

[0010] Silicon carbide (SiC) devices can provide a higher breakdown voltage and withstand higher voltages compared to silicon (Si) devices. Therefore, SiC devices may be suitable instead of Si devices for high-power applications requiring high breakdown voltages. SiC devices also exhibit a lower on-resistance (RDSon) compared to Si devices, and a lower RDSon can result in reduced conduction losses, thus improving efficiency. SiC devices can also operate at higher temperatures and offer desirable switching characteristics (e.g., higher switching frequencies) compared to Si devices. However, manufacturing processes for Si devices cannot be used to produce SiC devices.For example, the hardness of SiC is greater than the hardness of Si, which is why processes typically used for Si devices may not be applicable to SiC devices.

[0011] Fig. Figure 1 illustrates a side view of an example of a section of a two-stage oxide-trough silicon carbide MOSFET in one embodiment. A side view of a section of a semiconductor device 100 or of the device 100 herein is shown in Fig. The device 100 can be formed using a substrate 103 comprising a gate region 102 (or a gate electrode, hereinafter referred to as "Gate 102"), a source terminal 104 (hereinafter referred to as "Source 104"), a drain terminal 106 (hereinafter referred to as "Drain 106"), a passivation oxide layer 108, a drift region 110, a junction field-effect transistor (JFET) region 112, a first doped region 114, a second doped region 116, a base 118, an oxide region 120, and a shielding region 130. The substrate 103 can be a semiconductor substrate doped with first-type impurities, such as N-type impurities, such that the substrate 103 is of a first conductivity type. In the descriptions herein, the first conductivity type may be either N-type or P-type, and a second conductivity type may have a conductivity opposite to the first conductivity type.For example, if the first conductivity type is N-type, the second conductivity type is P-type and vice versa.

[0012] The device 100 can be a SiC trench MOSFET. In one embodiment, the device 100 can be one SiC trench MOSFET among a plurality of SiC trench MOSFETs in an integrated circuit. The trench MOSFET can be formed by vertically etching a trench 101 (e.g., in the -y direction) into a SiC substrate (e.g., substrate 103) and doping the remaining SiC substrate with impurities of various types and / or concentrations. The walls of the trench 101 can be lined with a layer of gate oxide (e.g., oxide region 120, described below), and the lined trench 101 can be filled with a conductive material, such as polysilicon, thereby forming the gate 102. Source 104 may be a conductivity type 1 area and Drain 106 may be a conductivity type 1 area.The passivation oxide 108 can be a layer of oxide that is intentionally formed to act as a barrier to protect the device 100 from environmental factors such as moisture, chemicals and environmental pollutants that could impair the functionality of the device 100.

[0013] The drift region 110 can be located between the base 118 and the substrate 103 and can extend along the walls of the trench 101 where the gate 102 is located. The drift region 110 can be a region in which charge carriers (e.g., electrons or holes) can drift from the source 104 to the drain 106. When a voltage is applied to the gate 102, an electric field is generated to form an inversion layer in a channel region (hereinafter referred to as "channel") 109. In one embodiment, the channel 109 can be of the second conductivity type and have a dopant concentration of approximately 1 × 10 15 cm-3 and 1 × 10 13 cm -3 The configuration varies. In some embodiments, impurities of the first type can be used to form channel 109, thereby enabling N-channel depletion-mode MOSFET operations. The electric field can conduct the charge carriers to move towards drain 106, thus allowing current to flow from source 104 to drain 106. The strength and distribution of the electric field in the drift region 110 can influence various electrical properties, such as on-resistance (RDSon), breakdown voltage, or other characteristics of the device 100.

[0014] The device 100 can further include a JFET region 112 formed within the drift region 110, providing a direct transition between the gate 102 and the channel 109. In one embodiment, the JFET region 112 can be located between an upper surface of the drift region 110 adjacent to the trench 101 and lower surfaces of the channel 109, the base 118, and the second doped region 116. In some cases, the JFET region 112 can be formed with a higher donor doping of the first conductivity type, for example, between 1 × 10⁻⁶. 16 cm -3 and 1 × 10 18 cm -3 may vary.

[0015] The first doped region 114 can be a region doped with first-type impurities, such as N-type impurities. The second doped region 116 can be a region doped with second-type impurities, such as P-type impurities. The first doped region 114 can have first-type conductivity, and the second doped region 116 can have second-type conductivity. The first doped region 114 and the second doped region 116 can be in contact with the source 104. The first doped region 114 can be in contact with the passivation oxide 108. If the device 100 is an N-type device, the first doped region 114 can be referred to as a first doped region, and the second doped region 116 can be referred to as a second doped region. In some aspects, the first endowed area 114 can also be described as the highly endowed area.If the first conductivity type is N-type, then the first doped region 114 can be created, for example, by ion implantation or diffusion, whereby N-type dopants, such as phosphorus (P) or arsenic (As), are implanted into the region, which ultimately becomes the first doped region 114. If the first conductivity type is N-type, then the second doped region 116 can be created, for example, by ion implantation or diffusion, whereby P-type dopants, such as boron (B), aluminum (Al), or gallium (Ga), are implanted into the region, which ultimately becomes the second doped region 114. The depth and doping concentration of the first doped region 114 and the second doped region 116 can be controlled to define the RDSon and the breakdown voltage of the device 100. For example, a doping concentration of approximately 1 × 10⁻⁵ in the first doped region 114 can be used. 19 cm -3 up to approximately 1 × 10 21cm -3 while the doping concentration of the second doped area 116 was approximately 1 × 10 18 cm -3 up to approximately 1 × 10 21 cm -3 may be.

[0016] The base 118 can be doped with impurities of the second type (e.g., the same as the second doped region 116), such as P-type impurities. The impurity concentration of the impurities used to dope the base 118 can be lower than the impurity concentration of the second doped region 116. By having a lower impurity concentration than the second doped region 116, the base 118 can allow majority charge carriers injected from the emitter (e.g., the source 104) to traverse the base 118 and reach the collector (e.g., the drain 106). In one embodiment, the doping concentration of the base 118 can be between approximately 1 × 10⁻⁶ and 1 × 10⁻⁶. 16 cm-3 up to approximately 1 × 10 18 cm -3 vary. In some embodiments, the base 118 may be lightly doped with impurities of the first type to achieve an accumulation-mode MOSFET (ACCUFET); in such cases, the doping concentration of the base 118 may range from approximately 1 × 10 14 cm -3 up to approximately 1 × 10 16 cm -3 vary. In other embodiments, the base 118 can be doped with impurities of the first type to achieve a depletion-mode MOSFET; in such cases, the doping concentration of the base 118 can range from approximately 1 × 10 16 cm -3 up to approximately 1 × 10 18 cm -3 vary.

[0017] In one aspect, the oxide layer lining the trench 101, or the gate oxide, can be an insulating material that separates the gate 102 from the semiconductor channel (e.g., channel 109) and other conductive layers or regions of the device 100. The insulating material lining the trench 101 can be, for example, silicon dioxide (SiO2) or other high-k dielectrics. The oxide layer can also help control the current flow between the source 104 and the drain 106 by modulating the electric field in the drift region 110. A thinner layer of gate oxide can provide relatively more efficient control over the channel, and a thicker layer of gate oxide can prevent gate oxide breakdown. The threshold voltage of the device 100 can also be controlled by the thickness of the gate oxide.If the electric field in the drift region 110 is too high, the gate oxide can degrade over time, negatively impacting the overall lifetime and reliability of the device 100. Oxide degradation can lead to shifts in the threshold voltage. In trench MOSFETs, the trench tends to have a relatively deep profile (e.g., along the y-axis) compared to its width (e.g., the x-axis). Thus, the electric field lines tend to concentrate at the bottom of the trench, causing the electric field below the trench (e.g., in the -y-direction) to be higher than in other areas, such as near the trench walls.

[0018] In some conventional devices, to attenuate the high electric field at the bottom of the trench, a P-shield, which is a P-type implant, can be positioned beneath the trench. However, adding the P-shield can negatively affect the ideal propagation resistance. Propagation resistance is the resistance that current encounters as it spreads from the gate to other areas of the device. Increasing the contact area between the gate and other areas of the device can reduce the propagation resistance, resulting in a lower RDSon and improved device performance. Adding the P-shield can reduce the contact area between the gate and other areas of the device, thereby increasing the propagation resistance.

[0019] In some conventional devices, the bottom section of the gate oxide lining the trench can be made thicker to reduce the electric field at the bottom of the trench. However, thermally growing a thick oxide in SiC can be challenging. For example, silicon (Si) and carbon (C) have strong covalent bonds that are difficult to break, making it difficult for oxygen to react with SiC and form a stable oxide layer, and requiring more energy to break the bonds for oxidation to occur. Furthermore, SiC has thermal stability that allows it to withstand high temperatures without decomposing, making it less reactive to oxygen at high temperatures and requiring more aggressive conditions to form the oxide layer. This also makes it difficult to achieve a thicker and smoother oxide layer.

[0020] Furthermore, conventional techniques for reducing the electric field at the bottom of the trench do not mitigate the high electric field at the trench corner and the lower part of the trench side walls. Some conventional techniques involve extending the P-shield laterally beneath the trench (e.g., along the x-axis) to reduce the electric field at the trench corner, but if the P-shield is wider and extends beyond the gate oxide, the propagation resistance increases. To be described in more detail below, the device 100 can have a gate oxide, designated as oxide region 120, having a bottom section and a lower side section that are thicker than an upper side section, together with a P-shield, designated as shield region 130, that does not extend beyond the gate oxide in the lateral direction (e.g.,(does not extend beyond the trench sidewall). The oxide region 120 can be produced using a multi-stage (e.g., two-stage) process that independently controls the thicknesses of the bottom section, the lower side section, and the upper side section of the oxide region 120. Furthermore, due to the different thicknesses, particularly the thicker lower side section of the oxide region 120, the shielding region 130 can be produced such that it has a width that does not extend beyond the gate oxide.

[0021] Fig. Figure 2 illustrates an example of a two-stage oxide-trough silicon carbide MOSFET in one embodiment. Descriptions of Fig. 2 can refer to components that are in Fig. 1 are shown. Fig. Figure 2 shows a cross-sectional view of an entire unit or cell of the device 100 implementing a SiC trench MOSFET. As in Fig. As shown in Figure 2, trench 101 is etched and formed between two first doped areas 114a, 114b (e.g., the first doped area), two second doped areas 116a, 116b (e.g., the second doped area), and two base areas 118a, 118b. Trench 101 can be etched in its entirety, as shown in Figure 2. Fig. Figure 2 shows a U-shape, and the shielding region 130 can extend over the bottom section of trench 101 without extending beyond the side walls of trench 101. The oxide region 120 has a thick bottom section, thick underside sections on the lower sections of the side of the oxide region 120, and thin topside sections on the upper sections of the side of the oxide region 120.

[0022] Fig. Figure 3 illustrates an example of an oxide region 120 in a two-stage oxide-trough silicon carbide MOSFET in one embodiment. Description of Fig. 3 can refer to components that are in Fig. 1 and Fig. 2 are shown. As in Fig. As shown in Figure 3, the oxide region 120 can contain a top section 304, a bottom section 306, and a bottom section 308. The thickness of the top section 304 is denoted as V. For example, the thickness V can vary from approximately 1 nm to approximately 20 nm. The thickness of the bottom section 306 is denoted as U. For example, the thickness U can vary from approximately 1 nm to approximately 500 nm. The thickness of the bottom section 308 is denoted as T. For example, the thickness T can vary from approximately 1 nm to approximately 500 nm. The thicknesses U and T can be greater than the thickness V. The thicknesses U and T can be the same or different.

[0023] The bottom section 308 can be in contact with the shielding region 130. The bottom section 308 and the shielding region 130 can contribute to reducing the electric field in the drift region 110 near the bottom of the trench 101, such as below the trench 101. The top section 304 can be in contact with the first doped region 114 and / or the base 118 and / or the JFET region 112. The bottom section 306 can be in contact with the JFET region 112 and the drift region 110. The bottom section 305 can contribute to reducing the electric field in the drift region 110 near sections of the side walls of the trench 101 and a corner 302 of the trench 101. The use of the bottom section 306 to reduce the electric field in the drift area 110 near corner 302 can enable the bottom section 308 to have a width W that is less than or equal to the width of the trench 101.In other words, the ground section 308 does not need to extend beyond a side wall of the trench 101 to reduce the electric field near corner 302. It should be noted that the width W of the ground section 308 can be dimensioned such that it does not extend beyond the side walls of the trench 101 and does not overlap with corner 302.

[0024] Fig. 4A to Fig. Figure 8C illustrates a series of steps in a fabrication process for a two-stage oxide-pitch silicon carbide MOSFET in one embodiment. Descriptions of Fig. 4A to Fig. 8C can refer to components that are in Fig. Figures 1 to 3 are shown. Fig. 4A The shielding region 130 can be implanted into a stack comprising the first doped region 114, the second doped region 116, the base 118, and the drift region 110. The implantation of the shielding region 130 can involve various techniques, such as the use of a photomask or an implantation mask, to selectively block or allow the implantation of second-conductivity dopants (e.g., aluminum) at the location of the shielding region 130 in the drift region 110. For example, an ion implanter can be used to introduce ions of dopant material into the SiC lattice to create the second-conductivity shielding region 130. Curing can be performed to activate the dopants, repair damage to the substrate caused by the ion implantation, and ensure that the dopants are properly incorporated into the lattice.In one embodiment, the shielding area 130 can have a dopant concentration of approximately 1 × 10. 15 cm -3 and 5 × 10 17 cm -3 varies. The (vertical) depth of the trench 101 into the drift area 110 (e.g. in the -y-direction) can be approximately 0.5 µm to approximately 10 µm and preferably between approximately 0.5 µm and approximately 2 µm.

[0025] In Fig. 4B After implantation of the shielding area 130, an oxide layer (hereinafter referred to as "oxide") 402 with a thickness t1 can be formed to line the walls of the trench 101. The oxide 402 can be formed by thermal oxidation of an oxide material. In some embodiments, however, the oxide 402 can be formed by conformal deposition of the oxide material. The oxide 402 can, for example, be a high-quality oxide that exhibits relatively superior properties compared to other oxides with respect to purity, stability, or specific functional properties. The oxide 402 can be formed from oxides such as silicon dioxide (SiO2). The duration of the oxidation process to form the oxide 402 can be controlled to define the thickness t1. For example, the oxidation process can be controlled to achieve an oxide 402 with a thickness t1 that varies between approximately 1 nm and approximately 500 nm.In some embodiments, a chemical-mechanical planarization process (CMP process) can be carried out to remove excess oxide material (e.g., oxide 402) from the upper surfaces of the device 100 and to . Fig. 5A to create the smooth upper surface shown.

[0026] In Fig. 5A After lining the trench 101 with the oxide 402, a conductive material 502, such as polysilicon, can be deposited in the trench 101 lined with the oxide 402. The conductive material 502 substantially fills a bottom section of the trench 101. In one embodiment, the thickness h1 of the conductive material 502 deposited in the trench 101 can be approximately 0 µm to approximately 1 µm. However, the thickness h1 of the conductive material 502 can vary based on the depth of the trench, ranging from 0% to 50% of the trench depth. The thickness h1 of the conductive material 502 can define a location of an uppermost section of the underlying section 306 of the oxide region 120 described below.

[0027] In Fig. In 5B, a nitride layer 512 can be deposited in the trench 101 along upper sections of the oxide 402 that are not covered by the conductive material 502. As shown in the figures, a lower surface of the deposited nitride layer 512 can be in direct contact with an upper surface of the conductive material 502. The formation of the nitride layer 512 can involve the deposition of a nitride material (e.g., silicon nitride) using various deposition methods. In an exemplary embodiment, the thickness of the nitride layer 512 can vary from approximately 10 nm to approximately 500 nm. The nitride layer 512 can act as a hard mask layer during the etching of the conductive material 502.

[0028] In Fig. In 6A, the nitride layer 512 is used as a hard mask to etch the conductive material 502. The conductive material 502 can be etched using various wet and dry etching techniques that selectively remove the conductive material 502 without removing the oxide 402 or the nitride layer 512. After the etching process, a first (horizontal) section a of the conductive material 502 remains on the bottom section of the trench 101, which is lined with the conductive material 502, and a second (vertical) section b of the conductive material 502 remains on opposite side walls of the trench 101, which is also lined with the oxide 402. In one embodiment, the thickness of the nitride layer 512 can determine the thickness of the remaining sections of the conductive material 502 within the trench 101.

[0029] In Fig. In 6B, after the etching process of the conductive material 502, the device 100 is subjected to a first thermal oxidation process in which the polysilicon in the conductive material 502 is oxidized to form, together with the oxide 402, an oxide layer (hereinafter referred to as "oxide") 602 of varying thicknesses, which covers the bottom section and the side walls of the trench 101. The thickness t2 of the oxide 602 formed on the bottom section of the trench 101 can vary between approximately 0 nm and 500 nm. The oxide 602 can, for example, be a high-quality oxide that exhibits relatively superior properties compared to other oxides with regard to purity, stability, or specific functional properties. The oxide 602 can be formed from oxides such as SiO2.

[0030] In Fig. 7A The nitride layer 512 can be removed from the device 100 using any suitable technique, including, for example, reactive ion etching (RIE). A cleaning process can be carried out to clean the upper sidewalls of the trench 101 after the removal of the nitride layer 512. A remaining section 702 of the oxide 602 remains within the trench 101 after the cleaning process. Fig. 7B A second thermal oxidation process can be carried out on the device 100 to form an oxide region 120. During the second thermal oxidation process, an upper side section 304 can be formed along exposed upper side walls of the trench 101 (i.e., side walls of the trench 101 not covered by the remaining section 702 of the oxide 602). Accordingly, the oxide region 120 can be formed by the combination of the remaining section 702 of the oxide 602 and the newly formed upper side section 304 of oxide material, which extends along the upper side walls of the trench 101 to an upper surface of the device 100. The duration of the second thermal oxidation process can be controlled such that the thickness V of the upper side section 304 can vary between approximately 1 nm and approximately 20 nm.

[0031] Since the duration of the oxidation process for defining the thickness t1 of oxide 402 and the thickness t2 of oxide layer 602 can be controlled independently or in separate steps, the thickness T of the bottom section 308 and the thickness U of the lower side section 306 can be individually defined to control the degree of reduction of the electric field at the bottom, side, and corner 302 of trench 101. As mentioned above, oxidation on a SiC substrate to form a relatively thick oxide can be challenging. To address this challenge, the process described herein can form oxide 402 and oxide 602 in different steps, with oxides 402 and 602 being combinable to form a thicker oxide, such as the thicker sections of oxide region 120. In one embodiment, the thickness T of the bottom section 308 can be substantially similar to the thickness t2.In another embodiment, the thickness T of the bottom section 308 can vary between approximately 1 nm and 500 nm, depending on the duration of the second oxidation process. The thickness U of the lower side section 306 can also vary between approximately 1 nm and 500 nm, depending on the duration of the second oxidation process.

[0032] In Fig. 8A A conductive material 810, such as polysilicon, can be deposited in the trench 101 on the top surface of the oxide region 120. Although not shown in the figures, the conductive material 810 can also be deposited on the top surface of the first doped region 114 and the second doped region 116. In such cases, the conductive material 810 can be etched such that portions of the conductive material 810 on the top surface of the first doped region 114 and the second doped region 116 can be removed, and a top surface of the remaining conductive material 810 can be aligned with the top surface of the first doped region 114 and the second doped region 116, as shown in Fig. 8A shown.

[0033] In Fig. 8B An additional layer of oxide 802 can be formed on the top surface of the conductive material 810 by oxidation. The oxide 802 can, for example, be a high-quality oxide that exhibits relatively superior properties compared to other oxides in terms of purity, stability, or specific functional properties. The oxide 802 layer can be formed from oxides such as SiO2. Fig. 8C allows the additional layer of oxide 802 to be etched to create the effect described in the original text. Fig. The passivation oxide 108 shown is formed. After etching, the source 104 can be added.

[0034] Fig. Figure 9A illustrates another example of a two-stage oxide-pit silicon carbide MOSFET in one embodiment. Descriptions of Fig. 9A can refer to components that are in Fig. 1 to Fig. 8B are shown. In one embodiment, it shows Fig. 9A a complete unit or cell of a device 900 implementing a SiC trench MOSFET with a split-gate arrangement together with the oxide region 120 and the shielding region 130 described herein. The device 900 can be a split-gate trench MOSFET comprising at least two gate electrodes 902, 904. The oxide region 120 can be arranged between the gates 902, 904 and the trench 101. In a further embodiment, the Fig. 9A Device 900 implements a SiC trench MOSFET with a shielding gate arrangement together with the oxide region 120 and the shielding region 130 described herein, such that the gate electrode 904 can serve as a shield and can have a different dopant concentration than the gate electrode 902. Fig. 9B to Fig. Figure 9E illustrates a series of steps in a manufacturing process of the device 900.

[0035] Fig. 9B shows a step that is based on Fig. 8A follows. Fig. 9B, the conductive material 710 can be etched such that portions of the conductive material 710 on the top of the first doped area 114 and the second doped area 116, and some portions located in the trench 101, can be removed. The remainder of the conductive material 710 forms the gate 904. Fig. 9C, an oxide layer (hereinafter referred to as "oxide") 910 can be formed on the top surface of the gate 904 by oxidation. The oxide 910 can be, for example, SiO2. In Fig. In 9D, a conductive material forming gate 902 can be deposited on oxide 910. Fig. 9E can add the additional layer of oxide 802 to the top of the entire surface. Fig. The stack shown in 9D is added to the passivation oxide 108 and the one in Fig. 9A shows Source 104 to form.

[0036] Fig. Figure 10 is a flowchart illustrating a process for fabricating a two-stage oxide-trough silicon carbide MOSFET in one embodiment. The process is shown in Figure 1000. Fig. Procedure 10 can be performed to fabricate semiconductor devices, such as Device 100 and / or Device 900 described here. An exemplary process may involve one or more operations, actions, or functions, as illustrated by one or more of Blocks 1002, 1004, 1006, 1008, 1010, and / or 1012. Although illustrated as discrete blocks, various blocks can be subdivided into additional blocks, combined into fewer blocks, eliminated, performed in a different order, or performed in parallel, depending on the desired implementation.

[0037] Process 1000 can begin at block 1002. At block 1002, a first oxide layer of a certain thickness can be formed to line a trench formed in a silicon carbide (SiC) substrate. In one embodiment, a shielding region can be formed beneath the trench before the first oxide layer is formed. The width of the shielding region can be less than or equal to the width of the trench. The shielding region does not need to overlap with a side wall of the trench.

[0038] Process 1000 can progress from block 1002 to block 1004. At block 1004, a conductive material, such as polysilicon, can form on a section of the trench floor lined with the first oxide layer.

[0039] Process 1000 can proceed from block 1004 to block 1006. At block 1006, a nitride layer can form over the conductive material and along trench sidewalls not covered by the conductive material. This nitride layer can be used as a hard mask to etch the conductive material. Using the nitride layer as a hard mask for etching the conductive material results in a remaining section of the conductive material having a thickness similar to that of the nitride layer.

[0040] Process 1000 can proceed from block 1006 to block 1008. At block 1008, an initial oxidation process can be carried out to form a bottom section and a lower side section of an oxide zone within the trench.

[0041] Process 1000 can proceed from block 1008 to block 1010. At block 1010, the nitride layer can be removed, and exposed trench sidewalls can be cleaned before a second oxidation process is carried out to form an upper side section of the oxide region. In one embodiment, the oxide region comprises the bottom section, the underside section, and the topside section. The thickness of the bottom section is greater than the thickness of the topside section, and the thickness of the underside section is greater than the thickness of the topside section. The oxide region lines different sections of the trench with varying oxide thicknesses.The thickness of the bottom section of the oxide region is a combination of the first thickness and a thickness of a horizontal section of the remaining section of the conductive material before it is oxidized, the thickness of the bottom section is the combination of the first thickness and a thickness of a vertical section of the remaining section of the conductive material before it is oxidized, and the thickness of the top section is determined by a duration of the second oxidation process.

[0042] Process 1000 can transition from block 1010 to block 1012. At block 1012, a gate electrode can be formed in the trench lined with the oxide region. In one embodiment, a second oxide layer can be formed on the gate electrode. Another gate electrode can be formed on the second oxide layer. A passivation oxide layer can be formed on this second gate electrode. Examples Example 1. Method for manufacturing a semiconductor device, comprising: Forming an initial oxide layer of initial thickness to line a trench formed in a silicon carbide (SiC) substrate; Formation of a conductive material on a section of the trench floor lined with the first oxide layer; Formation of a nitride layer over the conductive material and along the side walls of the trench; Using the nitride layer as a hard mask, etching the conductive material; Performing an initial oxidation process on a remaining section of the conductive material to form a bottom section and a lower side section of an oxide region within the trench; Removal of the nitride layer and cleaning of exposed side walls of the trench; Performing a second oxidation process on the exposed side walls of the trench to form an upper side section of the oxide region; and Forming a gate electrode in the trench lined with the oxide region. Example 2. Procedure according to Example 1, further comprising: Forming a shielding area under the trench before the first oxide layer forms. Example 3. Method according to Example 2, wherein the width of the shielding area is less than or equal to the width of the trench. Example 4. Procedure according to Example 2, wherein the shielding area does not overlap with a side wall of the trench. Example 5. Method according to Example 1, wherein using the nitride layer as a hard mask to etch the conductive material results in the remaining section of the conductive material having a thickness similar to that of the nitride layer. Example 6. Procedure according to Example 1, wherein: the oxide region comprises the bottom section, the underside section and the topside section; the thickness of the bottom section is greater than the thickness of the top section; and The thickness of the bottom section is greater than the thickness of the top section. Example 7. Procedure according to Example 6, wherein: The thickness of the bottom section is a combination of the first thickness and a thickness of a horizontal section of the remaining section of the conductive material; The thickness of the bottom section is the combination of the first thickness and a thickness of a vertical section of the remaining section of the conductive material; and The thickness of the top surface section is determined by the duration of the second oxidation process. Example 8. Procedure according to Example 1, further comprising: Formation of a second oxide layer on the gate electrode; Formation of another gate electrode on the second oxide layer; and Formation of a passivation oxide layer on the other gate electrode. Example 9. Method for manufacturing a semiconductor device, comprising: Forming a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate is formed by silicon carbide (SiC); Formation of a drift region of the first conductivity type in the semiconductor substrate; Formation of a channel of a second conductivity type opposite to the first conductivity type of the drift area; Forming a source region of the first conductivity type, where the source region is above the channel; Forming a trench adjacent to the canal, with the trench reaching the drift area; Forming an oxide region within the trench, wherein the oxide region lines the side walls of the trench, wherein: the oxide region comprises a bottom section, a bottom section and a top section; the thickness of the bottom section is greater than the thickness of the top section; and the thickness of the bottom section is greater than the thickness of the top section; Formation of a gate electrode within the trench lined with the oxide region; and Forming a shielding area of ​​the second conductivity type in contact with the bottom section of the trench, wherein a width of the shielding area is less than or equal to a width of the trench. Example 10. Method according to Example 9, wherein the underside section of the oxide region is in contact with the topside section of the oxide region. Example 11. Procedure according to Example 9, wherein the shielding area does not overlap with a side wall of the trench. Example 12. Method according to Example 9, wherein the drift region is in contact with at least a part of the top surface section of the oxide region and at least a part of the bottom surface section of the oxide region. Example 13. Method according to Example 9, wherein the thickness of the bottom section of the oxide region is in a range of 1 nm to 500 nm. Example 14. Method according to Example 9, wherein the thickness of the underside section of the oxide region is in a range of 1 nm to 500 nm. Example 15. Method according to Example 9, wherein the contamination concentration of the shielding area is lower than the contamination concentration of the channel. Example 16. Method according to Example 9, wherein a contamination concentration of the shielded area is in a range of 1 × 10 15 cm -3 up to 5 × 1017 cm -3 lies. Example 17. Method for manufacturing a semiconductor device, comprising: Forming a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate is formed by silicon carbide (SiC); Formation of a drift region of the first conductivity type in the semiconductor substrate; Formation of a channel of a second conductivity type opposite to the first conductivity type of the drift area; Formation of a source region of the first conductivity type above the channel; Forming a trench adjacent to the canal, with the trench reaching the drift area; Forming an oxide region within the trench, wherein the oxide region lines the side walls of the trench, wherein: the oxide region comprises a bottom section, a bottom section and a top section; the thickness of the bottom section is greater than the thickness of the top section; and the thickness of the bottom section is greater than the thickness of the top section; Form at least one gate electrode within the trench lined with the oxide region; and Forming a shielding area of ​​the second conductivity in contact with the bottom section of the trench, wherein a width of the shielding area is less than or equal to a width of the trench. Example 18. Method according to Example 16, wherein the underside section of the oxide region is in contact with the topside section of the oxide region. Example 19. Procedure according to Example 16, wherein the shielding area does not overlap with a side wall of the trench. Example 20. Method according to Example 16, wherein the drift region is in contact with at least a part of the top side of the oxide region and at least a part of the bottom side of the oxide region.

[0043] The terminology used herein serves only to describe certain embodiments and is not intended to limit the invention. As used herein, the singular forms "a," "an," and "the" are to include the plural forms unless the context clearly indicates otherwise. It is further understood that the terms "comprises" and / or "comprehensive," when used in this description, indicate the presence of specified features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0044] The corresponding structures, materials, actions, and equivalents of all means or step-plus functional elements, if any, in the following claims are to include any structure, material, or action for performing the function in combination with other claimed elements, as specifically claimed. The disclosed embodiments of the present invention have been set forth for the purpose of illustration and description, but are not intended to be exhaustive or limited to the invention in the disclosed forms. To the person skilled in the art, many modifications and variations are apparent without departing from the scope and spirit of the invention.The embodiments were selected and described to best explain the principles of the invention and its practical application, and to enable other persons skilled in the art to understand the invention in various embodiments with different modifications suitable for the particular use under consideration.

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