REAR CONTACTS FOR IMPROVED SOURCE / DRAIN CONNECTION

Abstract

Conductive backside contacts are shown beneath source or drain regions, extending into the source or drain region. A semiconductor device includes a gate structure around or otherwise on a semiconductor region extending from a source or drain region. The substrate beneath the semiconductor device can be removed from the backside to expose a sacrificial plug previously formed beneath the source or drain region. The sacrificial plug is removed to form a backside cavity beneath the source or drain region. A dielectric lining is formed within the backside cavity, followed by a directional etching process to create a depression through the lower surface of the source or drain region. The backside cavity and the corresponding depression are filled with a conductive material to form the backside contact.The back contact can contact a front contact within the source or drain area.

Description

BACKGROUND As the size of integrated circuits continues to scale down, a number of challenges arise. For example, reducing the size of memory and logic cells within the interconnect structure becomes increasingly difficult, as does reducing device spacing at the device layer. Due to the small size of transistor elements, such as the transistor gate, source, or drain, it can be difficult to provide effective contacts while maintaining desired operating speeds and power requirements. Accordingly, a number of non-trivial challenges remain in the fabrication of such high-density semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is an isometric view of an integrated circuit structure including back-side contacts extending into the source or drain regions, according to one embodiment of the present disclosure. Figs. 1B and 1C are different cross-sectional views of the integrated circuit from Fig. 1A, showing the back-side contacts extending into the source or drain regions according to one embodiment of the present disclosure. Figs. 2A and 2B are cross-sectional views illustrating a stage in an example process for forming an integrated circuit configured with back-side contacts extending into the source or drain regions, according to one embodiment of the present disclosure. Figs. 3A and 2BFigures 3B are cross-sectional views illustrating a further stage of the example process for forming an integrated circuit configured with back-side contacts extending into the source or drain regions, according to one embodiment of the present disclosure. Figures 4A and 4B are cross-sectional views illustrating a further stage of the example process for forming an integrated circuit configured with back-side contacts extending into the source or drain regions, according to one embodiment of the present disclosure. Figures 5A and 5B are cross-sectional views illustrating a further stage of the example process for forming an integrated circuit configured with back-side contacts extending into the source or drain regions, according to one embodiment of the present disclosure. Figures 6A and 6B are cross-sectional views illustrating a further stage of the example process for forming an integrated circuit configured with back-side contacts extending into the source or drain regions, according to one embodiment of the present disclosure.Figures 6B and 6B are cross-sectional views illustrating a further stage of the example process for forming an integrated circuit configured with back-side contacts extending into the source or drain regions, according to one embodiment of the present disclosure. Figures 7A and 7B are cross-sectional views illustrating a further stage of the example process for forming an integrated circuit configured with back-side contacts extending into the source or drain regions, according to one embodiment of the present disclosure. Figures 8A and 8B are cross-sectional views illustrating a further stage of the example process for forming an integrated circuit configured with back-side contacts extending into the source or drain regions, according to one embodiment of the present disclosure. Figures 9A and 9B are cross-sectional views illustrating a further stage of the example process for forming an integrated circuit configured with back-side contacts extending into the source or drain regions, according to one embodiment of the present disclosure.Figures 9B are cross-sectional views illustrating a further stage of the example process for forming an integrated circuit configured with back-side contacts extending into the source or drain regions, according to one embodiment of the present disclosure. Figures 10A and 10B are cross-sectional views illustrating a further stage of the example process for forming an integrated circuit configured with back-side contacts extending into the source or drain regions, according to one embodiment of the present disclosure. Figures 11A and 11B are cross-sectional views illustrating a further stage of the example process for forming an integrated circuit configured with back-side contacts extending into the source or drain regions, according to one embodiment of the present disclosure. Figures 12A and 13B are cross-sectional views illustrating a further stage of the example process for forming an integrated circuit configured with back-side contacts extending into the source or drain regions, according to one embodiment of the present disclosure.Figures 12B and 13A are cross-sectional views illustrating a further stage of the example process for forming an integrated circuit configured with back-side contacts extending into the source or drain regions, according to one embodiment of the present disclosure. Figures 13A and 13B are cross-sectional views illustrating a further stage of the example process for forming an integrated circuit configured with back-side contacts extending into the source or drain regions, according to one embodiment of the present disclosure. Figures 14A and 14B are cross-sectional views illustrating a further stage of the example process for forming an integrated circuit configured with back-side contacts extending into the source or drain regions, according to one embodiment of the present disclosure. Figures 15A and 16B are cross-sectional views illustrating a further stage of the example process for forming an integrated circuit configured with back-side contacts extending into the source or drain regions, according to one embodiment of the present disclosure.Figures 15B are cross-sectional views illustrating a further stage of the example process for forming an integrated circuit configured with back-side contacts extending into the source or drain regions, according to one embodiment of the present disclosure. Figures 16A and 16B are cross-sectional views illustrating a further stage of the example process for forming an integrated circuit configured with back-side contacts extending into the source or drain regions, according to one embodiment of the present disclosure. Figures 17A and 17B are cross-sectional views illustrating an example of a back-side interconnect connected to a front-side interconnect within a source or drain region, according to one embodiment of the present disclosure.Figure 18 illustrates a cross-sectional view of a chip package containing one or more semiconductor dies, according to some embodiments of the present disclosure. Figure 19 is a flowchart of a manufacturing process for a semiconductor device with backside contacts extending into the source or drain regions, according to one embodiment of the present disclosure. Figure 20 illustrates a computing system comprising one or more integrated circuits, as described herein in various ways, according to one embodiment of the present disclosure. Although the detailed description below is given with reference to illustrated embodiments, many alternatives, modifications, and variations thereof become apparent in light of the present disclosure. Furthermore, it is understood that the figures are not necessarily drawn to scale or intended to limit the present disclosure to the specific configurations shown. For example, although some figures generally depict perfectly straight lines, right angles, and smooth surfaces, an actual implementation of an integrated circuit structure may not have perfectly straight lines and right angles (e.g., some features may have tapered side walls and / or rounded corners), and some features may have a surface topology or otherwise be uneven due to real limitations of the machining equipment and techniques used. DETAILED DESCRIPTION Techniques are presented here for fabricating an integrated circuit with conductive backside contacts located beneath source or drain regions, extending into these regions. These techniques can be used in a wide range of integrated circuit applications and are particularly useful for logic and memory cells, such as those employing FinFETs, gate-all-around transistors (e.g., ribbonFETs and nanowire FETs), or forksheet transistors. In one example, a semiconductor device incorporates a gate structure around or otherwise on a semiconductor region. The semiconductor region might be, for instance, a fin of semiconductor material extending from a source or drain region, or one or more nanowires, nanoribbons, or nanosheets of semiconductor material extending from the source or drain region.The gate structure comprises a gate dielectric (e.g., a high-k dielectric gate material) and a gate electrode (e.g., a conductive material such as exit work material and / or gate filler metal). The substrate beneath the semiconductor device can be removed from the backside to expose a sacrificial plug previously formed beneath the source or drain region. The sacrificial plug is removed to form a backside cavity beneath the source or drain region. In one example, a dielectric lining is formed within the backside cavity, followed by a directional etching process to create a deep depression through the lower surface of the source or drain region. The backside cavity and the corresponding deep depression are then filled with a conductive material to form the deep backside contact.In some such examples, a deep front-side contact is already present through an upper surface of the source or drain region, so that the deep back-side contact is formed on a portion of the deep front-side contact within the source or drain region. The resulting conductive structure creates a through-hole that extends across the entire thickness of the source or drain region. Numerous variations and embodiments are evident from the present disclosure. General overview As mentioned above, a number of non-trivial challenges remain regarding the fabrication of integrated circuits. Specifically, backside interconnects have become increasingly popular for routing power and ground rails beneath the source or drain regions of various transistors. However, creating effective connections between these backside interconnects and the source or drain regions is challenging. Manufacturing constraints often result in undesirably high contact resistance between the backside contacts and the source or drain regions, leading to reduced transistor performance. Accordingly, and in one embodiment of the present disclosure, techniques are provided herefor forming conductive backside contacts that extend into the source or drain regions to provide a larger contact area. By contacting a larger portion of the source or drain region, the contact resistance can be drastically reduced. In some embodiments, a sacrificial plug is formed beneath a given source or drain region and is exposed from the backside of the structure after substrate removal. The sacrificial plug can then be selectively etched away to expose a lower surface of the source or drain region within a backside cavity. A dielectric lining can be conformally deposited within the cavity to cover the sidewalls and the exposed surface of the source or drain region. A directional etching process (e.g.,Reactive ion etching can be used to penetrate a portion of the dielectric lining on the source or drain region and to continue etching a depression through the lower surface of the source or drain region. One or more conductive materials can then be formed within the backside cavity and depression to create the backside contact extending into the source or drain region. According to some embodiments, a similar process can be performed on the front side of the source or drain region (e.g., prior to removing the substrate from the backside) to create a frontside contact extending below the upper surface of the source or drain region.In such examples, the backside contact can meet the previously formed frontside contact within the source or drain region to form a connected or combined contact that extends through the entire height of the source or drain region. The connected or combined contact not only establishes electrical contact with the given source or drain region but can also act as a conductive path to feed power or signals between topside and backside interconnects of the die. According to one embodiment, an integrated circuit comprises a semiconductor device with a semiconductor region extending in a first direction from a source or drain region, and a gate structure extending in a second direction above the semiconductor region, a dielectric layer below the gate structure, a conductive back contact extending through the dielectric layer and through at least a portion of the total height of the source or drain region, and a dielectric lining on sidewall surfaces of the conductive back contact. The dielectric lining is located between the conductive back contact and the dielectric layer, and at least a portion of the dielectric lining contacts a lower surface of the source or drain region. According to another embodiment, a method for forming an integrated circuit includes: forming a fin comprising semiconductor material, the fin extending over a substrate; forming a dielectric layer adjacent to a subfin of the fin; forming sacrificial gate and spacer structures over the fin; removing portions of the fin not covered by the sacrificial gates and spacer structures; removing a subfin region of the fin to form a subfin cavity; forming a sacrificial plug within the subfin cavity; forming a source or drain region at exposed ends of the semiconductor material and over the sacrificial plug; removing a portion of the substrate from a backside of the integrated circuit to expose a lower surface of the subfin and a lower surface of the sacrificial material; and removing the sacrificial plug from the backside to form a backside cavity.Forming a dielectric lining within the backside cavity; removing part of the dielectric lining on a lower surface of the source or drain region; etching a depression into the exposed lower surface of the source or drain region; and forming a conductive contact both within the backside cavity and within the depression. According to a further embodiment, an integrated circuit comprises a semiconductor device with a semiconductor region extending in a first direction from a source or drain region, a gate structure extending in a second direction above the semiconductor region, a dielectric layer below the gate structure, and a conductive contact extending through the dielectric layer and through the entire height of the source or drain region. The conductive contact has a first section with a tapered width from a lower surface of the source or drain region to a top surface of the first section, and a second section with a tapered width from a top surface of the source or drain region to the bottom surface of the second section.The conductive contact has a smallest width at an interface between the first section and the second section of the conductive contact. These techniques can be used with any type of non-planar transistor, including FinFETs (sometimes called dual-gate or tri-gate transistors) or nanowire and nanoband transistors (sometimes called gate all-around transistors), or stacked versions of any of these architectures, to name just a few. The source and drain regions can be, for example, doped sections from a particular fin or substrate, or epitaxial regions deposited during an etch-and-exchange process to form the source / drain. The type of dopant used in the source and drain regions depends on the polarity of the corresponding transistor.The gate structure can be implemented using a gate-first process, a gate-last process (sometimes referred to as a replacement metal gate or RMG process), or any other gate formation process. Any number of semiconductor materials, such as group IV materials (e.g., silicon, germanium, silicon germanium) or group III-V materials (e.g., gallium arsenide, indium gallium arsenide), can be used to form the transistors. The use of the techniques and structures provided herein may be detectable using tools such as electron microscopy, including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (SEM); composition mapping, X-ray crystallography or diffraction (XRD); energy-dispersive X-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high-resolution physical or chemical analysis, to name a few suitable examples. For instance, in some exemplary embodiments, such tools may indicate the presence of backside contacts beneath source or drain regions.One or more of the backside contacts would extend upwards into the corresponding source or drain regions. In some examples, one or more of the backside contacts would be considered to be connected to or otherwise in contact with one or more corresponding frontside contacts in the source or drain regions. It should be clear that the meanings of "above" and "over" in this disclosure should be interpreted as broadly as possible, so that "above" and "over" do not only mean "directly on" something, but also include the meaning of "over" something with an intervening feature or layer. Furthermore, spatial expressions such as "below," "under," "lower," "over," "upper," "top," "bottom," and the like may be used here to simplify the description and to describe a relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatial expressions are to be understood as encompassing various orientations of the device in use or operation in addition to the orientation shown in the figures.The device may be oriented differently (rotated by 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly. As used here, the term "layer" refers to a section of material that has a region of thickness. A monolayer is a layer consisting of a single layer of atoms of a given material. A layer may extend over the entirety of an underlying or overlying structure, or it may have a lesser extent than the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or inhomogeneous continuous structure, where the layer has a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between or on top of an upper and a lower face of the continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface.A layer can conform to a given surface (whether flat or curved) with a relatively uniform thickness across its entire thickness. Multiple layers formed from the same material (e.g., the same dielectric material) can be considered together as a single layer. Materials that are “different in composition” or “different in composition,” as used here, refer to two materials that have different chemical compositions. This difference in composition might consist, for example, of an element being present in one material but not the other (e.g., SiGe differs in composition from silicon), or of one material having all the same elements as another, but at least one of these elements being intentionally provided in a different concentration relative to the other material (e.g., SiGe with 70 atomic percent germanium differs in composition from SiGe with 25 atomic percent germanium). In addition to such a difference in chemical composition, the materials might also contain different dopants (e.g.,Gallium and magnesium) or the same dopants, but in different concentrations. In further embodiments, materials with different compositions can also refer to two materials that have different crystallographic orientations. For example, (110) silicon is different in composition from (100) silicon. Creating a stack with different orientations could be achieved, for example, by full-surface wafer transfer. If two materials are elementally different, then one of the materials has an element that is not present in the other material. architecture Fig. 1A is an isometric view of a portion of an integrated circuit incorporating various semiconductor devices 101 according to an embodiment of the present disclosure. Each of the semiconductor devices can be a non-planar metal-oxide-semiconductor (MOS) transistor, such as tri-gate (e.g., FinFET) or gate-all-around (GAA) transistors or forksheet transistors, although other transistor topologies and types could also benefit from the techniques provided herein. The examples herein illustrate semiconductor devices with a GAA structure (e.g., with nanoribbons or nanowires extending between the source and drain regions). It is noted that the structure in Fig. 1A is inverted, so that the back side of the structure is at the top and the front side of the structure is at the bottom. The semiconductor material used in each of the semiconductor devices can be formed from a semiconductor substrate. In some embodiments, the substrate is removed from the back side and replaced by any number of dielectric layers to form backside interconnects beneath various transistor elements. In the example illustrated in Fig. 1A, a dielectric base layer 102 can be formed beneath the semiconductor devices 101. In some examples, subfin regions of the semiconductor devices 101 are removed from the back side and replaced by dielectric material to form at least part of the dielectric base layer 102. One or more additional dielectric layers can be formed beneath the dielectric base layer 102 to form backside interconnects. One or more semiconductor regions of the devices can have fins that may be, for example, native to the substrate (formed from the substrate itself), such as silicon fins etched from a bulk silicon substrate. Alternatively, the fins may be formed from a material deposited onto the substrate. In one such exemplary case, a silicon germanium (SiGe) top layer can be deposited onto a silicon substrate and then patterned and etched to form a plurality of SiGe fins extending from that substrate. In other embodiments, the fins include alternating layers of a material (e.g.,Alternating layers of silicon and SiGe) enable the formation of nanowires and nanoribbons during a gate formation process, in which one type of alternating layer is selectively etched away to expose the other type of alternating layer within the channel region, allowing for a subsequent gate-all-around process. Again, the alternating layers can be deposited in an unstructured manner and then etched into fins or deposited into fin-shaped grooves. Each semiconductor device 101 comprises one or more semiconductor regions, such as one or more nanobands 104, extending between epitaxial source or drain regions 106 in a first direction along the X-axis. According to some embodiments, source or drain regions 106 can be either n-type or p-type regions. In some examples, n-type source or drain regions have silicon doped with phosphorus or arsenic, and p-type source or drain regions have silicon germanium doped with boron. Other examples may be configured differently. A gate structure 108, comprising a gate electrode and a gate dielectric, extends over one or more semiconductor regions of a given semiconductor device 101 in a second direction along the Y-axis to form the transistor gate. The gate electrode can represent any number of conductive layers, and the gate dielectric can represent any number of dielectric layers. The gate electrode can comprise any sufficiently conductive material, such as a metal, a metal alloy, or doped polysilicon. In some embodiments, the gate electrode has one or more exit work metal(s) surrounding the one or more semiconductor region(s). The gate electrode can also include a filler metal or other conductive material surrounding the exit work metal(s) to provide the entire gate electrode structure.The gate dielectric can comprise one or more arbitrary gate dielectric materials. In some embodiments, the gate dielectric includes a layer of native oxide material (e.g., silicon oxide) on the nanobands 104 or other semiconductor regions and a layer of a high-k dielectric material (e.g., hafnium oxide) on the native oxide. According to some embodiments, spacer structures 110 are present along the sidewalls of the gate structures 108. The spacer structures 110 can be any dielectric material, such as silicon nitride or silicon oxynitride, and provide separation between a given gate structure 108 and the adjacent source or drain region 106. The spacer structures 110 can extend along the sidewalls of the gate structure 108 in the second direction and over the entire height of the gate structure 108 along the Z-axis.In this example, the spacer structures 110 generally include both the upper spacers (sometimes referred to as gate spacers, which can be formed during dummy or initial gate formation) and lower spacers (sometimes referred to as inner gate spacers, which can be formed during source / drain processing). According to some embodiments, adjacent gate structures 108 can be separated from each other along the second direction (e.g., along the Y-axis) by a dielectric wall 112 (sometimes referred to as a gate cut). Any number of suitable dielectric materials can be used for the dielectric wall 112, such as silicon nitride or silicon oxynitride, or low-k versions thereof (e.g., porous silicon oxynitride). Any number of dielectric walls 112 can extend longitudinally along the X-axis and parallel to each other, and can extend along the Z-axis at least through the entire thickness of one or more gate structures 108 and up to (or through) a cap layer 114 on an upper surface of the gate structures 108, as shown in this example.According to some embodiments, the dielectric wall 112 extends further along the X-axis between several pairs of semiconductor devices and between the source or drain regions 106 of the devices. The dielectric cap layer 114 can extend longitudinally along the Y-axis along the upper surface of the gate structures 108. In some examples, the cap layer 114 can contain the same dielectric material as the dielectric wall 112. As further shown in the example of Fig. 1A, any number of conductive front-end contacts 116 are located on the upper surfaces of corresponding source or drain regions 106. Adjacent conductive front-end contacts 116 may be separated by the dielectric wall 112 along the second direction or may be connected to each other across or through the dielectric wall 112 (e.g., via a bridge conductor). The conductive front-end contacts 116 may contain any suitable conductive material, such as tungsten, ruthenium, cobalt, molybdenum, titanium, tantalum, or other metals or alloys thereof. The conductive front-end contacts 116 may be formed together so that they all contain the same conductive material. As further shown in the example of Fig. 1A, one or more conductive backside contacts 118, according to some embodiments, extend through a thickness of the dielectric base layer 102 and through at least a portion of the total thickness of the source or drain regions 106. The conductive backside contacts 118 may comprise any of the same materials specified above for the conductive frontside contacts 116. In some examples, the conductive backside contacts 118 and conductive frontside contacts 116 comprise the same conductive material. The conductive backside contacts 118 may be connected to backside power or ground rails or to a signal line interconnect structure.According to some embodiments, additional dielectric layers and conductive elements can be formed beneath the dielectric base layer 102 to create a backside interconnect structure (such as a power supply network and / or a signal line network). According to some embodiments, a dielectric lining 120 is present around portions of the backside contacts 118. The dielectric lining 120 can be formed within backside cavities prior to the formation of the backside contacts 118, such that the backside contacts 118 extend through a portion of the dielectric lining 120 before reaching the source or drain regions 106. The dielectric lining 120 can be any suitable dielectric material, for example, silicon nitride, silicon oxycarbonitride, or titanium oxide. The dielectric lining 120 can have a thickness of less than 5 nm or between 1 nm and 3 nm. Fig. 1B illustrates a cross-sectional view across the XZ plane from Fig. 1A, and Fig. 1C illustrates a cross-sectional view across the YZ plane from Fig. 1A according to some embodiments. The backside contacts 118 can extend through at least 30%, at least 40%, at least 50%, or at least 60% of the total height (e.g., along the Z direction) of the source or drain regions 106. In some examples, the backside contacts 118 extend through a portion of the source or drain regions 106 located above an XY plane along a bottom surface of the lowest set of nanoribbons 104 (e.g., the bottom surface of the semiconductor region extending between the source or drain regions). In some examples, the backside contacts 118 extend through a portion of source or drain regions 106 located above an XY plane along the lower surface of the second nanobands 104 from the bottom.It is noted that the dielectric lining 120 is located on the side walls of a lower part of the backside contacts 118 beneath the source or drain regions 106, and that part of the dielectric lining 120 is located directly on a lower surface of the source or drain regions 106. The representations of the backside contacts 118 shown in Fig. 1B and Fig. 1C are not to scale and are provided to give a general understanding of the exemplary geometry of the backside contacts 118. Manufacturing methodology Figures 2A to 16A and 2B to 16B contain cross-sectional views which together illustrate an example process for forming an integrated circuit configured with back-side contacts extending into the source or drain regions, according to an embodiment of the present disclosure. Figures 2A to 16A represent a similar cross-sectional view across the XZ plane in Figure 1A, while Figures 2B to 16B represent a cross-sectional view across the YZ plane in Figure 1A. Each set of figures sharing the same letter shows an example structure resulting from the process flow up to that point, such that the structure shown evolves as the process flow progresses, ending in the structure shown in Figures 16A and 16B, which is similar to the structure shown in Figures 1B and 1C.Such a structure can be part of a larger integrated circuit (such as a processor or a memory chip) that includes, for example, digital logic cells and / or memory cells and an analog mixed-signal circuit arrangement. Therefore, the illustrated integrated circuit structure can be part of a larger integrated circuit that includes other, not shown, integrated circuit arrangements. Exemplary materials and process parameters are given; however, it is understood that the present disclosure is not limited to any specific such materials or parameters. Figures 2A and 2B each illustrate a cross-sectional view through a substrate 201 with a series of material layers formed on top of the substrate, according to an embodiment of the present disclosure. Alternating material layers, including sacrificial layers 202 alternating with semiconductor layers 204, can be deposited on top of a substrate 201. The alternating layers are used to form GAA transistor structures. Any number of alternating sacrificial layers 202 and semiconductor layers 204 can be deposited on top of the substrate 201. Substrate 201 can, for example, be a bulk substrate comprising a group IV semiconductor material (such as silicon, germanium, or silicon germanium), a group III-V semiconductor material (such as gallium arsenide, indium gallium arsenide, or indium phosphide), and / or any other suitable material on which transistors can be formed. Alternatively, substrate 201 can be a semiconductor-on-insulator substrate comprising a desired semiconductor layer over a buried insulator layer (e.g., silicon over silicon dioxide). Alternatively, substrate 201 can be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe or alternating layers of indium gallium arsenide and indium phosphide). Any number of substrates can be used. In some embodiments, the semiconductor layers 204 have a different material composition than the sacrificial layers 202. In some embodiments, the semiconductor layers 204 are silicon germanium (SiGe), while the sacrificial layers 202 comprise a semiconductor material suitable for use as a nanoribbon, such as silicon (Si), SiGe, germanium, or III-V materials like indium phosphide (InP) or gallium arsenide (GaAs). In examples where SiGe is used in both the semiconductor layers 204 and the sacrificial layers 202, the germanium concentration differs between the semiconductor layers 204 and the sacrificial layers 202. For example, the semiconductor layers 204 may contain a higher proportion of germanium compared to the sacrificial layers 202.In some examples, the sacrificial layers 202 can be doped with either n-type dopants (to produce a p-channel transistor) or with p-type dopants (to produce an n-channel transistor). Although the dimensions may vary from one embodiment to the next, the thickness of each semiconductor layer 204 can be between approximately 5 nm and approximately 20 nm. In some embodiments, the thickness of each semiconductor layer 204 is essentially the same (e.g., within 1–2 nm). The thickness of each of the sacrificial layers 202 can be approximately the same as the thickness of each semiconductor layer 204 (e.g., approximately 5–20 nm). Each of the semiconductor layers 204 and sacrificial layers 202 can be deposited using any known material deposition technique, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or epitaxial growth. Figures 3A and 3B show cross-sectional views of the structure shown in Figures 2A and 2B, respectively, following the formation of a cap layer 302 and the subsequent formation of fins beneath the cap layer 302 according to one embodiment. The cap layer 302 can be any suitable hard mask material, such as a carbon hard mask (CHM) or silicon nitride. The cap layer 302 is structured in rows to form corresponding rows of fins from the stack of alternating layers of the sacrificial layers 202 and the semiconductor layers 204. The cap layer 302 extends along the top surface of each fin in a first direction, as can be seen in Figure 3A. According to some embodiments, an anisotropic etching process is continued through the layer stack into at least a portion of the substrate 201. Parts of the substrate 201 below the fins are not etched and form subfin regions 304. The etched portion of the substrate 201 can be filled with a dielectric filling 306, which acts as shallow trench insulation (STI) between adjacent fins. The dielectric filling material 306 can be any dielectric material, such as silicon dioxide. The subfin regions 304 represent remaining portions of the substrate 201 between the dielectric filling 306, according to some embodiments. Figures 4A and 4B show cross-sectional views of the structures shown in Figures 3A and 3B following the formation of sacrificial gates 402 according to some embodiments. A gate masking layer can first be structured into strips extending orthogonally across each of the fins (e.g., in a second direction) to form corresponding sacrificial gates 402 in strips beneath the gate masking layers. Subsequently, the gate masking layers can be removed or can remain as a capping layer over each sacrificial gate 402. According to some embodiments, the sacrificial gate material is removed in all areas not protected by the gate masking layers. The sacrificial gate 402 can be any material that can be selectively removed without damaging the semiconductor material of the fins. In some examples, the sacrificial gate 402 includes polysilicon. According to some embodiments, spacer structures 404 (also referred to as gate spacers or upper gate spacers) are formed along the sidewalls of the sacrificial gates 402. The spacer structures 404 can be deposited and then back-etched, so that the spacer structures 404 remain mainly only on the sidewalls of any exposed structures. In the cross-sectional view of Fig. 4B, the spacer structures 404 can also be formed along sidewalls of the exposed fins above the dielectric filling 306. Such sidewall spacers on the fins can be removed during a subsequent processing step when the source or drain regions are formed, or portions of the spacers can remain in the final structure.In some embodiments, the spacer structures 404 can be any suitable dielectric material, such as silicon nitride, silicon carbonitride, or silicon oxycarbonitride. In such an embodiment, the spacer structures 404 comprise a nitride, and the dielectric filling 306 comprises an oxide, thus providing a degree of etch selectivity during a final gate machining operation. Other etch-selective dielectric schemes (e.g., oxide / carbide, carbide / nitride) can also be used for the spacer structures 404 and the dielectric filling 306. In other embodiments, the spacer structures 404 and the dielectric filling 306 are identical or otherwise similar in composition when no etch selectivity is employed. Figures 5A and 5B show cross-sectional views of the structures shown in Figures 4A and 4B after the removal of exposed portions of the fins not protected by the sacrificial gates 402 and the spacer structures 404, according to some embodiments. The exposed fin portions can be removed using any anisotropic etching process, such as RIE. According to some embodiments, removing the exposed fin portions creates source or drain trenches alternating with gate trenches (currently filled with sacrificial gates 402) along the first direction. In some embodiments, at least a portion of the subfin regions 304 is also removed, so that an upper surface of the subfin regions 304 is recessed below an upper surface of the dielectric filling 306.In some embodiments, subfin areas 304 within the source / drain trenches are completely removed (as illustrated) to obtain subfin cavities 502. Figures 6A and 6B show cross-sectional views of the structures shown in Figures 5A and 5B following the removal of portions of the sacrificial layers 202 and the subsequent formation of internal spacers 602 (sometimes referred to as bottom gate spacers) according to an embodiment of the present disclosure. An isotropic etching process can be used to selectively deepen the exposed ends of each sacrificial layer 202 (while, for example, a comparatively small portion of the semiconductor layers 204 is etched). The internal spacers 602 can have a material composition similar to or exactly the same as that of the spacer structures 404. Accordingly, the internal spacers 602 can consist of any dielectric material exhibiting high etch selectivity towards semiconductor materials, such as silicon and / or silicon germanium.The internal spacers 602 can, for example, be conformally deposited above the sides of the fin structure using a conformal deposition process such as CVD or ALD and then back-etched using an isotropic etching process to expose the ends of the semiconductor layers 204. According to some embodiments, the internal spacers 602 have a similar width (e.g., along the first direction) to the spacer structures 404. According to some embodiments, dielectric material used to form internal spacers 602 can remain at the bottom of subfin cavities 502 as sacrificial plugs 604. In some embodiments, a separate material deposition process is performed to fill the source / drain grooves with a sacrificial material, which is subsequently recessed to form sacrificial plugs 604.The upper surface of the sacrificial plugs 604 may be located below the upper surface of the adjacent dielectric filling 306 and / or the adjacent subfin regions 304. As noted above, the sacrificial plugs 604 may be made of the same dielectric material as the internal spacers 602. In some examples, the sacrificial plugs 604 contain aluminum oxide or titanium nitride. Figures 7A and 7B show cross-sectional views of the structure shown in Figures 6A and 6B, respectively, after the formation of the source or drain regions 702 within the source / drain trenches according to some embodiments. The source or drain regions 702 can be formed in the areas previously occupied by the exposed fins between the spacer structures 404. According to some embodiments, the source or drain regions 702 are epitaxially grown from the exposed semiconductor material at the ends of the semiconductor layers 204. Any of the source or drain regions 702 can be NMOS source or drain regions (e.g., epitaxial silicon) or PMOS source or drain regions (e.g., epitaxial SiGe). Source or drain regions of one dopant type can be formed before the formation of source or drain regions of the other dopant type.In some examples, adjacent source or drain regions 702 along the second direction (e.g., as illustrated in Fig. 7B) exhibit alternating dopant types. The source or drain regions 702 can be formed directly over the sacrificial plug 604. In some examples, lower portions of the source or drain regions 702 are grown epitaxially from the exposed sidewall surfaces of the subfin regions 304 over the sacrificial plug 604. According to some embodiments, a dielectric filling 704 is provided between adjacent source or drain regions 702. In some examples, the dielectric filling 704 occupies a remaining volume within the source / drain trench around and above the source or drain regions 702. The dielectric filling material 704 can be any dielectric material, such as silicon dioxide. In some examples, the dielectric filling 704 extends to and is planar with a top surface of the spacer structures 404 (e.g., after a polishing process). A planarization process, such as chemical-mechanical polishing (CMP), can be used to remove any excess dielectric filling 704 and planarize the structure, as shown. Figures 8A and 8B show cross-sectional views of the structure shown in Figures 7A and 7B, respectively, after removal of the sacrificial gates 402 and sacrificial layers 202 according to some embodiments. In examples where gate masking layers are still present, they would be removed at this point. Once the sacrificial gates 402 have been removed, the fins extending between the spacer structures 404 are exposed. In the example where the fins include alternating semiconductor layers, sacrificial layers 202 are selectively removed to leave nanoribbons 802 extending between corresponding source or drain regions 702. Each vertical set of nanoribbons 802 represents the semiconductor region (or channel region) of another semiconductor device. It is noted that the nanoribbons 802 can have any geometry, and the use of the term "nanoribbon" is not intended to exclude any special geometries usable for a gate-all-around channel region (such as nanowires). In other embodiments, the nanoribbons 802 of a given channel region can be a single fin structure to provide a double-gate or tri-gate configuration.In further embodiments, the nanoribbons 802 of a given channel region can be nanosheets extending laterally (outward from the side) from a dielectric wall to provide a forksheet configuration. The sacrificial gates 402 and the sacrificial layers 202 can be removed using the same isotropic etching process or different isotropic etching processes. Figures 9A and 9B show cross-sectional views of the structure shown in Figures 8A and 8B after the formation of gate structures 902, subsequent gate caps 904, and front-side contacts 906 according to some embodiments. The gate structures 902 can each include a gate electrode on a gate dielectric. The gate dielectric can first be formed around the nanoribbons 802 prior to the formation of the gate electrode, which may include one or more conductive layers. The gate dielectric can comprise any gate dielectric material (such as silicon dioxide and / or a high-k dielectric).Examples of high-k dielectrics include hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc cniobate, to name just a few. In some embodiments, the gate dielectric comprises a layer of hafnium oxide with a thickness between approximately 1 nm and approximately 5 nm. In some embodiments, the gate dielectric may include one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and silicates of other transition metals). In some cases, the gate dielectric includes a first layer on the nanobands 802 and a second layer on top of the first layer. The first layer can, for example, be an oxide of the semiconductor material of the nanoribbons 802 (e.g.The first layer may be silicon dioxide) and the second layer may be a dielectric high-k material (e.g., hafnium oxide). The one or more conductive layers forming the gate electrode can be deposited using electroplating, electroless plating, CVD, PECVD, ALD, or PVD, to name a few examples. In some embodiments, the gate electrode comprises doped polysilicon, a metal, or a metal alloy. Examples of such metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and their carbides and nitrides. The gate electrode may, for example, include a metal filler material along with one or more exit work layers, resistance-reducing layers, and / or barrier layers. The exit work layers may, for example, comprise p-type exit work materials (e.g., tungsten) for PMOS gates or n-type exit work materials (e.g., titanium aluminum carbide) for NMOS gates. The gate cap 904 can be formed by first recessing the gate electrode and filling the recess with a dielectric material. The dielectric material can then be polished so that its upper surface is essentially coplanar with the upper surface of the spacer structures 404. According to some embodiments, the front-side contacts 906 can comprise any conductive material, such as tungsten, molybdenum, cobalt, titanium, tantalum, or ruthenium, or any alloys thereof, to establish an electrical contact with the underlying source or drain regions 702. As can be seen in the cross-section of Fig. 9B, a portion of the dielectric filling 704 is recessed to expose at least the upper surfaces of any number of source or drain regions 702, and a front-side contact 906 is formed within the recess using any metal deposition process. According to some embodiments, the front-side contacts 906 comprise one or more silicide layers (or optionally germanide layers) directly on the exposed surfaces of the source or drain regions 702.The front-side contacts 906 can extend along the source / drain trenches in the second direction on any number of source or drain areas 702. Figures 10A and 10B show cross-sectional views of the structure shown in Figures 9A and 9B, respectively, following the formation of dielectric walls 1002 extending between devices in the first direction, according to some embodiments. The dielectric walls 1002 extend to a depth of at least one full thickness of the gate structures 902 to insulate the gate structures along the second direction. In some embodiments, the dielectric walls 1002 extend into at least a portion of the dielectric filling 306 or through one full thickness of the dielectric filling 306. In some embodiments, the dielectric walls 1002 extend completely through the dielectric filling 306 and into a portion of the substrate 201. According to some embodiments, dielectric walls 1002 can be formed by first creating appropriate gate-cut recesses through the gate cap 904, the contact 906, and the gate structures 902 using any suitable metal-gate etching process that iteratively etches through portions of the gate electrode while simultaneously protecting the sidewalls of the recess from lateral etching, in order to provide a recess with a high height-to-width aspect ratio (e.g., an aspect ratio of 5:1 or higher, or 10:1 or higher). As shown in Fig. 10B, the gate-cut recesses extend in the first direction (e.g., into and out of the plane of the image) through several gate trenches and source / drain trenches to isolate adjacent gate structures and source or drain regions. The gate-cut recesses can be filled with one or more dielectric materials to form the dielectric walls 1002.For example, the dielectric walls 1002 can consist only of silicon dioxide, silicon nitride, or silicon carbide. In some examples, the dielectric walls 1002 include a first dielectric layer, which is deposited first, and a second dielectric layer or dielectric filling, which forms on top of the first dielectric layer. The first dielectric layer can consist of a high-k dielectric material (e.g., materials with a dielectric constant higher than that of silicon dioxide or higher than 3.9), while the second dielectric layer can consist of a low-k dielectric material (e.g., materials with a dielectric constant equal to or lower than that of silicon dioxide, such as porous silicon dioxide, or equal to or lower than 3.9).In the illustrated example, the dielectric walls 1002 separate each of the source or drain regions 702 along the second direction, together with their associated front-side contacts 906. In some examples where devices are tightly packed, the dielectric walls 1002 may contact one or more side walls of the source or drain regions 702. In some examples, the dielectric walls 1002 exist between some adjacent pairs of source or drain regions 702, but not between every adjacent pair of source or drain regions 702. Figures 11A and 11B show cross-sectional views of the structure shown in Figures 10A and 10B, respectively, after removal of the substrate 201 from the back side, thereby exposing a lower surface of the subfin regions 304, a lower surface of the dielectric filling 306, and a lower surface of the sacrificial plugs 604, according to some embodiments. According to some embodiments, any suitable backside lithography process can be performed to remove one or more of the sacrificial plugs 604. In the illustrated example, the left sacrificial plug in Figure 11B has been removed. These plugs can be removed from beneath source or drain regions that will not have backside contact, as described herein. Any suitable isotropic etching process can be used to remove the material of the sacrificial plugs 604 while etching little to none of the surrounding subfin regions 304 and the dielectric filling 306. Figures 12A and 12B show cross-sectional views of the structure shown in Figures 11A and 11B, respectively, after removal of the subfin regions 304 and subsequent formation of a dielectric base structure 1202 according to some embodiments. The dielectric base structure 1202 can represent any number of deposited dielectric material layers and can include any suitable dielectric material, such as silicon dioxide. According to some embodiments, a rear surface of the dielectric base structure 1202 is back-polished until a lower surface of the sacrificial plugs 604 is again exposed. Figures 13A and 13B show cross-sectional views of the structure shown in Figures 12A and 12B, respectively, after removal of the remaining sacrificial plugs 604 to form corresponding backside cavities 1302 beneath the source or drain regions 702, according to some embodiments. Any suitable isotropic etching process can be used to remove the material of the remaining sacrificial plugs 604, while little to none of the surrounding dielectric base structure 1202 and dielectric filling 306 is etched. At least one lower surface of the source or drain regions 702 can be exposed within the backside cavities 1302. Figures 14A and 14B show cross-sectional views of the structure shown in Figures 13A and 13B, respectively, after the formation of a dielectric lining 1402 according to some embodiments. The dielectric lining 1402 can be any suitable dielectric material, such as silicon nitride or titanium oxide, and can have a thickness between about 1 nm and about 3 nm. The dielectric lining 1402 can be deposited using any suitable conformal deposition method, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). The dielectric lining 1402 can be formed to cover the sidewalls of the backside cavities 1302 and the exposed lower surfaces of the source or drain regions 702.In some examples, parts of the dielectric lining 1402 extend further along the lower surface of the dielectric base structure 1202. Figures 15A and 15B show cross-sectional views of the structure shown in Figures 14A and 14B after a further etching process to form depressions 1502 extending into source or drain regions 702, according to some embodiments. A masking layer 1504 may initially be formed over the lower surface of the dielectric base structure 1202, while little to none of the masking layer 1504 is formed within the backside cavities 1302. In some embodiments, the masking layer 1504 is deposited using physical vapor deposition (PVD), such as sputtering, to preferably deposit the material on the planar lower surface of the dielectric base structure 1202. The masking layer 1504 may comprise any suitable hard dielectric mask material or a carbon hard mask (CHM). After the formation of the masking layer 1504, a directed RIE process can be performed to penetrate a portion of the dielectric lining 1402 on the lower surface of the source or drain regions 702. The etching process can then continue into the source or drain regions 702 to form depressions 1502. In some examples, the depressions 1502 extend through at least 30%, at least 40%, at least 50%, or at least 60% of the total height (e.g., along the Z-direction) of the source or drain regions 702. In some examples, the depressions 1502 extend through a portion of the source or drain regions 702 that lies above a plane that is coplanar with a bottom surface of the bottommost set of nanoribbons 802 or a bottom surface of the second-bottom set of nanoribbons 802.It is noted that a small portion of the dielectric lining 1402 may remain on the lower surface of the source or drain regions 702 around the opening to the depressions 1502. The depressions 1502 may also have a tapered width, forming an elongated oval shape with a domed, tapered, or flat end. Figures 16A and 16B show cross-sectional views of the structure depicted in Figures 15A and 15B after the formation of backside contacts 1602 within the cavities 1302 and 1502 according to some embodiments. The backside contacts 1602 can comprise any suitable conductive material, such as any of tungsten, ruthenium, molybdenum, or cobalt. The backside contacts 1602 will assume the shape of the cavities 1302 and 1502 and accordingly have a generally tapered profile as they extend through the source or drain regions 702. According to some embodiments, the portion of the backside contacts 1602 that extends through the source or drain regions 702 has an elongated oval shape with a convex, pointed, or flat end. This part of the backside contacts 1602 extends through at least 30%, at least 40%, at least 50%, or at least 60% of a total height (e.g.along the Z-direction) of the source or drain regions 702. In some examples, this portion of the backside contacts 1602 extends through a part of the source or drain regions 702 that lies above a plane that is coplanar with a bottom surface of the bottommost set of nanoribbons 802 or a bottom surface of the second-bottom set of nanoribbons 802. Since the sacrificial plugs 604 at the bottom of the source / drain trenches were self-aligned, the backside contacts 1602 can each be self-aligned with their corresponding source or drain regions 702. For example, a center of the backside contacts 1602 can be aligned within 1 nm of a center of the source or drain regions 702. According to some embodiments, the lithographically patterned and etched backside contacts can be connected to frontside contacts to form a combined or connected contact over the entire height of a given source or drain region. Figures 17A and 17B show cross-sectional views of another exemplary structure with a backside contact 1602 directly contacting a frontside contact 1702 within the source or drain region 702. The frontside contact 1702 can be formed during the frontside processing of the integrated circuit (e.g., prior to substrate removal 201).In some embodiments, another dielectric lining 1704 can be formed within a front-side cavity formed above the source or drain region 702, followed by a RIE process to form a front-side depression into the source or drain region, similar to the formation of the depression 1502 by the back side of the source or drain region 702. The front-side depression and the front-side cavity can then be filled with one or more conductive materials to form a front-side contact 1702. The front-side contact 1702 can include any of the conductive materials described above for the back-side contact 1602. In some examples, the front-side contact 1702 includes the same conductive material as the back-side contact 1602. The process described above for forming the backside contact 1602 remains unchanged. Accordingly, in some embodiments, the backside recess 1502 can expose a lower surface of the frontside contact 1702, so that the backside contact 1602 is formed directly on a portion of the frontside contact 1702 when the backside cavities 1302 and 1502 are filled. In some embodiments, a hole or recess can exist in the area where the frontside contact 1702 contacts the backside contact 1602. The hole or recess can be formed due to the tapered end profile of both the frontside contact 1702 and the backside contact 1602. Fig. 18 illustrates an exemplary embodiment of a chip package 1800 according to an embodiment of the present disclosure. As can be seen, the chip package 1800 has one or more dies 1802. One or more dies 1802 can have at least one integrated circuit with semiconductor devices, such as any of the semiconductor devices disclosed herein. In some exemplary configurations, one or more dies 1802 can have any other circuit arrangement used to form an interface with other devices formed on the dies or other devices connected to the chip package 1800. As can be further seen, the chip package 1800 has a package 1804 bonded to a package substrate 1806. The package 1804 can be any standard or proprietary package and can, for example, provide electromagnetic shielding and environmental protection for the components of the chip package 1800. The one or more dies 1802 can be conductively coupled to a package substrate 1806 using interconnects 1808 implemented with any number of standard or proprietary interconnection mechanisms, such as solder pads, a ball grid array (BGA), pins, or wire bonds, to name a few examples. The package substrate 1806 can be any standard or proprietary package substrate, but in some cases it has a dielectric material with conductive paths (e.g.,including conductive vias and leads) extending through the dielectric material between the faces of the housing substrate 1806 or between different positions on each face. In some embodiments, the housing substrate 1806 may have a thickness of less than 1 millimeter (e.g., between 0.1 millimeters and 0.5 millimeters), although any number of housing geometries may be used. Additional conductive contacts 1812 may be arranged on an opposite face of the housing substrate 1806 for conductive contacting, for example, a printed circuit board (PCB). One or more vias 1810 extend through a thickness of the housing substrate 1806 to provide conductive paths between one or more connections 1808 and one or more contacts 1812.The vias 1810 are illustrated for simplicity as single straight pillars through the housing substrate 1806, although other configurations can be used (e.g., Damascene, dual-Damascene, silicon vias, or an intermediate interconnect structure that meanders through the thickness of the substrate 1806 to make contact with one or more intermediate positions within it). In further embodiments, the vias 1810 are made by several smaller, stacked vias or are staggered at different positions across the housing substrate 1806. In the illustrated embodiment, the contacts 1812 are solder balls (e.g., for contact-bump-based connections or a ball-grid array arrangement), but any suitable housing bonding mechanism can be used (e.g.,Pins in a pin grid array arrangement or contact spots in a contact spot grid array arrangement). In some embodiments, a solder mask is arranged between the contacts 1812 to prevent a short circuit. In some embodiments, a potting compound 1814 can be arranged around the one or more dies 1802 contained within the housing 1804 (e.g., between the dies 1802 and the housing substrate 1806 as an underfill material, and between the dies 1802 and the housing 1804 as an overfill material). Although the dimensions and properties of the potting compound 1814 may vary from one embodiment to another, in some embodiments the thickness of the potting compound 1814 is less than 1 millimeter. Exemplary materials that can be used for the potting compound 1814 may include epoxy potting compounds. In some cases, the potting compound 1814 is thermally conductive in addition to being electrically insulating. methodology Fig. 19 is a flowchart of a method 1900 for forming at least part of an integrated circuit according to one embodiment. Various operations of the method 1900 may be illustrated in Figs. 2A-16A and 2B-16B. However, the correlation of the various operations of the method 1900 with the specific components illustrated in the aforementioned figures is not intended to imply any structural and / or application-related limitations. Rather, the aforementioned figures provide an embodiment of the method 1900. Other operations may be performed before, during, or after any of the operations of the method 1900. For example, the method 1900 does not explicitly describe various standard processes commonly performed to form transistor structures. Some of the operations of the method 1900 may be performed in a different order than the one illustrated. According to some embodiments, method 1900 begins with step 1902, in which a semiconductor fin is formed. The semiconductor material in the fin can be formed from a substrate such that the fin is an integral part of the substrate (e.g., etched from a bulk silicon substrate). Alternatively, the fin can also be formed from a material deposited onto an underlying substrate. In one such exemplary case, a cover layer of silicon germanium (SiGe) can be deposited onto a silicon substrate and then patterned and etched to form a plurality of SiGe fins extending from that substrate.In another such example, non-native fins can be formed in an aspect ratio trapping process, in which native fins are etched away to leave fin-shaped grooves that can then be filled with an alternative semiconductor material (e.g., from the IV or III-V material groups). In further embodiments, the fins include alternating material layers (e.g., alternating layers of silicon and SiGe) that enable the formation of nanowires and nanoribbons during a gate formation process, in which one type of alternating layer is selectively etched away to expose the other type of alternating layer within the channel region, allowing a gate-all-around process (GAA process) to be performed subsequently.Here too, the alternating layers can be deposited across the entire surface and then etched into fins or deposited in fin-shaped grooves. The fin can also include a cap structure, which is used to define the fin's position, for example, during a RIE process. The cap structure can be made of a dielectric material, such as silicon nitride. Method 1900 continues with process 1904, in which a dielectric layer is formed around a subfin region of the fin. In some embodiments, the dielectric layer extends between each pair of adjacent parallel fins and runs longitudinally in the same direction as the fins. In some embodiments, the anisotropic etching process that forms the fins also etches into a section of the substrate, and the dielectric layer can form within the recessed sections of the substrate. Accordingly, the dielectric layer acts as shallow trench insulation (STI) between adjacent fins. The dielectric layer can be any suitable dielectric material, such as silicon dioxide. Procedure 1900 continues with Procedure 1906, in which a sacrificial gate is formed over the fin. The sacrificial gate can be one of several sacrificial gates structured in strips using gate masking layers that run orthogonally across the fins and parallel to each other (e.g., forming a crosshatch pattern). The gate masking layer can be any suitable hard mask material, such as CHM or silicon nitride. The sacrificial gate itself can be formed from any suitable material that can be selectively removed at a later time without damaging the fin's semiconductor material. In one example, the sacrificial gate features polysilicon. According to some embodiments, spacer structures are also formed on the sidewalls of at least the sacrificial gate. These spacer structures can be deposited and then etched back, so that they remain primarily on the sidewalls of any exposed structures. In some cases, the spacer structures can also be formed along the sidewalls of the exposed fins that run orthogonally between the strips of the sacrificial gates. According to some embodiments, the spacer structures can be any suitable dielectric material, such as silicon nitride or silicon oxynitride. Method 1900 continues with process 1908, in which source / drain trenches are etched through the fin and through at least a portion of the subfin region. Any exposed portions of the fin not covered by the sacrificial gates or spacer structures can be removed using any anisotropic etching process, such as reactive ion etching (RIE). According to some embodiments, the RIE process continues to etch beyond the height of the fin through the subfin region adjacent to the dielectric layer. The etched portion of the subfin region can be identified as a subfin depression. Process 1900 continues with process 1910, in which a sacrificial material is formed within the subfin recesses. The sacrificial material can be any suitable material that can be selectively removed at a later time (e.g., by isotropic etching). In some examples, the sacrificial material is a dielectric material, such as silicon nitride, but the sacrificial material can also be aluminum oxide or titanium nitride. Method 1900 continues with process 1912, in which source or drain regions are formed at opposite ends of the fin. According to some embodiments, the source or drain regions are formed in the areas previously occupied by the exposed fin between the spacer structures. The source or drain regions can be epitaxially grown from the exposed semiconductor material of the fins (or optionally the nanoribbons, nanowires, or nanosheets) along the outer walls of the spacer structures. In some embodiments, the source or drain regions are NMOS source or drain regions (e.g., epitaxial silicon) or PMOS source or drain regions (e.g., epitaxial SiGe). A dielectric filling can be formed between and above the source or drain regions along a given source / drain trench.The dielectric fill can be any suitable dielectric material, such as silicon dioxide. In some examples, the dielectric fill extends above the source or drain regions and is planar with an upper surface of the spacer structures. The dielectric fill also acts as an electrical insulator between adjacent source or drain regions, although some adjacent source or drain regions may become interconnected during their growth. The source or drain regions can be grown directly above the sacrificial material at the bottom of the source / drain trench. Process 1900 continues with process 1914, in which the substrate is removed from the back of the structure to expose the lower surface, at least of the sacrificial material. The substrate can be removed using any number of isotropic etching, polishing, or grinding operations. The subfin regions can also be removed at this stage and replaced with one or more suitable dielectric materials, such as silicon dioxide, to form a dielectric base structure. Process 1900 continues with process 1916, in which the sacrificial material is removed from the backside, forming a dielectric lining within the resulting backside cavity. Any suitable isotropic etching process can be used to selectively remove the sacrificial layer material. The cavity left behind upon removal of the sacrificial material exposes at least a lower surface of the source or drain region directly above the cavity. According to some embodiments, the dielectric lining is deposited using any suitable conformal deposition method, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). The dielectric layer can be any suitable dielectric material, such as silicon nitride or titanium nitride, and can have a thickness between about 1 nm and about 3 nm. The dielectric lining can be configured to cover the sidewalls of the backside cavity and the exposed lower surface of the source or drain region. Method 1900 continues with process 1918, in which a portion of the dielectric lining is removed during a directional etching process that extends into the source or drain region. According to some embodiments, a deep depression is etched using the directional etching process (e.g., RIE) that extends through at least 30%, at least 40%, at least 50%, or at least 60% of the total height (e.g., along the Z-direction) of the source or drain region. In some examples, the depression extends through a portion of the source or drain region that lies above a plane coplanar with a bottom surface of the bottommost set of nanoribbons or a bottom surface of the second-bottom set of nanoribbons. A hard mask can be formed on the underside of the dielectric base structure to protect the sidewalls of the dielectric lining during the etching process.Thus, in some examples, a small portion of the dielectric lining remains on the lower surface of the source or drain regions around the opening of the depression. The depression may also have a tapered width, exhibiting an elongated oval shape with a domed, pointed, or flat end. Method 1900 continues with process 1920, in which a backside contact is formed within the backside cavity and within the depression in the source or drain region. According to some embodiments, the backside contact is formed directly on one or more exposed surfaces of the source or drain region within the depression. The backside contact may contain any suitable conductive material, such as cobalt, ruthenium, molybdenum, or tungsten. According to some embodiments, the backside contact is part of a backside intermediate interconnect structure to connect the source or drain region to a power or ground busbar. Due to the geometry of the depression, the backside contact may extend into the source or drain region, such as at least 30%, 40%, 50%, or 60% of the total height of the source or drain region.It is noted that if a front contact was previously formed which also extended into the source or drain region, then the back contact can be formed on part of the front contact within the source or drain region to give a combined or connected contact structure extending through the entire height of the source or drain region. As noted above, some of the operations can be performed in a different order to still produce the same or a similar final structure. For example, the semiconductor subfin regions can remain throughout operations 1916, 1918, and 1920 and are removed and replaced by the dielectric base structure after the backside contact is formed. Exemplary system Figure 20 shows an exemplary computing system implemented with one or more of the integrated circuit structures disclosed herein, according to some embodiments of the present disclosure. As can be seen, the computing system 2000 incorporates a mainboard 2002. The mainboard 2002 may include a number of components, including, among others, a processor 2004 and at least one communication chip 2006, each of which may be physically and electrically connected to or otherwise integrated into the mainboard 2002. It is understood that the mainboard 2002 may, for example, be any printed circuit board (PCB), be it a mainboard, a daughterboard mounted on a mainboard, or the only board of the system 2000, etc. Depending on its applications, the Computing System 2000 may include one or more other components that may or may not be physically and electrically coupled to the Mainboard 2002. These other components may, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, a keypad controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a loudspeaker, a camera, and a mass storage device (such as a hard disk drive, a compact disc (CD), a digital versatile disc (DVD), and the like).Each of the components included in the Computing System 2000 may comprise one or more integrated circuit structures or devices configured according to an exemplary embodiment (e.g., a module comprising one or more semiconductor devices having backside contacts extending into the source or drain regions, as specified herein in various ways). In some embodiments, several functions may be integrated into one or more chips (e.g., for example, the Communications Chip 2006 may be part of or otherwise integrated into the Processor 2004). The Communications Chip 2006 enables wireless communication for the transmission of data to and from the Computing System 2000. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data over a non-solid medium by using modulated electromagnetic radiation. The term does not imply that the associated devices contain no wires whatsoever, although this may be the case in some embodiments. The Communications Chip 2006 can implement any number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), and IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G and beyond. The Computing System 2000 can incorporate a variety of Communications Chips 2006. For example, a first Communications Chip 2006 can be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second Communications Chip 2006 can be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. The Processor 2004 of the Computing System 2000 comprises an integrated circuit die that is packaged within the Processor 2004. In some embodiments, the processor's integrated circuit die includes an on-board circuit arrangement implemented with one or more semiconductor devices, as described herein in various ways. The term "processor" may refer to any device or any part of a device that, for example, processes electronic data from registers and / or from memory to convert such electronic data into other electronic data that can be stored in registers and / or memory. The communication chip 2006 can also include an integrated circuit die that is packaged within the communication chip 2006. According to some such embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices, as described herein in various ways. In light of this disclosure, it is understood that a multi-standard wireless capability can be directly integrated into the processor 2004 (e.g., if the functionality of any 2006 chips is integrated into the processor 2004 instead of having separate communication chips). Furthermore, it should be noted that the processor 2004 can be a chipset with such wireless capability. In short, any number of the processor 2004 and / or the communication chips 2006 can be used. Likewise, any chip or chipset can have multiple functions integrated therein. In various implementations, the Computing System 2000 can be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music playback device, a digital video recorder, or any other electronic device that processes data or uses one or more integrated circuit structure(s) or device(s) formed using the disclosed techniques as described herein in various ways. It is understood that in some embodiments the various components of the Computing System 2000 can be combined with or integrated into a system-on-a-chip (SoC) architecture. In some embodiments, the components can be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software. Further exemplary embodiments The following examples concern further embodiments, from which numerous implementations and configurations become apparent. Example 1 is an integrated circuit comprising a semiconductor device with a semiconductor region extending in a first direction from a source or drain region and a gate structure extending in a second direction above the semiconductor region, a dielectric layer below the gate structure, a conductive back contact extending through the dielectric layer and through at least a portion of the total height of the source or drain region, and a dielectric lining on sidewall surfaces of the conductive back contact. The dielectric lining is located between the conductive back contact and the dielectric layer, and at least a portion of the dielectric lining contacts a lower surface of the source or drain region. Example 2 includes the integrated circuit according to Example 1, wherein the semiconductor area comprises one or more semiconductor nanoribbons. Example 3 includes the integrated circuit according to Example 2, wherein one or more semiconductor nanobands comprise germanium, silicon or any combination thereof. Example 4 includes the integrated circuit according to Example 2 or 3, wherein the conductive backside contact extends over a plane that is coplanar with a bottommost nanoband of one or more semiconductor nanobands. Example 5 includes the integrated circuit according to one of Examples 1 to 4, further comprising a conductive front-side contact extending through at least part of the total height of the source or drain region. Example 6 includes the integrated circuit according to Example 5, wherein the conductive front contact contacts the conductive back contact within the source or drain region. Example 7 includes the integrated circuit according to Example 5 or 6, wherein the dielectric lining is a first dielectric lining and the integrated circuit further comprises a second dielectric lining on sidewall surfaces of the conductive front-side contact, wherein at least a part of the second dielectric lining contacts an upper surface of the source or drain region. Example 8 includes the integrated circuit according to any one of Examples 5 to 7, wherein the conductive backside contact has a tapered width as it extends towards an upper surface of the source or drain region, and the conductive frontside contact has a tapered width as it extends towards the lower surface of the source or drain region. Example 9 includes the integrated circuit according to one of Examples 1 to 8, wherein the dielectric lining comprises silicon and nitrogen or titanium and oxygen. Example 10 includes the integrated circuit according to one of Examples 1 to 9, further comprising a conductive backside layer contacting a lower surface of the conductive backside contact. Example 11 is a die that includes the integrated circuit according to one of Examples 1 to 10. Example 12 is an electronic device comprising a chip package containing one or more dies. At least one of the one or more dies comprises a semiconductor region extending in a first direction from a source or drain region, a gate structure extending in a second direction above the semiconductor region, a dielectric layer below the gate structure, a conductive back contact extending through the dielectric layer and through at least a portion of the total height of the source or drain region, and a dielectric lining on sidewall surfaces of the conductive back contact. The dielectric lining is located between the conductive back contact and the dielectric layer along the first direction. At least a portion of the dielectric lining contacts a lower surface of the source or drain region. Example 13 includes the electronic device according to Example 12, wherein the semiconductor area comprises one or more semiconductor nanoribbons. Example 14 includes the electronic device according to Example 13, wherein one or more semiconductor nanoribbons comprise germanium, silicon or any combination thereof. Example 15 includes the electronic device according to Example 13 or 14, wherein the conductive backside contact extends over a plane that is coplanar with a bottommost nanoband of one or more semiconductor nanobands. Example 16 includes the electronic device according to any one of Examples 12 to 15, wherein the at least one of the one or more dies further comprises a conductive front-side contact extending through at least a part of the total height of the source or drain region. Example 17 includes the electronic device according to Example 16, wherein the conductive front contact contacts the conductive back contact within the source or drain region. Example 18 includes the electronic device according to Example 16 or 17, wherein the dielectric lining is a first dielectric lining and the at least one of the one or more Dies further comprises a second dielectric lining on sidewall surfaces of the conductive front-side contact, wherein at least a part of the second dielectric lining contacts an upper surface of the source or drain region. Example 19 includes the electronic device according to any of Examples 16 to 18, wherein the conductive backside contact has a tapered width as it extends towards an upper surface of the source or drain region, and the conductive frontside contact has a tapered width as it extends towards the lower surface of the source or drain region. Example 20 includes the electronic device according to one of Examples 12 to 19, wherein the dielectric lining comprises silicon and nitrogen or titanium and oxygen. Example 21 includes the electronic device according to any one of Examples 12 to 20, further comprising a conductive backside layer contacting a lower surface of the conductive backside contact. Example 22 includes the electronic device according to one of Examples 12 to 21, wherein the at least one of the one or more Dies further comprises a printed circuit board, wherein the chip package is attached to the printed circuit board. Example 23 is a method for forming an integrated circuit. The method involves: forming a fin encompassing semiconductor material, the fin extending over a substrate; forming a dielectric layer adjacent to a subfin of the fin; forming a sacrificial gate and spacer structures over the fin; removing portions of the fin not covered by the sacrificial gates and spacer structures; removing a subfin region of the fin to form a subfin cavity; forming a sacrificial plug within the subfin cavity; forming a source or drain region at exposed ends of the semiconductor material and over the sacrificial plug; removing a portion of the substrate from a backside of the integrated circuit to expose a lower surface of the subfin and a lower surface of the sacrificial material; and removing the sacrificial plug from the backside to form a backside cavity.Forming a dielectric lining within the backside cavity; removing part of the dielectric lining on a lower surface of the source or drain region; etching a depression into the exposed lower surface of the source or drain region; and forming a conductive contact both within the backside cavity and within the depression. Example 24 includes the procedure according to Example 23, wherein the etching of the depression comprises etching of the depression using reactive ion etching (RIE). Example 25 includes the method according to Example 23 or 24, wherein the sacrificial plug comprises titanium and nitrogen or silicon and nitrogen. Example 26 includes the method according to one of Examples 23 to 25, further comprising removing the subfin from the back side and replacing the subfin with a dielectric layer. Example 27 includes the method according to one of Examples 23 to 26, wherein the dielectric lining comprises silicon and nitrogen or titanium and oxygen. Example 28 includes the method of any one of Examples 23 to 27, wherein the depression is a first depression and the conductive contact is a first conductive contact. The method further comprises: etching a second depression through an upper surface of the source or drain region; and forming a second conductive contact within the second depression. Etching the first depression comprises etching the first depression into the exposed lower surface of the source or drain region and exposing at least part of the second conductive contact. Example 29 is an integrated circuit comprising a semiconductor device with a semiconductor region extending in a first direction from a source or drain region, a gate structure extending in a second direction above the semiconductor region, a dielectric layer below the gate structure, and a conductive contact extending through the dielectric layer and through the entire height of the source or drain region. The conductive contact has a first section with a tapered width from a lower surface of the source or drain region to a top surface of the first section, and a second section with a tapered width from a top surface of the source or drain region to the bottom surface of the second section. The conductive contact has a minimum width at an interface between the first and second sections of the conductive contact. Example 30 includes the integrated circuit according to Example 29, further comprising a dielectric lining on side walls of the conductive contact between the conductive contact and the dielectric layer. Example 31 includes the integrated circuit according to Example 30, wherein part of the dielectric lining contacts a lower surface of the source or drain region. Example 32 includes the integrated circuit according to one of Examples 29 to 31, wherein a width of the first section of the conductive contact on the lower surface of the source or drain region is within 2 nm of a width of the second section of the conductive contact on the upper surface of the source or drain region. Example 33 includes the integrated circuit according to Example 32, wherein the smallest width at the interface between the first section and the second section of the conductive contact is at least 5 nm smaller than the width of the first section of the conductive contact at the lower surface of the source or drain region and the width of the second section of the conductive contact at the upper surface of the source or drain region. Example 34 includes the integrated circuit according to one of Examples 29 to 33, wherein the semiconductor domain comprises one or more semiconductor nanoribbons. Example 35 includes the integrated circuit according to Example 34, wherein one or more semiconductor nanobands comprise germanium, silicon or any combination thereof. Example 36 includes the integrated circuit according to any one of Examples 29 to 35, further comprising: a conductive backside layer contacting a lower surface of the conductive contact; and a conductive frontside layer contacting an upper surface of the conductive contact. Example 37 is a die that includes the integrated circuit according to one of Examples 29 to 36. The foregoing description of the embodiments of the disclosure has been set forth for illustrative and descriptive purposes. It is not intended to be exhaustive or to limit the disclosure to the exact forms disclosed. Many modifications and variations are possible in view of the present disclosure. It is intended that the scope of the disclosure is not limited by this detailed description, but rather by the accompanying claims.

Claims

Integrated circuit comprising: a semiconductor device with a semiconductor region extending in a first direction from a source or drain region and a gate structure extending in a second direction above the semiconductor region; a dielectric layer below the gate structure; a conductive backside contact extending through the dielectric layer and through at least a portion of the total height of the source or drain region; and a dielectric lining on sidewall surfaces of the conductive backside contact, wherein the dielectric lining is located between the conductive backside contact and the dielectric layer and wherein at least a portion of the dielectric lining contacts a lower surface of the source or drain region. Integrated circuit according to claim 1, wherein the semiconductor area comprises one or more semiconductor nanoribbons. Integrated circuit according to claim 2, wherein one or more semiconductor nanoribbons comprise germanium, silicon or any combination thereof. Integrated circuit according to claim 2 or 3, wherein the conductive backside contact extends over a plane that is coplanar with a bottommost nanoband of one or more semiconductor nanobands. Integrated circuit according to one of claims 1 to 4, further comprising a conductive front-side contact extending through at least a part of the total height of the source or drain region. Integrated circuit according to claim 5, wherein the conductive front contact contacts the conductive back contact within the source or drain region. Integrated circuit according to claim 5 or 6, wherein the dielectric lining is a first dielectric lining and the integrated circuit further comprises a second dielectric lining on sidewall surfaces of the conductive front-side contact, wherein at least a part of the second dielectric lining contacts an upper surface of the source or drain region. Integrated circuit according to any one of claims 5 to 7, wherein the conductive backside contact has a tapered width as it extends towards an upper surface of the source or drain region, and the conductive frontside contact has a tapered width as it extends towards the lower surface of the source or drain region. Integrated circuit according to any one of claims 1 to 8, wherein the dielectric lining comprises silicon and nitrogen or titanium and oxygen. Integrated circuit according to any one of claims 1 to 9, further comprising a conductive backside layer that contacts a lower surface of the conductive backside contact. The one comprising the integrated circuit according to any one of claims 1 to 10. Electronic device comprising: a chip package comprising one or more dies, wherein at least one of the one or more dies comprises: a semiconductor region extending in a first direction from a first source or drain region; a gate structure extending in a second direction above the semiconductor region; a dielectric layer below the gate structure; a conductive backside contact extending through the dielectric layer and through at least a portion of the total height of the source or drain region; and a dielectric lining on sidewall surfaces of the conductive backside contact, wherein the dielectric lining is located between the conductive backside contact and the dielectric layer along the first direction and wherein at least a portion of the dielectric lining contacts a lower surface of the source or drain region. Electronic device according to claim 12, wherein the semiconductor region comprises one or more semiconductor nanoribbons and the conductive backside contact extends over a plane that is coplanar with a bottommost nanoribbon of the one or more semiconductor nanoribbons. Electronic device according to claim 12 or 13, wherein the at least one of the one or more dies further comprises a conductive front-side contact extending through at least a part of the total height of the source or drain region. Electronic device according to claim 14, wherein the conductive front contact contacts the conductive back contact within the source or drain region. Electronic device according to claim 14 or 15, wherein the conductive backside contact has a tapered width as it extends towards an upper surface of the source or drain region, and the conductive frontside contact has a tapered width as it extends towards the lower surface of the source or drain region. Integrated circuit comprising: a semiconductor device with a semiconductor region extending in a first direction from a source or drain region and a gate structure extending in a second direction above the semiconductor region; a dielectric layer below the gate structure; and a conductive contact extending through the dielectric layer and through an entire height of the source or drain region, wherein the conductive contact comprises a first section having a tapered width from a lower surface of the source or drain region to a top surface of the first section and a second section having a tapered width from a top surface of the source or drain region to the bottom surface of the second section, wherein the conductive contact has a smallest width at an interface between the first section and the second section of the conductive contact. Integrated circuit according to claim 17, further comprising a dielectric lining on side walls of the conductive contact between the conductive contact and the dielectric layer. Integrated circuit according to claim 18, wherein a part of the dielectric lining contacts a lower surface of the source or drain region. Integrated circuit according to one of claims 17 to 19, wherein a width of the first section of the conductive contact on the lower surface of the source or drain region is within 2 nm of a width of the second section of the conductive contact on the upper surface of the source or drain region. Integrated circuit according to claim 20, wherein the smallest width at the interface between the first section and the second section of the conductive contact is at least 5 nm smaller than the width of the first section of the conductive contact at the lower surface of the source or drain region and the width of the second section of the conductive contact at the upper surface of the source or drain region. Integrated circuit according to one of claims 17 to 21, wherein the semiconductor area comprises one or more semiconductor nanoribbons. Integrated circuit according to claim 22, wherein one or more semiconductor nanoribbons comprise germanium, silicon or any combination thereof. Integrated circuit according to one of claims 17 to 23, further comprising: a conductive back layer that contacts a lower surface of the conductive contact; and a conductive front layer that contacts an upper surface of the conductive contact. The one which includes the integrated circuit according to one of claims 17 to 24.

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