Semiconductor component and method for producing an electrically conductive structure of a metalizing structure

Abstract

In one embodiment, a semiconductor device is provided comprising a semiconductor substrate, having a first main surface, and a metallization structure arranged on the first main surface. The metallization structure has one or more electrically conductive structures, comprising a metallic diffusion barrier and a copper layer arranged on the metallic diffusion barrier. The metallic diffusion barrier has a thickness t, a top surface, a bottom surface, and a side surface extending between an upper edge formed between the top surface and the side surface, and a lower edge formed between the bottom surface and the side surface. The linear distance d between the upper edge and the lower edge is t ≤ d ≤ 1.1 t or t ≤ d ≤ 1.05 t.

Description

BACKGROUND

[0001] Transistors used in power electronics applications can be fabricated from silicon (Si) semiconductor materials. Common transistor devices for power applications include Si-CoolMOS®, Si-Power MOSFETs, and Si-IGBTs (Insulated-Gate Bipolar Transistors). More recently, silicon carbide (SiC) power devices have been considered. Semiconductor devices based on group III nitrides, such as gallium nitride (GaN) devices, are promising candidates for handling high currents, supporting high voltages, and providing very low on-resistance and fast switching times.

[0002] One or more semiconductor devices, such as transistors, can be enclosed in a package. The package includes a substrate or a conductor frame with external contacts used to mount the package onto a rewiring board, such as a printed circuit board (PCB). The package also includes internal electrical connections from the semiconductor device to the substrate or conductor frame. The package may contain a plastic potting compound that covers the semiconductor device and the internal electrical connections.

[0003] Reliable and encapsulated semiconductor devices are desirable. US 2018 / 0308927 A1 describes structures and methods for isolating semiconductor devices and improving device reliability under harsh environmental conditions. An isolation region is formed by ion implantation in a region of the semiconductor material surrounding a device. The implantation region may extend into singulation lanes of a wafer. A passivation layer is deposited over the implantation region and extends further into the singulation lanes than the isolation region to protect the isolation region from environmental conditions that could adversely affect it.

[0004] Further improvements in the reliability of components, even under harsh environmental conditions, are desirable. SUMMARY

[0005] In one embodiment, a semiconductor device is provided comprising a semiconductor substrate having a first primary surface and a metallization structure arranged on the first primary surface. The metallization structure includes one or more electrically conductive structures, the electrically conductive structure comprising a metallic diffusion barrier and a copper layer arranged on the metallic diffusion barrier. The metallic diffusion barrier has a thickness t, a top surface, a bottom surface, and a side surface extending between a top edge formed between the top surface and the side surface, and a bottom edge formed between the bottom surface and the side surface. The linear distance d between the top edge and the bottom edge is t ≤ d ≤ 1.1 t or t ≤ d ≤ 1.05 t.

[0006] In one embodiment, a method for fabricating an electrically conductive metallization structure is provided. The method comprises: forming a metallic diffusion barrier on a first major surface of a semiconductor substrate; forming a structured copper layer on the metallic diffusion barrier, wherein sections of the metallic diffusion barrier are exposed by the structured copper layer; removing the exposed sections of the metallic diffusion barrier by plasma etching; and forming one or more electrically conductive structures comprising the metallic diffusion barrier and the copper layer.

[0007] Further features and advantages will become apparent to the expert upon reading the following detailed description and examining the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The elements in the drawings are not necessarily shown to scale. Identical reference numerals denote identical or corresponding similar parts. The features of the various embodiments shown can be combined, provided they are not mutually exclusive. Exemplary embodiments are shown in the drawings and are explained in more detail in the following description. Fig. Figure 1 shows a cross-sectional view of a semiconductor device with a metallization structure. Fig. Figure 2 shows a flowchart of a process for producing an electrically conductive structure of a metallization structure. Fig. 3, which the Fig. 3A to 3G includes a method for producing a metallization structure on a semiconductor device. DETAILED DESCRIPTION

[0009] The following detailed description refers to the accompanying drawings, which form an integral part thereof and illustrate exemplary embodiments in which the invention can be implemented. In this context, directional terminology such as "top," "bottom," "front," "back," "leading," "trailing," and the like are used to describe the orientation of the respective figure(s). Since components of the embodiments can be arranged in a multitude of different orientations, the directional terminology serves only for illustration and is in no way to be interpreted restrictively.

[0010] It is understood that other embodiments may be used and that structural or logical modifications may be made without departing from the scope of protection of the present invention. The following detailed description is therefore not to be interpreted restrictively, and the scope of protection of the present invention is defined by the accompanying claims.

[0011] Several exemplary embodiments are described below. Identical structural features in the figures are indicated by identical or similar reference numerals. In the context of this description, "lateral" or "lateral direction" refers to a direction or extent that generally runs parallel to the lateral extent of a semiconductor material or semiconductor substrate. The lateral direction thus generally runs parallel to these surfaces or sides. In contrast, "vertical" or "vertical direction" refers to a direction that generally runs perpendicular to these surfaces or sides and thus to the lateral direction. The vertical direction therefore runs in the thickness direction of the semiconductor material or semiconductor substrate.

[0012] As used in this description, when an element, such as a layer, area, or substrate, is described as being "on" or "extending" onto another element, it may be located directly on or extending directly onto that other element, or there may be intermediate elements. However, when an element is described as being "directly on" or "extending directly onto" another element, there are no intermediate elements.

[0013] As used in this description, when an element is described as "connected" or "coupled" to another element, it may be directly connected or coupled to that other element, or there may be intervening elements. Conversely, when an element is described as "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0014] A depletion-mode device, such as a high-voltage depletion-mode transistor, has a negative threshold voltage, meaning it can conduct current at zero gate voltage. Such devices are normally on. An enhancement-mode device, such as a low-voltage enhancement-mode transistor, has a positive threshold voltage, meaning it cannot conduct current at zero gate voltage and is normally off.

[0015] In some embodiments, the semiconductor device is a component based on group III nitrides, such as a transistor, diode, or bidirectional switch.

[0016] As used herein, the term ‘group III nitride’ refers to a compound semiconductor containing nitrogen (N) and at least one group III element, including aluminum (Al), gallium (Ga), indium (In) and boron (B), and, without limitation, any of its alloys, such as aluminum nitride-gallium nitride (Al x Ga (1-x) N), indium gallium nitride (In y Ga (1-y) N), aluminum indium gallium nitride (Al x In y Ga (1-x-y) N), gallium arsenide phosphide nitride (GaAs a PbN (1-a-b) ) and aluminium indium gallium arsenide phosphide nitride (Al x In y Ga (1-x-y) As a PbN (1-a-b)Aluminium nitride-gallium nitride and AlGaN refer to an alloy with the formula Al x Ga (1-x) N is described, where 0 < x < 1.

[0017] As used herein, various device types and / or doped semiconductor regions may be identified as n-type or p-type; however, this is merely for the sake of simplicity and is not intended to be restrictive. Such a designation may be replaced by the more general description that a region or device is of a “first conductivity type” or a “second, opposite conductivity type,” where the first type may be either n-type or p-type, and the second type is correspondingly p-type or n-type.

[0018] In some embodiments, the semiconductor device is a silicon-based device, such as a nitride-based MOSFET (metal oxide semiconductor field-effect transistor), an IGBT (insulated-gate bipolar transistor), or a BJT (bipolar junction transistor). The transistor device can be a vertical transistor device with a drift path extending perpendicular to the main surfaces of the device.

[0019] The electrodes or terminals of the transistor device are referred to herein as source, drain, and gate. As used herein, these terms also include the functionally equivalent terminals of other transistor device types, such as an insulated-gate bipolar transistor (IGBT).For example, the term "source" includes not only a source of a MOSFET device or a superjunction device, but also an emitter of an IGBT (insulated-gate bipolar transistor) device as well as an emitter of a BJT (bipolar junction transistor) device; the term "drain" includes not only a drain of a MOSFET device or a superjunction device, but also a collector of an IGBT (insulated-gate bipolar transistor) device as well as a collector of a BJT device; and the term "gate" includes not only a gate of a MOSFET device or a superjunction device, but also a gate of an IGBT (insulated-gate bipolar transistor) device as well as a base of a BJT device.

[0020] Fig. Figure 1 shows a cross-sectional view of a semiconductor device 10 as well as an enlarged view of a section of the semiconductor device 10.

[0021] The semiconductor device 10 has a semiconductor substrate 12 which has a first main surface 13 on which a metallization structure 14 is arranged. The metallization structure 14 has one or more electrically conductive structures 15. In Fig. In Figure 1, the electrically conductive structure 15 has the form of a contact pad. The electrically conductive structure 15 can be described as a section, part, or element and forms part of an electrically conductive layer of the metallization structure, in some embodiments the topmost electrically conductive layer. The electrically conductive structure 15 can also be referred to as part of the power metal. The electrically conductive structure 15 is not limited to the form of a contact pad but can have other forms, for example, a metallic interconnect, such as a gate runner, or a metallic interconnect extending between two or more devices formed in the semiconductor substrate 12.

[0022] The contact pad 15 has a metallic diffusion barrier layer 16 and a copper layer 17, which is arranged on the metallic diffusion barrier layer 16 and forms an interface with it. The metallic diffusion barrier 16 has a top surface 20 that is in contact with the copper layer 17, and a bottom surface 23 that is in contact with a section of the metallization structure 14, in this case with the third sublayer 37-3 of the third electrically insulating layer 37. The metallic diffusion barrier 16 has a thickness t and a side surface 21, which can also be referred to as the end surface 21, the side surface 21 extending between an upper edge 19, formed between the top surface 20 and the side surface 21 of the metallic diffusion barrier 16, and a lower edge 22, formed between the bottom surface 23 and the side surface 21 of the metallic diffusion barrier 16.The side surface 21, which extends between the upper edge 19 and the lower edge 22, has a length such that the linear distance d, that is, the smallest distance between the upper edge 19 and the lower edge 22, has the value d.

[0023] The side surface 21 extends substantially perpendicular to the top 20 and bottom 23 of the metallic diffusion barrier 16. Consequently, the length of the side surface 21 and the linear distance d between the top edge 19 and the bottom edge 22 are substantially equal to the thickness t of the metallic diffusion barrier 16. The side surface 21 may not extend exactly perpendicular to the top 20 and bottom 23, but may be slightly inclined. Consequently, the distance d may be up to 10% greater than the thickness t or up to 5% greater than the thickness t, such that t ≤ d ≤ 1.1 t or t ≤ d ≤ 1.05 t.

[0024] In some embodiments, such as in Fig. As shown in Figure 1, the metallic diffusion barrier 16 has a lateral extent that is greater than the lateral extent of the copper layer 17 of the contact pad 15, such that the metallic diffusion barrier 16 projects beyond the copper layer 17 and has an outer peripheral edge section that is exposed and not covered by the copper layer 17 of the contact pad 15. Consequently, the side surfaces 24 of the copper layer 17 of the contact pad 15 extend from the top surface 25 of the copper layer 17 to a position between the top surface 20 of the metallic diffusion barrier 16.

[0025] In some embodiments, such as those which are in Fig. As shown in Figure 1, the side surface 24 of the copper layer 17 forms an angle α greater than 90° with the metallic diffusion barrier layer 16. For example, the angle α can be approximately 105°. In some embodiments, 90° ≤ α ≤ 145°. The angle can be measured between a tangent at the midpoint of the height of the copper layer 17 and the top surface 20 of the metallic diffusion barrier layer 16.

[0026] In some embodiments, the semiconductor device 10 further comprises an upper dielectric layer 26, which is arranged at least on the side surfaces 24 of the contact pad 15 and optionally on a peripheral edge region of the top surface 25, as well as on regions of the metallization structure 14 that are laterally adjacent to the contact pad 15. The dielectric layer 26 is in direct contact with the peripheral region of the top surface 25 and the side surface 24 of the copper layer 17, as well as with the metallic diffusion barrier layer 16.

[0027] The central section of the top surface 25 of the contact pad 15 remains exposed from the dielectric layer 26 and provides a contact area on which, for example, a bond wire 27 or another connector, such as a tape, clip, or solder, can be attached to provide an electrical connection to the semiconductor device(s) located in the semiconductor substrate 12. If the electrically conductive structure 15 provides a metallic connecting conductor, also referred to as a conductor or trace, the entire top surface 25 of the connecting conductor can be covered by the dielectric layer 26. If the electrically conductive structure 15 is a connecting conductor, it is also possible for the top surface to be partially covered or completely exposed.

[0028] The semiconductor substrate 12 can be made of silicon. In some embodiments, the semiconductor substrate 12 can be made of an alternative semiconductor material, such as silicon carbide, or may have one or more group III nitride layers. The metallic diffusion barrier 16 can be made of a WTi alloy or be formed by depositing two or more sublayers, for example, Ti / TiN or TaN / Ti. The metallic diffusion barrier 16 can be deposited, for example, by sputtering. Any metal or alloy or combination of metals and alloys suitable as a diffusion barrier for an upper copper layer 17 can be used. The copper layer 17 may be made entirely of copper or may contain a smaller proportion of one or more alloying elements, for example, Al.

[0029] The upper dielectric layer 26 can be formed from an oxide, for example silicon oxide, or a nitride, for example silicon nitride. The upper dielectric layer 26 can further comprise two or more sublayers. In the illustrated embodiment, the upper dielectric layer 26 comprises three sublayers. A first sublayer 26-1, for example formed from a nitride such as silicon nitride, is in direct contact with the peripheral edge region of the top surface 25 of the copper layer 17, with the side surface 24 of the copper layer 17, with the metallic diffusion barrier 16, and with sections of the metallization structure 14 that laterally surround the contact pad 15 and any other electrically conductive structures 15 present.A second sublayer 26-2, comprising an oxide, for example silicon oxide, is arranged on the first sublayer 26-1, and a third sublayer 26-3, comprising silicon nitride, is formed on the second sublayer 26-2.

[0030] During the intended operating lifetime of the semiconductor device 10, a thermomechanical stress is exerted on the passivation structure, including the dielectric layer 26. Due to the shape of the copper layer 17 and the exposed peripheral edge region of the metallic diffusion barrier layer 16, with its substantially vertical side surface, the upper dielectric layer 26 can be deposited uniformly, continuously, and without interruption onto the electrically conductive structure 15. This arrangement contributes to improving the integrity of the dielectric layer 26. The passivation integrity of the dielectric layer 26 is also improved under harsh environmental conditions.The improved integrity of the dielectric layer 26 can help provide protection against mobile ions, such as chloride ions, that may escape from the environment and / or from the molding compound used to form the package housing the semiconductor device 10. This improves the electrical isolation of the contact pads 15 of the semiconductor device 10 from one another. This is advantageous, for example, for the source and drain contact pads of a transistor device, which are typically connected to ground and a high potential, respectively. In some group III nitride-based HEMTs, the potential difference can be as high as 650 V.

[0031] In some embodiments, the transition between the side surface 24 of the copper layer 17 and the metallic diffusion barrier layer 16 can have a concave shape, which can further help to enable the formation of a uniform and continuous dielectric layer 26 on the contact pad 15, the metallic diffusion barrier layer 16 and the electrically insulating layer provided by the metallization structure 14 in areas adjacent to the contact pad 15, thereby improving the reliability of the semiconductor device 10.

[0032] In the semiconductor substrate 12, one or more semiconductor devices are formed which are electrically connected to the metallization structure 14 and to the contact pad 15 as well as to one or more other electrically conductive structures 15, which are shown in the cross-sectional view of Fig. 1 are not visible. In the Fig. In the embodiment shown in Figure 1, the semiconductor substrate 12 has a multilayer group III nitride-based structure 30 and a group III nitride transistor device 30. The group III nitride transistor device has a source electrode 31, a gate electrode 32, and a drain electrode 33, which are arranged on the first main surface 13 of the semiconductor substrate 12. The gate electrode 32 is arranged laterally between the source electrode 31 and the drain electrode 33.

[0033] In some embodiments, the metallization structure 14 has a multilayer stack comprising a first electrically conductive layer 34 in which the terminals of the transistor device 30 are arranged. Fig. 1 the source electrode 31, the gate electrode 32 and the drain electrode 33 are formed on the first main surface 13 of the semiconductor substrate 12.

[0034] The metallization structure 14 has a first electrically insulating layer 35 that extends over the first main surface 13 and the gate electrode 32, leaving a central section of the source electrode 31 and the drain electrode 33 exposed. The first electrically insulating layer 35 has three sublayers: a lower first sublayer 35-1, formed of silicon nitride; a second sublayer 35-2, formed of silicon oxide and arranged on top of the first sublayer 35-1; and a third sublayer 35-3, formed of silicon nitride and arranged on top of the second sublayer 35-2. The second sublayer 35-2, formed of silicon oxide, has a greater thickness than the first and third sublayers 35-1 and 35-3, which are formed of silicon nitride.

[0035] The metallization structure 14 further comprises a second electrically insulating layer 36 arranged on top of the first electrically insulating layer 35, and a third electrically insulating layer 37 arranged on top of the second electrically insulating layer 36. The second electrically insulating layer 36 has two sublayers: a lower first sublayer 36-1, formed of silicon nitride and in direct contact with the nitride sublayer 35-3, and a second sublayer 36-2, formed of silicon oxide and arranged on top of the first sublayer 36-1. The second sublayer 36-2, formed of silicon oxide, has a greater thickness than the first sublayer 36-1, which is formed of silicon nitride.

[0036] The third electrically insulating layer 37 has three sublayers: a lower sublayer 37-1, formed of silicon nitride and arranged directly on the oxide sublayer 36-2; a second sublayer 37-2, formed of silicon oxide and arranged on the first sublayer 37-1; and a third sublayer 37-3, formed of silicon nitride and arranged on the second sublayer 37-2. The second sublayer 37-2, formed of silicon oxide, has a greater thickness than the first and third sublayers 37-1 and 37-3, which are formed of silicon nitride. The upper surface of the third sublayer 37-3 is in contact with the metallic diffusion barrier 16 of the contact pad 15.

[0037] A first rewiring section 41 is arranged in the second electrically insulating layer 36 and extends further through the first electrically insulating layer 35 to contact the source electrode 31. A second, separate rewiring section 42 is arranged in the second electrically insulating layer 36 and extends through the first electrically insulating layer 35 to the drain electrode 33. The first and second rewiring sections 41, 42 extend through the thickness of the second electrically insulating layer 36.

[0038] In the cross-sectional view of Fig. Figure 1 shows the rewiring structure from the drain electrode 33 to the contact pad 15, such that the contact pad 15 provides a drain pad. A conductive via 43 extends through the third electrically insulating layer 37 to electrically connect the contact pad 15 to the rewiring section 42, which in turn is electrically connected to the drain electrode 33. In some embodiments, an additional metal layer may be formed between the conductive via 43 and the contact 42 to improve adhesion.

[0039] The source and gate contact pads of the transistor device are shown in the cross-sectional view of Fig. 1 not visible, but they show the structure of the in Fig. 1 shown and with reference to Fig. 1 described drain contact pads 15. For example, the source and gate pads can be arranged in a plane in front of or behind the drawing plane.

[0040] The multilayer group III nitride structure of the semiconductor substrate 12 is in Fig. Figure 1 shows the group III nitride structure 50 arranged on a substrate 51. The group III nitride structure 50 has a buffer layer structure 52 on the substrate 51, a GaN channel layer 53 on the buffer layer, and an AlGaN barrier layer 54 on the GaN channel layer 53, which forms a heterojunction structure between them carrying a two-dimensional charge gas, such as a two-dimensional electron gas (2DEG). The transistor device 30 can be a HEMT (high-electron mobility transistor). In this embodiment, the AlGaN barrier layer 54 forms the top surface of the group III nitride structure 50.

[0041] The substrate 51 has an upper or growth surface 55 suitable for supporting the epitaxial growth of one or more group III nitride-based layers. In some embodiments, the substrate 51 is a foreign substrate, that is, formed from a material other than group III nitride materials, and has the upper or growth surface 55 suitable for supporting the epitaxial growth of the one or more group III nitride-based layers. The foreign substrate 51 may, for example, be formed from silicon and may comprise monocrystalline silicon, an epitaxial silicon layer, or sapphire.

[0042] In some embodiments not shown, the group III nitride-based semiconductor structure 50 may further comprise a back barrier layer. The GaN channel layer 53 is formed on the back barrier layer and forms a heterojunction with the back barrier layer, and the barrier layer 54 is formed on the channel layer 53. The back barrier layer has a different band gap than the GaN channel layer 53 and may, for example, comprise AlGaN. The composition of the AlGaN in the back barrier layer may differ from the composition of the AlGaN used for the barrier layer 54.

[0043] A typical transition or buffer structure 52 for a silicon substrate has an AIN start layer on the silicon substrate, which can have a thickness of several hundred nm, followed by an Al x Ga (1-x)An N-layer sequence is used, with each layer having a thickness of several hundred nm. The Al content is reduced from approximately 50–75% to 10–25% before the GaN layer or an AlGaN back-barrier layer, if present, is grown. Alternatively, a superlattice buffer can be used. This also employs an AIN starter layer on the silicon substrate. Depending on the chosen superlattice, a sequence of AIN and Al is grown. x Ga (1-x) N-pairs grown, with the thickness of the AIN layer and the AlxGa (1-x) The N-layer is in the range of 2-25 nm. Depending on the desired breakdown voltage, the superlattice can have between 20 and 100 pairs. Alternatively, an Al x Ga (1-x) The N-layer sequence as described above can be used in combination with the superlattice mentioned above.

[0044] The gate electrode 32 can comprise a p-doped group III nitride layer 44, for example, p-doped gallium nitride, and a gate metal layer 45 arranged on the p-doped group III nitride layer 44. This structure of the gate electrode 32 provides an enhancement-type device that is normally off. In other embodiments, the gate electrode 32 can have a recessed structure to form an enhancement-type device. Alternatively, the group III nitride-based transistor device 30 can be a depletion-type device.

[0045] In alternative embodiments, the semiconductor substrate 12 can also be formed from other semiconductor materials, such as silicon carbide or silicon. In some embodiments, the semiconductor substrate 12 is formed as an epitaxial silicon layer. For example, the semiconductor device 30 can be a silicon-based MOSFET, IGBT, or BJT.

[0046] In the illustrated embodiments, the semiconductor device 10 has a lateral transistor device. However, the semiconductor device 10 can also have other device types, for example, other transistor device types such as vertical transistor devices, a bidirectional switch, a diode, two or more semiconductor devices such as a transistor device and a gate driver device, a power device and a logic device, or two transistor devices electrically connected by the metallization structure to provide a half-bridge circuit, or a bootstrap switch (diode).

[0047] A method for producing an electrically conductive structure of a metallization structure of a semiconductor device is now described with reference to Fig. 2 described. This procedure can be used to perform the in Fig. 1 to produce the contact pad 15 shown.

[0048] Fig. Figure 2 shows a flowchart 100 of a process for producing an electrically conductive structure of a metallization structure.

[0049] In Block 101, a metallic diffusion barrier is formed on a first primary surface of a semiconductor substrate. Further layers of the metallization structure can be positioned between the metallic diffusion barrier and the first primary surface of the semiconductor substrate. In this case, the metallic diffusion barrier is formed on the portion of the metallization structure that has already been fabricated and is located on the first primary surface of the semiconductor substrate. For example, the metallic diffusion barrier can be formed directly on an electrically insulating layer, such as a silicon nitride layer, of the metallization structure. The metallic diffusion barrier can, for example, be WTi, Ti / TiN, or TaN / Ta and can be fabricated by sputtering an alloy or a multilayer stack.

[0050] In block 102, a structured copper layer is formed on the metallic diffusion barrier, with sections of the metallic diffusion barrier exposed by the structured copper layer, i.e., by the sections of the copper layer that are formed on areas of the metallic diffusion barrier. For example, the copper layer can be deposited by electroplating. In one embodiment, a nucleation layer is deposited on the metallic diffusion barrier, for example by sputtering. A structured mask with one or more openings is deposited on the nucleation layer, with the nucleation layer exposed at the base of the one or more openings. The copper layer is then deposited onto the nucleation layer and into the one or more openings of the mask by electroplating. The nucleation layer can be made of copper.

[0051] In block 103, the portions of the metallic diffusion barrier exposed by the structured copper layer are removed by plasma etching. For example, plasma etching can be performed using SF6 and N2. This creates one or more electrically conductive structures that incorporate the metallic diffusion barrier and the copper layer. An electrically conductive structure can provide a contact pad or a rewiring trace. For example, the contact pad can be a source contact pad, a drain contact pad, a gate contact pad, an anode pad, a cathode pad, an input / output pad, an auxiliary pad such as a source sensing pad, a current sensing pad, or a Kelvin pad, or a pull-down gate pad. The rewiring trace can extend between two semiconductor devices, extend to a contact pad, or provide a gate trace.

[0052] Fig. 3 includes the Fig. 3A to 3G and discloses a method for fabricating an electrically conductive structure in the form of a contact pad 15, which is electrically connected to the drain electrode 33 of a lateral group III nitride transistor device 30, in particular a group III nitride HEMT. However, the method can also be used to fabricate other types of electrically conductive structures, for example, other types of contact pads and connecting leads, and is not limited to use with group III nitride-based devices, but can also be used for devices formed in other semiconductor materials, such as silicon or silicon carbide. Fig. Figure 3 shows the metallization structure 14 arranged on the first main surface 13 of the semiconductor substrate 12, with a specific number of electrically insulating and electrically conductive layers. However, the metallization structure 14 is not limited to the structure shown and can be used for metallization structures with fewer or more electrically conductive and electrically insulating layers than shown. The method can be used for the uppermost conductive layer of the metallization structure of a semiconductor device. The uppermost conductive layer can be referred to as the power metal.

[0053] Fig. Figure 3 shows the fabrication of an electrically conductive structure 15 in the uppermost electrically conductive layer of the metallization structure 14, which is arranged on the first main surface 13 of the semiconductor substrate 12. In this embodiment, the partially fabricated metallization structure 14 is built up on the first main surface 13 of the semiconductor device 30 and has first, second, and third electrically insulating layers 35, 36, 37, as described with reference to Fig. 1 described, which are formed on a source electrode 31, a gate electrode 32 and a drain electrode 33 of a first electrically conductive layer, wherein the second electrically conductive layer has a first rewiring section 41, which is arranged in the second electrically insulating layer 36 and extends through the first electrically insulating layer 35 to the source electrode 31, and a second rewiring structure 42, which is arranged in the second electrically insulating layer 36 and extends through the first electrically insulating layer 35 to the drain electrode 33. The top surface of the partially produced metallization structure 14 is provided in this embodiment by the upper nitride layer 37-3.

[0054] With reference to Fig. In step 3A, the process is continued by forming the metallic diffusion barrier layer 16 on the upper nitride sublayer 37-3. In some embodiments, a nucleation layer 63, for example a thin copper layer, is deposited on the metallic diffusion barrier layer 16. A nucleation layer 63 can be used if the copper layer 17 is to be deposited by electroplating. The nucleation layer 63 acts as an electrode in the electrolytic cell.

[0055] In some embodiments, an opening 44 is formed by the third electrically insulating layer 37, exposing a section of the second rewiring section 42. The metallic diffusion barrier layer 16 and the nucleation layer 63 are then deposited, so that the nucleation layer 63 and the metallic diffusion barrier layer are formed at the base of the opening 44 and are in direct contact with the second rewiring section 42. Alternatively, the opening 44 is formed by extending through the copper nucleation layer 63, the metallic diffusion barrier layer 16, and the third electrically insulating layer 37, so that at least a section of the second rewiring section 42 is exposed at the base of the opening 44.

[0056] The copper seed layer 63 can be deposited, for example, by sputtering and can have a thickness of a few nanometers. The metallic diffusion barrier layer 16 can, for example, have a thickness of approximately 20 nm to 2 µm, e.g., approximately 300 nm.

[0057] With reference to Fig. In 3B, a mask 60 is formed on the copper seed layer 63, the mask having at least one opening 61 that exposes the copper seed layer 63 and the through-hole 44. The opening 61 defines the position and lateral dimensions of the electrically conductive structure, for example, the contact pad 15, which is to be formed in the uppermost conductive layer of the metallization structure 14. The mask 60 can, for example, be made of photoresist and be structured by photolithographic methods.

[0058] With reference to Fig. In step 3C, copper 62 is deposited into the opening 61, filling the through-hole 44 to form the conductive via 43 between the contact pad 15 and the contact 42, thereby providing an electrically conductive rewiring structure for the drain electrode 33. In some embodiments, the copper 62 is deposited by electroplating onto the area of ​​the copper seed layer 63 exposed in the opening 61. The copper seed layer 63 extends under the mask 60 over the entire surface of the semiconductor device 10 and therefore serves as the electrode of the electrolytic cell for the electroplating process.

[0059] With reference to Fig. The mask 60 is then removed. At this stage, the copper layer 17 can have its final or near-final dimensions of the contact pad 15 and is positioned on the copper seed layer 63, which extends over the entire surface of the metallization structure 14. The area of ​​the copper seed layer 63 that was previously covered by the mask 60 is now exposed and not covered by the copper layer 17. The metallic diffusion barrier layer 16 also extends over the entire surface of the metallization structure 14.

[0060] With reference to Fig. 3E, and the enlarged representation of the side surface 24 of the contact pad 15, shows that the exposed area of ​​the copper seed layer 63, which was previously covered by the mask 60, is removed, for example, by wet etching. The wet etching process selectively removes the copper seed layer 63 from the material of the metallic diffusion barrier layer 16. The seed layer 63 remains under the copper layer 17 and forms part of the contact pad 15. An example of a suitable wet etching agent is H₂O₂ (8.0%). The area of ​​the metallic diffusion barrier layer 16, which was also located under the mask 60 and is positioned laterally adjacent to the contact pad 15, is exposed. The exposed area of ​​the metallic diffusion barrier layer 16 is then removed by plasma etching, as shown in Fig. 3E is schematically represented by arrows 64. The plasma etching process can also remove a top portion of the nitride sublayer 37-3. A remaining portion of this nitride sublayer 37-3 continues to cover the underlying oxide sublayer 37-2. After plasma etching, the lateral extents of the metallic diffusion barrier layer 16 and the copper layer 17 of the contact pad 15 are essentially equal. Plasma etching conditions can be employed using SF6 and N2 gases. The contact pad 15 can, for example, have a thickness of 50 nm to 20 µm, or 50 nm to 10 µm, or 50 nm to 7 µm.

[0061] During plasma etching of the exposed areas of the metallic diffusion barrier 16, the sections of the structured, electroplated copper layer 17 act as a mask. The use of plasma etching to remove the exposed areas of the metallic diffusion barrier 16 allows the side surface 21 of the covered or masked section of the metallic diffusion barrier 16, which remains beneath the copper layer 17, to have a substantially vertical shape and to be substantially perpendicular to both the top 20 and the bottom 23 of the metallic diffusion barrier 16, as can be seen more clearly in the enlarged view.Since the side surface 21 may not extend exactly perpendicular to the top 20 and the bottom 23 of the metallic diffusion barrier layer 16, deviations from an exactly vertical line are included, so that the linear distance d between the upper edge 19 and the lower edge 22 is at most 10% or at most 5% greater than the thickness t of the metallic diffusion barrier layer 16, i.e. t ≤ d ≤ 1.1 t or t ≤ d ≤ 1.05 t.

[0062] Fig. Figure 3F shows an optional process in which a further wet etching process is performed. In this optional process, the top surface 25 and the side surfaces 24 of the copper layer 17 of the contact pad 15 are etched, as shown in Fig. 3F is schematically represented by arrows 65. A selective wet etching process can be used. As is more easily seen in the enlarged view, the copper is selectively removed by wet etching, so that a peripheral edge section of the metallic diffusion barrier layer 16 is exposed and projects laterally beyond the maximum lateral extent of the copper layer 17. After the optional further wet etching process, the lateral extent of the metallic diffusion barrier layer of the contact pad 15 is greater than the lateral extent of the copper layer 17 of the contact pad 15.

[0063] The bottom surface of the copper layer 17 can be laterally larger than the top surface 25. The side surface 21 of the metallic diffusion barrier layer 16 is positioned laterally outside the maximum lateral extent of the copper layer 17 of the contact pad 15. The transition between the thicker and thinner sections of the top nitride sublayer 37-3 is also positioned laterally outside the maximum lateral extent of the copper layer 17 and is essentially coplanar with the side surface 21 of the metallic diffusion barrier layer 16. Depending on the etching conditions, the additional etching process can provide a concave transition between the copper layer 17 and the protruding peripheral edge section of the metallic diffusion barrier layer 16, so that the angle formed at the interface between the copper layer 17 and the metallic diffusion barrier layer 16 is smaller.The angle α formed between the midpoint of the height of the side surface 24 of the copper layer 17 and the metallic diffusion barrier layer 16 can be greater than 90°, for example 105°.

[0064] With reference to Fig. 3G, a dielectric layer 26 is subsequently deposited at least over the side surfaces 24 and the top surface of the semiconductor substrate 12, such that the protruding portion of the metallic diffusion barrier 16, which is not covered by the copper layer 17, is covered by the dielectric layer 26. The dielectric layer 26 can cover the entire metallization structure 14, except for those areas of the one or more copper structures 15 that are intended for an external contact 27, for example, for solder joints, bond wires, metallic strips, or clips. In some embodiments, the dielectric layer 26 has two or more sublayers, for example, three sublayers, such as a stack of silicon nitride, silicon oxide, and silicon nitride.

[0065] Typically, two or more electrically conductive structures 15 are formed. These electrically conductive structures 15 can be physically separated from each other and electrically isolated from each other, for example, a source pad, a drain pad, and a gate pad of the transistor device. In some embodiments, two or more electrically conductive structures can be formed integrally, for example, a gate pad and a connecting line.

[0066] While the drawings depict an electrically conductive structure in the form of the drain contact pad 15, the semiconductor device 10 further comprises at least one additional structure, for example, at least one source contact pad and at least one gate contact pad, as well as optionally one or more auxiliary pads and one or more connecting lines, which can be manufactured using the same process steps as the drain contact pad 15 shown in the drawings. The source contact pad and the gate contact pad, as well as any further auxiliary pads, can have the same structure as the contact pad 15 with the copper layer 17 and the metallic diffusion barrier 16 according to the Fig. 1 and Fig. 3.

[0067] The passivation integrity of the dielectric layer 26 deposited onto the contact pad 15, comprising the plasma-etched metallic diffusion barrier 16 and the copper layer 17, is improved, even under harsh environmental conditions. Due to the shape of the copper layer and the exposed peripheral edge region of the metallic diffusion barrier 16 with its essentially vertical side surface, the upper dielectric layer 26 can be deposited uniformly, continuously, and without interruption onto the electrically conductive structure 15. This contributes to improving the integrity of the dielectric layer 26 during operation of the semiconductor device 30 when thermomechanical stress is exerted on the passivation structure comprising the dielectric layer 26.The improved integrity of the dielectric layer 26 can help provide protection against mobile ions, such as chloride ions, that may escape from the environment and / or from the molding compound used to form the package housing in which the semiconductor device 10 is located. This improves the electrical isolation of the contact pads 15 of the semiconductor device 10 from one another, for example, the source and drain contact pads of a transistor device 10, which are typically connected to ground potential and a high potential, for example, 650 V in the case of some group III nitride-based HEMTs, respectively.

[0068] Although the present revelation is not limited to this, the following numbered examples illustrate one or more aspects of the revelation. Examples 1. Semiconductor device comprising: a semiconductor substrate, having a first principal surface; a metallization structure arranged on the first main surface, wherein the metallization structure has one or more electrically conductive structures, wherein the electrically conductive structure comprises a metallic diffusion barrier layer and a copper layer arranged on the metallic diffusion barrier layer, wherein the metallic diffusion barrier layer has a thickness t and a side surface extending between an upper edge formed between a top surface and the side surface, and a lower edge formed between a bottom surface and the side surface, wherein the linear distance d between the upper edge and the lower edge is t ≤ d ≤ 1.1 t or t ≤ d ≤ 1.05 t. 2. Semiconductor device according to Example 1, wherein the side surface extends substantially perpendicular to the first main surface. 3. Semiconductor device according to Example 1 or Example 2, wherein the metallic diffusion barrier layer has a top and an opposite bottom and the side surface extends substantially perpendicular to the top and bottom of the metallic diffusion barrier layer. 4. Semiconductor device according to one of Examples 1 to 3, wherein the metallic diffusion barrier layer has a peripheral edge section that protrudes from the copper layer and is not covered by the copper layer. 5. Semiconductor device according to one of Examples 1 to 3, wherein the copper layer has a top surface and side surfaces extending from the top surface to the metallic diffusion barrier layer. 6. Semiconductor device according to Example 5, wherein the side surface of the copper layer forms an angle greater than 90° with the top surface of the metallic diffusion barrier layer. 7. Semiconductor device according to one of examples 1 to 6, wherein a transition between the side surface of the copper layer and the metallic diffusion barrier layer has a concave shape. 8. Semiconductor device according to one of Examples 1 to 7, wherein the metallic diffusion barrier layer comprises one of the group consisting of WTi, Ti / TiN and TaN / Ta. 9. Semiconductor device according to one of Examples 1 to 8, further comprising an upper dielectric layer arranged over a peripheral edge section of the top surface of the copper layer and the side surfaces of the copper layer. 10. Semiconductor device according to Example 9, wherein the upper dielectric layer has two or more sublayers. 11. Semiconductor device according to Example 10, wherein the upper dielectric layer comprises a first sublayer having a nitride, a second sublayer having an oxide on the first sublayer, and a third sublayer having a nitride on the second sublayer. 12. Semiconductor device according to one of Examples 1 to 11, wherein the one or more electrically conductive structures comprise at least one of the group consisting of a contact pad and a rewiring line. 13. Semiconductor device according to Example 12, wherein the contact pad is a source contact pad, a drain contact pad, a gate contact pad, an anode pad, a cathode pad, an input / output pad, an auxiliary pad such as a source sensing pad, a current sensing pad or a Kelvin pad, or a pulldown gate pad and / or wherein the rewiring line extends between two semiconductor devices or extends to a contact pad. 14. Semiconductor device according to one of Examples 1 to 13, wherein the semiconductor substrate has a semiconductor device structure. 15. Semiconductor device according to Example 14, wherein the semiconductor device structure is a transistor structure or a diode structure or a logic element or a gate driver circuit or a bootstrap switch (diode). 16. Semiconductor device according to any of Examples 1 to 15, wherein the semiconductor substrate comprises Si or SiC or one or more Group III nitrides. 17. Semiconductor device according to one of Examples 1 to 16, wherein the metallization structure further comprises one or more additional conductive layers and one or more dielectric layers, and the one or more electrically conductive structures are arranged in an uppermost additional conductive layer. 18. Method for producing an electrically conductive structure of a metallization structure, comprising the method: Forming a metallic diffusion barrier layer on a first main surface of a semiconductor substrate; Forming a structured copper layer on the metallic diffusion barrier, with sections of the metallic diffusion barrier exposed by the structured copper layer; Removal of the exposed sections of the metallic diffusion barrier layer by plasma etching, and Forming one or more electrically conductive structures, comprising the metallic diffusion barrier layer and the copper layer. 19. Method according to Example 18, further comprising: Deposition of a copper seed layer onto the metallic diffusion barrier layer, and then Deposition of the copper layer onto the copper seed layer by means of electroplating. 20. Method according to Example 18 or Example 19, wherein the deposition of the copper layer is by means of electroplating: Forming a mask on the copper seed layer, wherein the mask has at least one opening that exposes the copper seed layer; Deposition of the copper layer into at least one opening and onto the exposed copper seed layer by means of electroplating. 21. A method according to one of Examples 18 to 20, further comprising: After forming the structured copper layer, remove the sections of the copper seed layer exposed by the structured copper layer using wet casting, and then Removal of the exposed metallic diffusion barrier layer by plasma etching. 22. A method according to one of Examples 18 to 21, further comprising: Performing a further etching process and removing a section of the top and side surfaces of the electrically conductive structure, and exposing a peripheral edge area of ​​the metallic diffusion barrier layer from the copper layer of the electrically conductive structure. 23. Method according to Example 22, wherein after the further etching process the side surface of the copper layer of the electrically conductive structure forms an angle greater than 90° with the top surface of the metallic diffusion barrier layer. 24. Method according to Example 22 or Example 23, wherein after the further etching process a transition between the copper layer and the metallic diffusion barrier layer of the electrically conductive structure has a concave shape. 25. Method according to any of Examples 18 to 24, wherein the metallization structure further comprises one or more additional conductive layers and one or more dielectric layers, and the one or more electrically conductive structures are arranged in an uppermost additional conductive layer. 26. A method according to any of Examples 18 to 25, wherein after plasma etching the metallic diffusion barrier layer has a thickness t and a side surface extending between an upper edge formed between a top surface and the side surface, and a lower edge formed between a bottom surface and the side surface, wherein the linear distance d between the upper edge and the lower edge is t ≤ d ≤ 1.1 t or t ≤ d ≤ 1.05 t. 27. Method according to Example 26, wherein the side surface of the metallic diffusion barrier layer is substantially perpendicular to the first main surface. 28. Method according to any one of Examples 22 to 27, wherein the metallic diffusion barrier layer has a peripheral edge section that protrudes from the copper layer and is not covered by the copper layer. 29. A method according to any of Examples 18 to 28, wherein after plasma etching the copper layer has a top surface and side surfaces extending from the top surface to the metallic diffusion barrier layer. 30. Method according to one of Examples 18 to 29, further comprising forming an upper dielectric layer over a peripheral edge section of the top surface of the copper layer and the side surfaces of the copper layer. 31. Method according to Example 30, wherein the upper dielectric layer has two or more sublayers. 32. Method according to Example 30 or Example 31, wherein the formation of the upper dielectric layer comprises the formation of a first sublayer comprising a nitride, the formation of a second sublayer comprising an oxide on the first sublayer, and the formation of a third sublayer comprising a nitride on the second sublayer. 33. Method according to any one of Examples 18 to 32, wherein the metallic diffusion barrier layer comprises one of the group consisting of WTi, Ti / TiN and TaN / Ta. 34. Method according to any of Examples 18 to 33, wherein the one or more electrically conductive structures comprise at least one from the group consisting of a contact pad and a rewiring line. 35. Method according to Example 34, wherein the contact pad is a source contact pad, a drain contact pad, a gate contact pad, an anode pad, a cathode pad, an input / output pad, an auxiliary pad such as a source sensing pad, a current sensing pad or a Kelvin pad. 36. Method according to one of Examples 18 to 35, wherein the substrate has a semiconductor device structure. 37. Method according to Example 36, wherein the semiconductor device structure is a transistor structure or a diode structure or a logic element or a gate driver circuit.

[0069] Spatially relative terms such as "under," "below," "lower," "above," "above," and the like are used to simplify the description and to explain the positioning of one element relative to another. These terms are to be understood as encompassing not only the orientation shown in the figures but also other orientations of the device. Furthermore, terms such as "first," "second," and the like are used to describe different elements, areas, sections, and the like, and are also not to be interpreted as restrictive. The same terms refer to the same elements throughout the description.

[0070] As used herein, the terms "with," "containing," "comprising," "possessing," and the like are open terms that indicate the presence of specified elements or features but do not exclude additional elements or features. The articles "a," "an," and "the" are to be understood as including both the plural and the singular unless the context clearly indicates otherwise. It is understood that the features of the various embodiments described herein may be combined unless expressly stated otherwise.

[0071] Although certain embodiments have been presented and described herein, it is apparent to those skilled in the art that a multitude of alternative and / or equivalent embodiments can be used instead of the specific embodiments presented and described without departing from the scope of protection of the present invention. The present application is intended to encompass all adaptations or modifications of the specific embodiments described herein. Accordingly, it is intended that the present invention is limited only by the claims and their equivalents. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 2018 / 0308927 A1

[0003]

Claims

Semiconductor device comprising: a semiconductor substrate, comprising a first main surface; a metallization structure arranged on the first main surface, wherein the metallization structure comprises one or more electrically conductive structures, wherein the one or more electrically conductive structures comprise a metallic diffusion barrier and a copper layer arranged on the metallic diffusion barrier, wherein the metallic diffusion barrier has a thickness t and a side surface extending between a top edge formed between a top surface and the side surface, and a bottom edge formed between a bottom surface and the side surface, wherein the linear distance d between the top edge and the bottom edge is t ≤ d ≤ 1.1 t or t ≤ d ≤ 1.05 t. Semiconductor device according to claim 1, wherein the metallic diffusion barrier layer has a peripheral edge section that protrudes from the copper layer and is not covered by the copper layer. Semiconductor device according to claim 1 or claim 2, wherein the one or more electrically conductive structures comprise at least one of the group consisting of a contact pad and a rewiring line. Semiconductor device according to one of claims 1 to 3, wherein the semiconductor substrate comprises at least one semiconductor device structure comprising a transistor structure or a diode structure or a logic element or a gate driver circuit or a bootstrap switch. Semiconductor device according to any one of claims 1 to 4, wherein the semiconductor substrate comprises Si or SiC or one or more group III nitrides. A method for producing an electrically conductive metallization structure, comprising: forming a metallic diffusion barrier layer on a first main surface of a semiconductor substrate; forming a structured copper layer on the metallic diffusion barrier layer, wherein sections of the metallic diffusion barrier layer are exposed by the structured copper layer; removing the exposed sections of the metallic diffusion barrier layer by plasma etching; and forming one or more electrically conductive structures comprising the metallic diffusion barrier layer and the copper layer. Method according to claim 6, further comprising: depositing a copper seed layer onto the metallic diffusion barrier layer, and then depositing the copper layer onto the copper seed layer by means of electroplating. The method of claim 7, wherein the deposition of the copper layer by electroplating comprises: forming a mask on the copper seed layer, wherein the mask has at least one opening that exposes the copper seed layer; depositing the copper layer into the at least one opening and onto the exposed copper seed layer by electroplating. Method according to any one of claims 6 to 8, further comprising: after forming the structured copper layer, removing sections of the copper seed layer exposed by the structured copper layer by means of wet etching, and then removing the exposed metallic diffusion barrier layer by means of plasma etching. Method according to one of claims 6 to 9, further comprising: performing a further etching process and removing a section of the top and side surfaces of the electrically conductive structure, and exposing a peripheral edge region of the metallic diffusion barrier layer from the copper layer of the electrically conductive structure. Method according to claim 10, wherein after the further etching process the side surface of the copper layer of the electrically conductive structure forms an angle greater than 90° with the top surface of the metallic diffusion barrier layer. Method according to any one of claims 6 to 11, wherein after plasma etching the metallic diffusion barrier layer has a thickness t and a side surface extending between an upper edge formed between a top surface and the side surface, and a lower edge formed between a bottom surface and the side surface, wherein the linear distance d between the upper edge and the lower edge is t ≤ d ≤ 1.1 t or t ≤ d ≤ 1.05 t. Method according to any one of claims 6 to 12, wherein after plasma etching the copper layer has a top surface and side surfaces extending from the top surface to the metallic diffusion barrier layer. Method according to one of claims 6 to 13, further comprising forming an upper dielectric layer arranged over a peripheral edge section of the top surface of the copper layer and the side surfaces of the copper layer of one or more electrically conductive structures. The method of claim 14, wherein the formation of the upper dielectric layer comprises forming a first sublayer comprising a nitride, forming a second sublayer comprising an oxide, on the first sublayer, and forming a third sublayer comprising a nitride, on the second sublayer.

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