Susceptor, apparatus and method for epitaxial growth of silicon wafers, epitaxial silicon wafer

Abstract

This disclosure provides a susceptor, apparatus and method for epitaxial growth of silicon wafers and an epitaxial silicon wafer, and belongs to the semiconductor manufacturing technology field. The susceptor for epitaxial growth of silicon wafers includes a disc-shaped mounting portion for mounting the silicon wafer and an annular peripheral portion extending radially outward from the disc-shaped mounting portion, wherein the annular peripheral portion has a plurality of spaced groove regions, the groove regions are uniformly distributed along the circumferential direction of the annular peripheral portion, the groove regions exhibit a fan-ring shape, and each of the groove regions has a plurality of pits arranged in an array.

Description

Technical Field

[0001] (Cross-reference to Related Applications) This disclosure claims priority based on Chinese Patent Application No. 202410508018.6 filed in China on April 25, 2024, and all of its contents are incorporated herein by reference.

[0002] This disclosure relates to the field of semiconductor manufacturing technology, and particularly to susceptors, apparatuses, and methods for epitaxial growth of silicon wafers, and epitaxial silicon wafers.

Background Art

[0003] Growing a single crystal thin film on a single crystal polished wafer is called an epitaxial silicon wafer. Compared with a polished wafer, an epitaxial silicon wafer has characteristics of fewer surface defects, excellent crystallinity, and controllable resistivity, and is widely used in highly integrated integrated circuit (IC) elements and metal-oxide-semiconductor field-effect transistor (MOS) processes. Generally, epitaxial growth is performed on a wafer by chemical vapor deposition. First, the wafer is transported to a susceptor for placing the wafer in the reaction chamber. Then, the temperature of the reaction chamber is raised. After reaching a predetermined temperature, a cleaning gas (such as hydrogen gas) is introduced to remove the natural oxide film on the wafer surface. Further, a silicon source gas is introduced to continuously and uniformly grow an epitaxial layer on the wafer surface.

[0004] The formation of an epitaxial layer on a wafer is mainly divided into two stages. In the first stage, the reaction chamber is self-cleaned by introducing hydrogen gas (H2) and etching gas (HCl). In the second stage, the epitaxial layer is grown by introducing hydrogen gas (H2), silicon raw material gas (SiHCl3 / H2), and doping gas (B2H6 / H2). In the first stage, the hydrogen gas acts as the main gas flow, transporting the etching gas (HCl) and reacting with by-products deposited in the reaction chamber, thereby cleaning the reaction chamber. In the second stage, the hydrogen gas reacts with the native oxide film on the wafer surface to obtain a clean epitaxial substrate. During the deposition stage, the hydrogen gas acts as the main gas flow, transporting the film-forming gas and doping gas, and growing an epitaxial layer with controllable resistivity on the wafer surface.

[0005] With the continuous advancement of semiconductor manufacturing process technology, the demands on the flatness of epitaxial silicon wafers are becoming increasingly stringent. Poorly flat epitaxial silicon wafers can cause defocusing, which can further affect the chemical mechanical polishing (CMP) process and impact product yield. When local flatness is poor on an epitaxial silicon wafer, over-polishing or under-polishing can occur. Over-polishing can cause early breakdown of the device, while under-polishing can cause errors in the device contacts. [Overview of the project] [Problems that the invention aims to solve]

[0006] To solve the above technical problems, this disclosure provides a susceptor, apparatus and method for epitaxial growth of silicon wafers, and an epitaxial silicon wafer, which can improve the flatness of the epitaxial silicon wafer. [Means for solving the problem]

[0007] To achieve the above objectives, the technical means employed by the embodiments of this disclosure are as follows:

[0008] Embodiments of this disclosure provide a susceptor for epitaxial growth of silicon wafers, the susceptor being, A disc-shaped mounting section for mounting the aforementioned silicon wafer, It includes an annular peripheral portion extending radially outward from the disc-shaped mounting portion, The annular periphery has a plurality of groove regions arranged at intervals, the groove regions are uniformly distributed along the circumferential direction of the annular periphery, the groove regions form a fan-shaped annulus, and each of the groove regions has a plurality of pits arranged in an array.

[0009] In some embodiments, the central angle corresponding to the sector in which the groove region exists is between 40° and 60°.

[0010] In some embodiments, four groove regions are uniformly distributed along the circumferential direction of the annular periphery.

[0011] In some embodiments, the depth of the pit is 0.1 millimeters to 1 millimeter, and / or The area of ​​the aforementioned pit is between 0.1 square millimeters and 0.4 square millimeters.

[0012] Embodiments of this disclosure further provide an apparatus for epitaxial growth of silicon wafers, the apparatus, The susceptor mentioned above, A reaction chamber for housing the susceptor, wherein the susceptor divides the reaction chamber into an upper reaction chamber and a lower reaction chamber, and the silicon wafer is placed in the upper reaction chamber; An air inlet for transporting silicon source gas into the upper reaction chamber to grow an epitaxial layer on the silicon wafer, It includes an exhaust port for discharging reaction exhaust gas generated by epitaxial growth from the reaction chamber.

[0013] Embodiments of this disclosure further provide a method for epitaxial growth of silicon wafers applicable to the above apparatus, the method being: The silicon wafer is the silicon wafer <100> The steps include: placing the crystal on the susceptor such that its crystal orientation aligns with the central axis of the groove region of the annular periphery; The steps include transporting silicon raw material gas through the air inlet into the upper reaction chamber and growing an epitaxial layer on the silicon wafer, The steps include: the flow rate of the silicon source gas flowing through the groove region becoming greater than the flow rate of the silicon source gas flowing through other regions of the annular periphery, thereby resulting in a uniform thickness of the epitaxial layer grown on the silicon wafer; The process includes the step of discharging the reaction exhaust gas generated by epitaxial growth from the reaction chamber through the exhaust port.

[0014] In some embodiments, the silicon wafer is the silicon wafer <100> The step of placing the crystal on the susceptor such that the crystal orientation aligns with the central axis of the groove region of the annular periphery is: The steps include obtaining the crystal orientation corresponding to the V-shaped groove in the silicon wafer, The V-shaped groove is of the silicon wafer <110> The process includes, if the silicon wafer is in the crystal orientation, positioning it on the susceptor such that the angle between the central axis of the V-shaped groove and the central axis of the groove region is 45°.

[0015] In some embodiments, the silicon wafer is the silicon wafer <100> The step of placing the crystal on the susceptor such that the crystal orientation aligns with the central axis of the groove region of the annular periphery is: The steps include obtaining the crystal orientation corresponding to the V-shaped groove in the silicon wafer, The V-shaped groove is of the silicon wafer <100> The process includes, if the silicon wafer is in the crystal orientation, positioning it on the susceptor such that the angle between the central axis of the V-shaped groove and the central axis of the groove region is 0°.

[0016] Embodiments of this disclosure further provide epitaxial silicon wafers fabricated using the above-described method for epitaxial growth of silicon wafers. When the epitaxial layer thickness of the epitaxial silicon wafer is 6 micrometers or less, the maximum value of the edge-site front-reference least squares range ESFQR of the epitaxial silicon wafer is 57.1 nanometers or less.

[0017] In some embodiments, when the epitaxial layer thickness of the epitaxial silicon wafer is 3 to 4 micrometers, the range of the ESFQR value of the epitaxial silicon wafer is 23 nanometers to 33.9 nanometers, and when the epitaxial layer thickness of the epitaxial silicon wafer is 4 to 6 micrometers, the range of the ESFQR value of the epitaxial silicon wafer is 37.4 nanometers to 57.1 nanometers. [Effects of the Invention]

[0018] The beneficial effects of this disclosure are as follows: In this embodiment, a groove region is formed on the annular periphery, multiple pits are installed in the groove region, and epitaxial growth is performed. When introducing silicon raw material gas into the reaction chamber, the installation of pits allows the flow rate of silicon raw material gas flowing through the groove region to be greater than the flow rate of silicon raw material gas flowing through other regions of the annular periphery. The growth rate differs depending on the crystal direction of the silicon wafer. When performing epitaxial growth, the silicon wafer is rotated at different angles according to the crystal direction corresponding to the V-shaped groove of the silicon wafer. By aligning the crystal direction of the silicon wafer with the position of the groove region and matching the crystal direction with the slow epitaxial layer growth rate with the groove region, the epitaxial layer growth rate in that crystal direction can be improved. This compensates for the epitaxial layer growth rates in different crystal directions of the silicon wafer and improves the flatness of the epitaxial silicon wafer. [Brief explanation of the drawing]

[0019] [Figure 1] It is a schematic diagram of the gas flow in an epitaxial reaction chamber. [Figure 2] It is a schematic diagram of the crystal direction of a silicon wafer. [Figure 3] It is a schematic diagram of the crystal direction of a silicon wafer. [Figure 4] It is a schematic diagram of the edge flatness of an epitaxial silicon wafer fabricated by the prior art. [Figure 5] It is a schematic diagram of the fabrication flow of an epitaxial silicon wafer according to the prior art. [Figure 6] It is a schematic diagram of a susceptor for epitaxial growth of a silicon wafer in the prior art. [Figure 7] It is a schematic diagram of a susceptor for epitaxial growth of a silicon wafer according to an embodiment of the present disclosure. [Figure 8] It is a schematic diagram of a susceptor for epitaxial growth of a silicon wafer according to an embodiment of the present disclosure. [Figure 9] It is a schematic diagram of the fabrication flow of an epitaxial silicon wafer according to an embodiment of the present disclosure. [Figure 10] It is a schematic diagram showing a silicon wafer with V-grooves in the <100> crystal direction placed on a susceptor according to an embodiment of the present disclosure. [Figure 11] It is a schematic diagram showing a silicon wafer with V-grooves in the <110> crystal direction placed on a susceptor according to an embodiment of the present disclosure. [Figure 12] It is a schematic diagram showing a silicon wafer with V-grooves in the <110> crystal direction placed on a susceptor according to an embodiment of the present disclosure. [Figure 13] It is a schematic diagram of the edge flatness of an epitaxial silicon wafer fabricated according to an embodiment of the present disclosure.

Embodiments for Carrying Out the Invention

[0020] To clarify the purpose, technical means and advantages of the embodiments of this disclosure, the technical means of the embodiments of this disclosure will be clearly and completely described below with reference to the drawings of the embodiments of this disclosure. The embodiments described are only some, and not all, embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure described are within the scope of this disclosure.

[0021] The flatness of an epitaxial silicon wafer typically includes flatness indices such as the Edge Site Frontsurface referenced least squares range (ESFQR), Site Frontsurface referenced least squares range (SFQR), and Global Backsurface-referenced Ideal plane range (GBIR). Here, ESFQR is used to evaluate the edge flatness of an epitaxial silicon wafer.

[0022] Figure 1 shows a schematic diagram of the gas flow in the epitaxial reaction chamber, with arrows indicating the direction of gas flow. After the silicon wafer is transported onto the susceptor 2 in the epitaxial reaction chamber, the susceptor 2 places the silicon wafer on it and rotates uniformly at a constant speed. After the reaction chamber is heated to a predetermined temperature, a clean gas (H2) is introduced and reaches the silicon wafer surface via the edges of the preheating ring 1 and susceptor 2 to remove the native oxide film on the silicon wafer surface. Subsequently, the main gas flow carries the deposition gas and doping gas, reaching the silicon wafer surface via the edges of the preheating ring 1 and susceptor 2 to grow an epitaxial layer with controllable resistivity.

[0023] Figures 2 and 3 show schematic diagrams of the crystal orientation of a silicon wafer. As shown in Figure 2, the 3 o'clock direction of the silicon wafer is the radial direction of 0° / 360°, and <110> In the case of the crystal direction, the radial directions rotated 90°, 180°, and 270° clockwise relative to the radial direction of 0° / 360° are also the radial directions of the silicon wafer. <110> The crystal orientation is the direction of the silicon wafer, and the radial directions rotated clockwise by 45°, 135°, 225°, and 315° relative to the radial direction of 0° / 360° are the directions of the silicon wafer. <100> This corresponds to the crystal direction. In other words, for this silicon wafer, there are four <110> The crystal orientation corresponds to four radial directions distributed at 90° intervals along the circumferential direction of the silicon wafer, and the four <100> Similarly, the crystal orientation corresponds to four radial directions distributed at 90° intervals along the circumferential direction of the silicon wafer, and adjacent <110> Crystal orientation and <100> The crystal orientations are spaced at 45° intervals along the circumferential direction of the silicon wafer. As shown in Figure 3, V-shaped grooves 4 are installed on the silicon wafer 3 to position the silicon wafer. The V-shaped grooves 4 are located on the silicon wafer. <100> It may correspond to the crystal direction, and the silicon wafer <110> It may also correspond to the crystal orientation.

[0024] Figure 4 shows a schematic diagram of the edge flatness of an epitaxial silicon wafer fabricated using conventional technology. Figure 4 shows the ESFQR results at a position 1 mm from the radial edge of a 300 mm diameter silicon wafer when using a conventional susceptor for epitaxial growth of silicon wafers. In Figure 4, the horizontal axis represents the radial angle of the silicon wafer, and the vertical axis represents the ESFQR value (in nanometers) of the silicon wafer at the corresponding angular position. As shown in Figure 4, the radial directions of 0° / 360°, 90°, 180°, and 270° are... <100> Corresponding to the crystal orientation region, the radial directions of 45°, 135°, 225°, and 315° are for silicon wafers. <110> This corresponds to the crystal orientation region. Edge flatness is good at radial positions of 0° / 360°, 90°, 180°, and 270°, but poor at radial positions of 45°, 135°, 225°, and 315°. (Epitaxial silicon wafer) <100> Crystal orientation and <110> The quality of edge flatness varies greatly depending on the crystal orientation. This is because the physical properties of a single-crystal silicon wafer differ depending on the crystal orientation, and the growth rate of the epitaxial layer differs in different crystal orientations of the silicon wafer. <110> The growth rate of the epitaxial layer in the crystal direction is determined by the silicon wafer. <100> This is greater than the growth rate of the epitaxial layer in the crystal direction.

[0025] To address the above issues, this disclosure provides a susceptor, apparatus, and method for epitaxial growth of silicon wafers, and an epitaxial silicon wafer, which can improve the flatness of the epitaxial silicon wafer.

[0026] Embodiments of this disclosure provide a susceptor for epitaxial growth of silicon wafers, the susceptor being, A disc-shaped mounting section for mounting the aforementioned silicon wafer, It includes an annular peripheral portion extending radially outward from the disc-shaped mounting portion, The annular periphery has a plurality of groove regions arranged at intervals, the groove regions are uniformly distributed along the circumferential direction of the annular periphery, the groove regions form a fan-shaped annulus, and each of the groove regions has a plurality of pits arranged in an array.

[0027] In this embodiment, a groove region is formed on the annular periphery, multiple pits are installed in the groove region, and epitaxial growth is performed. When introducing silicon raw material gas into the reaction chamber, the installation of pits allows the flow rate of silicon raw material gas flowing through the groove region to be greater than the flow rate of silicon raw material gas flowing through other regions of the annular periphery. The growth rate differs depending on the crystal direction of the silicon wafer. When performing epitaxial growth, the silicon wafer is rotated at different angles according to the crystal direction corresponding to the V-shaped groove of the silicon wafer. By aligning the crystal direction of the silicon wafer with the position of the groove region and matching the crystal direction with the slow epitaxial layer growth rate with the groove region, the epitaxial layer growth rate in that crystal direction can be improved. This compensates for the epitaxial layer growth rates in different crystal directions of the silicon wafer and improves the flatness of the epitaxial silicon wafer.

[0028] Figure 5 shows a schematic diagram of the manufacturing flow of an epitaxial silicon wafer using conventional technology. Figure 6 shows a schematic diagram of a susceptor for epitaxial growth of a silicon wafer using conventional technology. As shown in Figure 6, the conventional susceptor 2 includes a disc-shaped mounting portion 21 for mounting the silicon wafer and an annular peripheral portion 22 extending radially outward from the disc-shaped mounting portion 21. As shown in Figure 5, when manufacturing an epitaxial silicon wafer, first a single-crystal silicon ingot is manufactured, the single-crystal silicon ingot is cut into segments, a V-shaped groove is processed in a specific crystal direction of the ingot segment according to product requirements, and then the ingot segment is sliced, polished, cleaned and measured to obtain a substrate silicon wafer. The substrate silicon wafer is graded and sorted, and if the substrate silicon wafer is determined to be OK, the OK substrate silicon wafer is sorted into the corresponding carrier and the epitaxial growth process is started. If a silicon substrate wafer is deemed unacceptable (NG), it will be either reworked or scrapped.

[0029] Figures 7 and 8 show schematic diagrams of a susceptor for epitaxial growth of a silicon wafer according to an embodiment of the present disclosure. The susceptor 5 includes a disc-shaped mounting portion 51 and an annular peripheral portion 52 extending radially outward from the disc-shaped mounting portion 51. As shown in Figure 7, compared to the susceptor shown in Figure 6, in the embodiment of this disclosure, groove regions 6 are added to the annular periphery 52 of the susceptor 5. Multiple groove regions 6 are formed on the annular periphery 52, spaced apart from each other. The groove regions 6 are uniformly distributed along the circumferential direction of the annular periphery 52, and the groove regions 6 exhibit a fan-ring shape, that is, the groove regions 6 are axially symmetric, and the central axis of the groove regions 6 is in the radial direction of the susceptor 5. Multiple pits 61 are arranged in an array within each groove region 6, and the pits 61 are recessed downward compared to other areas of the annular periphery 52. ​​During epitaxial growth, the placement of the pits 61 increases the amount of gas that reaches the silicon wafer surface via the groove regions 6, thereby increasing the epitaxial layer growth rate of the silicon wafer region corresponding to the groove regions 6.

[0030] In this embodiment, when performing epitaxial growth, the silicon wafer <100> The crystal orientation can be aligned with the groove region 6 of the susceptor. In other words, the silicon wafer <100> The crystal orientation is aligned with the direction of the central axis of groove region 6. This ensures that during epitaxial growth, the silicon wafer <100> To improve the epitaxial layer growth rate in regions where crystal orientation exists, and to improve silicon wafer growth <110> The epitaxial layer growth rate in the crystal direction and <100> This reduces the difference in epitaxial layer growth rate in the crystal direction, thereby improving the growth rate of epitaxial silicon wafers. <110> This can improve edge flatness in the crystal direction.

[0031] In the technical means of this embodiment, the silicon wafer <100> The crystal orientation does not necessarily have to be in the direction of the central axis of the groove region 6, and the silicon wafer <100> It is sufficient to ensure that the angle between the crystal direction and the direction in which the central axis of groove region 6 exists is 20° or less. In other words, the silicon wafer <100> The angle between the crystal orientation and the direction in which the central axis of the groove region 6 exists may be 0°, 5°, 10°, 15°, or 20°. Furthermore, the silicon wafer <110> Because the epitaxial layer growth rate in the crystal direction is relatively large, <110> The epitaxial layer growth rate in the crystal direction and <100> In order to reduce the difference with respect to the epitaxial layer growth rate in the crystal direction, preferably, the annular peripheral portion 52 of the silicon wafer <110> In the radial direction corresponding to the crystal orientation, the groove region 6 is not provided.

[0032] In some embodiments, as shown in Figure 7, D1, D2, D3, or D4 are in the 45° direction of the susceptor, and the direction of the gas inlet, exhaust port, silicon wafer entrance / exit, or auxiliary gas inlet of the epitaxial reaction chamber is in the 0° direction of the susceptor. Four groove regions 6 can be uniformly arranged along the circumferential direction of the annular periphery 52, each corresponding to the direction of the gas inlet, exhaust port, silicon wafer entrance / exit, and auxiliary gas inlet of the epitaxial reaction chamber. As shown in Figures 2 and 3, the silicon wafer has four <100> This includes the crystal orientation. As a result, when a silicon wafer is placed on the susceptor 5 of this embodiment and epitaxial growth is performed, each of the silicon wafers <100> Each crystal orientation can be made to correspond to one groove region 6, <100> To improve the growth rate of epitaxial layers in the crystal direction, and to improve the growth rate of epitaxial silicon wafers <110> This effectively improves edge flatness in the crystal direction.

[0033] In some embodiments, as shown in Figure 8, the central angle a corresponding to the sector in which the groove region 6 exists may be 40° to 60°, for example, 40°, 45°, 50°, 55°, or 60°. This allows the silicon wafer to <100> After aligning the crystal orientation with the central axis of the susceptor groove region 6, the silicon wafer <100> This can effectively improve the edge flatness in the crystal direction and its vicinity.

[0034] In this embodiment, the pits 61 may be arranged along the radial direction of the susceptor 5, and the depth of the pits 61 may be 0.1 mm to 1 mm, for example, 0.1 mm, 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, or 1 mm. When the depth of the pits 61 is set to the above dimensions, the amount of silicon raw material gas that reaches the silicon wafer surface via the groove region 6 during epitaxial growth can be effectively increased.

[0035] The area of ​​the pit 61 may be between 0.1 square millimeters and 0.4 square millimeters, for example, 0.1 square millimeters, 0.2 square millimeters, 0.3 square millimeters, or 0.4 square millimeters. When the area of ​​the pit 61 is set to the above dimensions, the amount of silicon raw material gas that reaches the silicon wafer surface via the groove region 6 during epitaxial growth can be effectively increased.

[0036] In this embodiment, the orthographic projection of the pit 61 onto the horizontal plane may be a regular shape such as a rectangle, circle, or parallelogram, or it may be an irregular shape.

[0037] In some embodiments, the distribution density of the pits gradually decreases along the direction from the middle of the groove region toward the edge of the groove region. This results in the silicon wafer during epitaxial growth. <100> After aligning the crystal orientation with the central axis of the susceptor groove region 6, the silicon wafer <100> From the crystal direction <110> The degree of decrease in the growth rate in the crystal direction can be gradually reduced, thereby making the growth rate more uniform in the circumferential direction of the silicon wafer and making the thickness of the epitaxial layer grown on the silicon wafer more uniform. As a result, an epitaxial silicon wafer with better flatness can be obtained.

[0038] Embodiments of this disclosure further provide an apparatus for epitaxial growth of silicon wafers, the apparatus, The susceptor mentioned above, A reaction chamber for housing the susceptor, wherein the susceptor divides the reaction chamber into an upper reaction chamber and a lower reaction chamber, and the silicon wafer is placed in the upper reaction chamber; An air inlet for transporting silicon source gas into the upper reaction chamber to grow an epitaxial layer on the silicon wafer, It includes an exhaust port for discharging reaction exhaust gas generated by epitaxial growth from the reaction chamber.

[0039] In addition, similar to conventional apparatuses for the epitaxial growth of silicon wafers, this apparatus may further include a susceptor support frame, upper and lower quartz bells surrounding the reaction chamber, multiple heating lamps, mounting components, and a small gap between the radial edge of the susceptor and adjacent components, allowing the susceptor to rotate at a constant speed around its central axis by the drive of the susceptor support frame. This will not be repeated any further.

[0040] Embodiments of this disclosure further provide a method for epitaxial growth of silicon wafers applicable to the above apparatus, the method being: The silicon wafer is the silicon wafer <100> The steps include: placing the crystal on the susceptor such that its crystal orientation aligns with the central axis of the groove region of the annular periphery; The steps include transporting silicon raw material gas through the air inlet into the upper reaction chamber and growing an epitaxial layer on the silicon wafer, The steps include: the flow rate of the silicon source gas flowing through the groove region becoming greater than the flow rate of the silicon source gas flowing through other regions of the annular periphery, thereby resulting in a uniform thickness of the epitaxial layer grown on the silicon wafer; The process includes the step of discharging the reaction exhaust gas generated by epitaxial growth from the reaction chamber through the exhaust port.

[0041] In this embodiment, when performing epitaxial growth, the silicon wafer is rotated at different angles according to the crystal direction corresponding to the V-shaped groove of the silicon wafer, aligning the crystal direction of the silicon wafer with the position of the groove region. By aligning the crystal direction with the groove region, the epitaxial layer growth rate in that crystal direction can be improved. This compensates for the epitaxial layer growth rates in different crystal directions of the silicon wafer and improves the flatness of the epitaxial silicon wafer.

[0042] Figure 9 shows a schematic diagram of the manufacturing flow of an epitaxial silicon wafer according to the embodiment of this disclosure. When manufacturing an epitaxial silicon wafer, first a single-crystal silicon ingot is manufactured, the single-crystal silicon ingot is cut into segments, a V-shaped groove is processed in a specific crystal direction of the ingot segment according to the product requirements, and then the ingot segment is sliced, polished, cleaned and measured to obtain a substrate silicon wafer. The substrate silicon wafer is graded and sorted, and if the substrate silicon wafer is determined to be OK, the OK substrate silicon wafer is sorted into the corresponding carrier and the epitaxial growth process is started. If the substrate silicon wafer is determined to be NG, the substrate silicon wafer is reworked or scrapped.

[0043] As shown in Figure 9, the method for fabricating an epitaxial silicon wafer according to the embodiment of this disclosure further includes the following steps 101 to 104.

[0044] In step 101, a sorting rule for the substrate silicon wafer is set based on the V-groove direction.

[0045] V-grooves in silicon wafers are used to determine the crystal orientation of the silicon wafer, and depending on product requirements, the V-grooves in some silicon wafers are <110> Located in the crystal direction, the V-shaped grooves in some silicon wafers <100> It is located in the crystal direction. In this embodiment, it is necessary to obtain the crystal direction corresponding to the V-shaped groove of the silicon wafer.

[0046] In step 102, when sorting the approved substrate silicon wafers with different V-groove orientations onto the corresponding carriers, they are rotated at different angles.

[0047] In related technologies, when a silicon wafer is placed on a susceptor, the V-shaped groove of the silicon wafer is generally aligned with the 0° direction of the susceptor, that is, with the direction of the gas inlet, exhaust port, silicon wafer entrance / exit, or auxiliary gas inlet of the epitaxial reaction chamber.

[0048] In step 103, the V-shaped groove <110> The substrate silicon wafer, oriented in the crystal direction, is rotated by 45°.

[0049] The V-shaped groove is of the silicon wafer <110> If oriented in the crystalline direction, the V-shaped groove will not enter the epitaxial reaction chamber. <110> The substrate silicon wafer, oriented in the crystal direction, is rotated by 45°, and after the silicon wafer is placed on the susceptor, the angle between the central axis of the V-shaped groove and the central axis of the groove region becomes 45°. This allows the silicon wafer to <100> The crystal orientation can be made to align with the groove region 6 of the susceptor. In other words, the silicon wafer <100> The crystal orientation is aligned with the direction of the central axis of groove region 6. During epitaxial growth, the silicon wafer <100> To improve the epitaxial layer growth rate in regions where crystal orientation exists, and to improve silicon wafer growth <110> The epitaxial layer growth rate in the crystal direction and <100> This reduces the difference in epitaxial layer growth rate in the crystal direction, and the epitaxial silicon wafer <110> This can improve edge flatness in the crystal direction.

[0050] In step 104, the V-shaped groove <100> The substrate silicon wafer, oriented in the crystal direction, is rotated 0°.

[0051] The V-shaped groove is of the silicon wafer <100> If oriented in the crystalline direction, the V-shaped groove will not enter the epitaxial reaction chamber. <100> By rotating the substrate silicon wafer in the crystal direction by 0°, that is, by not rotating it, the silicon wafer is positioned on the susceptor such that the angle between the central axis of the V-shaped groove and the central axis of the groove region is 0°. This allows the silicon wafer to <100> The crystal orientation can be made to align with the groove region 6 of the susceptor. In other words, the silicon wafer <100> The crystal orientation is aligned with the direction of the central axis of groove region 6. During epitaxial growth, the silicon wafer <100> To improve the epitaxial layer growth rate in regions where crystal orientation exists, and to improve silicon wafer growth <110> The epitaxial layer growth rate in the crystal direction and <100> This reduces the difference in epitaxial layer growth rate in the crystal direction, and the epitaxial silicon wafer <110> This can improve edge flatness in the crystal direction.

[0052] Figure 10 shows a V-shaped groove according to an embodiment of this disclosure. <100> A schematic diagram is shown showing a silicon wafer 3 oriented in the crystal direction placed on a susceptor. As shown in Figure 2, the V-shaped groove 4 of the silicon wafer is <100> When in the crystal direction, the regions 45° and 135° away from the V-groove 4 in this silicon wafer are the silicon wafer <110> The crystal orientation is such that the regions 90° and 180° away from the V-groove 4 in this silicon wafer are the silicon wafer <100> This corresponds to the crystal direction.

[0053] As shown in Figure 7, a groove region 6 exists in the 0° edge region of the susceptor. Compared to the 45° direction of the susceptor, the gas flow rate in this groove region 6 in the 0° direction of the susceptor increases during epitaxial growth, and an increase in gas flow rate accelerates the growth rate of the epitaxial layer. Therefore, in order to make the growth rate of different regions of the silicon wafer the same during epitaxial growth, the silicon wafer <100> The crystal orientation and the 0° direction of the susceptor (the direction in which the groove region of the susceptor exists) are aligned, and the silicon wafer <110> The crystal orientation and the 45° direction of the susceptor must be aligned. This ensures that during epitaxial growth, the silicon wafer <100> The epitaxial layer growth rate in the crystal direction increases, and the silicon wafer of the epitaxial layer <100> Crystal orientation and <110> The thickness is the same in the crystal direction.

[0054] As shown in Figure 10, since the orientation of the susceptor is fixed when the epitaxial reaction chamber is mounted, the 0° direction in which the groove region 6 exists on the edge of the susceptor is the direction of the gas inlet, exhaust port, silicon wafer entrance / exit, or auxiliary gas inlet of the epitaxial reaction chamber. The V-shaped groove <100> By rotating a silicon wafer in the crystal direction by 0°, that is, by not rotating it, the silicon wafer <100> The crystal orientation and the 0° direction of the susceptor (the direction corresponding to the groove region of the susceptor, where the gas flow rate on the silicon wafer surface increases) are aligned, and the silicon wafer <110> By aligning the crystal orientation with the 45° direction of the susceptor, it is possible to compensate for differences in epitaxial layer growth rates due to different crystal orientations of silicon wafers and improve the edge flatness of silicon epitaxial wafers.

[0055] Figures 11 and 12 show a V-shaped groove according to the embodiment of this disclosure. <110> A schematic diagram is shown showing a silicon wafer oriented in the crystal direction placed on a susceptor. As shown in Figure 11, the V-shaped groove 4 of the silicon wafer 3 is <110> When in the crystal direction, the regions 45° and 135° away from the V-groove 4 in this silicon wafer are the silicon wafer <100> The crystal orientation is such that the regions 90° and 180° away from the V-groove 4 in this silicon wafer are the silicon wafer <110> This corresponds to the crystal direction.

[0056] As shown in Figure 7, a groove region 6 exists in the 0° edge region of the susceptor. Compared to the 45° direction of the susceptor, the gas flow rate in this groove region 6 in the 0° direction of the susceptor increases during epitaxial growth, and an increase in gas flow rate accelerates the growth rate of the epitaxial layer. Therefore, in order to make the growth rate of different regions of the silicon wafer the same during epitaxial growth, the silicon wafer <100> The crystal orientation and the 0° direction of the susceptor (the direction in which the groove region of the susceptor exists) are aligned, and the silicon wafer <110> The crystal orientation and the 45° direction of the susceptor must be aligned. This ensures that during epitaxial growth, the silicon wafer <100> The epitaxial layer growth rate in the crystal direction increases, and the silicon wafer of the epitaxial layer <100> Crystal orientation and <110> The thickness is the same in the crystal direction.

[0057] As shown in Figure 12, since the orientation of the susceptor is fixed when the epitaxial reaction chamber is mounted, the 0° direction in which the groove region 6 exists on the edge of the susceptor is the direction of the gas inlet, exhaust port, silicon wafer entrance / exit, or auxiliary gas inlet of the epitaxial reaction chamber. The V-shaped groove <110> By rotating a silicon wafer oriented in the crystal direction by 45°, the silicon wafer <100> The crystal orientation and the 0° direction of the susceptor (the direction corresponding to the groove region of the susceptor, where the gas flow rate on the silicon wafer surface increases) are aligned, and the silicon wafer <110> By aligning the crystal orientation with the 45° direction of the susceptor, it is possible to compensate for differences in epitaxial layer growth rates due to different crystal orientations of silicon wafers and improve the edge flatness of silicon epitaxial wafers.

[0058] Embodiments of this disclosure further provide epitaxial silicon wafers fabricated using the above-described method for epitaxial growth of silicon wafers. When the epitaxial layer thickness of the epitaxial silicon wafer is 6 micrometers or less, the maximum value of the edge-site front-reference least squares range ESFQR of the epitaxial silicon wafer is 57.1 nanometers or less.

[0059] Figure 13 shows a schematic diagram of the edge flatness of an epitaxial silicon wafer fabricated according to an embodiment of this disclosure. In Figure 13, the horizontal axis represents the radial angle of the silicon wafer, and the vertical axis represents the ESFQR value (in nanometers) of the silicon wafer at the corresponding angular position. It can be seen that the phenomenon of periodic fluctuations in 45° intervals in the edge flatness of the epitaxial silicon wafer is improved, the edge flatness quality of the epitaxial silicon wafer is improved, the ESFQR value of the epitaxial silicon wafer is reduced by 14 nanometers, and the quality and yield of the epitaxial silicon wafer can be effectively improved.

[0060] In some embodiments, the ESFQR value of the epitaxial silicon wafer is inversely proportional to the depth of the pit and inversely proportional to the area of ​​the pit. If other parameters of the susceptor remain constant, increasing the pit depth increases the amount of gas participating in the film deposition reaction in the groove region during the epitaxial growth process, resulting in a better compensation effect for differences in epitaxial layer growth rates due to different crystal orientations of the silicon wafer, a smaller ESFQR value, and a more pronounced improvement in the edge flatness quality of the fabricated epitaxial silicon wafer. If other parameters of the susceptor remain constant, increasing the pit area increases the amount of gas participating in the film deposition reaction in the groove region during the epitaxial growth process, resulting in a better compensation effect for differences in epitaxial layer growth rates due to different crystal orientations of the silicon wafer, a smaller ESFQR value, and a more pronounced improvement in the edge flatness quality of the fabricated epitaxial silicon wafer.

[0061] In some embodiments, when the epitaxial layer thickness of the epitaxial silicon wafer is 3 to 4 micrometers, the range of the ESFQR value of the epitaxial silicon wafer is 23 nanometers to 33.9 nanometers, and when the epitaxial layer thickness of the epitaxial silicon wafer is 4 to 6 micrometers, the range of the ESFQR value of the epitaxial silicon wafer is 37.4 nanometers to 57.1 nanometers.

[0062] In specific example 1, the V-shaped groove <100> A silicon wafer is selected with the crystal orientation, and the central angle corresponding to the sector in which the susceptor groove region exists is 40° to 50°, for example, 45°. The depth of the pit is 0.1 mm to 1 mm, for example, 0.48 mm to 0.52 mm, and also 0.5 mm. The area of ​​the pit is 0.1 square millimeters to 0.4 square millimeters, for example, 0.18 square millimeters to 0.22 square millimeters, and also 0.2 square millimeters. The silicon wafer is placed on the susceptor, and the angle between the central axis of the V-shaped groove and the central axis of the groove region is 0°, and the silicon wafer <100> Epitaxial growth was performed with the crystal orientation aligned with the groove region of the susceptor. During the epitaxial growth process, the flow rate of hydrogen gas (H2) as the transport gas was 80,000 sccm, the flow rate of the film deposition gas (SiHCl3 / H2) was 6,000 sccm, and the film deposition reaction temperature was 1,100°C. An epitaxial layer with a thickness of 3.3 to 3.5 micrometers, for example, 3.5 micrometers, was grown, and the resulting epitaxial silicon wafer had an ESFQR value of 29.3 ± 4.6 nanometers. Compared to conventional technology, the ESFQR value of the epitaxial silicon wafer was reduced by 8.6 nanometers, improving the quality of the epitaxial silicon wafer. This is because the pits installed in the groove region increased the process gas flow rate in the groove region, and the silicon wafer <100> The epitaxial layer growth rate in the crystal direction is accelerated, and in the epitaxial layer growth process <110> Crystal orientation and <100> This is because the difference in growth rates in the crystal direction was compensated for.

[0063] In specific example 2, the V-shaped groove <100> A silicon wafer is selected in the crystal direction, and the central angle corresponding to the sector in which the susceptor groove region exists is 40° to 50°, for example, 45°. The depth of the pit is 0.78 mm to 0.82 mm, for example, 0.8 mm. The area of ​​the pit is 0.38 square millimeters to 0.42 square millimeters, for example, 0.4 square millimeters. The silicon wafer is placed on the susceptor, and the angle between the central axis of the V-shaped groove and the central axis of the groove region is 0°, and the silicon wafer <100> Epitaxial growth was performed with the crystal orientation aligned with the groove region of the susceptor. During the epitaxial growth process, the flow rate of hydrogen gas (H2) as the transport gas was 80,000 sccm, the flow rate of the film deposition gas (SiHCl3 / H2) was 6,000 sccm, and the film deposition reaction temperature was 1,100°C. An epitaxial layer with a thickness of 3.3 to 3.5 micrometers, for example, 3.5 micrometers, was grown, and the resulting epitaxial silicon wafer had an ESFQR value of 26.8 ± 3.8 nanometers. Compared to conventional technology, the ESFQR value of the epitaxial silicon wafer was reduced by 11.1 nanometers, improving the quality of the epitaxial silicon wafer. This is because the pits installed in the groove region increased the process gas flow rate in the groove region, and the silicon wafer <100> The epitaxial layer growth rate in the crystal direction is accelerated, and in the epitaxial layer growth process <110> Crystal orientation and <100> This is because the difference in growth rate in the crystal direction was compensated for. Furthermore, compared to Specific Example 1, the depth and area of ​​the pits in the groove region increased, which increased the amount of gas participating in the film deposition reaction in the groove region during the epitaxial growth process. This improved the compensation effect for the difference in epitaxial layer growth rate due to different crystal directions of the silicon wafer, resulting in a smaller ESFQR value and a more pronounced improvement in the edge flatness quality of the fabricated epitaxial silicon wafer.

[0064] In specific example 3, the V-shaped groove <100> A silicon wafer is selected with the crystal orientation, and the central angle corresponding to the sector in which the susceptor groove region exists is 40° to 50°, for example, 45°. The depth of the pit is 0.1 mm to 1 mm, for example, 0.48 mm to 0.52 mm, and also 0.5 mm. The area of ​​the pit is 0.1 square millimeters to 0.4 square millimeters, for example, 0.18 square millimeters to 0.22 square millimeters, and also 0.2 square millimeters. The silicon wafer is placed on the susceptor, and the angle between the central axis of the V-shaped groove and the central axis of the groove region is 0°, and the silicon wafer <100> Epitaxial growth was performed with the crystal orientation aligned with the groove region of the susceptor. During the epitaxial growth process, the flow rate of hydrogen gas (H2) as the transport gas was 80,000 sccm, the flow rate of the film deposition gas (SiHCl3 / H2) was 6,000 sccm, and the film deposition reaction temperature was 1,100°C. An epitaxial layer with a thickness of 4.8 to 5 micrometers, for example, 5 micrometers, was grown, and the ESFQR value of the resulting epitaxial silicon wafer was 48.4 ± 8.7 nanometers. Compared to conventional technology, the ESFQR value of the epitaxial silicon wafer was reduced, improving the quality of the epitaxial silicon wafer. This is because the pits installed in the groove region increased the process gas flow rate in the groove region, and the silicon wafer <100> The epitaxial layer growth rate in the crystal direction is accelerated, and in the epitaxial layer growth process <110> Crystal orientation and <100> This is because the difference in growth rates in the crystal direction was compensated for.

[0065] In specific example 4, the V-shaped groove <100> A silicon wafer is selected in the crystal direction, and the central angle corresponding to the sector in which the susceptor groove region exists is 40° to 50°, for example, 45°. The depth of the pit is 0.78 mm to 0.82 mm, for example, 0.8 mm. The area of ​​the pit is 0.38 square millimeters to 0.42 square millimeters, for example, 0.4 square millimeters. The silicon wafer is placed on the susceptor, and the angle between the central axis of the V-shaped groove and the central axis of the groove region is 0°, and the silicon wafer <100> Epitaxial growth was performed with the crystal orientation aligned with the groove region of the susceptor. During the epitaxial growth process, the flow rate of hydrogen gas (H2) as the transport gas was 80,000 sccm, the flow rate of the film deposition gas (SiHCl3 / H2) was 6,000 sccm, and the film deposition reaction temperature was 1,100°C. An epitaxial layer with a thickness of 4.8 to 5 micrometers, for example, 5 micrometers, was grown, and the ESFQR value of the resulting epitaxial silicon wafer was 43.8 ± 6.4 nanometers. Compared to conventional technology, the ESFQR value of the epitaxial silicon wafer was reduced, improving the quality of the epitaxial silicon wafer. This is because the pits installed in the groove region increased the process gas flow rate in the groove region, and the silicon wafer <100> The epitaxial layer growth rate in the crystal direction is accelerated, and in the epitaxial layer growth process <110> Crystal orientation and <100> This is because the difference in growth rate in the crystal direction was compensated for. Furthermore, compared to Specific Example 3, the depth and area of ​​the pits in the groove region increased, which increased the amount of gas participating in the film deposition reaction in the groove region during the epitaxial growth process. This improved the compensation effect for the difference in epitaxial layer growth rate due to different crystal directions of the silicon wafer, resulting in a smaller ESFQR value and a more pronounced improvement in the edge flatness quality of the fabricated epitaxial silicon wafer.

[0066] In this specification, each embodiment and example is described in a progressive manner. Parts that are the same or similar between embodiments can be referenced to one another, while each embodiment focuses on describing the parts that differ from the other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively brief, and relevant parts can be found in the description of the product embodiments.

[0067] Unless otherwise defined, technical or scientific terms used in this disclosure have their ordinary meanings as understood by a person of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are used solely to distinguish different components. Similar terms such as “includes” or “contains” mean that the element or article appearing before the term includes the elements or articles and their equivalents listed after the term, but do not exclude other elements or articles. Similar terms such as “connected” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Up,” “down,” “left,” “right,” etc., are used solely to indicate relative positional relationships, and their relative positional relationships may change accordingly after the absolute position of the subject being described changes.

[0068] When an element such as a layer, film, region, or substrate is described as being "above" or "below" another element, it should be understood that the element may be located "directly" above or below the other element, or an intermediate element may exist.

[0069] In the description of the embodiments above, specific features, structures, materials, or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0070] While specific embodiments of this disclosure have been described above, the scope of protection of this disclosure is not limited to these. Any modifications or substitutions that a person skilled in the art could easily conceive of within the scope of this disclosure should be included in the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A susceptor for epitaxial growth of silicon wafers, A disc-shaped mounting section for mounting the aforementioned silicon wafer, It includes an annular peripheral portion extending radially outward from the disc-shaped mounting portion, A susceptor wherein the annular periphery has a plurality of groove regions arranged at intervals, the groove regions are uniformly distributed along the circumferential direction of the annular periphery, the groove regions form a fan-ring shape, and each of the groove regions has a plurality of pits arranged in an array.

2. The susceptor according to claim 1, wherein the central angle corresponding to the sector in which the groove region exists is 40° to 60°.

3. The susceptor according to claim 1, wherein four groove regions are uniformly distributed along the circumferential direction of the annular peripheral edge.

4. The depth of the pit is 0.1 millimeters to 1 millimeter, and / or The susceptor according to claim 1, wherein the area of ​​the pit is 0.1 square millimeters to 0.4 square millimeters.

5. Apparatus for epitaxial growth of silicon wafers, A susceptor according to any one of claims 1 to 4, A reaction chamber for housing the susceptor, wherein the susceptor divides the reaction chamber into an upper reaction chamber and a lower reaction chamber, and the silicon wafer is placed in the upper reaction chamber; An air inlet for transporting silicon source gas into the upper reaction chamber to grow an epitaxial layer on the silicon wafer, An apparatus including an exhaust port for discharging reaction exhaust gas generated by epitaxial growth from the reaction chamber.

6. A method for epitaxial growth of a silicon wafer, applicable to the apparatus described in claim 5, The steps include: placing the silicon wafer on the susceptor such that the <100> crystal direction of the silicon wafer aligns with the central axis of the groove region of the annular periphery; The steps include transporting silicon raw material gas through the air inlet into the upper reaction chamber and growing an epitaxial layer on the silicon wafer, The steps include: the flow rate of the silicon source gas flowing through the groove region becoming greater than the flow rate of the silicon source gas flowing through other regions of the annular periphery, thereby resulting in a uniform thickness of the epitaxial layer grown on the silicon wafer; A method comprising the step of discharging reaction exhaust gas generated by epitaxial growth from the reaction chamber through the exhaust port.

7. The step of placing the silicon wafer on the susceptor such that the <100> crystal direction of the silicon wafer aligns with the central axis of the groove region of the annular periphery is: The steps include obtaining the crystal orientation corresponding to the V-shaped groove in the silicon wafer, The method according to claim 6, comprising the step of arranging the silicon wafer on the susceptor such that the angle between the central axis of the V-shaped groove and the central axis of the groove region is 45°, when the V-shaped groove is in the <110> crystal direction of the silicon wafer.

8. The step of placing the silicon wafer on the susceptor such that the <100> crystal direction of the silicon wafer aligns with the central axis of the groove region of the annular periphery is: The steps include obtaining the crystal orientation corresponding to the V-shaped groove in the silicon wafer, The method according to claim 6, further comprising the step of arranging the silicon wafer on the susceptor such that the angle between the central axis of the V-shaped groove and the central axis of the groove region is 0°, when the V-shaped groove is in the <100> crystal direction of the silicon wafer.

9. An epitaxial silicon wafer produced using the method for epitaxial growth of a silicon wafer according to any one of claims 6 to 8, An epitaxial silicon wafer in which the epitaxial layer thickness of the epitaxial silicon wafer is 6 micrometers or less, wherein the maximum value of the edge site front-facing least squares range ESFQR of the epitaxial silicon wafer is 57.1 nanometers or less.

10. When the epitaxial layer thickness of the epitaxial silicon wafer is 3 micrometers to 4 micrometers, the range of the ESFQR value of the epitaxial silicon wafer is 23 nanometers to 33.9 nanometers. The epitaxial silicon wafer according to claim 9, wherein when the epitaxial layer thickness of the epitaxial silicon wafer is 4 micrometers to 6 micrometers, the range of the ESFQR value of the epitaxial silicon wafer is 37.4 nanometers to 57.1 nanometers.

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