Semiconductor device and manufacturing process

DE102026100412A1Undetermined Publication Date: 2026-08-27TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
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Patent Information

Application Number
DE102026100412
Authority / Receiving Office
DE · DE
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-05-29
Filing Date
2026-01-05
Publication Date
2026-08-27
Patent Text Reader

Abstract

A slope on the surface of a semiconductor wafer, located in an edge region, is filled before bonding the two wafers to each other to minimize or eliminate the likelihood of gap formation between the edges. To fill the slope, one or more dielectric bonding layers are fabricated over the wafer's surface such that the top surface of the uppermost layer is located at a greater vertical height than the bottom surface of the lowermost layer. The one or more bonding layers can then be etched and / or planarized to remove excess material.
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