Device for picking up existing silicon chips in three-dimensionally integrated stacks

Abstract

Device comprising: a first chip (110) comprising a multi-core processor, the first chip (110) having a device side (120) of the first chip (110) and a backside (125) of the first chip (110), the device side (120) of the first chip (110) being adjacent to and connected to a package substrate (310), the backside (125) of the first chip (110) having a first region corresponding to a surface of the first chip (110); a plurality of conductive substrate vias, TSVs, (130), wherein the plurality of TSVs (130) connects from the device side (120) of the first chip (110) to the backside (125) of the first chip (110); and a plurality of upper chips (210), each of the plurality of upper chips (210) being adjacent to the backside (125) of the first chip (110), the plurality of upper chips (210) being configured to collectively encompass a total surface area corresponding to the first region of the first chip (110), the plurality of upper chips (210) comprising: a first upper die (210A or 210B or 210C or 210D; 610A or 610B or 620) with a memory unit, wherein the first upper die (210A or 210B or 210C or 210D; 610A or 610B or 620) has a device side of the first upper die (210A or 210B or 210C or 210D; 610A or 610B or 620) and a backside of the first upper die, the device side of the first upper die being coupled to the backside of the first die in a face-to-back bonding configuration, wherein the plurality of TSVs (130) couple the device side of the first upper die (210A or 210B or 210C or 210D; 610A or 610B or 620) to the component side (120) of the first chip (110); a second upper chip (210B or 210C or 210D or 210A; 610B or 620 or 610A) adjacent to the back side (125) of the first chip (110); and a third upper chip (210C or 210D or 210A or 210B; 620 or 610A or 610B) adjacent to the back side (125) of the first chip (110), wherein the device further comprises a redistribution layer (150) for connecting the plurality of TSVs (130) to a plurality of contact points on the device side of the first upper chip (210A or 210B or 210C or 210D; 610A or 610B or 620), and a spacer material made of a dielectric material on the backside (125) of the first chip (110).

Description

Field of the invention

[0001] The invention relates to the field of packaging technology and encapsulation of integrated circuits. In particular, the invention relates to a device for accommodating existing silicon chips in three-dimensionally integrated stacks. Background of the invention

[0002] Efforts are being made to stack chips or semiconductor die to increase performance without taking up more space (e.g., a larger portion of the surface area) on a printed circuit board. These efforts are particularly driven by the requirements of sophisticated mobile phones, smartphones, and other mobile devices. Chip manufacturers have integrated dynamic RAM and static RAM (DRAM and SRAM), flash memory, and other storage into a structure or stack of interconnected integrated circuits, but these integration efforts have historically been limited due to the additional space required by the wiring technology (e.g., wire bonding) used to connect the chips.Chip or die stacking technology connects two or more dies together to form a structure of interconnected integrated circuits. The chips or dies can be connected using interconnect wiring along the sides of the stack or using metal vias at the junctions between dies.

[0003] A common approach to stacking chips or dies is called face-to-face bonding. In this configuration, the component sides of two respective dies are stacked on top of each other so that the component sides face each other, and metallic vias electrically connect the dies at the junction from one die to the other. In a representation of a face-to-face bonded structure with connected integrated circuits, a central processing unit (CPU) or logic chip and a memory chip (e.g., an SRAM chip or a DRAM chip) are stacked together in a face-to-face bonded configuration.A heat sink may be attached to the main body of the CPU or logic chip, and the power and input / output (IO) connections to the package or circuit board are attached to the main body of the memory die using bump technology. Through-silicon vias (TSVs) may be used to pass through the memory die and connect to the metal junction from one die to another.

[0004] In the above example, since the through-silicon vias pass through the active silicon memory region of the second die (e.g., a memory die), sufficient area must be allocated in the circuit to accommodate the through-silicon vias. These vias may be larger (more than ten times) than the minimum design rules for a given process due to power / energy dissipation requirements. Power / energy for both dies is supplied via the through-silicon vias. Power / energy requirements dictate approximately one through-silicon via per bump contact.In flip-chip technology, bumps are typically arranged in a uniform, widely spaced pattern across an entire two-dimensional chip, allowing for a high number of uniform power and ground connections in the top metal layer. This requires that the circuitry in the second chip (e.g., memory die) be designed to accommodate these vias with appropriate spacing from neighboring geometries. This requires that the second chip be specifically designed to precisely match the via requirements of the first chip.

[0005] Another bonding configuration is a face-to-back bonding configuration. To stay with the example of a CPU die and a memory die, in a face-to-back bonding configuration the position of the two dies is swapped. For example, the signal and power lines of the first die (CPU die) are connected to the package in a conventional way using standard bump technology. The power and signal connections for the second die (e.g. memory die) are routed through the first die using vias through silicon. The power / energy requirements of a memory chip are typically lower than for a CPU or logic chip, so the number of vias through silicon required by the first die (e.g.The amount of energy that would need to run on the CPU chip could be considerably smaller and would not need to be spatially distributed uniformly across the chip. This means that the design and layout of the CPU chip are affected to a much lesser extent by the three-dimensional bonding of a second chip.

[0006] US 2003 / 0063450 A1 relates to a system for connecting a multi-chip assembly to a printed circuit board or other substrate. An exemplary electronic multi-chip system comprises: a substrate having conductors formed thereon, a base IC chip having a first surface facing the substrate and a second surface parallel to the first surface, a first secondary IC chip located between the first surface of the base IC chip and the substrate and connected to the first surface of the base IC chip via first conductive signal paths, and conductive contacts extending between the first surface of the base IC chip and the conductors on the substrate and configured to transmit first signals between the base IC chip and the conductors on the substrate. The conductive contacts comprise resilient spring contacts.

[0007] US 6 150 724 A relates to a manufacturing method for a compact flip-chip semiconductor device with a ball grid array (BGA) containing a plurality of integrated circuits (ICs). The flip-chip semiconductor device is formed, for example, by producing a mother chip with a first set of bumps and a second set of bump contacts. A daughter chip is also produced, which has conductive bumps. The daughter chip and the mother chip are placed facing each other, and contact is made between the bumps of the daughter chip and the bump contact areas of the mother chip. After the daughter chip and the mother chip are connected, the mother chip is contacted to an IC package using the bumps. The package uses a plurality of metal layers that are selectively connected to one another by conductive vias to conduct signals between the mother chip, the daughter chip, and external terminals of the package.

[0008] US 2002 / 0139577 A1 relates to an interconnect system utilizing a vertical signal path along an edge of an integrated circuit chip. An exemplary interconnect system for providing a signal path from a first circuit node of an integrated circuit (IC) to a second circuit node external to the IC, wherein the IC is formed on a semiconductor substrate having horizontal top and bottom surfaces and a peripheral edge extending between the top and bottom surfaces. The interconnect system comprises: a conductor external to the semiconductor substrate extending downward from the top surface to the bottom surface near the peripheral edge of the substrate, first means for conductively connecting the conductor to the first circuit node, and second means for conductively connecting the conductor to the second circuit node. Summary of the invention

[0009] It can therefore be considered an object of the present invention to propose a device for efficient use of space on a printed circuit board.

[0010] The above object is achieved according to the invention with the device according to the main claim 1. The dependent claims define further developments of the device according to the invention. Short description of the drawings

[0011] Certain features, aspects, and advantages of the embodiments will become more apparent from the following detailed description, the appended claims, and the accompanying drawings: Fig. 1 shows an exploded top view of an interconnected integrated circuit structure comprising a first chip and a plurality of singulated or non-singulated chips arranged to occupy a surface area of ​​the first chip. Fig. 2 shows a view of the top of the structure from Fig. 1 and shows bond pads associated with each of the second chips. Fig. 3 shows a side view along line 3-3'. Fig. 4 shows the structure of Fig. 2 along the line 3-3' and represents a redistribution layer for electrically connecting the contacts on the second chips with vias through silicon on the first chip. Fig. 5 shows an embodiment of a surface of the first chip. Fig. 6 shows another embodiment of an interconnected integrated circuit structure comprising a first chip and a plurality of second chips. Fig. 7 shows a flow diagram of one embodiment of a method for forming a structure with connected integrated circuits. Fig. Figure 8 shows a schematic side view of an electronic assembly as part of a desktop calculator. Detailed description

[0012] The Fig. 1 to 3 show different views of an embodiment of a structure with connected integrated circuits including a first chip 110 and a number of singulated or non-singulated second chips 210 connected on / to chip 110. Chip 110 is, for example, a CPU or a logic chip. In one embodiment, chips 210 (including individual chips 210A, chip 210B, chip 210C, and chip 210D) are memory chips (e.g., SRAM, DRAM) or other chips or a combination of different chips (e.g., logic and memory). The plurality of chips represented by chips 210 together have a chip dimension (surface area) that is close to or corresponds to a dimension (surface area) of the first chip 110. By way of example, chip 110, which is a CPU or a logic chip, can, for example, have a surface area of ​​400 mm 2Each of the chips 210 (chip 210A, chip 210B, chip 210C, chip 210D) in this example has a surface area of ​​100 mm 2 so that the total surface area occupied by the chips 210 is also 400 mm 2 If the chips 210 are memory structures, e.g., DRAM, the chips can be selected so that the chips together form an acceptable match for DRAM density and chip dimensions. In terms of density, a DRAM chip size can be 1 GB according to current technologies, with the number of chips being four, as shown. Alternatively, for a lower DRAM capacity (e.g., 512 KB or 256 KB), the number of chips 210 can be larger (e.g., eight 512 KB chips with 60 mm 2 per chip (480 mm 2 )).

[0013] Fig. 1 shows two examples of chips 210. In one example, each of the chips 210 (chip 210A, chip 210B, chip 210C, and chip 210D) is singulated and assembled as a distinguishable unit on the chip 110. Alternatively, the multiple chips may be scribed and attached to the chip 110 as a single unit.

[0014] Memory chips (e.g., SRAM, DRAM) are available either as chips or in wafer form. These chips are typically used in wire-bonded applications. For example, these chips can have 4-32 I / O plus supply bond pads per chip. These bond pads are typically arranged in a narrow column, one or two bond pads wide, through the center of the chip. Fig. Figure 2 shows the chips 210 (e.g., chip 210A, chip 210B, chip 210C, and chip 210D) with a column of bond pads 220, two bond pads wide, through the center of each chip (shown using dashed lines to indicate that the bond pads, in the view of Fig. 2, arranged on an opposite surface of the chips).

[0015] In one embodiment, chip 110 may be a multi-core processor. A multi-core processor generally includes multiple full execution cores within a physical processor, each operating at the same frequency. The cores typically share the same packaging / housing. Referring to Fig. 1, the chip 110 may be, for example, a dual-core processor or a quad-core processor (shown) or a processor with an even larger number of cores.

[0016] In one embodiment, the chip 110 and the chips 210 are connected in a face-to-back bond configuration. Referring to the Fig. 3, chip 110 has a number of through-silicon vias (TSVs) 130 formed therein. The through-silicon vias 130 comprise a conductive material, e.g., copper, which is used to connect chip 110 and / or contacts 320 on package 310 to contacts (e.g., bond pads) on chips 210 (chip 210C and chip 210D, as shown). Fig. 3 shows the chip 110 with the device side 120 adjacent to and connected to the package 310 by means of vias through silicon 130 extending through the chip 110 (from a device side to a backside (surface 125)). The vias through silicon from a conductive material, such as copper, may be formed as part of the process steps used to manufacture the chip 110. In this way, the vias through silicon 130 may be patterned to interface with the contact pads 220 (see Fig. 2) of the second chips are aligned. Fig. 3 shows vias through silicon 130 extending from the electrical contacts 320 (e.g., solder bumps on bond pads) to the bond pads 220 of the second chips 210C and 210D. The chips 210 may be arranged such that a component side (bond pad side) of each chip is located on the backside of the chip 110. Fig. 3 further shows a heat sink 410 connected to a backside of the chips 210.

[0017] In some embodiments, the through-silicon vias associated with chip 110 are not aligned with contacts (e.g., bond pads) of chips 210. In such situations, an electrically conductive redistribution layer, e.g., in the form of a metallic layer, e.g., made of copper, may be patterned on either the backside of chip 110 or the device side of chips 210. Such a redistribution layer may serve as an interconnect between the contact points (e.g., bond pads) of chips 210 and the through-silicon vias 130. Fig. 4 shows the structure with connected integrated circuits of the Fig. 2 along the layer through lines 3-3' according to another embodiment. In this example, the contact points 220 of chip 210C and chip 210D are not aligned with the through-silicon vias 130 extending between the package 310 and through the chip 110. Fig. 4 shows a redistribution layer 150 made of, for example, a conductive material, such as copper, which in one embodiment is patterned on a backside of the chip 110. Fig. 5 shows a back surface of the chip 110 with vias through silicon 130A and 130B extending through the chip 110 to the back surface. Fig. 5 further shows a patterned redistribution layer 150 extending laterally from each via through silicon 130A. In this example, the vias through silicon 130B would be aligned with contact points of the second chips 210. As an example, the redistribution layer 150 may be formed of a conductive material, such as copper, patterned using photolithographic techniques, e.g., depositing a copper material on a backside surface of the chip 110, followed by a masking step for defining the redistribution layer 150 and an etching step for patterning the redistribution layer as fingers extending laterally from the vias through silicon 130A to a desired position for electrical contact with the contact points of the second chips 210C and 210D.The redistribution layer 150 may be connected to contact points of the chips 210, for example by means of solder connections, as may the vias through silicon 130B.

[0018] Where necessary, a spacer material, for example made of a dielectric material, may be formed in conjunction with the redistribution layer on a surface of the chip 110 or chips 210 to fill any gaps between the chips. Fig. 4 shows a spacer material 160 formed with the redistribution layer 150 on a surface of the chip 110.

[0019] In the description, with reference to the Fig. 1 to 5 show four chips 210, for example, memory chips (e.g., DRAM or SRAM), each having a similar chip size. It is apparent that in other embodiments, chips with different functions and different dimensions can be stacked on top of one another. Fig. 6 shows a top view of a structure with connected integrated circuits of chip 510 of, for example, a CPU or a logic chip. Chips 610A and 610B of, for example, a DRAM memory are arranged on one surface (for example, a back surface) of chip 510. Also arranged on the back of chip 510 is chip 620, which has a larger chip dimension (cross-sectional area) than either chip 610A or chip 610B. Chip 620 is, for example, an SRAM memory. In this example, chip 610A, chip 610B, and chip 620 are described as memory chips, but it should be understood that other forms of chips, such as CPU or logic chips, may be used as well.

[0020] Fig. Figure 7 shows a flow diagram of a method for forming a structure with interconnected integrated circuits. In this embodiment, memory chips are assembled on a surface, e.g., a back surface of a CPU or logic chip. As noted above, it will be appreciated that the choice of chip type may vary.

[0021] With reference to Fig. 7, the memory requirements for an interconnected integrated circuit structure are initially determined (block 710). For example, the desired memory requirements may correspond to one GB of DRAM memory for an interconnected integrated circuit structure.

[0022] After the memory requirements have been determined, a number of memory chips is selected such that the sum of the surface areas of multiple chips approximates the surface area (e.g., the back surface) of a CPU logic chip (block 720). For example, if the surface area of ​​a CPU or logic chip is 400 mm 2 and 1 GB DRAM memory chips are available with a surface area of ​​100 mm 2 , correspond to four DRAM memory chips (4 - 100 mm 2 ) a surface of the CPU or logic chip.

[0023] Following the selection of the memory chips, the contact points (supply and I / O contact points) of the memory chips are examined, and a pattern is compared to a pattern of through-silicon vias desired for the CPU logic chip. At this point, a determination is made as to whether a redistribution layer is required (block 730). If a redistribution layer is not required, the contacts on the backside of the CPU or logic chip can be patterned (block 740). If a redistribution layer is necessary, a redistribution layer is patterned on a backside surface of a CPU or logic chip, and contacts to the redistribution layer are provided (block 750).

[0024] Once contacts are provided on a surface (e.g., a back surface) of a CPU chip, the multiple memory chips are connected to the CPU or logic chip, e.g., through solder connections (block 760). Following the connection of the memory chips to the CPU or logic chip, the connected chip stack may be connected to a substrate package, including the through-silicon vias extending through the memory chips (block 770). A heat sink and any other process techniques typically used in assembling package substrates may then follow.

[0025] Fig. Figure 8 shows a side view of an electronic assembly including a structure with connected integrated circuits that can be physically and electrically connected to a printed circuit board (PCB). The electronic assembly can be part of an electronic system, such as a computer (e.g., desktop, laptop, handheld, server, etc.), a wireless communication device (e.g., cellular phone, cordless phone, pager, etc.), computer accessories (e.g., printer, scanner, monitor, etc.), consumer electronics (e.g., television, radio, stereo, tape and compact disc player, video cassette recorder, MP3 (motion picture experts group, audio layer 3 player, etc.), and the like. Fig. Figure 8 shows the case as part of a desktop computer. Fig.Figure 8 shows an electronic assembly 800 including an integrated circuit structure 805 that is physically and electrically connected to the package substrate 810. The package substrate 810 can be used to connect the chip 100 to the printed circuit board 820, such as a motherboard or other circuit board.

Claims

[1] Device comprising: a first chip (110) comprising a multi-core processor, the first chip (110) having a device side (120) of the first chip (110) and a backside (125) of the first chip (110), the device side (120) of the first chip (110) being adjacent to and connected to a package substrate (310), the backside (125) of the first chip (110) having a first region corresponding to a surface of the first chip (110); a plurality of conductive substrate vias, TSVs, (130), wherein the plurality of TSVs (130) connects from the device side (120) of the first chip (110) to the backside (125) of the first chip (110); and a plurality of upper chips (210), each of the plurality of upper chips (210) being adjacent to the backside (125) of the first chip (110), the plurality of upper chips (210) being configured to collectively encompass a total surface area corresponding to the first region of the first chip (110), the plurality of upper chips (210) comprising: a first upper die (210A or 210B or 210C or 210D; 610A or 610B or 620) with a memory unit, wherein the first upper die (210A or 210B or 210C or 210D; 610A or 610B or 620) has a device side of the first upper die (210A or 210B or 210C or 210D; 610A or 610B or 620) and a backside of the first upper die, the device side of the first upper die being coupled to the backside of the first die in a face-to-back bonding configuration, wherein the plurality of TSVs (130) couple the device side of the first upper die (210A or 210B or 210C or 210D; 610A or 610B or 620) to the component side (120) of the first chip (110); a second upper chip (210B or 210C or 210D or 210A; 610B or 620 or 610A) adjacent to the back side (125) of the first chip (110); and a third upper chip (210C or 210D or 210A or 210B; 620 or 610A or 610B) adjacent to the back side (125) of the first chip (110), wherein the device further comprises a redistribution layer (150) for connecting the plurality of TSVs (130) to a plurality of contact points on the device side of the first upper chip (210A or 210B or 210C or 210D; 610A or 610B or 620), and a spacer material made of a dielectric material on the backside (125) of the first chip (110). [2] The device of claim 1, wherein at least one contact point (220) of the plurality of contact points is not aligned with a TSV of the plurality of TSVs (130). [3] The device of claim 1 or 2, further comprising a fourth upper chip (210D or 210A or 210B or 210C) adjacent to the backside (125) of the first chip (110).

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