Control system that is reconfigurable during operation and method therefor

Abstract

A control system that is reconfigurable during operation, the control system comprising: a main controller (101) configured to generate a bit stream containing reconfiguration information according to a user command; and a first follower controller (102), characterized in that the first follower controller (102) has: a first dynamic reconfiguration module (526) being a field-programmable gate array reconfigured according to the reconfiguration information that calculates a control value; a static reconfiguration module (523) which is a field programmable gate array (FPGA) that controls operation of a target device according to the control value; and a control unit (510) that reconfigures the first dynamic reconfiguration module (526) and the static reconfiguration module (523) according to the reconfiguration information, the main controller (101) has: a reconfiguration library storage unit (330) that stores functional information indicating a connection relationship between gates of the first dynamic reconfiguration module (526) or the static reconfiguration module (523); a reconfiguration information combining unit (320) that extracts functional information according to the command and generates the reconfiguration information by combining the extracted functional information; and an entry management unit (340) that generates a bit stream containing the reconfiguration information, and the control system further comprises: an auxiliary communication unit (350) that transmits the bit stream to the first slave controller (102), wherein, if the entry management unit (340) generates reconfiguration time information that is the time for transmitting the bit stream according to the command, the auxiliary communication unit (350) transmits the bit stream to the first slave controller (102) every predetermined period.

Description

[Technical field]

[0001] The present invention relates to a control system and a method therefor, more particularly to a control system that is reconfigurable during operation and a method therefor. [Background information]

[0002] Robots and similar devices use servo motors for their operation. The (work) processes of the devices can be controlled by controlling the servo motors.

[0003] Typically, a master controller and slave controllers are used to perform sequence control. The master controller sends a control signal to each of the slave controllers, and each slave controller controls the servo motor according to the control signal. The master controller can be connected to multiple slave controllers, and each slave controller controls the associated servo motor.

[0004] The slave controller typically has a functional board package responsible for operating the servo motor. However, the slave controller has the disadvantage that it can only control the associated servo motor. In other words, if the servo motor is replaced with a different model, the slave controller must also be replaced.

[0005] From JP 2001-322 078 A, a control system according to the preamble of claim 1 is known. From JP 2005-275 938 A, a follower controller is known, comprising: a first dynamic reconfiguration module, which is a field-programmable gate array reconfigured according to the reconfiguration information; a static reconfiguration module, which is a field-programmable gate array (FPGA); and a control unit, which reconfigures the first dynamic reconfiguration module and the static reconfiguration module according to the reconfiguration information. From KR 10 2007 0 071 645 A, a follower controller is known, which calculates a control value and controls the operation of a target device according to the control value.Common procedures for the dynamic reconfiguration of FPGAs are shown in US 2007 / 0 283 311 A1, US 6 836 842 B1, EP 1 187 042 A1, US 6 678 646 B1, US 7 640 526 B1, US 7 640 527 B1, US 5 931 959 A and CN 1 01 788 931 A. From DE 11 2008 003 042 T5 it is known to connect a master controller, a first slave controller and a second slave controller in a double ring structure of a network. [Revelation][Technical Problem]

[0006] The present invention provides a control system and method thereof that is reconfigurable during operation by changing a control method of a device, by reconfiguring the structure of the FPGA (Field Programmable Gate Array), while maintaining control of the device. [Technical Solution]

[0007] This object is achieved by a control system of claim 1. Further developments are the subject of the dependent claims. The control system according to the present invention comprises a main controller (or master controller) that generates a bit stream containing reconfiguration information according to a user's command. The first slave controller (or auxiliary controller or slave controller) comprises: a first dynamic reconfiguration module, which is a field programmable gate array (FPGA) reconfigured according to the reconfiguration information and calculates a control value; a static reconfiguration module, which is an FPGA, that controls operation of a target device according to the control value; and a control unit (or monitoring unit) that reconfigures the first dynamic reconfiguration module and the static reconfiguration module according to the reconfiguration information.

[0008] The control unit may reconfigure an FPGA structure of the first dynamic reconfiguration module independently of the operation of the static reconfiguration module.

[0009] The first follower controller may also include a second dynamic reconfiguration module that is an FPGA that is reconfigured according to the reconfiguration information and that calculates a control value, and the control unit may control the second dynamic reconfiguration module to be reconfigured according to the reconfiguration information if the capacity of the reconfiguration information is greater than a predetermined value and maintain the operation of the first dynamic reconfiguration module until the second dynamic reconfiguration module is completely reconfigured.

[0010] The control unit may stop (or pause) the operation of the first dynamic reconfiguration module when the second dynamic reconfiguration module is fully reconfigured.

[0011] The main controller includes: a reconfiguration library storage unit that stores function information indicating a connection relationship between gates of the first dynamic reconfiguration module or the static reconfiguration module; a reconfiguration information combining unit that extracts function information according to the command and generates the reconfiguration information by combining the extracted function information; and an entry management unit that generates a bit stream containing the reconfiguration information.

[0012] The control system also includes an auxiliary (or slave) communication unit that transmits the bit stream to the first slave controller, and if the entry management unit generates reconfiguration time information that is the time (or period) for transmitting the bit stream according to the command, the auxiliary communication unit can transmit the bit stream to the first slave controller every predetermined period.

[0013] The control system may also include a second slave controller, which is a controller having the same configuration as the first slave controller, wherein the master controller may generate the bit stream containing reconfiguration information according to both the first slave controller and the second slave controller.

[0014] The main controller, the first slave controller and the second slave controller can be connected in a double-ring structure of the network.

[0015] In case the target device is changed, the static reconfiguration module may be an FPGA that is reconfigured according to the reconfiguration information. [Description of the characters] Fig. 1 shows a control system. Fig. Figure 2 shows an example of a bit stream generated by a main controller of the control system. Fig. Figure 3 is a block diagram showing a conceptual structure of the main controller. Fig. 4 shows an example of how the main controller generates reconfiguration information. Fig. Figure 5 is a block diagram briefly showing functional units that form a first slave controller. Fig. Figure 6 is a flowchart showing how the control system controls operation of a servo motor. [Manner of invention]

[0016] Fig. 1 shows a control system that is reconfigurable during operation according to an embodiment of the present invention.

[0017] Referring to Fig. 1, the control system according to an embodiment of the present invention includes a main controller 102, a first follower controller (or auxiliary controller) 102 and a second follower controller (or auxiliary controller) 103. Although in the Fig. 1 illustrates two slave controllers, the control system according to one embodiment of the present invention may include a plurality of slave controllers (or slave controllers), depending on the environment in which the present invention is used. Furthermore, each slave controller may be connected to at least one sensor that senses each servomotor, as well as acceleration, heat, etc., from each servomotor.

[0018] The master controller 101 receives an operation command from an input device such as a personal computer (not shown). Here, the command received from the input device is a signal indicating an operation command according to one of the operation modes of the servo motor. The master controller 101 can compare at least one of the reconfiguration information instructing reconfiguration of an FPGA (Field Programmable Gate Array) arranged in a slave controller with the received command and store the reconfiguration information. For example, the master controller 101 can generate a bitstream by inserting the command received from the input device and the reconfiguration information compared with the command.

[0019] For example, in the case that there are two slave controllers 102, 103, as in Fig. 1, the master controller 101 generates a bit stream by inserting at least a first reconfiguration information belonging to (in other words, associated with) the first slave controller 102 and a second reconfiguration information belonging to (in other words, associated with) the second slave controller 103.

[0020] The structure of the bitstream is described in detail below with reference to the Fig. 2 described.

[0021] Fig. 2 shows an example of a bit stream generated by a main controller of the control system according to an embodiment of the present invention.

[0022] The master controller 101 generates a bit stream containing reconfiguration information instructing reconfiguration of the FPGA located in the first slave controller 102 and the second slave controller 103 to control the servo motors connected to the first slave controller 102 and the second slave controller 103, respectively.

[0023] Here, the master controller 101 may allow the reconfiguration information to be arranged after the slave (or auxiliary) identification number, which is information for identifying each of the slave controllers, in the bit stream so that each slave controller can easily retrieve the corresponding reconfiguration information.

[0024] For example, in Fig. 2, first slave identification information 210 and first reconfiguration information 220 are slave identification information and reconfiguration information corresponding to the first slave controller 102, and second slave identification information 230 and second reconfiguration information 240 are slave identification information and reconfiguration information corresponding to the second slave controller 103. The first slave controller 102 can search for the first slave identification information 210 included in the bit stream, can recognize data between the first slave identification information 210 and the next slave identification information as the first reconfiguration information 220, and can extract the first reconfiguration information 220 from the bit stream.

[0025] Referring to Fig. 1, the main controller 101 may periodically generate a plurality of bit streams according to a command received from the input device.

[0026] For example, if the command received from the input device instructs the servo motor to repeat operation and stop steps at predetermined intervals, the main controller 101 may generate a bit stream containing reconfiguration information for performing the operation of the servo motor and generate a bit stream containing reconfiguration information for performing the stop of the servo motor at predetermined intervals.

[0027] The structure of the main controller 101 is described in detail below with reference to Fig. 3 described.

[0028] Fig. Figure 3 is a block diagram showing a conceptual structure of the main controller. Refer to Fig. 3, the main controller 101 includes a host communication unit 310, a reconfiguration information combining unit 320, a reconfiguration library storage unit 330, an entry management unit 340, and an auxiliary (or slave) communication unit 350.

[0029] The host communication unit 310 receives a user command from the input device via a network. The host communication unit 310 transmits the received command to the reconfiguration information combining unit 320.

[0030] The reconfiguration information combining unit 320 extracts one or more functional information stored in the reconfiguration library storage unit according to the command received from the host communication unit, and generates reconfiguration information by combining the extracted functional information.

[0031] Here, according to one embodiment of the present invention, the functional information may contain information about a connection relationship between gates of the FPGA of the follower controllers, and may be represented in various forms, for example, as a bit string. Furthermore, according to one embodiment of the present invention, the FPGA may execute a specific function when the FPGA is reconfigured according to the functional information. The steps for generating the reconfiguration information will be described in detail later with reference to Fig. 4. Here, the reconfiguration information combining unit 320 transmits the generated reconfiguration information to the entry management unit 340.

[0032] The entry management unit 340 generates reconfiguration time information and reconfiguration mode information based on the reconfiguration information received from the reconfiguration information combining unit 320.

[0033] Here, the reconfiguration time information indicates whether the bit stream containing the reconfiguration information is sent immediately or when the auxiliary communication unit 350 sends the bit stream periodically.

[0034] The reconfiguration mode information indicates whether each of the slave controllers that received the bit stream will reconfigure the FPGA.

[0035] The entry management unit 340 adds the reconfiguration mode information to the reconfiguration information, generates a bit stream containing each of the reconfiguration information and slave identification information, and transmits the bit stream to the auxiliary communication unit 350 together with the reconfiguration time information.

[0036] The auxiliary communication unit 350 transmits the bit stream to the first slave controller 102 or the second slave controller 103, depending on the reconfiguration time information. Specifically, if the reconfiguration time information indicates that the bit stream is to be transmitted immediately, the auxiliary communication unit 350 transmits the bit stream to the slave controller immediately. If the reconfiguration time information indicates that the bit stream is to be transmitted according to a transmission period, the auxiliary communication unit 350 transmits the bit stream to the first slave controller 102 or the second slave controller 103 at each of the specified transmission periods.

[0037] Referring back to Fig. 1, the master controller 101 transmits the generated bit stream to the first slave controller 102. Here, the master controller 101 may be connected to the first slave controller 102 and the second slave controller 103 in a double-ring structure. In particular, in the case where the bit stream transmitted by the master controller 101 to the first slave controller 102 is not received by the second slave controller 103, the double-ring structure may enable the master controller 101 to transmit the generated bit stream back to the second slave controller 103. Therefore, according to an embodiment of the present invention, normal operation is possible even if each network between the master controller 101, the first slave controller 102, and the second slave controller 103 is interrupted.

[0038] The first slave controller 102 extracts the reconfiguration information from the bit stream received from the master controller 101, reconfigures the FPGA according to the reconfiguration information, and controls the servo motor using the reconfigured FPGA. The structure of the first slave controller 102 will be described in detail later with reference to Fig. 5 described.

[0039] Fig. 4 shows an example of how the main controller generates reconfiguration information.

[0040] Referring to Fig. 4, the reconfiguration information combining unit 320 of the main controller 101 receives a command from the input device. The reconfiguration information combining unit 320 retrieves the necessary functional information from the reconfiguration storage unit 330 according to the received command. The reconfiguration library storage unit 330 can store one or more functional information. The reconfiguration information combining unit 320 can prestore a list of functional information necessary for reconfiguring the FPGA according to each command received from the user.Accordingly, once a command is received, the reconfiguration information combining unit 320 searches the list for function information that matches the command, extracts function information included in the searched list from the reconfiguration library storage unit 330, and generates reconfiguration information by combining the function information.

[0041] For example, the reconfiguration library storage unit 330 can store function information about the algorithm to be executed by the follower controllers, function information indicating a function that receives data from a sensor for monitoring the servo motor, and function information indicating a function that controls operation of an actual motor. The reconfiguration information combining unit 320 receives COMMAND1 from an input device 410 and searches the list for function information that matches COMMAND1. The reconfiguration information combining unit 320 confirms that the function information included in the list of function information is ALGORITHM1, SENSOR INPUT 1, and MOTOR DRIVE2 and retrieves each of the function information from the reconfiguration library storage unit 330.The reconfiguration information combining unit 320 generates reconfiguration information 420 according to COMMAND1 by combining the extracted function information. The reconfiguration information combining unit 320 can transmit the reconfiguration information 420 to the entry management unit 340.

[0042] Although the main controller 101 is described as generating reconfiguration information by having the reconfiguration information combining unit 320 extract and combine functional information, it is also possible for the reconfiguration information combining unit 320 to pre-store reconfiguration information according to each command therein and transmit the reconfiguration information according to a particular command to the entry management unit 340 when the particular command is received. Accordingly, it is possible for the main controller 101 to extract reconfiguration information without a particular step of combining the functional information and transmit the reconfiguration information to the entry management unit 340.

[0043] Fig. 5 is a block diagram briefly showing functional units that form a first slave controller. Referring to Fig. 5, the first slave controller 102 includes a control unit 510 and a reconfiguration unit 520.

[0044] The control unit 510 receives a bit stream from the main controller 101 and extracts reconfiguration information from the bit stream. The control unit 510 checks whether the reconfiguration mode information contained in the reconfiguration information indicates a reconfiguration of the FPGA. If the reconfiguration mode information does not indicate a reconfiguration of the FPGA, the control unit 510 does not perform the step of reconfiguring the FPGA. If the reconfiguration mode information indicates a reconfiguration of the FPGA, the control unit 510 reconfigures a gate array structure of the reconfiguration unit 520 according to the reconfiguration information.For example, if the reconfiguration information indicates an FPGA structure in which data is received from the sensor according to the monitoring of the servo motor, and the received data is calculated according to a predetermined algorithm, and the servo motor is controlled according to the result of the calculation, the control unit 510 controls the reconfiguration unit 520 to reconfigure the FPGA according to the reconfiguration information.

[0045] Here, although the previously described control unit 510 has determined to perform the reconfiguration according to the reconfiguration mode information, according to another embodiment of the present invention, the control unit 510 may determine whether or not the FPGA needs to be reconfigured based on whether or not reconfiguration information according to the corresponding follower is included in the bit stream.

[0046] The reconfiguration unit 520 includes a static reconfiguration module 523, a first dynamic reconfiguration module 526, and a second dynamic reconfiguration module 529, which are formed with the FPGA. The static reconfiguration module 523, which is a module that controls the operation of the servo motor, can control the servo motor to perform rotational acceleration, counter-rotational acceleration, stop, etc., according to a signal received from the dynamic reconfiguration modules (i.e., the first dynamic reconfiguration module 526 and the second dynamic reconfiguration module 529). Since the static reconfiguration module 523 directly controls the operation of the servo motor, no reconfiguration is performed while the first follower controller 102 controls the operation of the servo motor. However, in the event that the servo motor is replaced with another type of device, the static reconfiguration module 523 can perform reconfiguration.In particular, in the event that the user provides a command to control the replaced other type of device through the input device, the master controller 101 may transmit a bit stream containing the reconfiguration information for reconfiguration to the static reconfiguration module 523 to correspond to this command, for example, to the control unit 510 of the first slave controller 102. Then, the control unit 510 reconfigures the gate array structure of the static reconfiguration module 523 according to the reconfiguration information contained in the bit stream, so that the replaced other type of device can be controlled.

[0047] Furthermore, the first dynamic reconfiguration module 526 has reconfigured the FPGA according to the control unit's control but independently of the static reconfiguration module 523. This means that the first dynamic reconfiguration module 526 is reconfigured regardless of whether the static reconfiguration module 523 is currently controlling or reconfiguring the servo motor.

[0048] For example, the dynamic reconfiguration module 526 receives a rotation speed of the servo motor from the sensor that detects the rotation speed of the servo motor and can perform a calculation according to an algorithm predetermined for the rotation speed of the servo motor if the rotation speed exceeds a certain speed. The dynamic reconfiguration module 526 can transmit a control value, which is the result of a calculation, to the static reconfiguration module 523. Furthermore, the static reconfiguration module 523 can adjust the rotation speed to a speed corresponding to the control value.

[0049] In another example of reconfiguration of the first dynamic reconfiguration module 526, assume that controlling the servo motor requires successively receiving data from a first sensor, a second sensor, and a third sensor and performing a calculation with a first algorithm, and that the bit stream for this is generated by the main controller 101. In this case, the control unit 510 may receive a first bit stream from the main controller 101. Here, the first bit stream contains reconfiguration information indicating an FPGA structure for receiving the data from the first sensor and performing a calculation with the first algorithm. The control unit 510 then controls the first dynamic reconfiguration module 526 to reconfigure the FPGA structure according to the reconfiguration information. Here, the static reconfiguration module 523 may continue to control the servo motor.After the reconfiguration is completed, the first dynamic reconfiguration module 526 receives the data from the first sensor according to the FPGA structure and outputs a control value calculated by the first algorithm. The first dynamic reconfiguration module 526 sends the control value to the static reconfiguration module 523. The static reconfiguration module 523 continues to control the servo motor according to the control value.

[0050] Subsequently, the control unit 510 may receive a second bit stream from the main controller 101. The second bit stream contains reconfiguration information indicating an FPGA structure for receiving the data from the second sensor and performing the calculation with the first algorithm. Following the steps described above, the first dynamic reconfiguration module 526 is then reconfigured into an FPGA structure that allows receiving the data from the second sensor. Furthermore, the static reconfiguration module 523 continues to control the servo motor according to the control value.

[0051] Subsequently, the control unit 510 may receive a third bit stream from the main controller 101. The third bit stream contains reconfiguration information indicating an FPGA structure for receiving the data from the third sensor and performing the calculation with the first algorithm. Following the steps described above, the first dynamic reconfiguration module 526 is then reconfigured into an FPGA structure that allows receiving the data from the third sensor. Furthermore, the static reconfiguration module 523 continues to control the servo motor according to the control value.

[0052] Accordingly, the data from the first sensor, the second sensor and the third sensor can be received sequentially.

[0053] Conventional operating controllers required a module for each sensor to receive the data from the respective sensor if data from the sensors is received sequentially, and inevitably had to have a sufficiently large circuit.

[0054] However, it is possible for the first slave controller 510 to use a dynamic reconfiguration module 526 to sequentially receive data from the sensors to control the servo motor, while using the static reconfiguration module 523 to maintain control of the servo motor. Accordingly, the control system can be made relatively smaller than conventional operational controllers.

[0055] Here, the functions of the static reconfiguration module 523 and the first dynamic reconfiguration module 526 are not limited to the description herein. In other words, the functions of the static reconfiguration module 523 and the first dynamic reconfiguration module 526 may vary depending on the reconfiguration information received from the control unit 510.

[0056] The second dynamic reconfiguration module 529 has the same configuration as that of the first dynamic reconfiguration module 526 and can be reconfigured using the same reconfiguration steps as those of the first dynamic reconfiguration module 526.

[0057] In another embodiment of the present invention, the control unit 510 may reconfigure the FPGA structure of the first dynamic reconfiguration module 526 or the second dynamic reconfiguration module 529 depending on the capacity of the reconfiguration information extracted from the bitstream.

[0058] For example, if the first dynamic reconfiguration module 526 is assumed to be currently operating, the control unit 510 reconfigures the FPGA of the second dynamic reconfiguration module 529, which is not currently operating, according to the reconfiguration information if the capacity of the reconfiguration information is greater than a predetermined capacity. After the reconfiguration is completed, the second dynamic reconfiguration module 529 sends a reconfiguration completion signal indicating that the reconfiguration is completed to the control unit 510. Once the reconfiguration completion is received, the control unit 510 sends an operation stop request to request the operation stop to the first dynamic reconfiguration module 526, which is currently operating. The first dynamic reconfiguration module 526 stops the operation according to the operation stop request.Here, the second dynamic reconfiguration module 529, in which the FPGA structure is reconfigured according to the reconfiguration information, performs a calculation and sends the result of the calculation to the static reconfiguration module 523. Then, after receiving the result of the calculation from the second dynamic reconfiguration module 529, the static reconfiguration module 523 can control the servo motor.

[0059] Although it is described above that the control unit 510 determines whether the capacity of the reconfiguration information of the bit stream received from the main controller 101 is larger than a predetermined value, it is also possible in another embodiment that the main controller 101 determines whether the capacity of the reconfiguration information is larger than a predetermined value and can insert information corresponding to the determination into a header (in other words, a header field) of the reconfiguration information.

[0060] Here, the control unit 510 can check the information in the header of the reconfiguration information and perform the reconfiguration steps of the first dynamic reconfiguration module 526 or the second dynamic reconfiguration module 529.

[0061] Fig. Figure 6 is a flowchart showing how the control system controls operation of a servo motor.

[0062] Referring to Fig. 6, the main controller 101 receives a command from an input device in step 610.

[0063] In step 620, the master controller 101 generates a bit stream for controlling the servo motor according to the command received in step 610. Here, the master controller 101 generates a bit stream containing reconfiguration information indicating an FPGA structure of a slave controller required for controlling the servo motor according to the command. The master controller 101 sends a bit stream to the first slave controller 102.

[0064] In step 630, the first slave 102 extracts reconfiguration information from the received bit stream. After extracting the reconfiguration information, the first slave 102 may send the bit stream to the second slave 103. The second slave 103, having received the bit stream, may be operated in the same manner as the first slave 102 after step 630.

[0065] In step 640, the first follower controller 102 reconfigures the structure of the reconfiguration unit, which is an FPGA module, according to the reconfiguration information. Here, the first follower controller 102 reconfigures the second dynamic reconfiguration module 529 in the case where the first follower controller 102 needs to stop controlling the servo motor if the first dynamic reconfiguration module 526, which is currently controlling the servo motor among a plurality of dynamic reconfiguration modules, has been reconfigured according to the reconfiguration information. Once the reconfiguration of the second dynamic reconfiguration module 526 is completed, the first follower controller 102 can stop the operation of the first dynamic reconfiguration module 523 and can control the servo motor using the second dynamic reconfiguration module 529 and the static reconfiguration module 523.Furthermore, the first follower controller 102 can independently reconfigure the first static reconfiguration module 523, the first dynamic reconfiguration module 526, and the second dynamic reconfiguration module 529 according to the reconfiguration information. That is, if the reconfiguration information only shows the structure of the first dynamic reconfiguration module 526 or the second dynamic reconfiguration module 529, the first follower controller 102 can reconfigure the first dynamic reconfiguration module 526 or the second dynamic reconfiguration module 529 while the static dynamic reconfiguration module 523 controls the servo motor.

[0066] In step 650, the first slave controller 102 controls the operation of the servo motor by using the reconfiguration unit reconfigured in step 640.

[0067] Although it has been described that the control system controls the servo motor, it should be recognized that devices other than the servo motor can be controlled by configuring the reconfiguration information to suit other devices.

[0068] So far, the present invention has been described with reference to specific embodiments, but there are many other embodiments, in addition to the previously described embodiments, in the claims of the present invention. Anyone skilled in the art to which the present invention belongs should be able to understand that the present invention can be embodied in modified form without departing from the essential features of the present invention. Accordingly, the included embodiments are to be understood in an illustrative and not restrictive sense. The scope of the present invention is to be defined by the appended claims. [Industrial applicability]

[0069] The control system and method therefor according to an embodiment of the present invention can flexibly control various devices by reconfiguring a gate array structure according to a user's input.

[0070] The control system and method therefor according to an embodiment of the present invention can reduce the size of a control device by reconfiguring a gate array structure and controlling the device using the reconfigured gate array.

Claims

[1] A control system that is reconfigurable during operation, the control system comprising: a main controller (101) configured to generate a bit stream containing reconfiguration information according to a user command; and a first follower controller (102), characterized by , that the first follower controller (102) has: a first dynamic reconfiguration module (526) being a field-programmable gate array reconfigured according to the reconfiguration information that calculates a control value; a static reconfiguration module (523) which is a field programmable gate array (FPGA) that controls operation of a target device according to the control value; and a control unit (510) that reconfigures the first dynamic reconfiguration module (526) and the static reconfiguration module (523) according to the reconfiguration information, the main controller (101) has: a reconfiguration library storage unit (330) that stores functional information indicating a connection relationship between gates of the first dynamic reconfiguration module (526) or the static reconfiguration module (523); a reconfiguration information combining unit (320) that extracts functional information according to the command and generates the reconfiguration information by combining the extracted functional information; and an entry management unit (340) that generates a bit stream containing the reconfiguration information, and the control system further comprises: an auxiliary communication unit (350) that transmits the bit stream to the first slave controller (102), wherein, if the entry management unit (340) generates reconfiguration time information that is the time for transmitting the bit stream according to the command, the auxiliary communication unit (350) transmits the bit stream to the first slave controller (102) every predetermined period. [2] The control system of claim 1, wherein the control unit (510) reconfigures an FPGA structure of the first dynamic reconfiguration module (526) independently of the operation of the static reconfiguration module (523). [3] The control system of claim 1, wherein the first follower controller (102) further comprises a second dynamic reconfiguration module (529) which is an FPGA that is reconfigured according to the reconfiguration information and that calculates a control value, and wherein the control unit (510) controls the second dynamic reconfiguration module (529) to be reconfigured according to the reconfiguration information if the capacity of the reconfiguration information is greater than a predetermined value, and maintains the operation of the first dynamic reconfiguration module (526) until the second dynamic reconfiguration module (529) is completely reconfigured. [4] The control system of claim 3, wherein the control unit (510) stops the operation of the first dynamic reconfiguration module (526) when the second dynamic reconfiguration module (529) is fully reconfigured. [5] Control system according to claim 1, further comprising a second follower controller (103), which is a controller having the same configuration as the first follower controller (102), wherein the master controller (101) generates the bit stream containing reconfiguration information corresponding to both the first slave controller (102) and the second slave controller (103). [6] A control system according to claim 5, wherein the main controller (101), the first slave controller (101) and the second slave controller (103) are connected in a double ring structure of a network. [7] The control system of claim 1, wherein, in case the target device is changed, the static reconfiguration module (523) is an FPGA reconfigured according to the reconfiguration information.

Images