Memories that use hybrid error correction code techniques

Abstract

System (200) comprising: Memory devices (220) for providing data storage corresponding to a range of memory addresses, wherein a first portion (110, 130) of the memory addresses is protected by an error correction code, ECC, technique and a second portion (120) of the memory addresses is not protected by the ECC technique; a memory controller coupled to the memory devices (220), the memory controller having a plurality of processing paths, and wherein a first set (330-335) of the processing paths operates to apply the ECC technique to data, and a second set (310-315) of the processing paths operates to cause the data to be stored without the ECC technique, and wherein the memory controller selectively applies the ECC technique based on an address corresponding to a memory access request, characterized in that the memory access request comprises a read request in the second part (120) of the memory addresses, and ECC data returned in a corresponding memory read operation in the second part (120) of the memory addresses are ignored, so that ECC error handling is performed as if no ECC error had occurred.

Description

TECHNICAL FIELD

[0001] Embodiments of the invention relate to memory systems. In particular, embodiments of the invention relate to the use of hybrid error correction code techniques to provide more efficient memories. BACKGROUND

[0002] Error-correcting code (ECC) techniques are used to detect and / or correct errors in memory and can be used, for example, in mission-critical applications. Memory errors with ECC do not cause a system failure, but rather allow a system to detect and correct the error and continue operating. The use of ECC techniques is becoming widespread and is also desirable in other applications. However, the ECC overhead may be prohibitive for some applications where ECC is desirable.

[0003] WO 2011 / 031 260 A1 describes a system having a memory subsystem with at least one memory device and a memory controller for controlling access to the memory subsystem, wherein the memory controller is configured to store data with error correction code (ECC) information in a first part of the memory subsystem and to store data without ECC information in a second part of the memory subsystem. SUMMARY OF THE INVENTION

[0004] The object underlying the invention is achieved by the subject matter of the independent claims. Further advantageous embodiments are specified in the subclaims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Embodiments of the invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which like reference numerals refer to similar elements. Fig. Figure 1 is a conceptual illustration of an example memory table that includes both ECC-protected zones and non-ECC-protected zones. Fig. 2 is a block diagram of one embodiment of an electronics. Fig. 3 is a block diagram of one embodiment of a memory subsystem with selectable ECC processing. Fig. Figure 4 is a flow diagram of a technique for selectively using ECC techniques. DETAILED DESCRIPTION

[0006] In the following description, numerous specific details are provided. However, embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0007] Partial memory write throughput as part of ECC protection can experience up to 70% degradation due to a read / modify / write process for the checksum calculation required by ECC techniques. This performance degradation during partial writes can pose a serious problem for integrated graphics performance, for example, because integrated graphics frequently update the frame buffer stored in system memory with numerous partial writes. Therefore, applying ECC to integrated graphics results in a performance degradation that can negate the benefits of ECC protection. This may also be applicable to other situations.

[0008] Techniques described here provide a "non-ECC" window or region in a memory table. This is an area in the memory table where ECC operations (e.g., read / modify / write, checksum calculation) do not apply. In one embodiment, this region is specified by a starting address and size or extent; however, other techniques for specifying the non-ECC window may also be used.

[0009] Using the integrated graphics example, the region of system memory reserved for the integrated graphics would be allocated to a non-ECC window. The same can also be true for video encoding and decoding blocks, which also share system memory normally protected by ECC. These regions for integrated graphics, as well as video encoding and decoding, do not require the protection provided by ECC because, depending on the screen refresh rate, if a pixel has a defect and appears the wrong color, it will appear for, say, 1 / 24 or 1 / 60 of a second. This may be imperceptible to a user.

[0010] Various embodiments of the techniques described herein use one or more registers (or other memory elements) to define one or more non-ECC windows in memory protected by ECC techniques, as well as logic that checks incoming addresses for read and write operations in the memory controller against the window. For addresses that fall within the non-ECC window, partial writes do not incur the "read-merge-checksum-calculate-write" penalty, but are written directly with the checksum value as "arbitrary." For read operations, the checksum can be ignored, and checksum errors can be suppressed.

[0011] Currently, a system designer must choose between overriding graphics performance protection and ECC protection. Some systems address this problem by adding a shared cache to a graphics core. This causes the memory controller to see a full cache line instead of a partial cache line, and therefore eliminates the need for the read / modify / write operation. This is a costly addition to a graphics core and is not applicable, for example, to embedded systems where performance and cost must be kept as low as possible.

[0012] Fig. Figure 1 is a conceptual illustration of an example memory table that includes both ECC-protected and non-ECC-protected zones. The example of Fig. 1 illustrates only one ECC-free region; however, any number of ECC-free regions can be supported in a similar manner. The example of Fig. Figure 1 illustrates the ECC-free region near the “top” of the memory region; however, the ECC-free regions can also be placed in other locations.

[0013] In the example of Fig. 1, the ECC-protected region 130 includes conventional memory space (e.g., 0 to 640 KB), upper memory space (e.g., 640 KB to 1 MB), and a portion of extended memory space (e.g., 1 MB and higher). In one embodiment, the ECC-free region 120 is located within the extended memory space. In one embodiment, the ECC-protected region 110 also exists above the ECC-free region 120. In alternative embodiments, multiple ECC-free regions may be created within the extended memory space.

[0014] Fig. 2 is a block diagram of an embodiment of an electronic system. Fig. The electronics shown in Figure 2 are intended to represent a range of electronics (either wired or wireless), such as desktop computer systems, laptop computer systems, cellular telephones, personal digital assistants (PDAs), including cellular-enabled PDAs, and set-top boxes. Alternative electronic systems may include more, fewer, and / or different components. The electronics of Fig. 2 can any of the electronics of Fig. 1 represent.

[0015] The electronics 200 includes bus 205 or another communication device for communicating information, and processor 210 coupled to bus 205, which can process information. While the electronics 200 is shown with a single processor, the electronics 200 may include multiple processors and / or coprocessors. The electronics 200 may further include random access memory (RAM) or another dynamic storage device 220 (referred to as main memory) coupled to the bus 205, and may store information and instructions that can be executed by the processor 210. The memory 220 may also be used to store temporary variables or other intermediate information during the execution of instructions by the processor 210. In one embodiment, the memory 220 may be a memory system as described above with respect to Fig. 1 is organized.

[0016] Electronics 200 may also include read-only memory (ROM) and / or another static storage device 230 coupled to bus 205, which may store static information and instructions for processor 210. Data storage device 240 may be coupled to bus 205 to store information and instructions. Data storage device 240 (such as a magnetic disk or optical disk and corresponding drive) may be coupled to electronics 200.

[0017] Electronics 200 may also be coupled via bus 205 to display device 250, such as a cathode ray tube (CRT) or liquid crystal display (LCD), to display information to a user. Alphanumeric input device 260, including alphanumeric and other keys, may be coupled to bus 205 to communicate information and command selections to processor 210. Another type of user input device is cursor control 270, such as a mouse, trackball, or cursor arrow keys, for communicating directional information and command selections to processor 210 and for controlling cursor movement on display 250.

[0018] The electronics 200 may further include network interfaces 280 to enable access to a network, such as a local area network. The network interfaces 280 may include, for example, a wireless network interface having antenna 285, which may represent one or more antennas. The network interfaces 280 may also include, for example, a wired network interface to communicate with remote devices via the network cable 287, which may be, for example, an Ethernet cable, a coaxial cable, a fiber optic cable, a serial cable, or a parallel cable.

[0019] In one embodiment, the network interfaces 280 may provide access to a local area network, for example, by conforming to the IEEE 802.11b and / or IEEE 802.11g standards, and / or the wireless network interface may provide access to a personal area network, for example, by conforming to Bluetooth standards. Other wireless network interfaces and / or protocols may also be supported. IEEE 802.11b conforms to IEEE Std. 802.11b-1999 "Local and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: Higher Speed ​​Physical Layer Extension in the 2.4 GHz Band," approved September 16, 1999, and related documents. IEEE 802.11g conforms to IEEE Std. 802.11g-2003 "Local and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, Amendment 4: Further Higher-Speed ​​Extension in the 2.4 GHz Band," approved June 27, 2003, and associated documents. Bluetooth protocols are described in "Bluetooth System Specification: Core, Version 1.1," published February 22, 2001, by the Bluetooth Special Interest Group, Inc. Associated, and previous or subsequent versions of the Bluetooth standard may also be supported.

[0020] In addition to or instead of communication via wireless LAN standards, the network interfaces 280 may enable wireless communications using, for example, Time Division Multiple Access (TDMA) protocols, Global System for Mobile Communications (GSM) protocols, Code Division Multiple Access (CDMA) protocols, and / or any other type of wireless communication protocol.

[0021] Fig. Figure 3 is a block diagram of one embodiment of a memory subsystem with selectable ECC processing. In one embodiment, the memory subsystem supports four main types of memory transactions: 1) writes with ECC disabled, 2) reads with or without ECC enabled, 3) writes with ECC enabled, and 4) prefetch reads associated with read / write / modify (RMW) cycles required for partial ECC writes.

[0022] For example, when ECC is enabled by software selection, all writes (at least all partial writes) are completed over more than two memory accesses: a read of the memory location to prefetch the already existing data (via path 340-345), an internal merging of the read data with the new write data on a byte-by-byte basis (via path 378), and a rewrite of the memory location including new ECC values ​​(via path 330-335).

[0023] In one embodiment, path 310-315 includes mechanisms (e.g., bus lines) for sending memory write command information, byte write enable signals, and the data to be written from a memory transaction queue to a memory interface (e.g., DDR3, DDR4). In one embodiment, path 320-325 includes mechanisms (e.g., bus lines) for sending memory read command information from the memory transaction queue to the memory interface.

[0024] In one embodiment, path 330-335 includes mechanisms (e.g., bus lines) for sending memory write command information, byte write enable signals, ECC write data generated by ECC data generator 360, and data to be written. Path 340-345 includes mechanisms (e.g., bus lines) for sending memory read command information to the memory interface. The memory read command information is also sent to transaction location storage 375, which uses the memory read command information for RMW rewrite operations on path 378.

[0025] In one embodiment, the memory transaction queue provides write data and BWE to write data and BWE storage 365, which stores the data and forwards it to transaction location storage 375, which uses it for RMW rewrite operations on path 378. Path 378 provides the data to the memory transaction queue.

[0026] The storage subsystem of Fig. 3 is improved by providing a mechanism to identify system memory regions that do not require ECC processing and memory regions that do. With this improved capability, ECC can be enabled or disabled for each transaction type. In the above example, software-programmable ECC-free address space registers and comparison circuits (e.g., 390) are provided in the memory subsystem.

[0027] In one embodiment, if a specific transaction address matches one of the ECC-free regions, the corresponding memory transaction is executed without ECC processing. In the case of a memory read, the returned ECC data is "ignored," and ECC error processing continues as if no ECC error was encountered (i.e., no error flags are asserted, no error handling occurs, etc.). In the case of a write, only one memory access is required (via path 310-315) rather than having to perform an RMW (via one or more of paths 330-335, 340-345, 378).

[0028] In one embodiment, the address range comparator(s) 390 compare memory access addresses sent to the memory transaction queue with one or more addresses stored in registers of the ECC-free address range 395, which define the boundaries of one or more ECC-free regions in memory. In response to the address range comparator(s) 390 comparison, an ECC transaction enable signal is selectively asserted to the path(s) used by the memory transaction queue to send data to the memory interface depending on whether or not ECC techniques should be applied.

[0029] During read operations, ECC data checking circuits 380 and error handling circuits 385 operate to selectively use ECC data as described above. In some situations, data read from memory may be combined for rewrite operations by per-byte write data combining circuits 370.

[0030] Fig. Figure 4 is a flowchart of a technique for the selective use of ECC techniques. The technique of Fig. 4 can be used to provide a memory allocation that corresponds to the Fig. 1 and can be made, for example, using the arrangement of Fig. 3 are supported.

[0031] A memory address corresponding to a memory access is received, 410. This memory address may be received in any manner known in the art. In the example of Fig. 3, the memory address is received and compared in the memory subsystem; however, other configurations may also be supported.

[0032] The memory address is compared to one or more ECC-free regions, 420. In one embodiment, the memory subsystem includes two or more registers used to define the boundaries of one or more ECC-free regions; however, other configurations may also be supported. In the example of Fig. 3, the memory address is received and compared in the memory subsystem; however, other configurations may also be supported.

[0033] If the address corresponds to an ECC-free region, 430, a path through the memory subsystem that does not apply ECC protection is selected, 440. As described above with respect to Fig. 3, one or more paths through the memory subsystem may be provided that do not utilize ECC protection. In one embodiment, the comparison circuits control an enable signal to determine whether or not ECC protection is applied.

[0034] The non-ECC-protected data is written to memory, 450. The memory can be any type of memory, such as DDR-3 or DDR-4 compliant memory. Other memory types can be supported similarly.

[0035] If the address does not correspond to an ECC-free region, 430, a path through the memory subsystem that applies ECC protection is selected, 445. As described above with respect to Fig. 3, one or more paths may be provided through the memory subsystem that utilizes ECC protection. In one embodiment, the comparison circuits control an enable signal to determine whether or not ECC protection is applied.

[0036] ECC protection is applied to the data, 455. All state-of-the-art ECC techniques can be supported. The protected ECC data is written to the memory, 465. The memory can be any type of memory, such as DDR-3 or DDR-4 compliant memory. Other memory types can be supported similarly.

[0037] This results in more efficient use of available memory bandwidth, reducing the average latency for each memory transaction, and increasing the total memory bandwidth available to each application. The identification of ECC-free regions can be achieved through mechanisms other than address range mapping. For example, specific application streams (e.g., video or graphics pixel updates) can be marked in such a way that the memory subsystem selects the ECC-free path for transactions originating from those application sources. Using hybrid error-correcting code (ECC) techniques. A memory access request having an associated address is received. A memory controller determines whether the address corresponds to a first region of memory for which ECC techniques are applied or a second region of memory for which ECC techniques are not applied.The memory access is processed using ECC techniques when the address corresponds to the first region of the memory, and it is processed without using the ECC techniques when the address corresponds to the second region of the memory.

[0038] The memory access request may be a read request. The memory access request includes a write request. The second part of the memory addresses may be configurable. The second part of the memory addresses may be used to store graphics data. The second part of the memory addresses may be located in a dedicated memory region. The memory devices may be dynamic random access memory (DRAM) devices.

[0039] A system may be used, wherein the system may include memory devices to provide data storage corresponding to a range of memory addresses. A first portion of the memory addresses are protected by an ECC technique, and a second portion of the memory addresses are not protected by the ECC technique. A memory controller may be coupled to the memory devices. The memory controller may have a plurality of processing paths. A first set of the processing paths applies the ECC technique to data, and a second set of the processing paths causes the data to be stored without applying the ECC technique. The memory controller selectively applies the ECC technique based on an address corresponding to a memory access request.

[0040] The memory access request may be a read request. The memory access request may include a write request. The second part of the memory addresses may be configurable. The second part of the memory addresses may be used to store graphics data. The second part of the memory addresses may be located in a dedicated memory region. The memory devices may be DRAM devices.

[0041] A memory control circuit may include a first interface for communicating with processing circuitry, and a second interface for communicating with memory devices and control circuitry coupled to the first interface and the second interface. The control circuitry receives a memory access request having an associated address via the first interface, determines whether the address corresponds to a first region of memory for which ECC techniques are applied or a second region of memory for which ECC techniques are not applied, processes the memory access using ECC techniques if the address corresponds to the first region of memory, and processes the memory access without using ECC techniques if the address corresponds to the second region of memory.

[0042] The memory access request may be a read request. The memory access request may include a write request. The second part of the memory addresses may be configurable. The second part of the memory addresses may be used to store graphics data. The second part of the memory addresses may be located in a dedicated memory region. The memory devices may be DRAM devices.

[0043] References in the specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The use of the phrase "in one embodiment" in various places in the specification does not necessarily all refer to the same embodiment.

Claims

[1] System (200) comprising: Memory devices (220) for providing data storage corresponding to a range of memory addresses, wherein a first portion (110, 130) of the memory addresses is protected by an error correction code, ECC, technique and a second portion (120) of the memory addresses is not protected by the ECC technique; a memory controller coupled to the memory devices (220), the memory controller having a plurality of processing paths, and wherein a first set (330-335) of the processing paths operates to apply the ECC technique to data, and a second set (310-315) of the processing paths operates to cause the data to be stored without the ECC technique, and wherein the memory controller selectively applies the ECC technique based on an address corresponding to a memory access request, characterized by , that the memory access request comprises a read request in the second part (120) of the memory addresses, and ECC data returned in a corresponding memory read operation in the second part (120) of the memory addresses are ignored, so that ECC error handling is performed as if no ECC error had occurred. [2] The system (200) of claim 1, wherein the memory access request comprises a write request. [3] The system (200) of claim 1, wherein the second portion (120) of the memory addresses is configurable. [4] The system (200) of claim 1, wherein the second portion (120) of the memory addresses is used to store graphics data. [5] The system (200) of claim 1, wherein the second portion (120) of the memory addresses is located in an allocated memory region. [6] The system (200) of claim 1, wherein the memory devices (220) comprise dynamic random access memory, DRAM, devices. [7] Method comprising: receiving (410) a memory access request having a linked address; determining (420, 430) whether the address corresponds to a first region (110, 130) of a memory for which error correction code, ECC, techniques are applied or a second region (120) of the memory for which no ECC techniques are applied; processing (445, 455, 465) the memory access using ECC techniques when the address corresponds to the first region (110, 130) of the memory; processing (440, 450) the memory access without using the ECC techniques if the address corresponds to the second region (120) of the memory, characterized by , that memory access without using ECC techniques involves a read operation in which returned ECC data is ignored, so that ECC error handling is performed as if no ECC error had occurred. [8] The method of claim 7, wherein the memory access comprises a write operation. [9] The method of claim 7, wherein determining (420, 430) whether the address corresponds to the first region (110, 130) of the memory for which ECC techniques are applied or to the second region (120) of the memory for which no ECC techniques are applied comprises comparing (420) the address with at least two addresses stored in registers corresponding to boundaries of the second region (120) of the memory. [10] The method of claim 7, wherein processing the memory access request comprises selecting one of a plurality of paths by a memory controller according to whether or not ECC techniques are applied to the memory access. [11] The method of claim 7, wherein the second region (120) of memory addresses is used to store graphics data. [12] The method of claim 7, wherein the second region (120) of memory addresses is located in a dedicated memory region. [13] Device (200) comprising: a first interface to communicate with processing circuits; a second interface to communicate with storage devices (220); Control circuits coupled to the first interface and the second interface, wherein the control circuits receive a memory access request having an associated address via the first interface to determine whether the address corresponds to a first region (110, 130) of a memory for which ECC techniques are applied or a second region (120) of the memory for which no ECC techniques are applied, to process the memory access using ECC techniques if the address corresponds to the first region (110, 130) of the memory, and to process the memory access without using the ECC techniques if the address corresponds to the second region (120) of the memory, characterized by , that the processing of memory access without using ECC techniques involves a read operation in which returned ECC data is ignored, so that ECC error handling is performed as if no ECC error had occurred. [14] The apparatus (200) of claim 13, wherein determining whether the address corresponds to the first region (110, 130) of memory for which ECC techniques are applied or a second region (120) of memory for which no ECC techniques are applied comprises comparing the address to at least two addresses stored in registers corresponding to boundaries of the second region of memory. [15] The apparatus (200) of claim 13, wherein processing the memory access request comprises selecting one of a plurality of paths by a memory controller according to whether or not ECC techniques are applied for the memory access. [16] The apparatus (200) of claim 13, wherein the second region (120) of memory addresses is used to store graphics data. [17] The apparatus (200) of claim 13, wherein the memory devices (220) comprise dynamic random access memory, DRAM, devices. [18] The apparatus (200) of claim 17, wherein the DRAM devices comprise DDR4 compliant devices.

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