Moving change log table to align with partition

Abstract

The present disclosure generally relates to a method of operating a storage device. The storage device is comprised of a controller, a random access memory (RAM) unit, and an NVM unit, where the NVM unit is comprised of a plurality of partitions. The RAM unit includes a first logical-to-physical address table, and the NVM unit includes a second logical-to-physical address table. The partitions are divided into segments, and each divided segment is aligned with a change log table. Data is written in order into each partition, and only one divided segment of each partition is updated at a time. Each time a partition is erased or written in the NVM unit, the first logical-to-physical address table is updated, and the second logical-to-physical address table is periodically updated to match the first logical-to-physical address table.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Application No. 16 / 883,901, filed May 26, 2020, the entire contents of which are incorporated herein by reference. Background Technology Technical Field

[0003] The embodiments disclosed herein relate generally to storage devices, such as solid-state drives (SSDs).

[0004] Description of related fields

[0005] Storage devices such as SSDs are used in computers for applications requiring relatively low latency and high capacity storage. For example, SSDs can exhibit lower latency than hard disk drives (HDDs), especially for random reads and writes. Typically, an SSD's controller receives commands to read data from a host device or write data to the storage device. Data is read and written to one or more erase blocks in the storage device. When a write command is received, the data associated with the write command has a logical block address (LBA). A logical-to-physical address (L2P) table stored in the SSD's volatile memory associates one or more LBAs of the data with the physical address stored in the SSD at the time the data is written. The L2P table is updated whenever data is erased from the SSD to point to a sentinel value (e.g., "empty"), such as during a garbage collection operation.

[0006] However, data can be written to any physical location within the storage device, and the L2P table is updated sequentially as commands are received. Therefore, when data is erased from a physical location on the storage device, several sentinel values ​​may be included in the L2P table in an misaligned or discontinuous manner. Since volatile memory can be lost or erased in the event of a power outage, a copy of the L2P table is also stored on the storage device. The L2P table on the SSD must be periodically updated in the change log to match the L2P table stored in volatile memory to prevent data loss. Because the change log size of the L2P table is the same as the partition size, the change log of the entire L2P table stored on the storage device can be updated, which is a burden on the SSD. Furthermore, in the event of a power outage, a portion of the L2P table in volatile memory is programmed or copied to the L2P table stored on the storage device, which may result in a significant amount of time being spent writing "empty" data instead of using time for more important information about the current data storage location.

[0007] Therefore, a new approach is needed to improve power-loss protection of change logs in storage devices. Summary of the Invention

[0008] This disclosure relates throughout to a method of operating a storage device. The storage device comprises a controller, random access memory (RAM) cells, and an NVM cell, wherein the NVM cell comprises multiple partitions. The RAM cells include a first logical-to-physical address table, and the NVM cell includes a second logical-to-physical address table. These partitions are divided into segments, and each segment is aligned with a change log table. Data is written sequentially to each partition, and only one segment is updated per partition at a time. Each time a partition is erased or written to in the NVM cell, the first logical-to-physical address table is updated, and the second logical-to-physical address table is periodically updated to match the first logical-to-physical address table.

[0009] In one embodiment, the storage device includes non-volatile memory cells. The capacity of the non-volatile memory cells is divided into multiple partitions. The non-volatile memory cells include multiple dies, and each die includes multiple erase blocks. The storage device further includes volatile memory cells. The volatile memory cells store a first logical-to-physical address table. The first logical-to-physical address table associates logical block addresses of data with physical addresses where the data is stored in the non-volatile memory cells. The storage also includes a controller coupled to the non-volatile memory cells and the volatile memory cells. The controller is configured to sequentially write data to each partition of the multiple partitions and to divide the first logical-to-physical address table into segments. The size of each segment is aligned with a change log table. The controller is further configured to update a second logical-to-physical address table stored in the non-volatile memory cells. The second logical-to-physical address table is updated according to the segment size.

[0010] In another embodiment, the storage device includes non-volatile memory cells. The capacity of the non-volatile memory cells is divided into multiple partitions. The non-volatile memory cells include multiple dies, and each die includes multiple erase blocks. The storage device also includes volatile memory cells. The storage device further includes a controller coupled to the non-volatile memory cells and the volatile memory cells. The controller is configured to sequentially write data associated with one or more commands to a first partition of the multiple partitions, wherein each partition of the multiple partitions is divided into multiple segments, the segment size being aligned with a change log table. The controller is further configured to update a first logical-to-physical address table stored in the volatile memory cells. The controller is also configured to update the first logical-to-physical address table, which associates logical block addresses of data associated with one or more commands with physical addresses of the data associated with one or more commands stored in the first partition. The controller is further configured to erase the data associated with one or more commands from the first partition and update the first logical-to-physical address table to indicate that the first partition is empty. The controller is also configured to update a second logical-to-physical address table stored in non-volatile memory cells to match the first logical-to-physical address table. The second logical-to-physical address table is updated according to the segment size.

[0011] In another embodiment, the storage device includes non-volatile memory cells. The capacity of the non-volatile memory cells is divided into multiple partitions. The non-volatile memory cells further include multiple dies, and each die includes multiple erase blocks. The storage device also includes volatile memory cells. The volatile memory cells store a first logical-to-physical address table. The first logical-to-physical address table associates logical block addresses of data with physical addresses where the data is stored in the non-volatile memory cells. Furthermore, the storage device includes: means for dividing each of the multiple partitions into multiple segments, wherein each segment is aligned with a change log table; and means for updating the segment of the partition each time a command to write data to the partition is received. The storage device further includes means for updating the first logical-to-physical address table each time data is erased from the non-volatile memory cells. Data erased from the non-volatile memory cells is performed according to partition capacity. The storage device includes means for updating a second logical-to-physical address table stored in the non-volatile memory cells to match the first logical-to-physical address table. The second logic updates the physical address table according to the segment size. Attached Figure Description

[0012] Therefore, a detailed understanding of the foregoing features of this disclosure, a more specific description of this disclosure, and the foregoing brief overview can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of this disclosure and should therefore not be considered as limiting its scope, as this disclosure allows for other equally effective embodiments.

[0013] Figure 1 This is a schematic block diagram illustrating a storage system according to one implementation scheme.

[0014] Figure 2 This is a block diagram illustrating a method for operating a storage device to execute read or write commands according to one embodiment.

[0015] Figure 3A This illustrates a partition namespace used in a storage device according to one implementation scheme.

[0016] Figure 3B Showing a target according to one implementation scheme Figure 3A A state diagram of the partition namespace of the storage device.

[0017] Figure 4 This is a schematic block diagram illustrating a storage system according to another embodiment.

[0018] Figure 5 This illustrates a storage device, according to one implementation, divided into partitions of change log segments.

[0019] For ease of understanding, the same reference numerals are used where possible to denote the same elements common in the accompanying drawings. It is conceivable that elements disclosed in one embodiment may be advantageously used in other embodiments without specific description. Detailed Implementation

[0020] In the following text, reference is made to embodiments of this disclosure. However, it should be understood that this disclosure is not limited to the specifically described embodiments. Rather, consider any combination of the following features and elements (whether or not related to different embodiments) to achieve and practice this disclosure. Furthermore, while embodiments of this disclosure may achieve advantages over other possible solutions and / or over the prior art, achieving a particular advantage through a given embodiment is not a limitation of this disclosure. Therefore, the following aspects, features, embodiments, and advantages are illustrative only and should not be considered elements or limitations of the appended claims unless expressly stated in the claims. Similarly, reference to “this disclosure” should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered elements or limitations of the appended claims unless expressly stated in the claims.

[0021] This disclosure relates throughout to a method of operating a storage device. The storage device comprises a controller, random access memory (RAM) cells, and an NVM cell, wherein the NVM cell comprises multiple partitions. The RAM cells include a first logical-to-physical address table, and the NVM cell includes a second logical-to-physical address table. These partitions are divided into segments, and each segment is aligned with a change log table. Data is written sequentially to each partition, and only one segment is updated per partition at a time. Each time a partition is erased or written to in the NVM cell, the first logical-to-physical address table is updated, and the second logical-to-physical address table is periodically updated to match the first logical-to-physical address table.

[0022] Figure 1 This is a schematic block diagram illustrating a storage system 100 according to one or more technologies of the present disclosure, wherein storage device 106 can be used as a storage device for host device 104. For example, host device 104 can utilize storage cells 110 (such as non-volatile memory (NVM)) included in data storage device 106 to store and retrieve data. In the following description, for simplicity, non-volatile storage cells may be referred to as non-volatile memory (NVM). Host device 104 includes host DRAM 138. In some examples, storage system 100 may include multiple storage devices, such as storage device 106, that can operate as a storage array. For example, storage system 100 may include multiple storage devices 106 configured to collectively serve as a low-cost / independent disk (RAID) redundant array of mass storage devices for host device 104.

[0023] Storage system 100 includes host device 104, which can store data to and / or retrieve data from one or more storage devices, such as storage device 106. Figure 1 As shown, host device 104 can communicate with storage device 106 via interface 114. Host device 104 can include any of a variety of devices, including computer servers, network attached storage (NAS) units, desktop computers, laptops, tablets, set-top boxes, mobile phones such as so-called "smart" phones, so-called "smart" tablets, televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, etc.

[0024] Storage device 106 includes a controller 108, an NVM 110, a power supply 111, a first random access memory (RAM) or volatile memory 112, such as dynamic random access memory (DRAM), and an interface 114. The controller 108 may include a parity check engine or XOR engine 124 and a second RAM or volatile memory 118, such as static random access memory (SRAM). XOR engine 124 is a parity check engine and is referred to as an XOR engine for illustrative purposes. However, XOR engine 124 may include other embodiments of parity check engines. In the following description, for simplicity and illustrative purposes, the first RAM or volatile memory 112 may be referred to as DRAM memory, and the second RAM or volatile memory 118 may be referred to as SRAM memory.

[0025] In some examples, for clarity, storage device 106 may include Figure 1 Additional components not shown. For example, storage device 106 may include a printed circuit board (PCB) to which components of storage device 106 are mechanically attached, and the PCB includes conductive traces for electrically interconnecting components of storage device 106, etc. In some examples, the physical dimensions and connector configuration of storage device 106 may conform to one or more standard form factors. Some exemplary standard form factors include, but are not limited to, 2.5″ data storage devices (e.g., HDDs or SSDs), 1.8″ data storage devices, peripheral component interconnects (PCI), PCI expansion (PCI-X), PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini cards, MiniPCI, etc.). In some examples, storage device 106 may be directly coupled (e.g., directly soldered) to the motherboard of host device 104.

[0026] The interface 114 of storage device 106 may include one or both of a data bus for exchanging data with host device 104 and a control bus for exchanging commands with host device 104. Interface 114 may operate according to any suitable protocol. For example, interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI, PCIe, Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Compute Fast Link (CXL), Open Channel SSD (OCSSD), etc. Electrical connections (e.g., data bus, control bus, or both) of interface 114 are electrically connected to controller 108, thereby providing an electrical connection between host device 104 and controller 108, allowing data exchange between host device 104 and controller 108. In some examples, the electrical connection of interface 114 can also allow storage device 106 to receive power from host device 104. For example, as Figure 1 As shown, power supply 111 can receive power from host device 104 via interface 114.

[0027] Storage device 106 includes NVM 110, which may include multiple memory devices. NVM 110 can be configured to store and / or retrieve data. For example, the memory devices of NVM 110 can receive data and messages instructing the memory devices to store data from controller 108. Similarly, the memory devices of NVM 110 can receive messages instructing the memory devices to retrieve data from controller 108. In some examples, each memory device in the memory device may be referred to as a die. In some examples, a single physical chip may include multiple dies (i.e., multiple memory devices). In some examples, each memory device in the memory device may be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 412MB, 1GB, 2GB, 3GB, 8GB, 16GB, 22GB, 54GB, 128GB, 256GB, 412GB, 1TB, etc.).

[0028] In some examples, each memory device of the NVM 110 may include any type of non-volatile memory device, such as flash memory devices, phase-change memory (PCM) devices, resistive random access memory (ReRAM) devices, magnetoresistive random access memory (MRAM) devices, ferroelectric random access memory (F-RAM) devices, holographic memory devices, hard disk drives (HDDs), and any other type of non-volatile memory device.

[0029] NVM 110 may include multiple flash memory devices. These flash memory devices may be NAND- or NOR-based and may store data based on the charge contained in the floating gate of the transistors used for each flash memory cell. In a NAND flash memory device, the flash memory device may be divided into multiple blocks, which may be further divided into multiple pages. Each block within a particular memory device may include multiple NAND cells. Rows of NAND cells may be electrically connected using word lines to define pages within the multiple pages. A corresponding cell within each page may be electrically connected to a corresponding bit line. Furthermore, the NAND flash memory device may be a 2D or 3D device and may be a single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), or other higher-level cell iterations. Controller 108 may write data to and read data from the NAND flash memory device at the page level and erase data from the NAND flash memory device at the block level.

[0030] A portion of the NVM 110 can be formatted as logical blocks, such that the capacity of the NVM 110 is divided into multiple partitions or multiple streams. Each partition or each stream comprises multiple physical blocks or erase blocks of the NVM 110, and each erase block within an erase block is associated with multiple logical blocks. Each logical block within an logical block is associated with a unique LBA or sector. Each partition or each stream may have a size aligned with the capacity of one or more erase blocks of the NVM 110. When the controller 108 receives a command from, for example, a host device 104, the controller 108 can read data from and write data to the multiple logical blocks associated with the multiple erase blocks of the NVM 110.

[0031] Storage device 106 includes a power supply 111 that can provide power to one or more components of storage device 106. When operating in standard mode, power supply 111 can use power provided by an external device such as host device 104 to power one or more components. For example, power supply 111 can use power received from host device 104 via interface 114 to power one or more components. In some examples, power supply 111 may include one or more power storage components configured to power one or more components when operating in a shutdown mode, such as when power is stopped from receiving power from external devices. In this way, power supply 111 can be used as an onboard backup power source. Some examples of one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, etc. In some examples, the amount of electricity that can be stored by one or more power storage components can be a function of the cost and / or size (e.g., area / volume) of one or more power storage components. In other words, as the amount of electricity stored by one or more power storage components increases, the cost and / or size of one or more power storage components also increases.

[0032] Storage device 106 also includes volatile memory that can be used by controller 108 to store information. The volatile memory may include one or more volatile memory devices. In some examples, controller 108 may use the volatile memory as a cache. For example, controller 108 may store cached information in the volatile memory until the cached information is written to NVM 110. Examples of volatile memory 112 include, but are not limited to, RAM, DRAM 112, SRAM 118, and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, DDR5, LPDDR5, etc.)). Figure 1 As shown, the volatile memory can consume power received from power supply 111.

[0033] Different types of volatile memory can use different access attributes. For example, DRAM 112 can be configured for longer burst accesses to allow for improved bandwidth (BW) on the same access bus. Alternatively, DRAM 112 can be used for smaller accesses, so that random small accesses can have better latency. Controller 108 includes additional optional SRAM and / or embedded MRAM 126. Embedded MRAM 126 is another alternative memory that can be used in another implementation. Similarly, access to MRAM 126 can be optimized for different design purposes, but the number of embedded MRAM 126 in SSD controller 108 may be cost-sensitive. Therefore, the selection of how much data and which data goes into advanced non-volatile memory and advanced volatile memory will be subject to system trade-offs.

[0034] Storage device 106 includes a controller 108 that can manage one or more operations of storage device 106. For example, controller 108 can manage reading data from NVM 110 and / or writing data to NVM via a switching mode (TM) bus 128. Controller 108 may include an XOR engine 124. Data may be stored in DRAM 112, SRAM 118, or both DRAM 112 and SRAM 118. In some embodiments, when storage device 106 receives a write command from host device 104, controller 108 can initiate a data storage command to store data in NVM 110 and monitor the progress of the data storage command. Controller 108 can determine at least one operating characteristic of storage system 100 and store at least one operating characteristic in NVM 110.

[0035] Figure 2 This is a block diagram illustrating a method 200 for operating a storage device to execute read or write commands according to one embodiment. Method 200 can be used with a storage system 100 having a host device 104 and a storage device 106 including a controller 108. Method 200 can also be used with a device having a host device and a storage device including an command processor.

[0036] Method 200 begins with operation 250, in which the host device writes commands as entries to a commit queue. At operation 250, the host device may write one or more commands to the commit queue. Commands can be read or write commands. The host device may include one or more commit queues. The host device may write one or more commands to the commit queue in any order (i.e., commit order), regardless of the order in which the commands are written (i.e., the order in which they are processed).

[0037] In operation 252, the host device writes one or more updated commit queue tail pointers and rings a doorbell or sends an interrupt signal to notify or signal the storage device that a new command is ready to be executed. If there is more than one commit queue, the host may write updated commit queue tail pointers and send a doorbell or interrupt signal for each commit queue. In operation 254, in response to receiving a doorbell or interrupt signal, the storage device's controller retrieves a command from one or more commit queues, and the controller receives or the DMA reads the command.

[0038] In operation 256, the controller processes a command and writes or transfers the data associated with that command to the host device memory. The controller can process more than one command at a time. The controller can process one or more commands in commit order or sequential order. Processing a write command may include: identifying the partition for which the data associated with the command is to be written, writing the data to one or more logical block addresses (LBAs) of that partition, and advancing the write pointer of that partition to identify the next available LBA within that partition.

[0039] In operation 258, once the command has been fully processed, the controller writes the completion entry corresponding to the executed command to the completion queue of the host device and moves or updates the CQ head pointer to point to the newly written completion entry.

[0040] In operation 260, the controller generates an interrupt signal or doorbell signal and sends it to the host device. The interrupt signal indicates that the command has been executed and the data associated with the command is available in the memory device. The interrupt signal further notifies the host device that the completion queue is ready to be read or processed.

[0041] In operation 262, the host device processes the completion entry. In operation 264, the host device writes the updated CQ header pointer to the storage device and rings the doorbell or sends an interrupt signal to the storage device to release the completion entry.

[0042] Figure 3A A partition namespace (ZNS) 302 view used in storage device 300 according to one embodiment is shown. Storage device 300 can present the ZNS 302 view to a host device. Figure 3B A state diagram 350 of ZNS 302 of storage device 300 according to one embodiment is shown. Storage device 300 may be Figure 1 The storage system 100 includes storage device 106. Storage device 300 may have one or more ZNS 302, and each ZNS 302 may have a different size. In addition to the one or more partition namespaces 302, storage device 300 may further include one or more general namespaces. Furthermore, ZNS 302 may be a partition block command (ZBC) for SAS and / or a partition device ATA command set (ZAC) for SATA. Due to the possible relationship between logical and physical activities, host-side partitioning activity may be more directly related to media activity within the partition drive.

[0043] In storage device 300, ZNS 302 is the number of NVMs that can be formatted into logical blocks so that the capacity is divided into multiple partitions 306a-306n (collectively referred to as partition 306). NVMs can be... Figure 1The storage cells or NVM 110. Each partition in partition 306 includes multiple physical blocks or erase blocks (not shown) of the storage cells or NVM 304, and each erase block is associated with multiple logical blocks (not shown). Each partition in partition 306 may have a size aligned with the capacity of one or more erase blocks of the NVM or NAND device. When controller 308 receives a command from a host device (not shown) or a host device's submission queue, controller 308 may read data from and write data to the multiple logical blocks associated with the multiple erase blocks (EB) of ZNS 302. Each logical block is associated with a unique LBA or sector.

[0044] In one implementation, NVM 304 is a NAND device. The NAND device includes one or more dies. Each of the one or more dies includes one or more planes. Each of the one or more planes includes one or more erase blocks. Each of the one or more erase blocks includes one or more word lines (e.g., 256 word lines). Each of the one or more word lines can be addressed in one or more pages. For example, an MLC NAND die can use the top and bottom pages to reach two bits in each cell of the entire word line (e.g., 16 KiB per page). Furthermore, each page can be accessed at a granularity equal to or smaller than a full page. The controller can frequently access NAND with a user data granularity LBA size of 512 bytes. Therefore, as mentioned in the description below, the NAND location is equal to a granularity of 512 bytes. Thus, the LBA size is 512 bytes and the page size of the two pages of the MLC NAND is 16 KiB, resulting in 32 LBAs per word line. However, the NAND location size is not intended to be limiting and is only used as an example.

[0045] When data is written to an erase block, one or more logical blocks within partition 306 are updated accordingly to track the data's location within NVM 304. Data can be written to one partition 306 at a time until partition 306 is full, or to multiple partitions 306 such that multiple partitions 306 may become partially full. Similarly, when data is written to a particular partition 306, the data can be written block by block at a time, page by page or word by word, in NAND position order, until moving to an adjacent block (i.e., writing to the first erase block until the first erase block becomes full before moving to the second erase block), or it can be written in multiple blocks at a time, page by page or word by word, to partially fill each block in a parallel manner (i.e., writing to the first NAND position or page of each erase block before writing to the second NAND position or page of each erase block). This sequential programming of each NAND position is a typical non-restrictive requirement for many NAND EBs.

[0046] When controller 308 selects an erase block to store data for each partition, it can select the erase block during the partition's open time, or it can select the erase block when the first word line of that particular erase block needs to be filled. This can be even more significant when using the method described above, which involves fully filling an erase block before starting the next erase block. Controller 308 can use this time difference to select a more optimized erase block on an on-the-fly basis. The decision of which erase block is allocated and assigned to each partition and its consecutive LBAs can occur continuously within controller 308 for zero or more concurrent partitions.

[0047] Each partition in partition 306 is associated with a partition start logical block address (ZSLBA) or a partition start sector. The ZSLBA is the first available LBA in partition 306. For example, the first partition 306a is associated with ZSLBA. a SLBA is associated with the second partition 306b and Z. b SLBA is associated with the third partition 306c and Z. c SLBA is associated with the fourth partition 306d and Z. d SLBA is associated, and the nth partition 306n (i.e., the last partition) is associated with Z. n SLBAs are associated. Each partition 306 is identified by its ZSLBA and is configured to receive sequential writes (i.e., data is written to the NVM 110 in the order in which write commands are received).

[0048] When data is written to partition 306, the write pointer 310 is advanced or updated to point to or indicate the next available block in partition 306 for writing data, in order to track the next write start point (i.e., the completion point of a previous write is equal to the start point of a subsequent write). Therefore, the write pointer 310 indicates where subsequent writes to partition 306 will begin. A subsequent write command is a "partition append" command, in which the data associated with the subsequent write command is appended to partition 306 at the location indicated by the write pointer 310 as the next start point. A sorted list of LBAs within partition 306 can be stored for write sorting. Each partition 306 can have its own write pointer 310. Therefore, when a write command is received, the partition is identified by its ZSLBA, and the write pointer 310 determines the position where the writing of data within the identified partition begins.

[0049] Figure 3B Showing targets Figure 3A State diagram 350 of ZNS 302. In state diagram 350, each partition can be in different states, such as empty, active, full, or offline. When a partition is empty, it contains no data (i.e., any erase blocks in the partition do not currently store data), and the write pointer is at ZSLBA (i.e., WP = 0). Once a write is made to the partition scheduler or a partition open command is issued by the host, the empty partition will switch to an open and active partition. Partition Management (ZM) commands can be used to move partitions between the partition open and partition closed states (both active states). If a partition is active, it includes writable open blocks and can provide the host with a description of the recommended time in the active state. Controller 308 includes ZM. Partition metadata can be stored in ZM and / or controller 308.

[0050] The term "write" includes programming user data in zero or more NAND locations within an erase block and / or in some filled NAND locations within an erase block before all available NAND locations have been filled. The term "write" may also include moving a partition to full due to: internal drive processing needs (due to open block data retention issues caused by erroneous bits accumulating faster on open erase blocks), storage device 300 closing or filling a partition due to resource constraints (such as too many open partitions to trace or a discovered defective state), or host device closing a partition due to issues such as no more data to send to the drive, computer shutdown, error handling on the host, limited host resources for tracing, etc.

[0051] Active partitions can be open or closed. An open partition is an empty or partially full partition that is ready to be written to and has currently allocated resources. Data received from the host device using write commands or partition append commands can be programmed into an open erase block that is not currently filled with previously filled data. A closed partition is an empty or partially full partition that is not currently receiving continuous writes from the host. Moving a partition from an open state to a closed state allows the controller 308 to reallocate resources to other tasks. These tasks may include, but are not limited to, other open partitions, other regular non-partitioned areas, or other controller requirements.

[0052] In open and closed partitions, the write pointer points to a position within the partition between the end of the ZSLBA and the end of the partition's last LBA (i.e., WP > 0). The active partition can switch between open and closed states as specified by ZM, or this switching occurs when writes are scheduled to the partition. Additionally, ZM can reset the active partition to clear or erase the data stored in it, causing the partition to switch back to an empty partition. Once the active partition is full, it switches to a full state. A full partition is one completely filled with data, and there are no more available sectors or LBAs for writing data (i.e., WP = partition capacity (ZCAP)). In a full partition, the write pointer points to the end of the partition's writable capacity. Read commands for data stored in a full partition can still be executed.

[0053] Partitions can have any total capacity, such as 256 MiB or 512 MiB. However, a small portion of each partition may be inaccessible for writing data but still readable, such as the portion of each partition storing XOR data and one or more excluded erase blocks. For example, if partition 306 has a total capacity of 512 MiB, then the ZCAP might be 470 MiB, which is the capacity available for writing data, while 42 MiB is unavailable for writing data. The writable capacity (ZCAP) of a partition is equal to or less than the total partition storage capacity. Storage device 300 can determine the ZCAP of each partition when a partition is reset. For example, controller 308 or ZM can determine the ZCAP of each partition. When a partition is reset, storage device 300 can determine the ZCAP of that partition.

[0054] ZM can reset a full partition, thereby scheduling the erasure of data stored in that partition and causing it to switch back to an empty partition. When resetting a full partition, although the partition may be marked as an empty partition available for writing, the data on that partition may not be immediately erased. However, the reset partition must be erased before switching to open and active partitions. Partitions can be erased at any time between a ZM reset and a ZM open. When resetting a partition, storage device 300 can determine the new ZCAP of the reset partition and update the writable ZCAP attribute in the partition metadata. An offline partition is a partition where data cannot be written. An offline partition can be full, empty, or partially full but not active.

[0055] Since resetting a partition erases all data stored in the partition or schedules the erasure of all data stored in the partition, the need for garbage collection of individual erase blocks is eliminated, thus improving the overall garbage collection process of storage device 300. Storage device 300 may mark one or more erase blocks for erasure. When a new partition is about to be formed and storage device 300 anticipates ZM opening, one or more erase blocks marked for erasure may be erased. Storage device 300 may further determine and create the physical support for the partition when erasing the erase block. Therefore, once a new partition is opened and an erase block is selected to form the partition, that erase block will be erased. Furthermore, each time a partition is reset, a new LBA and write pointer 310 order for partition 306 may be selected, allowing partition 306 to tolerate out-of-order command reception. Write pointer 310 may optionally be turned off, allowing commands to be written to any starting LBA indicated by the command.

[0056] Re-reference Figure 3A When the host sends a write command to write data to partition 306, controller 308 pulls the write command in and identifies it as a write to the newly opened partition 306. Controller 308 selects a set of exponents (EBs) to store the data associated with the write command to the newly opened partition 306, and the newly opened partition 306 becomes the active partition 306. The write command can be a command to write new data or a command to move valid data to another partition for garbage collection purposes. Controller 308 is configured to read new commands from a commit queue filled by the host device via DMA.

[0057] In the empty partition 306 that has just been switched to active partition 306, data is assigned to partition 306 and a set of associated sequential LBAs starting from the ZSLBA of partition 306, as the write pointer 310 indicates the logical block associated with the ZSLBA as the first available logical block. This data can be written to one or more erase blocks or to a NAND location already allocated for the physical location of partition 306. After the data associated with the write command is written to partition 306, the write pointer 310 is updated to point to the next LBA available for host writes (i.e., the completion point of the first write). The write data from this host write command is sequentially programmed into the next available NAND location in the erase block selected for partitioning based on the physical support.

[0058] For example, controller 308 may receive a first write command or a first partition append command to third partition 306c. The host sequentially identifies which logical block of partition 306 is used to write the data associated with the first command. The data associated with the first command is then written to the first or next available LBA in third partition 306c as indicated by write pointer 310, and write pointer 310 is advanced or updated to point to the next available LBA available for host write (i.e., WP > 0). If controller 308 receives a second write command or a second partition append command to third partition 306c, the data associated with the second write command is written to the next available LBA in third partition 306c identified by write pointer 310. Once the data associated with the second command has been written to third partition 306c, write pointer 310 is again advanced or updated to point to the next available LBA available for host write. Resetting third partition 306c moves write pointer 310 back to Z. c SLBA (i.e., WP=0), and the third partition 306c is switched to an empty partition.

[0059] Figure 4 This is a schematic block diagram illustrating a storage system 400 according to one embodiment. In the following description, for simplicity and illustrative purposes, the non-volatile storage unit 404 is referred to as an NVM. System 400 includes a host 402, a storage device 406, and an NVM 404. The host 402 may be... Figure 1 The host 104. Additionally, NVM 404 can be... Figure 1 NVM 110 and / or Figure 3A The NVM 310.

[0060] Figure 4 Storage device 406 is an SSD 406. SSD 406 can be storage device 106 or... Figure 3AStorage device 300. SSD 406 is an example of a possible implementation of the storage device. Other implementations of the storage device may exist. SSD 406 includes controller 408 and first volatile memory 410, such as DRAM, and other components not shown. Controller 408 may be Figure 1 The controller 108. DRAM 410 can be Figure 1 The first volatile memory 410 may be referred to as DRAM memory in the following description for the purpose of simplification and illustration.

[0061] DRAM 410 includes a first logical-to-physical address (L2P) table 420 and one or more change log tables 430 (referred to as change log tables 430). When SSD 406 receives a command from host 402, the command is associated with a logical block address (LBA). The LBA pointer of the data associated with the command is then associated with the physical location in NVM 404 where the data is stored. Controller 408 is configured to update the first L2P table 420 so that the LBA of the data is associated with the physical location in NVM 404 where the corresponding data is stored using the pointer. The first L2P table 420 is divided into one or more segments (e.g., L2P segments), such as Z0SLBA422, Z1SLBA424, Z2SLBA426, and Z... N SLBA 428, where N represents a variable value of the last L2P segment in the first L2P table 420. Each L2P segment 422, 424, 426, 428 includes one or more LBA pointers pointing from the LBA to the corresponding NAND location or cell (e.g., a 4KiB-sized location) in the partition of NVM 404, where data associated with the LBA is currently being physically stored.

[0062] The first L2P table 420 includes multiple L2P segments. These L2P segments may correspond to partitions within NVM 404, which could be... Figure 3A Partition 306. Since data is written to partitions sequentially, each L2P segment 422, 424, 426, 428 can include multiple sequential pointers for each partition. Therefore, each L2P segment 422, 424, 426, 428 begins with the corresponding partition start logical block address (ZSLBA), such as... Figure 3A Z in area 306c c SLBA.

[0063] Furthermore, when data is written, erased, or updated in the NVM 404, these changes are reflected in the change log table 430 of the corresponding L2P segments 422, 424, 426, and 428. The change log table 430 tracks changes to each L2P segment 422, 424, 426, and 428, and its size is smaller than the L2P segment size (i.e., the change log segment). Then, after certain conditions are met, such as after a predetermined time has elapsed, the change log table 430 is filled, and / or after a power outage event, the change log table 430 is copied to a second L2P table 440 of the NVM 404. In one implementation, if the partition size, such as... Figure 3A The first partition 306a is 512 MiB, and the L2P segments contain approximately 131,072 pointers of size 4B. Therefore, in this implementation, each L2P segment is approximately 512 KiB in size. Since the change log table 430 only tracks changes for each L2P segment, also referred to herein as "Δ", the change log table 430 is approximately 1 KiB in size. The aforementioned values ​​are not intended to be limiting, but rather to provide examples of possible implementations.

[0064] DRAM 410 includes a secondary or optional change log table 432 to track updates to change log table 430. The optional change log table 432 may store pointers to checkpoints in change log table 430, where checkpoints mark the beginning of data not replicated to NVM 404. Additionally, change log table 430 may include the checkpoints themselves. In one embodiment, checkpoints may be located at defined locations such that their locations are always known. Checkpoints may be evenly spaced throughout the optional change log table 432 and / or change log table 430 (i.e., there is the same amount of data between each checkpoint). In another embodiment, the checkpoint locations may not be evenly spaced (i.e., the amount of data differs between each checkpoint). For example, the optional change log table 432 may track the locations of checkpoints scattered throughout change log table 430. DRAM 410 may have one or more optional change log tables 432.

[0065] In another implementation, a separate NVM medium or NVM medium region can be used to track the change log table. A common example is attaching a NOR chip to the controller via an SPI interface, allowing powerful programs to replace the data without garbage collection, at the cost of additional space on the SSD.

[0066] The partition capacity of an NVM 404 can be 256 MiB or 512 MiB, minus the physical capacity lost due to storing parity data, controller metadata, or growth defect errors. Each partition can include multiple erase blocks that constitute the partition capacity. Erase blocks consist of word lines. For example, an erase block for a TLC memory can have 256 word lines, where each word line is 16 KiB / page and each word line consists of three pages. The total size of an erase block for a TLC memory is 256 word lines * 3 pages / word line * 16 KiB / page = 12,288 KiB or 12 MiB minus the space lost for storing metadata. The values ​​used to indicate erase block size and partition capacity are not intended to limit or constrain, but rather to provide examples of possible erase block sizes and possible partition sizes. Figure 3A The ZCAP mentioned in the text may be applicable Figure 4 The partition size. Furthermore, each partition in an NVM 404 can have the same ZCAP or the same size.

[0067] NVM 404 includes multiple partitions (not shown) with the ability to store user data, parity data, and metadata. NVM 404 also includes a second L2P table 440. Because DRAM 410 is a volatile memory cell, a power outage can cause data in DRAM 410 to be flushed to NVM 404, or data in DRAM 410 may be lost. In the event of a power outage, SSD 406 may have one or more capacitors storing sufficient charge to power SSD 406 and program the data in the first L2P table 420 of DRAM 410 to the second L2P table 440 of NVM 404. Furthermore, the power outage infrastructure can update the second L2P table 440 with data from the first L2P table 420 approximately every 20 seconds or approximately three times per minute, such that if a capacitor fails, L2P table 440 can contain current LBA pointer information, or be updated whenever change log table 430 reaches its capacity (i.e., when dedicated change log space, which may be 1 KiB of space, is exhausted). For example, once change log table 430 reaches its capacity, it is replicated to a second L2P table 440 in NVM 404. The previously mentioned update times are for illustrative purposes only and are not intended to limit or constrain the time between updates. The second L2P table 440 is periodically updated to reflect the first L2P table 420. Similar to the first L2P table 420, each L2P segment 442, 444, 446, and 448 of the second L2P table 440 is equal in size to the corresponding partition.

[0068] SSD 406 receives one or more commands from host 402, and these commands are transmitted to controller 408 before being written to NVM 404. Each of the one or more commands determines which partition of NVM 404 the data associated with the write command should be stored. For example, partitions such as Figure 3A The 306a can have multiple word lines or NAND locations available for data. Write pointers, such as... Figure 3A Pointer 310 indicates the first available word line or NAND location within the partition for writing data. When the host receives another write command, the pointer moves to the next available word line or NAND location. Writing data to the NVM 404 is sequential, not random. Furthermore, the first partition of the NVM 404 can be filled to capacity before the second partition is filled, and the second partition can be filled to capacity before the third partition is filled, and so on.

[0069] If word line interleaving occurs (e.g., fog-like fine programming), data will be written sequentially, or partially sequentially, to the first partition (such as...). Figure 3A For each erase block (such as EB0 and EB1) or word line (such as WL0 and WL1) of partition 306a, the LBA segment pointer updates the first L2P table 420 in DRAM 410 using the current position of the data associated with each LBA within the partition. Controller 408 can update the second L2P table 440 approximately every 20 seconds or approximately three times per minute using the information in the first L2P table 420. Furthermore, each time an erase block is written or updated, the LBA pointers associated with the erase block in the first L2P table 420 are updated. For example, if data associated with the first LBA is written to EB0 of the first partition, the pointer associated with EB0 of the first partition in the first L2P table 420 is updated to show that EB0 of the first partition contains the data associated with the first LBA. The second L2P table 440 is updated after a predetermined time to match the first L2P table 420.

[0070] Furthermore, in conventional SSDs that do not utilize ZNS, when data in an erase block is deallocated (e.g., trimmed, erased, or unmapped), pointers point to a sentinel value, such as "empty," indicating that the space previously occupied by the data is empty. An "empty" value can be a sentinel value indicating deallocated data. In the following description, for illustrative purposes, the term "empty" value can be used synonymously with "sentinel value." When data stored in multiple erase blocks is erased, the first L2P table 420 will consist of multiple pointers pointing to "empty." Because the DRAM 410's capabilities are limited when copying "empty" values ​​to the second L2P table 440, "empty" values ​​are difficult to power-loss protected against. To make this process more efficient, "empty" transfers can be prioritized; however, the overall transfer speed from the first L2P table 420 to the second L2P table 440 may still be a bottleneck.

[0071] Bottlenecks may arise from DRAM access bandwidth or increased SSD activity, such as additional change log programming and data movement access bandwidth, or NAND durability, etc. Bottlenecks can also occur due to misaligned "null" LBA pointers in the first L2P table 420 (i.e., "null" LBA pointers are not ordered but randomly arranged). Since the controller 408 must distinguish between valid LBA pointers and "null" pointers, misaligned "null" pointers can cause bottlenecks, potentially slowing down transfers from the first L2P table 420 to the second L2P table 440. Bottlenecks can also occur due to multiple partially filled L2P segments. Partially filled L2P segments indicate that more buffers are currently in use than optimally, reducing the total amount of volatile memory available for storing other data.

[0072] By associating the size of the L2P segments with the size of the partition, information stored in the first L2P table 420 can be copied more efficiently to the second L2P table 440, and power outage infrastructure can be optimized. In an SSD utilizing ZNS, data can only be erased when the entire partition is erased (i.e., data cannot be erased from a single erase block). Instead of erasing individual erase blocks, data is only erased if the entire partition can be erased. If the entire partition cannot be erased, the LBA pointer will point to an expired erase block. Although the LBA pointer will point to an expired LBA, there will be no misaligned "null" pointers in the first L2P table 420. Instead, when the entire partition is erased, each LBA pointer in the L2P segments (such as Z0SLBA 422) in the first L2P table 420 will point to "null". Therefore, each LBA pointer pointing to "null" will be aligned in the change log. A "null" pointer indicates that the entire erased partition is empty.

[0073] Instead of erasing individual erase blocks scattered across a single partition or multiple partitions, "empty" pointers may no longer be randomly scattered throughout the first L2P table 420. The entire L2P segment will point to "empty" because L2P segment data and corresponding partition data are correlated. Since the entire L2P table segment is "empty," the transfer from the first L2P table 420 to the second L2P table 440 is simplified. During the transfer to the second L2P table 440, DRAM 410 may no longer need to expend excessive resources distinguishing between "empty" pointers and valid LBA pointers. The second L2P table 440 is updated to match the first L2P table 420, showing that the first L2P segment is "empty" and the second L2P segment, such as Z1SLBA 444, has pointers to the second partition (such as...). Figure 3A The current LBA pointer of the second partition (306b).

[0074] Figure 5 This illustration shows a partition 500 of a storage device divided into change log segments according to one embodiment. The partition 500 shown can represent any partition in the storage device, such as… Figure 3A The first partition is 306a. Furthermore, partition 500 may correspond to the first L2P segment, such as... Figure 4 Z0SLBA 422. Partition 500 is divided into multiple segments aligned with change log tables (i.e., change log segments 508a-508n, collectively referred to as change log segments 508), where each change log segment 508 records data changes within the partition corresponding to the first partition segment. Each change log segment 508 represents a change log table, such as... Figure 4 The change log table is 430. In other words, change log segment 508 represents the amount of changes that can be tracked before the change log table is populated to capacity. In one implementation, the partition segment size can be any suitable size to evenly divide the partitions.

[0075] exist Figure 5In this configuration, erased or empty partitions (e.g., partitions currently not storing data) are indicated by an empty partition marker 502, while partitions with capacity are indicated by a partition capacity marker 504. A write pointer 506 indicates the current location of data written to partition 500. As data is written to partition 500, one or more change log segments 508 are populated with the corresponding change or update to the data location within the storage device. As each change log segment 508 is populated, the data in the change log table is programmed into the associated L2P table segments, such as Z0SLBA 422 and / or Z0SLBA 442. Therefore, data in change log segments 508 that have been copied to volatile memory and / or the NVM is considered "original values," meaning the controller recognizes that the data in that partition is the current value. In the event of a power outage, the controller is able to prioritize relevant data or ignore all stable change log segments (e.g., "original values" or fully filled contiguous areas) to preserve current data after a power outage.

[0076] Whenever a change log segment, such as change log segments 508a, 508b, or 508c, is filled to capacity, change log table 430 is copied to the first and / or second L2P tables 420, 440, and then erased or cleared. Since data is written to partitions sequentially, only one change log segment 508 can be programmed at a time. When a change log segment, such as change log segment 508d, is currently tracking partition changes, change log table 430 and / or the tracked changes can be stored in a buffer (not shown) located in DRAM 410. The buffer is larger than change log table 430. When a change log segment, such as change log segment 508c, is programmed into volatile memory and / or the corresponding L2P table portion of the NVM, the volatile memory buffer is returned to the available buffer pool. Since change log segment 508d is currently being programmed, the volatile memory buffer is utilized. However, within partition 500, the minimum total number of buffers is utilized, such as, in this example, one buffer. By using a minimal number of buffers in volatile memory, more volatile memory space can be used to store other data, such as user data or controller metadata.

[0077] Null pointers in the Logical-to-Physical Address (L2P) table point to data that has been erased or moved within a partition of the non-volatile memory. The first L2P table in DRAM records the location of all data in the NVM by associating the data's LBA with the physical location where the data is stored in the NVM. After a period of time, the first L2P table is copied to a second L2P table in the NVM as a power-loss protection infrastructure. For more efficient data transfer, entire L2P segments are associated with their corresponding partitions, and L2P segments are transferred from the first L2P table to the second L2P table. By associating each L2P segment with its corresponding partition, the first L2P table can be copied to the second L2P table in a faster and more efficient manner, especially during power-loss events.

[0078] Furthermore, since data can only be erased from the NVM partition size, the entire change log segment or L2P segment associated with that partition points to "null". All "null" pointers reside in the same change log segment or L2P segment, thus aligning together, rather than having unaligned "null" pointers throughout the first L2P table. The transfer from the first L2P table to the second L2P table is optimized because the device may no longer need to allocate as many resources to distinguish between "null" and valid pointers, potentially speeding up the process and utilizing less power. Therefore, the process of deallocating or unmapping "null" LBA pointers from the L2P table is faster and more efficient.

[0079] In one embodiment, the storage device includes non-volatile memory cells. The capacity of the non-volatile memory cells is divided into multiple partitions. The non-volatile memory cells include multiple dies, and each die includes multiple erase blocks. The storage device further includes volatile memory cells. The volatile memory cells store a first logical-to-physical address table. The first logical-to-physical address table associates logical block addresses of data with physical addresses where the data is stored in the non-volatile memory cells. The storage also includes a controller coupled to the non-volatile memory cells and the volatile memory cells. The controller is configured to sequentially write data to each partition of the multiple partitions and to divide the first logical-to-physical address table into segments. The size of each segment is aligned with a change log table. The controller is further configured to update a second logical-to-physical address table stored in the non-volatile memory cells. The second logical-to-physical address table is updated according to the segment size.

[0080] The volatile memory cells are DRAM, and the non-volatile memory cells are NAND flash memory. The second logical-to-physical address table is updated approximately every 20 seconds. Each partition is divided into an even number of segments. The second logical-to-physical address table is updated each time a segment is filled to its capacity. The storage device includes one or more capacitors configured to power a controller, which is configured to use the power supplied by the one or more capacitors to update the second logical-to-physical address table to match the first logical-to-physical address table in the event of a power failure. One segment is written at a time. Each of the multiple partitions is erased according to its partition capacity. The second logical-to-physical address table is updated each time a partition is erased.

[0081] In another embodiment, the storage device includes non-volatile memory cells. The capacity of the non-volatile memory cells is divided into multiple partitions. The non-volatile memory cells include multiple dies, and each die includes multiple erase blocks. The storage device also includes volatile memory cells. The storage device further includes a controller coupled to the non-volatile memory cells and the volatile memory cells. The controller is configured to sequentially write data associated with one or more commands to a first partition of the multiple partitions, wherein each partition of the multiple partitions is divided into multiple segments, the segment size being aligned with a change log table. The controller is further configured to update a first logical-to-physical address table stored in the volatile memory cells. The controller is also configured to update the first logical-to-physical address table, which associates logical block addresses of data associated with one or more commands with physical addresses of the data associated with one or more commands stored in the first partition. The controller is further configured to erase data associated with one or more commands from the first partition and update the first logical-to-physical address table to indicate that the first partition is empty. The controller is also configured to update a second logical-to-physical address table stored in non-volatile memory cells to match the first logical-to-physical address table. The second logical-to-physical address table is updated according to the segment size.

[0082] The volatile memory cells are DRAM memory, and each segment begins with the partition's starting logical block address. The second logical-to-physical address table is updated approximately three times per minute. The first partition comprises multiple segments, and one segment is updated each time data is written to the first partition. The second logical-to-physical address table is updated during power-down events. Each partition comprises 32 segments.

[0083] In another embodiment, the storage device includes non-volatile memory cells. The capacity of the non-volatile memory cells is divided into multiple partitions. The non-volatile memory cells further include multiple dies, and each die includes multiple erase blocks. The storage device also includes volatile memory cells. The volatile memory cells store a first logical-to-physical address table. The first logical-to-physical address table associates logical block addresses of data with physical addresses where the data is stored in the non-volatile memory cells. Furthermore, the storage device includes: means for dividing each of the multiple partitions into multiple segments, wherein each segment is aligned with a change log table; and means for updating the segment of the partition each time a command to write data to the partition is received. The storage device further includes means for updating the first logical-to-physical address table each time data is erased from the non-volatile memory cells. Data erased from the non-volatile memory cells is performed according to partition capacity. The storage device includes means for updating a second logical-to-physical address table stored in the non-volatile memory cells to match the first logical-to-physical address table. The second logic updates the physical address table according to the segment size.

[0084] The storage device further includes means for updating the second logical-to-physical address table to match the first logical-to-physical address table in the event of a power failure. Data is erased from non-volatile storage cells according to the partition size. Each of the multiple partitions has the same size, and each partition is divided into an even number of segments. The storage device includes means for sequentially writing data associated with each command to each of the multiple partitions.

[0085] While the foregoing describes embodiments of this disclosure, other and additional embodiments of this disclosure may be contemplated without departing from the basic scope of this disclosure, the scope of which is defined by the appended claims.

Claims

1. A storage device, the storage device comprising: A non-volatile memory cell, wherein the capacity of the non-volatile memory cell is divided into multiple partitions, and wherein the non-volatile memory cell includes multiple dies, each of the multiple dies including multiple erase blocks; A volatile memory cell, wherein the volatile memory cell stores a first logical-to-physical address table and a change log table, the first logical-to-physical address table associating logical block addresses of data with physical addresses where the data is stored in the non-volatile memory cell, wherein the change log table tracks changes made to the first logical-to-physical address table, and the change log table has a smaller capacity than the first logical-to-physical address table. and A controller, coupled to the non-volatile memory unit and the volatile memory unit, wherein the controller is configured to: Write data sequentially to each of the multiple partitions; The first logical-to-physical address table is divided into several segments, wherein each segment is aligned with the capacity of the change log table; Update the second logical-to-physical address table stored in the non-volatile memory cell, wherein the second logical-to-physical address table is updated according to the segment size of the first logical-to-physical address table; and When a predetermined time expires, the capacity of the change log table is filled, or a power outage event occurs, the change log table is copied to the second logical-to-physical address table.

2. The storage device of claim 1, wherein the volatile memory cell is a DRAM memory, and wherein the non-volatile memory cell is a NAND memory.

3. The storage device according to claim 1, wherein the second logical-to-physical address table is updated every 20 seconds.

4. The storage device of claim 1, wherein each partition is divided into an even number of segments.

5. The storage device of claim 1, wherein the second logical-to-physical address table is updated each time a segment of the second logical-to-physical address table is filled to capacity.

6. The storage device of claim 1, further comprising one or more capacitors configured to provide power to the controller, wherein the controller is configured to use the power provided by the one or more capacitors to update the second logical-to-physical address table to match the first logical-to-physical address table in a power failure event.

7. The storage device of claim 1, wherein a segment of the second logical-to-physical address table is written at one time.

8. The storage device of claim 1, wherein each of the plurality of partitions is erased according to its partition capacity.

9. The storage device of claim 8, wherein the second logical-to-physical address table is updated each time a partition is erased.

10. A storage device, the storage device comprising: A non-volatile memory cell, wherein the capacity of the non-volatile memory cell is divided into multiple partitions, and wherein the non-volatile memory cell includes multiple dies, each of the multiple dies including multiple erase blocks; A volatile memory cell configured to store a change log table and a first logical-to-physical address table, the change log table tracking changes made to the first logical-to-physical address table; and A controller, coupled to the non-volatile memory unit and the volatile memory unit, wherein the controller is configured to: Data associated with one or more commands is written sequentially to the first partition of the plurality of partitions, wherein each partition of the plurality of partitions is divided into multiple segments, the size of which is aligned with the capacity of the change log table; Update the first logical-to-physical address table, which associates the logical block address of the data associated with the one or more commands with the physical address of the data associated with the one or more commands stored in the first partition; Erase the data associated with the one or more commands from the first partition; Update the first logical-to-physical address table to show that the first partition is empty; The second logical-to-physical address table stored in the non-volatile memory cell is updated to match the first logical-to-physical address table, wherein the second logical-to-physical address table is updated according to the size of the delimiter segment for each partition; as well as When a predetermined time expires, the capacity of the change log table is filled, or a power outage event occurs, the change log table is copied to the second logical-to-physical address table.

11. The storage device of claim 10, wherein the volatile memory cell is a DRAM memory, and wherein each partition segment of each partition begins with the partition start logical block address.

12. The storage device of claim 10, wherein the second logical-to-physical address table is updated 3 times per minute.

13. The storage device of claim 10, wherein the first partition comprises a plurality of delimiters, and wherein each time data is written to the first partition, one delimiter of the first partition is updated.

14. The storage device of claim 10, wherein the second logical-to-physical address table is updated during a power outage event.

15. The storage device of claim 10, wherein each partition comprises 32 partition segments.

16. A storage device, the storage device comprising: A non-volatile memory cell, wherein the capacity of the non-volatile memory cell is divided into multiple partitions, and wherein the non-volatile memory cell includes multiple dies, each of the multiple dies including multiple erase blocks; A volatile memory cell stores a first logical-to-physical address table and a change log table, wherein the first logical-to-physical address table associates a logical block address of data with a physical address in which the data is stored in the non-volatile memory cell, and wherein the change log table tracks changes made to the first logical-to-physical address table. A means for dividing each of the plurality of partitions into a plurality of segments, wherein each of the plurality of segments is aligned with the capacity of the change log table; A means for updating the partition's delimiter segment each time a command to write data to the partition is received; A means for updating the first logical-to-physical address table each time data is erased from the non-volatile memory cell, wherein the data is erased from the non-volatile memory cell according to the partition capacity size; A means for updating a second logical-to-physical address table stored in the non-volatile memory cell to match the first logical-to-physical address table, wherein the second logical-to-physical address table is updated according to the partition segment size of each partition; as well as A means for copying the change log table to the second logical-to-physical address table when one or more of the following events occur: a predetermined time period expires, the capacity of the change log table is filled, or a power outage occurs.

17. The storage device of claim 16, further comprising means for updating the second logical-to-physical address table to match the first logical-to-physical address table in the event of a power failure.

18. The storage device of claim 16, wherein the data is erased from the non-volatile storage cell according to the size of the partition.

19. The storage device of claim 16, wherein each of the plurality of partitions has the same size, and wherein each partition is divided into an even number of segments.

20. The storage device of claim 19, further comprising means for sequentially writing the data associated with each command to each of the plurality of partitions.

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