Package substrates with multiple microplatelets

Abstract

Component comprising: a first microplate (204) embedded within a first package substrate (102); a second microplate (206) having a greater width than the first microplate (204) and coupled to an upper surface of the first microplate (204); a data link (212) from the second microplate (206) to the first microplate (204) located at an interface between the first microplate (204) and the second microplate (206); a link (210) from the second microplate (206) to the first package substrate (102) located at an interface between the second microplate (206) and the first package substrate (102) outside the perimeter of the first microplate (204) and configured to transmit power or data from the package substrate to the second microplate (206);a second packet substrate (404, 504) having a greater width than the second microplatelet (206) and coupled to an upper surface of the second microplatelet (206); and a connection (408, 508) from the second packet substrate (404, 504) to the first packet substrate (102) located at an interface between the second packet substrate (404, 504) and the first packet substrate (102) outside the perimeter of the second microplatelet (206), configured to transmit current to the second packet substrate (404, 504) or to transmit data to or from the second packet substrate (404, 504).

Description

Technical FieldThe disclosure herein relates generally to semiconductor dice and dice packages.BackgroundStacked die semiconductor embodiments may utilize interconnect traces that pass through one or more dies to transmit data to or connect it to the power supply. As the size of semiconductor devices continuously decreases, efficient designs are desired to improve signal and power transfer.The publication US 2009 / 0 127 686 A1 describes a package structure with a plurality of semiconductor dies. The package structure therein includes a substrate having a die receptacle in which vias are formed.The publication US 2012 / 0 091 575 A1 describes a semiconductor package and a method for producing the same.US 2011 / 0 108 999 A1 describes a microelectronic package having a die which is connected to a plurality of electrically conductive pads.The publication US 2012 / 0 049 382 A1 describes packages which have bumpless build-up layer (BBUL).Brief Description of the DrawingsFIG. 1 is a block diagram of a die assembly according to an example embodiment. FIG. 2 is a block diagram of a multi-die package according to an example embodiment. FIG. 3 is a block diagram of another multi-die package according to an example embodiment. FIG. 4 is a block diagram of another multi-die package according to an example embodiment. FIG. 5 is a block diagram of another multi-die package according to an example embodiment. FIG. 6 is a flow diagram of a method according to an example embodiment. FIG. 7 is a block diagram of an electronic component according to an example embodiment.DESCRIPTION OF THE EMBODIMENTSIn the following description and drawings, specific embodiments are sufficiently illustrated that they can be practiced by one skilled in the art. Other embodiments may incorporate structural, logical, electrical, procedural, or other changes. Portions and features of some embodiments may be included in or replaced with other embodiments. The embodiments set forth in the claims include all available equivalents of those claims.FIG. 1 is an illustration of an embedded die assembly 100. The embedded die assembly 100 is comprised of a package substrate 102, a first die 104, a second die 106, and a number of interconnects 108. A connection 110 may be passed through the first die 104 to connect the second die 106 to a bus 112 in the package substrate 102. Thus, a connection 110 passes through the first die 104. The presence of the connection 110 by the first die 104 may destroy valuable space in the first die 104 and complicate routing. The presence of the connection 110 through the first die 104 may cause undesired electrical interference with data signals. A connection, such as connection 110, may be a through silicon via (TSV). A through silicon via is limited in power that can be transferred due to the geometry available in known fabrication methods. It is desirable to have a device that can have multiple dice embedded in a package substrate, where all dice can connect directly to the package substrate without using connections that pass through a die in a package substrate.FIG. 2 is an illustration of a component 200 according to an example embodiment. The device 200 may include the first and second dice 204 and 206, and at least one first die to substrate interconnect 208, at least one second die to substrate interconnect 210, and at least one second die to first die interconnect 212 included in a package substrate. In certain examples, the first and second dice, 204 and 206, are flip-chip dice.In certain examples, the package substrate 202 may be a package substrate with bumpless build-up layers (BBUL) package substrates), wherein one or more of the dice 204, 206 are embedded in the package substrate. A BBUL package substrate includes one or more dice embedded in a substrate having one or more build-up layers (built-up layers) formed below the dice. In certain examples, a standard micro via formation process (micro-via formation process) formation process, such as laser drilling, interconnects between build-up layers and dice, or die pads, may be formed. The build-up layers may be formed using standard high-density integration patterning technology (high-density integration).The package substrate 202 may include the first and second dice 204 and 206 embedded therein. In certain examples, the second die 206 may be stacked on the first die 204 at a top surface of the first die. In certain examples, the second die 206 may be coupled to the first die 204 at a top surface of the first die. The first or second die, 204 or 206, may be analog, digital, or a combination thereof. An analog die is a die using predominantly analog components, whereas a digital die is a die using predominantly digital components. Some examples of types of dice include, among many others, memory, radio, processor, arithmetic unit, or any combination thereof.The package substrate 202 may include one or more buses. In the illustrated example of FIG. 2, package substrate 200 includes two buses, 214 aand 214 b. Bus 214a or 214b may be, among other things, a power bus or a data bus. In certain examples, bus 214a is a power bus and bus 214b is a ground bus. In certain examples, bus 214a is a power bus and bus 214b is a data bus.The second die 206 may include a footprint that includes a dimension (e.g., a width) that is greater than a corresponding dimension of a footprint of the first die 204. In certain examples, the larger dimension of the second die 206 may allow connections between the second die 206 and the package substrate outside the perimeter of the first die 204 without requiring a through silicon via. Including a second die 206 having a larger footprint than a first die 204 at least in one dimension may allow cost savings by sharing circuits among the dies based on how well they can scale / reduce in manufacturing processes. For example, rather than using a less expensive technology for circuits that are not well scaled to the reduced size, more expensive technology fabrication techniques may be used to fabricate the second die 206, and more expensive newer generation technology may reduce die size for circuits that are well scaled to be incorporated into the first die 204. Including a second die 206 having a larger footprint than a first die 204 at least in one dimension may enable separation of functionality and manufacturing flexibility. In certain examples, a first embedded die 204 may be used in all manufactured packages, but a second die 206 may include different types of functionality or logic, thereby enabling the creation of different systems.In certain examples, the first die 204 is an analog die and the second die 206 is a digital die. In certain examples, the first die 204 is a digital die and the second die 206 is an analog die. Including an analog die stacked on a top surface of a digital die may help reduce noise and electromagnetic interference issues, as the analog die may be closer to the exterior environment and may not be as susceptible to noise or electromagnetic interference as the digital die. The device 200 may include at least one first die to substrate interconnect 208 located at an interface between the first die 204 and the package substrate 202. In certain examples, the at least one first die-to-substrate interconnect 208 may be included in a first level interconnect. In certain examples, the at least one first die-to-substrate interconnect 208 may be coupled between the first die 204 and the package substrate bus 214 aor 214 b.The device 200 may include at least one second die to substrate interconnect 210 located at an interface between the second die 206 and the package substrate 202. In certain examples, the at least one second die to substrate connection 210 may be outside the perimeter of the first die 204. In certain examples, the at least one second die-to-substrate interconnect 210 may be coupled between the second die 206 and the package substrate bus 214 aor 214 b. In certain examples, the at least one first die to substrate connection 208 and the second die to substrate connection 210 may be connections that transfer stream or data from the package substrate to the first or second die, 204 or 206.The device 200 may include at least one second die to first die connection 212 located at an interface between the first and second dies 204 and 206. In certain examples, the at least one second die to first die connection 212 may be included in a logic-to-logic interconnect. In certain examples, the at least one second die to first die connection 212 is a data connection that routes data between the first and second dies 204 and 206.In certain examples, it may be useful to pre-stack the first and second dice, 204 and 206, prior to embedding the dice in the package substrate 202. In certain examples, pre-stacking the dice may be performed using flip-chip, wire bonding (wire bonding), or other technique. In certain examples, pre-stacking the dice prior to embedding them in the package substrate may be performed using a thermal compression bonding technique (thermal compression bonding technique). In certain examples, pre-stacking the first and second dice using thermoplastically bonding may help preserve the dimensions of the dice. In certain examples, the dice may be pre-stacked, and then a bumpless build-up layer (BBUL) package substrate may be formed around the pre-stacked dice.FIG. 3 is an illustration of first and second pre-stacked dice 300. In certain examples, the first and second dice may be pre-stacked (i.e., stacked before being embedded in a package substrate) using thermoplastically bonding. In certain examples, the first die 204 may include at least one first die to substrate contact 308 operable to connect the first die 204 to a package substrate. In certain examples, the at least one contact 308 from the first die to the substrate may be included in a first level interconnect. In certain examples, the second die 206 includes at least one second die to substrate contact 310 operable to directly connect to a package substrate. The at least one second die to substrate contact 310 may be outside the perimeter of the first die 204. In certain examples, pre-stacking may create at least one second die to first die connection 212 located at an interface between the first and second dies, 204 and 206. In certain examples, the at least one second die to first die connection 212 may be included in a logic-to-logic interconnect. In certain examples, the second die includes at least one third die to second die contact 302 operable to connect the second die 206 to a third die that may be stacked over a top surface of the second die. In certain examples, the at least one third die to second die contact 302 may be included in a logic-to-memory interconnect. Although FIG. 3 shows two stacked dice, it should be appreciated that any number of dice may be stacked and embedded in accordance with the present disclosure.FIG. 4 is an illustration of a component 400 according to an example embodiment. The device 400 may include a multi-embedded die package substrate 402 and a second package substrate (e.g., third die) 404 stacked over a top surface of the multi-embedded die substrate 402. The multi-embedded die package substrate may be substantially similar to the device 200 of FIG. 2. The multi-embedded die package substrate 402 may include a second die coupled to a top surface of a first die as described with respect to FIG. 2 or 3. The multi-embedded die package substrate 402 may include at least one connection from the first die to the substrate, from the second die to the substrate, and from the second die to the first die, as described with reference to FIG. 2. The multi-embedded die package substrate 402 may include first and second buses operable to transfer power or data as described with respect to FIG. 2.The device 400 may include a second package substrate 404 stacked over a top surface of the package substrate with a plurality of embedded dice 402. The second package substrate 404 may include a third die. In certain examples, the third die may be a memory. In certain examples, the memory may be dual data rate memory (e.g., DDR2 or DDR3 memory). Stacking the second package substrate 404 over the top surface of the multi-embedded die package substrate 402 may produce a package on package architecture (package on package architecture) component 500. In certain examples, the second package substrate 404 may be connected to the multi-embedded die package substrate 402 using wire bonding, flip-chip, or other connection technology.The device 400 may include at least one interconnect 408 from the second package substrate (e.g., the third die) to the first package substrate located at an interface between the second package substrate 404 and the substrate of the multi-embedded die package substrate 402. The at least one interconnect 408 from the second package substrate to the first package substrate may connect between the second package substrate 404 and a bus included in the package substrate with multiple embedded dice. In certain examples, the at least one connection from the second package substrate to the first package substrate may be outside the perimeter of the second die of the multi-embedded die package substrate 402. In certain examples, the at least one interconnect 408 transfers power from the second package substrate to the first package substrate 404 to the second package substrate. In certain examples, the at least one connection 408 transfers data to / from the second package substrate 404 from the second package substrate to the first package substrate.FIG. 5 is an illustration of a component 500 according to an example embodiment. The device 500 may include a multi-embedded die package substrate 502 and a second package substrate (e.g., third die) 504 stacked over a top surface of the multi-embedded die substrate 502. The multi-embedded die package substrate may be substantially similar to the device 200 of FIG. 2. The multi-embedded die package substrate 502 may include a second die coupled to a top surface of a first die, as described with reference to FIG. 2 or 3. The multi-embedded die package substrate 502 may include at least one connection from the first die to the substrate, from the second die to the substrate, and from the second die to the first die, as described with reference to FIG. 2. The multi-embedded die package substrate 502 may include first and second buses operable to transfer power or data as described with respect to FIG. 2.The device 500 may include a second package substrate 504 stacked over a top surface of the package substrate with a plurality of embedded dice 502. The second package substrate 504 may include a third die. In certain examples, the third die may be a memory. In certain examples, the memory may be dual data rate memory (e.g., DDR2 or DDR3 memory). Stacking the second package substrate 504 over the top surface of the package substrate with multiple embedded dice 502 may produce a package-on-package architecture device 500. In certain examples, the second package substrate 504 may be stacked over the multi-embedded die package substrate 502 using thermoplastically bonding. In certain examples, the second package substrate 504 may be connected to the multi-embedded die package substrate 502 using wire bonding, flip-chip, or other connection technology. In certain examples, the second package substrate 504 may include a memory device that communicates to the second die using a logic-to-memory interface, such as the logic-to-memory interface of FIG. 3. In certain examples, the third die may communicate to the first die, the second die, or the package substrate using a ball grid array (BGA) interface. In certain examples, the second package substrate 504 may be coupled to the multi-embedded die package substrate 502 at a top surface of the multi-embedded die package substrate.The device 500 may include at least one interconnect 506 from the second package substrate (e.g., the third die) to the second die located at an interface between the second die of the multi-embedded die package substrate 502 and the second package substrate 504. In certain examples, the device 500 may include a logic-to-memory interface including the at least one interconnect 506 from the second package substrate to the second die. The at least one interconnect 506 from the second package substrate to the second die may transfer data between the second die and the second package substrate 504. In certain examples, the second package substrate to second die interconnect 506 may be configured as a package-to-package interconnect.The device 500 may include at least one interconnect 508 from the second package substrate (e.g., the third die) to the first package substrate located at an interface between the second package substrate 504 and the substrate of the multi-embedded die package substrate 502. The at least one interconnect 508 from the second package substrate to the first package substrate may connect between the second package substrate 504 and a bus included in the package substrate with multiple embedded dice. In certain examples, the interconnects, at least one, from the second package substrate to the first package substrate may be outside the perimeter of the second die of the multi-embedded die package substrate 502. In certain examples, the at least one interconnect 508 transfers power from the second package substrate to the first package substrate 504 to the second package substrate. In certain examples, the at least one link 408 transfers data to / from the second package substrate 504 from the second package substrate to the first package substrate.FIG. 6 illustrates a flow diagram of a method 600 for manufacturing a component according to an example embodiment. The method 600 may include pre-stacking the first and second dice 602. The first or second die may be predominantly analog, predominantly digital, or a combination thereof. The second die may include a width (e.g., a footprint having a dimension) greater than a corresponding width (e.g., a corresponding dimension of a footprint) of the first die. The second die may be stacked over a top surface of the first die. The pre-stacking may be performed using a flip-chip method, a wire bonding method, a thermoplastically joining method, or another joining method. At 604, a substrate may be formed around the first and second dice. The substrate may be a bumpless build-up layer substrate. At least one connection from the second die to the substrate may be formed at an interface between the second die and the substrate at 606. The at least one connection from the second die to the substrate may be formed outside the perimeter of the first die. The at least one connection from the second die to the substrate may be between the second die and a bus included in the substrate. The bus may carry power or data signals. At 608, at least one connection from the first die to the substrate may be formed at an interface between the first die and the substrate. The at least one connection from the first die to the substrate may be between the first die and a bus included in the substrate.At 610, a third die (e.g., a second package substrate) may be stacked over the second die. The third die may be coupled to the second die at a top surface of the second die. The third die may be analog, digital, or a combination thereof. In certain examples, the third die is a memory die. The third die may include a width greater than the corresponding width of the second die. At 612, at least one connection from the third die to the second die may be formed at an interface between the third die and the second die. The at least one connection from the third die to the second die may transfer data between the second and third dies. At least one third die to substrate connection located at an interface between the third die and the substrate may be formed at 614. The at least one third die to substrate connection (e.g., a second substrate package to first substrate package connection) may be formed outside the perimeter of the second die. The at least one connection from the third die to the substrate may be between the third die and a bus included in the substrate. At 616, at least one first to second die connection may be formed between the first and second dies. The at least one connection from the second die to the first die may transfer data between the first and second dies.An example of an electronic component using a die as described in the present disclosure is included to show an example of a higher-level component application for the present disclosure. FIG. 7 is a block diagram of an electronic device 700 incorporating at least one die according to at least one embodiment of the invention. The electronic device 700 is merely an example of an electronic system in which embodiments of the present invention may be used. Examples of electronic devices 700 include, but are not limited to, workstation computers, tablet computers, cellular phones, personal data assistants, MP4 or other digital music players, radios, etc. In this example, the electronic device 700 includes a data processing system including a system bus 702 to couple the various components of the system. The system bus 702 provides communication links among the various components of the electronic device 700 and may be deployed as a single bus, as a combination of buses, or in any other suitable manner.An electronic package 710 is coupled to the system bus 702. The electronic package 710 may include any circuit or combination of circuits. In one embodiment, the electronic assembly 710 includes a processor 712, which may be of any type. As used herein, "processor" means any type of computer circuit, such as, but not limited to, a microprocessor, a microcontroller, a complex instruction set computing (CISC) microprocessor, a reduced instruction set (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a graphics processor, a digital signal processor (DSP), a multi-core processor, or any other type of processor or processing circuit.Other types of circuits that may be included in the electronic device 710 are custom circuitry, an application specific integrated circuit (ASIC), or the like, such as one or more circuits (such as communication circuitry 714) for use in wireless devices such as cellular phones, pagers, personal data assistants, portable computers, radio telephones, and similar electronic systems. The integrated circuit may perform any other type of function.The electronic device 700 may also include external memory 720, which in turn may include one or more storage elements suitable for the particular application, such as main memory 722 in the form of random access memory (RAM), one or more hard disk drives 724, and / or one or more drives that handle removable storage media 726 such as compact disks (CD), digital video disks (DVD), and the like.The electronic device 700 may also include a visual display device 716, one or more speakers 718, and a keyboard and / or controller 730, which may include a mouse, trackball, touch screen, voice recognition device, or any other device that allows the system user to input and receive information to and from the electronic device 700.Additional Indications and ExamplesIn Example 1, a device includes a first die within a package substrate, a second die having a width greater than that of the first die and coupled to a top surface of the first die, at least one first die-to-substrate connection located at an interface between the first die and the package substrate, and at least one second die-to-substrate connection located at an interface between the second die and the package substrate outside the perimeter of the first die.In Example 2, the component of Example 1 includes a second die to first die connection located at an interface between the first die and the second die.In Example 3, the connection from the second die to the first die of any one or more of Examples 1 and 2 is a data connection.In Example 4, the first die to substrate connection and the second die to substrate connection of any one or more of Examples 1-3 are power connections.In Example 5, the at least one first die to substrate connection of any one or more of Examples 1 to 4 includes at least one data connection and at least one power connection.In Example 6, the first die of any one or more of Examples 1-5 is a digital die.In Example 7, the second die of any one or more of Examples 1-6 is an analog die.In Example 8, the package substrate of any one or more of Examples 1 to 7 is configured as a bumpless build-up layer package substrate.In Example 9, a device includes a first die embedded within a first package substrate, a second die having a width greater than that of the first die and coupled to a top surface of the first die, a second die to first die interconnect located at an interface between the first die and the second die, a second die to substrate interconnect located at an interface between the second die and the package substrate outside the perimeter of the first die, a second package substrate having a width greater than that of the second die and coupled to a top surface of the second die, and a second package substrate to first package substrate interconnect from the second package substrate, which is located at an interface between the second package substrate and the first package substrate outside the perimeter of the second die.In Example 10, the device of any one or more of Examples 1 to 9 includes a connection from the second package substrate to the second die located at an interface between the second die and the second package substrate.In Example 11, the second package substrate of any one or more of Examples 1 to 10 is a memory die.In Example 12, the second package substrate to second die interconnect of any one or more of Examples 1-11 is a dual data rate interconnect.In Example 13, the connection from the second die to the first die of any one or more of Examples 1 to 12 is a data connection.In Example 14, the first and second dice of any one or more of Examples 1 to 13 are digital and analog, respectively.In Example 15, the first package substrate of any one or more of Examples 1 to 14 is configured as a bumpless build-up layer package substrate.In Example 16, the second die of any one or more of Examples 1 to 15 is embedded in the first package substrate.In Example 17, a device includes a first die embedded within a first package substrate, a second die embedded within the first package substrate, the second die including a width greater than that of the first die and coupled to a top surface of the first die, a first die to second die connection located at an interface between the first die and the second die, a second die to substrate connection located at an interface between the second die and the first package substrate outside the perimeter of the first die, a second package substrate having a width greater than that of the second die and coupled to a top surface of the second die, and a connection from the second package substrate to the first package substrate located at an interface between the first package substrate and the second package substrate outside the perimeter of the second die.In Example 18, the first package substrate of any one or more of Examples 1 to 17 is configured as a bumpless build-up layer substrate.In Example 19, the second package substrate of any one or more of Examples 1 to 18 is configured as a bumpless build-up layer substrate.In Example 20, the component of any one or more of Examples 1 to 19 includes a connection from the second package substrate to the second die located at an interface between the second die and the second package substrate.In Example 21, the second package substrate to second die interconnect of any one or more of Examples 1-20 is configured as a package-to-package interconnect.In Example 22, the first die, the second die, and the second package substrate of any one or more of Examples 1-21 are a digital die, an analog die, and a memory package, respectively.In Example 23, a method includes pre-stacking the first and second dice, wherein the second dice includes a width greater than that of the first dice, and wherein the second dice is stacked over the first dice, forming a first package substrate around the first and second dice, and forming a connection from the second dice to the substrate that is located outside the perimeter of the first dice at an interface between the second dice and the first package substrate.In Example 24, forming the first package substrate of any one or more of Examples 1 to 23 includes forming a substrate with bumpless build-up layer.In Example 25, pre-stacking the first and second dice of any one of Examples 1 to 24 includes the order of the thethermal compression bonding.In Example 26, the method of any one or more of Examples 1 to 25 includes forming a first die to substrate connection located at an interface between the first die and the first package substrate.In Example 27, the method of any one or more of Examples 1 to 26 includes stacking a second package substrate on the second die, the second package substrate including a width greater than that of the second die, forming a connection from the second package substrate to the second die located at an interface between the second die and the second package substrate, and forming a connection from the second package substrate to the first package substrate located at an interface between the first package substrate and the second package substrate outside the perimeter of the second die.

Claims

A component comprising: a first die (204) embedded within a first package substrate (102); a second die (206) having a greater width than the first die (204) and coupled to a top surface of the first die (204); a data connection (212) from the second die (206) to the first die (204) located at an interface between the first die (204) and the second die (206); a connection (210) from the second die (206) to the first package substrate (102) located at an interface between the second die (206) and the first package substrate (102) outside the perimeter of the first die (204) and configured to transfer power or data from the package substrate to the second die (206); a second package substrate (404, 504) having a greater width than the second die (206) and coupled to a top surface of the second die (206); and a interconnect (408, 508) from the second package substrate (404, 504) to the first package substrate (102) located at an interface between the second package substrate (404, 504) and the first package substrate (102) outside the perimeter of the second die (206) configured to transfer power to the second package substrate (404, 504) or to transfer data to or from the second package substrate (404, 504).The device of claim 1, comprising a connection (506) from the second package substrate (404, 504) to the second die (206) located at an interface between the second die (206) and the second package substrate (404, 504).The device of claim 1, wherein the second package substrate (404, 504) includes a memory die.The device of claim 3, wherein the connection from the second package substrate (404, 504) to the second die (206) is a dual data rate connection.The component of claim 1, wherein the first die (204) is digital and the second die (206) is analog.The device of claim 1, wherein the first package substrate (102) is configured as a bumpless build-up layer package substrate.The device of claim 1, wherein the second die (206) is embedded in the first package substrate (102).A component comprising: a first die (204) embedded within a first package substrate (102); a second die (206) embedded within the first package substrate (102), the second die (206) including a greater width than the first die (204) and coupled to a top surface of the first die (204); a data connection (212) from the first to the second die (206) located at an interface between the first die (204) and the second die (206); a connection (210) from the second die (206) to the first package substrate (102) located at an interface between the second die (206) and the first package substrate (102) outside the perimeter of the first die (204) and configured to transfer power or data from the package substrate to the second die (206); a second package substrate (404, 504) having a width greater than the width of the second die (206) and coupled to a top surface of the second die (206); and a connection (408, 508) from the second package substrate (404, 504) to the first package substrate (102) located at an interface between the first package substrate (102) and the second package substrate (404, 504) outside the perimeter of the second die (206) configured to transfer power to the second package substrate (404, 504) or to transfer data to or from the second package substrate (404, 504).The device of claim 8, wherein the first package substrate (102) is a bumpless build-up layer substrate.The device of claim 9, wherein the second package substrate (404, 504) is a bumpless build-up layer substrate.The device of claim 8, comprising a connection (506) from the second package substrate (404, 504) to the second die (206) located at an interface between the second die (206) and the second package substrate (404, 504).The device of claim 11, wherein the interconnect (506) from the second package substrate (404, 504) to the second die (206) is configured as a package-to-package interconnect.The component of claim 9, wherein the first die (204) is digital and the second die (206) is analog and the second package is a memory package.A method comprising: pre-stacking (602) a first (204) and a second die (206), wherein the second die (206) includes a greater width than the first die (204), and wherein the second die (206) is stacked over the first die (204); forming (604) a first package substrate (102) around the first and second dies (206); forming (606) a second die (206)-to-substrate connection (210) located at an interface between the second die (206) and the first package substrate (102) outside the perimeter of the first die (204) and configured to transfer power or data from the package substrate to the second die (206); forming (616) a data connection (212) from the second die (206) to the first die (204) located at an interface between the first die (204) and the second die (206); stacking a second package substrate (404, 504) over a top surface of the second die (206), wherein the second package substrate (404, 504) includes a greater width than the second die (206); forming a connection (408, 508) from the second package substrate (404, 504) to the first package substrate (102) located at an interface between the second package substrate (404, 504) and the first package substrate (102) outside the perimeter of the second die (206) configured to transfer power to the second package substrate (404, 504) or to transfer data to or from the second package substrate (404, 504).The method of claim 14, wherein forming the first package substrate (102) includes forming a bumpless build-up layer substrate.The method of claim 14, wherein pre-stacking the first and second dice includes thermoplastically bonding.The method of claim 14, comprising forming a bond (208) from the first die (204) to the substrate located at an interface between the first die (204) and the first package substrate (102).The method of claim 14, comprising: forming a connection (506) from the second package substrate (404, 504) to the second die (206) located at an interface between the second package substrate (404, 504) and the second die (206).

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