Device, system and method for switched power transmission to an I / O interface

Abstract

Device comprising the following: a power gate logic (330) for coupling with a control logic (320), wherein the control logic (320) monitors a first of several connections (305), wherein a serial input / output (I / O) interface comprises a protocol stack comprising a physical layer and a link layer, wherein resources of the serial I / O interface have a first resource set which serves to support communication only via the first connection from the plurality of connections, wherein the power gate logic (330) is configured to decouple a link layer resource of the first resource set from a respective power supply in response to a detection of a change in the total number of active paths of the first connection by the control logic (320), wherein the power gate logic (330) is configured to decouple the link layer resource of the first set of resources from the respective power supply.regardless of whether another link layer resource of the first set of resources is decoupled from a respective power supply.

Description

BACKGROUND 1. Technical field

[0001] One or more embodiments of the invention generally relate to the field of computer systems. In particular, certain embodiments relate to power transmission in a computer system. 2. State of the art

[0002] Energy-efficient operation is an increasingly important requirement for many computing applications. On servers and other computing platforms, the operation of input / output (I / O) interface hardware contributes significantly to overall power consumption. Performance analysis for various computing platforms has shown that the bandwidth of I / O connections can generally be quite low, even when these computing platforms are operating near peak system performance loads. Even when no transaction is being processed across a platform's I / O connection, allocated I / O interface resources consume near their peak performance. The power waste during such periods of low bandwidth utilization results in poor energy efficiency.

[0003] The power consumption of such I / O hardware has traditionally been reduced by scaling the link speed and / or link width. Some link power reduction schemes use dynamic link width modulation (DLW), which dynamically adjusts the link width based on bandwidth requirements and switches a clock otherwise used to operate the currently inactive hardware for the link. Current I / O link power management (LPM) policies, such as LOs, LOp, and L1, rely on clock switching. However, as successive generations of computer systems continue to scale in size and speed, the operation of such computer systems is increasingly sensitive to incremental improvements in power efficiency.

[0004] US 7,188,263 B1 describes an arrangement that enables a further reduction in power consumption when a system comprises two or more electrical components that can be placed in two or more power consumption states. The arrangement can utilize existing circuitry to selectively deactivate certain state transition detectors, thereby achieving additional power reduction.

[0005] US 2008 / 0005303 A1 describes a method for determining that the utilization of a logical connection has reached a first threshold. The logical connection includes a first number of active physical connections. The method also includes deactivating one or more physical connections to generate a second number of active physical connections. The second number is smaller than the first number. The method further includes determining that the second number of active physical connections has not been used for a certain period of time and deactivating another set of connections.

[0006] US 2008 / 0 082 840 A1 describes a method for providing a bus interface, comprising operating first circuits using a first supply voltage in a normal operating mode, wherein the first circuits comprise at least a portion of the data path circuits of the bus interface. The exemplary method further comprises shutting down the first circuit to a low-power operating mode and operating the second circuit using the first supply voltage in the normal operating mode. The method also comprises operating the second circuit using a second supply voltage in the low-power operating mode. The second circuit comprises a power management control circuit configured to receive a power management event indication signal.

[0007] The invention is defined in claim 1 and the subordinate claims. Embodiments of the invention are defined in the subclaims. BRIEF DESCRIPTION OF THE DRAWING

[0008] The various embodiments of the present invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings. They show: Fig. 1 is a block diagram of an element of a system for providing power switching of an I / O interface according to an embodiment, Fig. 2 is a block diagram of elements of a protocol stack of an I / O interface for which power switching is provided, according to one embodiment, Fig. 3 is a block diagram of elements of a system for providing power switching according to an embodiment, Fig. 4 is a flowchart of elements of a method for switching power for an I / O interface according to one embodiment, Fig. 5 is a block diagram of elements of a system for providing power switching according to an embodiment, Fig. 6 is a block diagram of elements of a computing system for switching power for an I / O interface according to one embodiment. Fig. 7 is a block diagram of elements of a mobile device for switching power for an I / O interface according to one embodiment, and Fig. 8 is a block diagram of elements of a computing system for switching power for an I / O interface according to one embodiment. DETAILED DESCRIPTION

[0009] Embodiments discussed herein in various respects provide power switching mechanisms and techniques for selectively decoupling and / or selectively coupling hardware resources of an I / O interface from a power supply. Current clock switching techniques conserve only dynamic power, but not leakage power, which is a significant contributor to the overall power consumption of I / O interface hardware. For example, by relying on clock switching through current serial I / O link power management (LPM) policies, the problem of power inefficiency due to leakage power is not addressed. In contrast, certain embodiments provide, in various ways, the ability to switch the power supply to inactive I / O interface hardware to conserve leakage power as well as dynamic power.For example, such power switching can be performed selectively for different hardware, such as on a per-connection basis, to significantly improve performance scaling with I / O bandwidth utilization.

[0010] Fig. 1 shows elements of an illustrative computer system 100 for providing power circuitry according to one embodiment. Computer system 100 may include, for example, a personal computer hardware platform such as a desktop computer, a laptop computer, a handheld computer such as a tablet, palmtop, smartphone, media player, and / or the like, and / or other such computer system. Alternatively or additionally, computer system 100 may provide operation as a server, workstation, or other such computer system. According to one embodiment, computer system 100 includes one or more mechanisms for controlling power delivery at a per-connection granularity level.

[0011] According to one embodiment, computer system 100 includes a device 110 and a device 130 for communicating with each other via an interconnect 120. Device 110 and device 130 may each variously comprise any of a variety of devices capable of performing input / output (I / O) communications, such communications following, for example, a serial point-to-point I / O protocol.Examples of such types of devices capable of performing I / O communications include a processor, a network controller, a memory controller, and various peripheral devices, including, but not limited to, a computer mouse, a keyboard, a hard disk drive, a solid-state drive, a CD-ROM drive, a DVD-ROM drive, an expansion card, a graphics card, a microphone, a printer, a display, a speaker, and / or the like. Here, "input / output" refers to communication with a device having an I / O interface in question. However, such communications may also be performed, for example, between two components of a single computer platform.

[0012] By way of illustration and without limitation, interconnect 120 may include a physical interconnect compatible with a serial I / O specification. For example, interconnect 120 may be compatible with a Peripheral Component Interconnect (PCD) specification such as the PCI Local Bus Specification, Release 3.0, 2004, available from the PCI Special Interest Group, Portland, OR, USA (hereinafter referred to as the "PCI Bus"), the PCI Express (PCIe) Specification, Release 2.0, 2006, available from the aforementioned PCI Special Interest Group, Portland, OR, USA, and / or the like. According to such an embodiment, device 110 and device 130 may be a processor and a peripheral device, respectively.According to an alternative embodiment, device 110 and device 130 may each be processors, with interconnect 120 including, for example, hardware for supporting QuickPath Interconnect (QPI) communications or other such interprocessor communications. According to another embodiment, interconnect 120 is compatible with a Universal Serial Bus (USB) standard, such as the USB 3.0 standard published in November 2008 by the USB 3.0 Promoter Group.

[0013] Interconnect 120 may be any of a variety of other interconnect hardware types, including other serial interconnects and various parallel interconnects that support one or more variable-width interconnects. The term "interconnect" is understood to include a channel, a bus, or other such set of lanes that may operate together as a functional group. For illustrative purposes, and without limitation, interconnect 120 may be a parallel bus coupled between a memory controller and a memory device, such as a dynamic random access memory (DRAM), a Rambus DRAM (RDRAM), and / or the like.Alternatively, the interconnect 120 may be one of an Inter-Integrated Circuit (I2C) bus, a Video Graphics Array (VGA) interconnect, and a High Definition Multimedia Interface interconnect.

[0014] According to one embodiment, device 110 includes an I / O interface 105 for supporting communications over interconnect 120. I / O interface 105 may include various resources, for example, including circuitry or other hardware that at least partially implement respective operations for exchanging communications with interconnect 120. Computer system 100 may include power transfer logic 140, for example, including hardware, firmware, and / or execution software, for switching power transfer to such resources of I / O interface 105 in various ways.Switching power transfer to such resources of I / O interface 105 may include, for example, independently coupling resources to one or more respective power supplies (not shown) and / or independently decoupling such resources therefrom. This power coupling / decoupling may be performed at a per-link granularity, including independent power coupling / decoupling for resources specific to a different respective serial communication link. Part or all of power transfer logic 140 may be incorporated into device 110 according to an alternative embodiment. Additionally or alternatively, power transfer logic 140 may provide power switching for device 130, although particular embodiments are not limited in this regard.

[0015] Certain features of various embodiments are discussed herein with reference to selectively switching power to resources of a serial I / O interface. However, this discussion may be expanded to additionally or alternatively apply to switching power to resources of any of a variety of parallel I / O interface types.

[0016] Fig. Figure 2 shows elements of a protocol stack 200 of a serial I / O interface for which power circuitry may be provided according to one embodiment. The serial I / O interface may operate in a system that includes, for example, some or all of the features of computer system 100. According to one embodiment, protocol stack 200 is implemented in an interface that provides some or all of the functionality of I / O interface 105.

[0017] Protocol stack 200 may at least partially implement communications over a serial interconnect, such communications being compatible with, for example, a PCIe or other point-to-point serial communications standard. Protocol stack 200 may include any of a variety of layered communication stacks, such as a Common Standard Interface (CSI) stack, a PCIe stack, or another such protocol stack. By way of illustration and without limitation, protocol stack 200 may be a PCIe protocol stack including a transaction layer 210, a link layer 220, and a physical layer 230. Certain features of a serial I / O interface are discussed herein with reference to a specific embodiment of a PCIe protocol stack.However, this discussion can be extended to apply additionally or alternatively to any of a variety of other layered protocol stacks of a serial I / O interface.

[0018] According to one embodiment, the transaction layer 210 is intended to provide an interface between processing logic of a device and the interconnect architecture, such as that of the data link layer 220 and the physical layer 230. In this regard, responsibilities of the transaction layer 210 may include, for example, assembling and / or disassembling packets (i.e., transaction layer packets or TLPs). The transaction layer 210 may additionally or alternatively implement other functionality, including, but not limited to, credit-based scheduling with segmented transactions and / or the like.

[0019] The link layer 220, also referred to as the data link layer 220, may act as an intermediary between the transaction layer 210 and the physical layer 230. According to one embodiment, the link layer 220 provides one or more mechanisms for exchanging transaction layer packets (TLPs) between components of a connection. For example, the link layer 220 may accept TLPs assembled by the transaction layer 210, apply a packet sequence identifier, calculate and apply an error detection code, and / or pass the modified TLPs to the physical layer 230 for transmission to another device. The physical layer 230 may include logic to physically transmit a packet to an external device.For example, the physical layer 230 may include a transmit logic section to prepare outgoing information for transmission and a receiver logic section to identify and prepare received information before passing it to the link layer 220.

[0020] According to one embodiment, the layers of protocol stack 200 each include respective hardware resources for variously implementing the functionality of that layer. For purposes of illustration, and not limitation, transaction layer 210 may include a set of transmit resources 212 for assembling packets for transmission from the device having the serial I / O interface and a set of receive resources 214 for disassembling packets received from such a device. Similarly, link layer 220 and physical layer 230 may include a set of transmit resources 222 and a set of transmit resources 232, respectively, which prepare in various ways for the transmission of packets assembled by set of transmit resources 212. Alternatively or additionally, link layer 220 and physical layer 230 may include a set of receive resources 224 anda set of receive resources 234, each of which prepares packets received in different ways for decomposition by the set of receive resources 214.

[0021] The protocol stack 200 may support multiple connections, for example, serial point-to-point connections, each having one or more respective lanes at a given time. Each lane may have a serial channel, which may be implemented, for example, as a differential signal line, a single-ended signal line, or a fiber optic channel. For example, a connection may be a unidirectional point-to-point connection, with each lane of the connection used to send data from a device, or each lane of the connection used to receive data sent to that device. Alternatively, a connection may be bidirectional, with, for example, one or more lanes of the connection sending data from a device in different ways and one or more other lanes of the connection receiving data sent to that device in different ways.The multiple connections supported by protocol stack 200 may include at least one connection that may have different total numbers of lanes currently active at different times in implementing respective communications. For brevity, such a connection is referred to herein as a "variable width" connection, where "width" should be understood as indicating the total number of currently active lanes of the connection.

[0022] At the multiple connections supported by protocol stack 200, certain resources of protocol stack 200 may support only one such connection. For example, one or more of resource sets 212, 214, 222, 224, 232, 234 may enable communication over a first of the multiple connections, with one or more of these resource sets not being used to enable communication of any other of the multiple connections. According to such an embodiment, at least in connection with the multiple connections, one or more of these resource sets may be referred to as being specific or dedicated to that first connection. These resources may be connection-specific, at least in part, as a result of the hard-wired circuitry of the serial I / O interface, although certain embodiments are not limited in this regard.

[0023] Fig. 3 shows elements of a system 300 for providing power switching according to one embodiment. For example, system 300 may include some or all of the features of system 100. According to one embodiment, system 100 includes a processor, peripheral, or other device (such as device 100), including a serial I / O interface, wherein the device is coupled to or includes logic that provides some or all of the functionality of power transfer logic 140.

[0024] The system 300 may include a power transfer unit 310 that includes logic, for example, including hardware, firmware, and / or execution software, to selectively switch the transfer of power to various resources of the serial I / O interface of the system 300. The power transfer unit 310 may include some or all of the features of the power transfer logic 140. According to one embodiment, the power transfer unit 310 is coupled in various ways to various resources of a serial I / O interface (also referred to herein as "interface resources" or simply "resources" for brevity). The interface resources may variously support multiple communication links, for example, point-to-point serial links, each having one or more respective lanes at a given time.

[0025] For illustrative purposes, and without limitation, power transfer unit 310 may couple to resource set 340a, where resource set 340a may include, for example, one or more receive resources 342a and / or one or more transmit resources 344a. Alternatively or additionally, resource set 340a may include one or more resources used for both transmitting and receiving data. Resource set 340a may include any of a variety of additional or alternative resources, according to various embodiments. Of the multiple connections supported by the serial I / O interface of system 300, resource set 340a may support communication of only a particular connection.For example, the operation of resource set 340a may enable communication over a first connection 305 of the plurality of connections, with communication of any other of the plurality of connections being implemented independently of resource set 340a.

[0026] Certain features of various embodiments are discussed herein in the context of a resource set specific to a bidirectional connection, where resource set 340a includes, for example, one or more receive resources 342a for a bidirectional connection for receiving communications and one or more transmit resources 344a for that bidirectional connection for sending communications. However, this discussion may be expanded to additionally or alternatively apply to a set of interface resources specific to a unidirectional connection. For example, one or more receive resources 342a may be a set of resources specific to a unidirectional receive connection, and / or one or more receive resources 342b may be a set of resources specific to a unidirectional transmit connection.

[0027] According to one embodiment, the serial I / O interface of system 300 includes, in addition to resource set 340a, other resources for supporting communication with the connection or connections of the plurality of connections other than the first connection 305. By way of illustration, and without limitation, the serial I / O interface may include a resource set 340b that includes one or more receive resources 342b and / or one or more transmit resources 344b. The resource set 340b may be specific to a different one of the plurality of connections, although particular embodiments are not limited in this regard.For example, operation of resource set 340b may enable communication over a second connection, such as a second bidirectional connection, from the plurality of connections, where resource set 340b is not operable to enable communication of any other of the plurality of connections.

[0028] The power transfer unit 310 may include control logic 320 to monitor a connection, wherein, of the multiple connections of the serial I / O interface, a resource set of the serial I / O interface is specific to that connection. For example, the control logic may monitor the bidirectional connection 305 corresponding to the resource set 340a. When monitoring such a connection 305, the control logic 320 may monitor one or more lanes of the connection, for example, to detect a respective level of lane activity (or inactivity) for each such lane. Alternatively or additionally, the control logic 320 may receive a dedicated message from the serial I / O interface identifying the activity (or inactivity) of one or more lanes.Any of a variety of conventional mechanisms for monitoring an I / O interface may be adapted for control logic 320 to monitor connection 305 according to various embodiments.

[0029] According to one embodiment, when monitoring connection 305, control logic 320 monitors a count value LCount 322 of a total number of active lanes of connection 305. The activity (or inactivity) of a lane may be determined, for example, based on the rate of information exchange across the lane, for example, based on a comparison of such information exchange rate to zero (0) or another threshold. According to one embodiment, monitored connection 305 is a variable-width connection, where, for example, a value of LCount 322 identifies a current width of connection 305. Control logic 320 may monitor the width of one or more additional or alternative connections, according to various embodiments.

[0030] Based on the monitoring, control logic 320 may detect a change in LCount 322. In response to the detected change in LCount 322, power transfer unit 310 may change the state of power transfer to one or more serial I / O interface resources. For example, power transfer unit 310 may further include power gating logic 330 coupled between resource set 340a and one or more power supplies. Power gating logic 330 may include logic to selectively couple interface resources to a power supply and / or selectively decouple those interface resources from a power supply, where, for example, those resources may be selectively coupled / decoupled independently of one another.For illustrative purposes, and without limitation, power gate logic 330 may include switching logic, including, for example, illustrative switching elements SE1 332, SE2 334, each coupled between a power supply and a respective interface resource (or set of interface resources). SE1 332 may selectively provide power coupling / decoupling to, for example, only one or more resources of resource set 340a. Alternatively or additionally, SE2 334 may selectively provide power supply coupling / decoupling to only one or more resources of resource set 340b.

[0031] One or more switching elements of power gate logic 330, for example, SE1 332 and SE2 334, may operate independently of each other. By way of illustration and without limitation, SE1 332 may decouple one or more receive resources 342a and / or one or more transmit resources 344a from a power supply, for example, in response to LCount 322 changing to zero or another threshold (or, according to one embodiment, below a threshold). This decoupling of one or more resources of resource set 340a may occur while the state of the power coupling (e.g., coupled or decoupled) with SE2 334 remains unchanged.

[0032] Alternatively or additionally, such decoupling of one or more resources of resource set 340a may occur while the power coupling state for one or more other resources of resource set 340a remains the same. For example, SE1 332 may selectively provide power to only a subset of the resources in resource set 340a, with, for example, one or more other resources of resource set 340a being powered independently of SE1 332. According to one embodiment, power gating logic 330 includes one or more other switching elements (not shown) to provide selective power coupling / decoupling to such other resources of resource set 340a independently of the selective power coupling / decoupling by SE1 332.

[0033] Certain features of various embodiments are discussed herein with respect to selectively coupling different interface resources to the same power supply and / or selectively decoupling different interface resources from the same power supply. However, this discussion may be expanded to additionally or alternatively apply to selectively coupling interface resources to a different respective power supply and / or selectively decoupling interface resources from a different respective power supply.

[0034] Fig. 4 shows elements of a method 400 for providing power switching for an I / O interface according to one embodiment. The method 400 may switch power transmission to an interface such as the I / O interface 105. According to one embodiment, the method 400 is executed by logic comprising some or all of the functionality of the power transmission unit 310.

[0035] The method 400 may monitor a first of a plurality of connections at 410, wherein an I / O interface has resources comprising a first set of resources operable to support communication only over the first connection. The I / O interface may be configured to couple to an interconnect compliant with, for example, a PCI interconnect standard. According to one embodiment, the I / O interface is located on a first processor, the interconnect being provided for communication between the first processor and a second processor. According to one embodiment, the first set of resources comprises resources of a physical layer of a protocol stack. Alternatively or additionally, the first set of resources may comprise resources of a link layer and / or resources of a transaction layer in such a protocol stack.

[0036] The method 400 may further detect, at 420, a change in the total number of active lanes of the first interconnect based on the monitoring. Upon detecting the change at 420, for example, communications over the interconnect may be detected to negotiate a width change for the first interconnect. Alternatively or additionally, upon detecting the change at 420, a transition to a standby state (e.g., L1) or other low-power state by another device that is a target of the I / O communication may be detected.

[0037] In response to determining the change in the total number of active lanes of the first connection, the method 400 may, at 430, decouple a resource of the first resource set from a respective power supply. For example, the power decoupling at 430 may occur in response to determining that no lanes of the first connection are active. According to one embodiment, the power decoupling at 430 is independent of any power decoupling for any other interface resource. For example, the power decoupling at 430 may be independent of any decoupling of a resource of a second resource set from a respective power supply, where the second resource set is specific to a second of the plurality of connections. Alternatively or additionally, the decoupling at 430 may be independent of any power decoupling of any other resource of the first resource set.According to one embodiment, monitoring is resumed or continued at 410 after the decoupling has occurred at 430 and while other resources of the first resource set continue to be powered. These other resources of the first resource set may, for example, maintain state information for the first connection.

[0038] According to one embodiment, method 400 further comprises one or more operations (not shown) for coupling—e.g., re-coupling—one or more interface resources to a power supply. For example, monitoring may be resumed or continued at 410 after decoupling at 430, wherein another change in the total number of active lanes is detected based on the additional monitoring. In response to detecting the other change in the total number of active lanes, the resource previously decoupled from power at 430 may be recoupled to the respective power supply. This coupling may, for example, occur in response to detecting activity of at least one lane of the first connection.

[0039] Certain embodiments independently decouple one or more interface resources of a layer in a protocol stack, where these one or more resources are specific to a particular one of a plurality of connections. These one or more resources may be distinguished from conventional interface resources, for example, at least in that the one or more resources are in a performance range specific to the hardware for that particular connection. However, these one or more resources may implement any functionality of the protocol stack layer using otherwise conventional techniques and / or mechanisms.

[0040] By way of illustration and without limitation, physical layer resources to be independently power-coupled and / or decoupled may include scrambling circuitry for providing data scrambling and / or descrambling functionality, for example, including per-lane and / or link width scrambling / descrambling.Alternatively or additionally, these physical layer resources may include one or more of pre-emphasis logic for highlighting a portion of a data transmission, a byte lock circuit for identifying a reference point in a data frame, a clock compensation FIFO for enabling communication operations spanning different clock domains, a de-skewing buffer and / or control logic, a frequency compensation buffer, 8b / 10b encoder (or decoder) logic, and / or a variety of other such logic for implementing physical layer functionality.Examples of link layer resources that may be decoupled independently of a power supply include, for example, logic for fragmenting a packet for transmission over a link, logic for defragmenting a packet received over a link, error detection and / or error correction logic such as a cyclic redundancy check (CRC) generation / checking circuit, and / or a variety of other such logic for implementing link layer functionality. Any of a variety of additional or alternative resources of the physical layer, the link layer, and / or other layers of a protocol stack may be independently power-coupled / decoupled according to various embodiments.

[0041] For example, according to one illustrative embodiment, power gating logic 330 responds to the inactivity of lanes in a link by performing power decoupling for one or more resources specific to that link, but without performing power decoupling for other resources specific to that link. According to one embodiment, the other resource maintains state information for the link. By way of illustration and without limitation, the other resource includes one or more physical layers, such as control registers, status registers, a training state and state machine (LTSSM), and / or other such resources, that maintain the state of the link.Alternatively, the other resource may comprise one or more link layer resources such as a link layer control register, status register, reentrant state machine, and / or the like.

[0042] Fig. 5 shows elements of a system 500 for providing a power circuit according to one embodiment. For example, system 500 may include some or all of the features of system 300. According to one embodiment, system 500 includes a processor, peripheral, or other device (such as device 100), including a serial I / O interface, wherein the device is coupled to or includes logic that provides some or all of the functionality of power transfer unit 310.

[0043] According to one embodiment, the serial I / O interface of system 500 includes resources to support communication with multiple connections, including one or more variable-width connections. In supporting this communication, the serial I / O interface may implement a layered protocol stack. By way of illustration and without limitation, the serial I / O interface may implement a link layer of a protocol stack, for example, with a link-layer resource set 510a specific to a first connection and a link-layer resource set 510n for a second connection different from the first connection.Alternatively or additionally, the serial I / O interface may implement a physical layer of such a protocol stack, for example, with a physical layer resource set 520a specific to the first connection and a physical layer resource set 520n specific to the second connection different from the first connection.

[0044] According to one embodiment, the link layer resource set 510a comprises one or more transmit resources 512a for transmitting data, a receive resource 514a for receiving data, and according to one embodiment, another resource 516a for transmitting data, receiving data, or both. Similarly, the link layer resource set 510n may comprise one or more of a transmit resource 512n, a receive resource 514n, and according to one embodiment, another resource 516a for transmitting data, receiving data, or both. Alternatively, the physical layer resource set 520a may comprise one or more transmit resources 522a for transmitting data, a receive resource 524a for receiving data, and according to one embodiment, another resource 526a for transmitting data, receiving data, or both.Similarly, the physical layer resource set 520n may include one or more of a transmit resource 522n, a receive resource 524n, and, according to one embodiment, another resource 516a for transmitting data, receiving data, or both.

[0045] In implementing the protocol stack, a link layer finite state machine (FSM) 530 of the system 500, or other such logic, may operate to variously provide control signals 532 for respective operations of the link layer resource set 510a and / or the link layer resource set 510n. Alternatively or additionally, the system 500 may include a physical layer FSM 540, or other such logic, to variously provide control signals 542 for respective operations of the physical layer resource set 520a and / or the physical layer resource set 520n. Some or all of the control signals 532, 542 may correspond to conventional techniques for operating a protocol stack and may not be limited to particular embodiments.

[0046] System 500 may include circuitry for switching power transfer to serial I / O interface resources. For example, system 500 may include a power-switching FSM 550 or other such logic to selectively control the coupling of various interface resources to a respective power supply. For example, power-switching FSM 550 may include some or all of the features of power transfer unit 310. According to one embodiment, power-switching FSM 550 performs method 400.

[0047] The power-switching FSM 550 may receive one or more signals from the link-layer FSM 530 and / or the physical-layer FSM 540 to monitor one of the multiple connections supported by the interface resources of the system 500. By way of illustration, and without limitation, the power-switching FSM 550 may monitor a first connection supported by the link-layer resource set 510a and / or the physical-layer resource set 520a, wherein, of the multiple connections, the link-layer resource set 510a and / or the physical-layer resource set 520a supports communication of only that first connection.According to one embodiment, the power switching FSM 550 may further monitor a second connection supported by the link layer resource set 510n and / or the physical layer resource set 520n, wherein, of the plurality of connections, the link layer resource set 510n and / or the physical layer resource set 520n supports communication of only that second connection.

[0048] Based on the monitoring, the power-switching FSM 550 may detect a change in a width of the first connection. In response to such a change in the first connection, the power-switching FSM 550 may implement a set of power-saving operations for changing the width of the first connection. By way of illustration and without limitation, in response to the first connection having no active traces, the power-switching FSM 550 may decouple one or more of a set of power lines 552a from a respective power supply, for example, the same power supply, in various ways. The set of power lines 552a may supply different respective ones of the transmit resource 512a, the receive resource 514a, and the resource 516a in various ways.Alternatively or additionally, the power-switching FSM 550 may decouple one or more of a set of power lines 554a from a respective power supply, for example, the same power supply, in various ways. The set of power lines 552a may supply different ones of the transmit resource 522a, the receive resource 524a, and the resource 526a in various ways.

[0049] According to one embodiment, the power-switching FSM 550 may further detect, for example, based on the monitoring, a change in the width of the second connection with the link layer FSM 530 and / or the physical layer FSM. In response to such a change in the second connection, the power-switching FSM 550 may implement a set of power-saving operations for changing the width of the second connection. By way of illustration and without limitation, in response to the second connection having no active lanes, the power-switching FSM 550 may decouple one or more of a set of power lines 552n, each in different ways, from a respective power supply, for example, the same power supply. The set of power lines 552n may supply different respective ones of the transmit resource 512n, the receive resource 514n, and the resource 516n in different ways.Alternatively or additionally, the power-switching FSM 550 may decouple one or more of a set of power lines 554n from a respective power supply, for example, the same power supply, in various ways. The set of power lines 552n may supply different ones of the transmit resource 522n, the receive resource 524n, and the resource 526n in various ways.

[0050] The selective power coupling / decoupling of a resource of the link layer resource set 510a and the physical layer resource set 520a may be independent of a selective power coupling / decoupling of another resource of the link layer resource set 510a and the physical layer resource set 520a. Alternatively or additionally, the selective power coupling / decoupling of a resource of the link layer resource set 510a and the physical layer resource set 520a may be independent of a selective power coupling / decoupling of a resource of the link layer resource set 510n and the physical layer resource set 520n.

[0051] Fig. 6 is a block diagram of one embodiment of a computing system in which power switching may be implemented. System 600 represents a computing device according to an embodiment described herein and may be a laptop computer, a desktop computer, a server, a gaming or entertainment control system, a scanner, a copier, a printer, or other electronic device. System 600 may include a processor 620 that provides processing, operational management, and execution of instructions for system 600. Processor 620 may include any type of microprocessor, central processing unit (CPU), processing core, or other processing hardware for providing processing for system 600.The processor 620 controls the overall operation of the system 600 and may be or include one or more general purpose or special purpose programmable microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or the like, or a combination of these devices.

[0052] A memory subsystem 630 represents the main memory of system 600 and provides intermediate storage for code to be executed by processor 620 or data values ​​to be used in executing a routine. Memory subsystem 630 may include one or more storage devices such as read-only memory (ROM), flash memory, one or more varieties of random access memory (RAM), or other storage devices, or a combination of these devices. Memory subsystem 630 stores and hosts, among other things, an operating system (OS) 636 for providing a software platform for executing instructions in system 600. Additionally, other instructions 638 are stored and executed by memory subsystem 630 to provide the logic and processing of system 600. OS 636 and instructions 638 are executed by processor 620.

[0053] The storage subsystem 630 may include a storage device 632 where it stores data, instructions, programs, or other components. According to one embodiment, the storage subsystem includes a memory controller 634, which is a memory controller according to an embodiment described herein and which provides power transfer mechanisms. According to one embodiment, the memory controller 634 provides instructions to the storage device 632. The instructions may be used to provide the storage device 632 with access to data.

[0054] The processor 620 and the memory subsystem 630 are coupled to a bus / bus system 610. The bus 610 is an abstraction representing one or more separate physical buses, communication lines / interfaces, and / or point-to-point connections connected by suitable bridges, adapters, and / or controllers. Therefore, the bus 610 may include, for example, one or more of a system bus, a peripheral component interconnect (PCI) bus, a HyperTransport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), or an Institute of Electrical and Electronics Engineers (IEEE) Standard 1394 bus (commonly referred to as "Firewire"). The buses or bus 610 may also correspond to interfaces in a network interface 650.

[0055] System 600 may also include one or more input / output (I / O) interfaces 640, a network interface 650, one or more internal mass storage devices 660, and a peripheral interface 670 coupled to bus 610. I / O interface 640 may include one or more interface components through which a user communicates with system 600 (e.g., through video, audio, and / or alphanumeric communication). Network interface 650 provides system 600 with the ability to communicate with remote devices (e.g., servers, other computing devices) over one or more networks. Network interface 650 may include an Ethernet adapter, wireless interconnect components, a USB (universal serial bus), or other wired or wireless standards-based or proprietary interfaces.

[0056] Memory 660 may be or include a conventional medium for storing large amounts of data in a non-volatile manner, such as one or more magnetic disks, semiconductor disks, or optical-based disks, or a combination thereof. Memory 660 maintains code or instructions and data 662 in a permanent state (i.e., the value is maintained despite interruptions in power to system 600). Memory 660 may be generally considered "memory," although memory 630 is the executing memory or working memory for supplying instructions to processor 620. While memory 660 is non-volatile, memory 630 may include volatile memory (i.e., the value or state of the data is indeterminate if power to system 600 is interrupted).

[0057] Peripheral interface 670 may include a hardware interface not specifically mentioned above. Peripherals generally refer to devices that connect independently to system 600. A dependent connection is a connection where system 600 provides the software and / or hardware platform upon which operation is performed and with which a user interacts.

[0058] Fig. Figure 8 shows elements of an illustrative computer system 800 for providing power management according to one embodiment. For example, computer system 800 may include some or all of the features of computer system 100. According to one embodiment, computer system 800 includes a processor 810 and a memory device, such as the illustrative dual in-line memory module (DIMM) 840, coupled thereto via a parallel interconnect 820.

[0059] Processor 810 may include a central processing unit (CPU), a security processor, a graphics processor, a coprocessor, or the like. Processor 810 is an example of a device type that may include a parallel I / O interface for which power circuitry is provided according to one embodiment. By way of illustration and without limitation, processor 810 may include memory control logic 830 for coupling to parallel interconnect 820, where memory control logic 830 may, for example, provide various mechanisms for controlling operations of DIMM 840. Memory control logic 830 may, for example, include some or all of the features of I / O interface 105.

[0060] According to one embodiment, memory control logic 830 operates for processor 810 to read and / or write data from and / or to DRAM devices 842a, ..., 842x of DIMM 840 in various ways. Memory control logic 830 may implement any of a variety of additional or alternative I / O interface functionalities according to various embodiments. DIMM 840 is an example of a device type that may participate in communications with the parallel I / O interface of another device, for which power switching is provided according to one embodiment.

[0061] According to one embodiment, the memory control logic supports multiple links, each communicating over interconnect 820, where, for example, at least one such link is a variable-width link. Processor 810 may include or couple to logic, such as illustrative power switching circuitry 812, to provide fine-grained power switching for memory control logic 830 that is selective on a link-specific basis. This power switching may, for example, exploit short idle intervals to conserve DDR leakage current and may additionally occasionally switch power across all links.

[0062] For example, during a self-refresh (SR) cycle for some or all of the DIMMs 840, a significant portion of the memory control logic 830 may be powered down. There may be some critical architectural states / logic distributed within the memory control logic 830 that must be kept "alive" and cannot be powered down. These states / logic may include, for example, configuration registers 834 specific to a given interconnect. Additionally or alternatively, the memory control logic 830 may include scheduler logic 836 and / or datapath circuitry 838 specific to the given interconnect. According to one embodiment, the scheduler logic 836 and the datapath circuitry 838 must both remain powered even if the specific interconnect transitions to a state where it has no currently active lanes.Alternatively or additionally, such states / logic may include logic that drives a clock enable (CKE) pin low to maintain the DIMM 840 in self-refresh, a state machine for maintaining an indication that the DIMM 840 is in self-refresh and / or to enable an appropriate self-refresh exit sequence, transaction queues and associated logic flags that identify whether queues are empty, and / or the like.

[0063] According to one embodiment, memory control logic 830 includes other logic specific to a given one of a plurality of interconnects, which may be selectively power-switched, for example, in response to a change in the number of active lanes of the given interconnect. For example, memory control logic 830 may further include address decoding logic 832 configured to perform address decoding operations for a specific interconnect. According to one embodiment, address decoding logic 832 may be decoupled from some or all of the power by switching in response to the specific interconnect transitioning to a state in which it has no currently active lanes.Any of a variety of additional or alternative components (not shown) of the memory control logic 830 may be selectively power switched by a power switching circuit according to various embodiments.

[0064] Fig. 7 is a block diagram of one embodiment of a mobile device in which power switching may be implemented. Device 700 represents a mobile computing device such as a computing tablet, a cellular phone or smartphone, a wireless-enabled e-reader, or other mobile device. It should be noted that certain of the components are illustrated generically, and that not all components of such a device are illustrated in device 700.

[0065] Device 700 may include a processor 710 that performs the primary processing operations of device 700. Processor 710 may include one or more physical devices such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. According to one embodiment, processor 710 includes optical interface components in addition to a processor die. Accordingly, the processor die and the photonic components are located in the same package. Such a processor package may be optically connected with an optical connector, according to one embodiment described herein.

[0066] The processing operations performed by processor 710 include executing an operating platform or operating system upon which applications and / or device functions are executed. The processing operations include operations related to I / O (input / output) with a human user or with other devices, operations related to power management, and / or operations related to connecting device 700 to another device. The processing operations may also include operations related to audio I / O and / or display I / O.

[0067] According to one embodiment, device 700 includes an audio subsystem 720 representing hardware components (e.g., audio hardware and audio circuitry) and software components (e.g., drivers, codecs) associated with providing audio functions to the computing device. Audio functions may include a speaker and / or headphone output, as well as a microphone input. Devices for such functions may be integrated into device 700 or connected to device 700. According to one embodiment, a user interacts with device 700 by providing audio commands that are received and processed by processor 710.

[0068] The display subsystem 730 represents hardware components (e.g., display devices) and software components (e.g., drivers) that provide a user with a visual and / or tactile display for interacting with the computing device. The display subsystem 730 may include a display interface 732, which may include the particular screen or hardware device used to provide a display to a user. According to one embodiment, the display interface 732 includes logic separate from the processor 710 to perform at least some processing related to the display. According to one embodiment, the display subsystem 730 includes a touchscreen device that provides both output and input to a user.

[0069] An I / O controller 740 represents hardware devices and software components related to interaction with a user. The I / O controller 740 may manage hardware that is part of the audio subsystem 720 and / or the display subsystem 730. Additionally, the I / O controller 740 illustrates a connection point for additional devices that connect to the device 700, whereby a user could interact with the system. For example, devices that can be connected to the device 700 could include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I / O devices for use with specific applications such as card readers or other devices.

[0070] As mentioned above, the I / O controller 740 may interact with the audio subsystem 720 and / or the display subsystem 730. For example, input from a microphone or other audio device may provide input or commands for one or more applications or functions of the device 700. Additionally, audio output may be provided instead of or in addition to the display output. In another example, if the display subsystem includes a touchscreen, the display device also acts as an input device, managed at least in part by the I / O controller 740. There may also be additional buttons or switches on the device 700 to provide I / O functions managed by the I / O controller 740.

[0071] According to one embodiment, I / O controller 740 manages devices such as accelerometers, cameras, light or other environmental sensors, gyroscopes, a global positioning system (GPS), or other hardware that may be included in device 700. The input may be part of direct user interaction, as well as provide environmental input to the system to influence its operations (such as noise filtering, setting indicators for brightness detection, applying a flash for a camera, or other features).

[0072] According to one embodiment, device 700 includes power management 750 that manages battery power usage, battery charging, and features related to power saving. Storage subsystem 760 may include storage device(s) 762 for storing information in device 700. Storage subsystem 760 may include non-volatile storage devices (the state does not change when power to the storage device is interrupted) and / or volatile storage devices (the state is indeterminate if power to the storage device is interrupted). Storage subsystem 760 may store application data, user data, music, photos, documents, or other data, as well as system data (long-term or temporary) related to the execution of the applications and functions of system 700.According to one embodiment, the memory subsystem 760 includes a memory controller 764 (which could also be considered part of the controller of the system 700 and possibly considered part of the processor 710). According to one embodiment, the memory controller 764 issues commands for accessing the memory 762.

[0073] Connectivity 770 may include hardware devices (e.g., wireless and / or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable device 700 to communicate with external devices. The device could consist of separate devices such as other computing devices, wireless access points or base stations, and peripherals such as headsets, printers, or other devices.

[0074] Connectivity 770 may include several different connectivity types. For example, device 700 is depicted with cellular connectivity 772 and wireless connectivity 774. Cellular connectivity 772 generally refers to cellular network connectivity provided by wireless carriers, such as GSM (Global System for Mobile Communications) or variations or derivatives, CDMA (Distinctive Multiple Access) or variations or derivatives, TDM (Time Division Multiple Access) or variations or derivatives, LTE (Long Term Evolution - also referred to as "4G"), or other cellular service standards. Wireless connectivity 774 refers to wireless connectivity that is not based on cellular, and may include personal area networks (such as Bluetooth), local area networks (such as Wi-Fi), and / or wide area networks (such as WiMax), or other wireless communication.Wireless communication refers to the transmission of data using modulated electromagnetic radiation over a non-fixed medium. Wired communication occurs over a fixed communication medium.

[0075] Peripheral connections 780 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) for forming peripheral connections. It should be noted that device 700 could be a peripheral device ("to" 782) to other computing devices, as well as have peripheral devices connected to it ("from" 784). Device 700 typically includes a "port connector" to connect other computing devices for purposes such as managing (e.g., downloading and / or uploading, modifying, synchronizing) content on device 700. Additionally, a port connector may enable device 700 to connect certain peripherals that enable device 700 to control content output, for example, to audiovisual or other systems.

[0076] In addition to a proprietary port connector or other proprietary connection hardware, device 700 may establish peripheral connections 780 via common or standards-based connectors. Common types may include a Universal Serial Bus (USB) connector (which may have any of a number of different hardware interfaces), DisplayPort, including Mini DisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or another type.

[0077] According to one aspect, an apparatus comprises power gating logic for coupling to control logic, the control logic monitoring a first of a plurality of connections, a serial input / output (I / O) interface having resources comprising a first set of resources operable to support communication only over the first connection, the power gating logic decouples a resource of the first set of resources from a respective power supply in response to detection by the control logic of a change in the total number of active lanes of the first connection.

[0078] According to one embodiment, the plurality of connections further includes a second connection, wherein the resources further comprise a second resource set operable to support communication only over the second connection, wherein the power gating logic decouples the resource of the first resource set from the respective power supply regardless of a resource of the second resource set being decoupled from a respective power supply. According to one embodiment, the power gating logic is operable to decouple the resource of the first resource set from the respective power supply in response to a detection by the control logic that no lanes of the first connection are active.According to one embodiment, the power gate logic is operable to decouple the resource of the first resource set from the respective power supply regardless of another resource of the first resource set being decoupled from a respective power supply.

[0079] According to one embodiment, the other resource of the first resource set maintains state information for the connection. According to one embodiment, the control logic is further to monitor the plurality of connections after the resource of the first resource set has been decoupled from the respective power supply and while the other resource of the first resource set is being powered. According to one embodiment, the I / O interface is for communication compatible with a Peripheral Component Interconnect (PCI) communication standard. According to one embodiment, the I / O interface is for communication between a first processor and a second processor.

[0080] According to another aspect, a system comprises an input / output (I / O) interface having resources including a first set of resources for supporting communication only over a first of a plurality of connections. The system further comprises a power transfer unit having control logic for monitoring the first connection, the control logic for detecting a change in the total number of active lanes of the first connection. The power transfer unit further comprises power gating logic coupled to the control logic, the power gating logic for decouplering a resource of the first set of resources from a respective power supply in response to a change in the total number of active lanes of the first connection.

[0081] According to one embodiment, the plurality of connections further includes a second connection, wherein the resources further include a second resource set operable to support communication only over the second connection, wherein the power gating logic is operable to decouple the resource of the first resource set from the respective power supply regardless of whether a resource of the second resource set is decoupled from a respective power supply. According to one embodiment, the power gating logic is operable to decouple the resource of the first resource set from the respective power supply in response to a detection by the control logic that no lanes of the first connection are active.According to one embodiment, the power gate logic is operable to decouple the resource of the first resource set from the respective power supply regardless of another resource of the first resource set being decoupled from a respective power supply.

[0082] According to one embodiment, the other resource of the first resource set maintains state information for the connection. According to one embodiment, the control logic is further to monitor the plurality of connections after the resource of the first resource set has been decoupled from the respective power supply and while the other resource of the first resource set is being powered. According to one embodiment, the I / O interface is for communication compatible with a Peripheral Component Interconnect (PCI) communication standard. According to one embodiment, the I / O interface is for communication between a first processor and a second processor.

[0083] According to one aspect, a method monitors a first of a plurality of connections, an input / output (I / O) interface having resources including a first set of resources configured to support communication only over the first connection, and detects, based on the monitoring, a change in the total number of active lanes of the first connection. The method further comprises, in response to detecting the change in the total number of active lanes of the first connection, decoupling a resource of the first set of resources from a respective power supply.According to one embodiment, the plurality of connections further include a second connection, wherein the resources further comprise a second resource set operable to support communication only via the second connection, wherein the decoupling of the resource of the first resource set from the respective power supply is independent of a decoupling of a resource of the second resource set from a respective power supply. According to one embodiment, the decoupling of the resource of the first resource set from the respective power supply occurs in response to detecting that no lanes of the first connection are active. According to one embodiment, the decoupling of the resource of the first resource set from the respective power supply is independent of a decoupling of another resource of the first resource set from a respective power supply.According to one embodiment, the other resource of the first resource set maintains state information for the connection. According to one embodiment, the I / O interface is for communication compatible with a Peripheral Component Interconnect (PCI) communication standard. According to one embodiment, the I / O interface is for communication between a first processor and a second processor.

[0084] According to another aspect, instructions are stored on a computer-readable storage medium that, when executed by one or more processing units, cause the one or more processing units to perform a method. The method includes monitoring a first of a plurality of connections, wherein an input / output (I / O) interface has resources including a first set of resources operable to support communication only over the first connection, and detecting a change in the total number of active lanes of the first connection based on the monitoring. The method further comprises, in response to detecting the change in the total number of active lanes of the first connection, decoupling a resource of the first set of resources from a respective power supply.

[0085] According to one embodiment, the plurality of connections further includes a second connection, wherein the resources further comprise a second resource set configured to support communication only over the second connection, wherein the power gating logic decouples the resource of the first resource set from the respective power supply regardless of a resource of the second resource set being decoupled from a respective power supply. According to one embodiment, the decoupling of the resource of the first resource set from the respective power supply occurs in response to detecting that no lanes of the first connection are active.

[0086] According to one embodiment, the decoupling of the resource of the first resource set from the respective power supply is independent of a decoupling of another resource of the first resource set from a respective power supply. According to one embodiment, the other resource of the first resource set maintains state information for the connection. According to one embodiment, the I / O interface is for communication compatible with a Peripheral Component Interconnect (PCI) communication standard. According to one embodiment, the I / O interface is for communication between a first processor and a second processor.

[0087] Techniques and architectures for managing power transfer are described herein. In the foregoing description, for explanatory purposes, numerous specific details are set forth in order to provide a thorough understanding of certain embodiments. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without these specific details. In other instances, structures and devices are presented in block diagram form to avoid obscuring the description.

[0088] A reference in the specification to "a single embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The occurrences of the phrase "according to an embodiment" in various places in the specification do not necessarily all refer to the same embodiment.

[0089] Some sections of the detailed description presented here have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by professionals in computer science to most effectively convey the substance of their work to other professionals. An algorithm is considered here and generally to be a self-consistent sequence of steps that lead to a desired result. The steps are those that require physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated.It has occasionally proved convenient, particularly for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0090] It should be borne in mind, however, that all these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.Unless specifically stated otherwise, as will be understood from the discussion provided herein, discussions throughout this specification using such terms as "processing" or "calculating" or "computing" or "determining" or "displaying" or the like refer to the operation and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within registers and memories of the computer system into other data similarly represented as physical quantities within the memories or registers of the computer system or in other such information storage, transmission, or display devices.

[0091] Certain embodiments also relate to an apparatus for performing the operations presented herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer that is selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium such as a disk, including, but not limited to, floppy disks, optical disks, CD-ROM and magneto-optical disks, read-only memories (ROM), random access memories (RAM) such as dynamic random access memory (DRAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions and coupled to a computer system bus.

[0092] The algorithms and displays presented herein do not inherently relate to any particular computer or other device. Various general-purpose systems may be used with programs according to the teachings presented herein, or it may prove convenient to construct a more specialized device for performing the required method steps. The required structure for a variety of these systems will be apparent from the description presented herein. In addition, certain embodiments are not described with reference to a particular programming language. It should be understood that a variety of programming languages ​​may be used to implement the teachings of these embodiments described herein.

[0093] Apart from what is described herein, various modifications may be made to the disclosed embodiments and implementations without departing from their scope. Therefore, the explanations and examples presented herein should be construed as illustrative and not in a limiting sense. The scope of the invention should be measured solely by reference to the following claims.

Claims

[1] Device comprising: a power gate logic (330) for coupling to a control logic (320), wherein the control logic (320) monitors a first of a plurality of connections (305), wherein a serial input / output (I / O) interface comprises a protocol stack comprising a physical layer and a link layer, wherein resources of the serial I / O interface comprise a first set of resources operable to support communication of the plurality of connections only via the first connection, wherein the power gate logic (330) is configured to decouple a link layer resource of the first set of resources from a respective power supply in response to detection by the control logic (320) of a change in the total number of active lanes of the first connection, wherein the power gate logic (330) is configured to decouple the link layer resource of the first set of resources from the respective power supply,regardless of whether any other link layer resource of the first set of resources is decoupled from a respective power supply. [2] The apparatus of claim 1, wherein the plurality of connections (305) further comprises a second connection, wherein the serial I / O interface resources further comprise a second resource set operable to support communication only over the second connection, wherein the power gating logic (330) is operable to decouple the link layer resource of the first resource set from the respective power supply regardless of whether a resource of the second resource set is decoupled from a respective power supply. [3] The apparatus of any of claims 1 and 2, wherein the power gate logic (330) is operable to decouple the link layer resource of the first resource set from the respective power supply in response to the control logic (320) detecting that no lanes of the first link are active. [4] The apparatus of claim 1, wherein the other link layer resource of the first resource set maintains state information for the link. [5] The apparatus of claim 4, wherein the control logic (320) further monitors the plurality of links (305) after the link layer resource of the first resource set has been decoupled from the respective power supply and while the other link layer resource of the first resource set is being powered. [6] The device of any one of claims 1 to 3, wherein the serial I / O interface is provided for communication compatible with a Peripheral Component Interconnect, PCI, communication standard. [7] Apparatus according to any one of claims 1 to 3, wherein the serial I / O interface is provided for communication between a first processor and a second processor. [8] System which includes: an input / output, I / O, interface comprising a protocol stack comprising a physical layer and a link layer, wherein resources of the I / O interface have a first resource set for supporting communication only over a first of a plurality of connections (305), and a power transmission unit comprising: a control logic (320) for monitoring the first connection, the control logic (320) being operable to detect a change in the total number of active lanes of the first connection, and a power gate logic (330) coupled to the control logic (320), wherein the power gate logic (330) is configured to decouple a link layer resource of the first set of resources from a respective power supply in response to the change in the total number of active lanes of the first link, wherein the power gate logic (330) is configured to decouple the link layer resource of the first set of resources from the respective power supply regardless of whether another link layer resource of the first set of resources is decoupled from a respective power supply. [9] The system of claim 8, wherein the plurality of connections (305) further comprises a second connection, wherein the serial I / O interface resources further comprise a second resource set operable to support communication only over the second connection, wherein the power gating logic (330) is operable to decouple the link layer resource of the first resource set from the respective power supply regardless of whether a resource of the second resource set is decoupled from a respective power supply. [10] The system of any of claims 8 and 9, wherein the power gate logic (330) is operable to decouple the link layer resource of the first resource set from the respective power supply in response to the control logic (320) detecting that no lanes of the first link are active. [11] The system of claim 8, wherein the other link layer resource of the first resource set maintains state information for the link. [12] The system of claim 11, wherein the control logic (320) further monitors the plurality of links (305) after the link layer resource of the first resource set has been decoupled from the respective power supply and while the other link layer resource of the first resource set is being powered. [13] The system of any one of claims 8 to 10, wherein the I / O interface is provided for communication compatible with a Peripheral Component Interconnect, PCI, communication standard. [14] The system of any one of claims 8 to 10, wherein the I / O interface is provided for communication between a first processor and a second processor. [15] Procedure comprising the following steps: Monitoring a first of a plurality of connections (305), wherein an input / output, I / O, interface comprises a protocol stack comprising a physical layer and a link layer, wherein resources of the serial I / O interface comprise a first resource set operable to support communication of the plurality of connections only via the first connection, Detecting a change in the total number of active lanes of the first connection based on the monitoring and Decoupling a resource of the first set of resources from a respective power supply in response to detecting the change in the total number of active lanes of the first link, regardless of whether any other link layer resource of the first set of resources is decoupled from a respective power supply. [16] The method of claim 15, wherein the plurality of connections (305) further comprises a second connection, wherein the serial I / O interface resources further comprise a second resource set operable to support communication only over the second connection, wherein the decoupling of the link layer resource of the first resource set from the respective power supply is independent of a decoupling of a resource of the second resource set from a respective power supply. [17] A method according to any one of claims 15 and 16, wherein the decoupling of the link layer resource of the first resource set from the respective power supply occurs in response to the detection that no lanes of the first link are active. [18] The method of claim 15, wherein the other link layer resource of the first resource set maintains state information for the link. [19] A method according to any one of claims 15 to 17, wherein the I / O interface is provided for communication compatible with a Peripheral Component Interconnect, PCI, communication standard. [20] A method according to any one of claims 15 to 17, wherein the I / O interface is provided for communication between a first processor and a second processor. [21] A computer program product having stored thereon instructions which, when executed by a processor, carry out the method according to any one of claims 17 to 20.

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