semiconductor device

Abstract

A semiconductor device (500) comprising: a first memory gate (522a) disposed in a first region (504) of the semiconductor device, the first memory gate (522a) comprising a first gate conductor layer (516) disposed over a charge-trapping dielectric (514); a first select gate (534a) disposed in the first region adjacent to a sidewall of the first memory gate (522a); a second select gate (534b) disposed adjacent to the first select gate (534a) in the first region (504) such that the first select gate (534a) is disposed between the first memory gate (522a) and the second select gate (534b); a sidewall dielectric (524) disposed between the sidewall of the first memory gate (522a) and the first select gate (534a);a logic gate (544) arranged in a second region (506) of the semiconductor device (500) and comprising the first gate conductor layer (516);a select gate dielectric (512a) disposed between the first memory gate (522a) and a second memory gate (522b) and below the first select gate (534a) and the second select gate (534b) such that the select gate dielectric (512a) is continuous;

Description

Field of the invention

[0001] This disclosure generally relates to improved embedded semiconductor devices and methods and apparatus for fabricating such semiconductor devices. State of the art

[0002] Flash memory allows stored data to be retained even when the power to the memory is removed. A flash memory cell stores data either by storing electrical charge in an electrically isolated floating gate of a field-effect transistor (FET) or by storing electrical charge in a dielectric layer underlying a control gate of a field-effect transistor (FET). The stored electrical charge controls the threshold of the FET, thereby controlling the memory state of the flash memory cell.

[0003] A flash memory cell is typically programmed using hot carrier injection to inject charge carriers either onto a floating gate or into charge traps in a dielectric layer underlying a control gate. High drain and gate voltages are used to accelerate the programming process. The flash memory cell therefore conducts a high current during programming, which is undesirable in low-voltage or low-power applications.

[0004] A split-gate memory cell is a type of flash memory cell in which a select gate (AG) is placed next to a storage gate (SG), providing a lower current during hot-carrier-based programming. During programming of the split-gate cell, the select gate is biased at a relatively low voltage, and only the storage gate is biased at a high voltage to provide the vertical electric field necessary for hot-carrier injection. Since carrier acceleration in the channel region predominantly occurs below the select gate, the relatively low voltage at the select gate above this region results in more efficient carrier acceleration in the horizontal direction compared to a conventional memory cell. This makes hot-carrier injection more efficient, with lower current and lower power consumption during programming.A split-gate cell can be programmed using techniques other than hot carrier injection, and depending on the technique, the advantage over the conventional flash memory cell during the programming process may vary.

[0005] Another advantage of the split-gate cell is fast read time. Because the select gate is in series with the memory gate, the erased state of the memory gate can be near or in depletion mode (i.e., threshold voltage, Vt, less than zero volts). Even when the erased memory gate is in such depletion mode, the select gate in the off state prevents the channel from conducting significant current. With the threshold voltage of the erased state at or below zero, the threshold voltage of the programmed state does not need to be very high while still providing a reasonable read margin between the erased and programmed states. The resulting voltages applied to both the select gate and the memory gate during the read operation are less than or equal to the supply voltage.Because the supply voltage does not have to be raised to a higher level, the reading process becomes faster.

[0006] It is also becoming increasingly common to monolithically incorporate multiple field-effect devices on the same substrate as the memory cells to provide improved efficiency, security, functionality, and reliability. As such, many processes are tailored to conform to standard CMOS manufacturing. For example, a chip with split-gate cells may also incorporate other field-effect devices to perform various logic and voltage control processes.

[0007] These other field-effect devices may include transistors tailored for high-speed operation, while other transistors are tailored to handle higher-than-normal operating voltages. However, integrating both on the same substrate along with the split-gate cell is challenging, as each requires different manufacturing parameters. Accordingly, there is a need for a device and methods for integrating these split-gate memory cells and other field-effect devices with improved performance, cost, and manufacturability.

[0008] The prior art includes the documents US 7 888 221 B2, US 6 642 103 B2 and US 2011 / 0 242 888 A1. BRIEF SUMMARY OF THE INVENTION

[0009] A semiconductor device is provided. According to embodiments, the semiconductor device comprises a memory gate arranged in a first region of the semiconductor device. The memory gate may comprise a first gate conductor layer, formed, for example, from polycrystalline silicon ("poly") and arranged over a charge-trapping dielectric. A select gate may be arranged in the first region of the semiconductor device adjacent to a sidewall of the memory gate. A sidewall dielectric may be arranged between the sidewall of the memory gate and the select gate. Additionally, the device may comprise a logic gate arranged in a second region of the semiconductor device that includes the first gate conductor layer.

[0010] A method of manufacturing a semiconductor device including a first region and a second region is provided. According to the method, the second region is masked, and a layer of gate conductor is disposed over a charge-trapping dielectric in the first region. The gate conductor layer may be etched to form a memory gate. A sidewall dielectric may be disposed on a sidewall of the memory gate, and a second layer of gate conductor may be formed. The second layer of gate conductor may then be etched to form a select gate adjacent to the sidewall of the memory gate. The first region may then be masked, and a logic gate may be formed in the second region of the semiconductor device.

[0011] Further features and advantages of embodiments of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. It should be understood that the invention is not limited to the specific embodiments described herein. Such embodiments are presented here for illustrative purposes only. Additional embodiments will be apparent to those skilled in the relevant art(s) based on the teachings contained herein. BRIEF DESCRIPTION OF THE DRAWINGS / FIGURES

[0012] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying schematic drawings, in which corresponding reference symbols indicate corresponding parts. Furthermore, the accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present invention and, together with the description, serve to explain the basic principles of the invention and to enable any person skilled in the art to make and use the invention. Fig. 1 illustrates a cross-section of a split-gate memory cell according to various embodiments. Fig. 2 is a circuit diagram of a memory cell in a memory array according to various embodiments. Fig. 3 illustrates a cross-section of a semiconductor device according to various embodiments. Fig. 4 is a functional block diagram of a memory device according to various embodiments. Fig. 5A- Fig. 5l illustrate a cross-section of a memory device at various points during its manufacture according to various embodiments. Fig. 6A- Fig. 6D illustrate a cross-section of a memory device at various points during its manufacture according to various embodiments. Fig. 7 is a flowchart illustrating a method of manufacturing a semiconductor device according to various embodiments. Fig. 8 is a flowchart illustrating a method of manufacturing a semiconductor device according to various embodiments. Fig. 9 is a flowchart illustrating a method of manufacturing a semiconductor device according to various embodiments. Fig. 10 is a flowchart illustrating a method of manufacturing a semiconductor device according to various embodiments. Fig. 11A- Fig. 11E illustrate a cross-section of a memory device at various points during its manufacture according to various embodiments.

[0013] The features and advantages of embodiments of the present invention will become more fully understood from the detailed description set forth below, when taken in conjunction with the drawings. In the drawings, like reference numerals generally identify identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION OF THE INVENTION

[0014] This specification discloses one or more embodiments incorporating the features of this invention. The disclosed embodiment(s) are merely exemplary of the present invention. The present invention is defined by the claims appended hereto.

[0015] The described embodiment(s) and references in the specification to "an embodiment," "an embodiment," etc., indicate that the described embodiment(s) include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Furthermore, such terms do not necessarily refer to the same embodiment. Further, it is understood that where a particular feature, structure, or characteristic is described in connection with one embodiment, it is within the skill of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments, whether expressly described or not.

[0016] Before describing the various embodiments in more detail, an explanation will be given regarding certain terms that may be used throughout the descriptions.

[0017] The term "etch" or "etching" is used herein to generally describe a manufacturing process for patterning a material such that at least a portion of the material remains after the etching process is complete. For example, it should be understood that the process of etching silicon involves the steps of patterning a masking layer (e.g., photoresist or a hard mask) over the silicon and then removing the silicon regions no longer protected by the masking layer. In this way, the silicon regions protected by the mask would remain after the etching process is complete. However, in another example, etching can also refer to a process that does not use a mask but still leaves at least a portion of the material behind after the etching process is complete.

[0018] The above description serves to distinguish the term "etching" from "removal." Etching a material involves leaving at least a portion of the material behind after the process is complete. Removing a material, on the other hand, involves removing substantially all of the material during the process. However, in some embodiments, "removal" is considered a broad term that may include etching.

[0019] Throughout the descriptions herein, reference is made to various regions of the substrate upon which the field-effect devices are fabricated. It should be understood that these regions may exist anywhere on the substrate, and further, the regions may not be mutually exclusive. That is, in some embodiments, portions of one or more regions may overlap. Although up to three distinct regions are described herein, it should be understood that any number of regions may exist on the substrate and may denote areas with certain types of devices or materials. In general, the regions are used to conveniently describe areas of the substrate that include similar devices.

[0020] The terms "deposit" or "deposit" are used herein to describe the act of applying a layer of material to the substrate. Such terms are intended to describe all possible layer-forming techniques, including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc. According to various embodiments, for example, deposition may be performed according to any corresponding well-known method. For example, deposition may include any process in which material is grown on, coated with, or transferred to a substrate.Some well-known technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), and plasma-enhanced CVD (PECVD).

[0021] The "substrate" used throughout the descriptions is most often considered silicon. However, the substrate may also be any of a wide group of semiconductor materials, such as germanium, gallium arsenide, indium phosphide, etc. In other embodiments, the substrate may be electrically non-conductive, such as a glass or sapphire wafer.

[0022] As used herein, "mask" may include any suitable material that allows selective removal (e.g., etching) of an unmasked portion of a material. According to some embodiments, masking structures may include a photoresist, such as poly(methyl methacrylate) (PMMA), poly(dimethylglutarimide) (PMGI), a phenol-formaldehyde resin, a suitable epoxy, etc.

[0023] Before describing such embodiments in more detail, it is instructive to present an exemplary memory cell and environment in which the present embodiments may be implemented.

[0024] Fig. 1 illustrates an example of a non-volatile split-gate memory cell 100. The memory cell 100 is formed on a substrate 102, such as silicon. The substrate 102 is typically p-type or a p-type well, while a first doped source / drain region 104 and a second doped source / drain region 106 are n-type. However, it is also possible for the substrate 102 to be n-type, while the regions 104 and 106 are p-type.

[0025] The memory cell 100 includes two gates, a select gate (AG) 108 and a store gate (SG) 110. Each gate may be a doped gate conductor layer formed by well-known techniques, such as deposition and etching techniques, to define the gate structure. The select gate 108 is disposed over a dielectric layer 112. The store gate 110 is disposed over a charge-trapping dielectric 114 comprising one or more dielectric layers. In one example, the charge-trapping dielectric 114 includes a charge-trapping silicon nitride layer sandwiched between two silicon dioxide layers to create a three-layer stack, collectively and generally referred to as "ONO." Other charge trapping dielectrics may include, but are not limited to, a silicon-rich nitride film or any film comprising silicon, oxygen, and nitrogen in various stoichiometries.For electrical isolation between the two gates, a vertical dielectric 116 is also disposed between the select gate 108 and the memory gate 110. In some examples, the vertical dielectric 116 and the charge-trapping dielectric 114 are the same dielectric, while other examples form one dielectric before the other (e.g., they may have different dielectric properties). As such, the vertical dielectric 116 does not need to comprise the same film structure as the charge-trapping dielectric 114. Regions 104 and 106 are created by implanting dopants, for example, using an ion implantation technique. Regions 104 and 106 form the source or drain of the split-gate transistor, depending on which potentials are applied to each.In split-gate transistors, for convenience, region 104 is commonly referred to as the drain, while region 106 is commonly referred to as the source, regardless of the relative bias voltages. It should be understood that this description is intended to provide a general overview of a typical split-gate architecture and that, in actual practice, many more detailed steps and layers are provided to form the final memory cell 100.

[0026] An exemplary write, read, and erase operation will now be described with respect to memory cell 100. To write a bit to memory cell 100, a positive voltage, for example, on the order of 5 volts, is applied to region 106 while region 104 and substrate 102 are grounded. A low positive voltage, for example, on the order of 1.5 volts, is applied to select gate 108, while a higher positive voltage, for example, on the order of 8 volts, is applied to memory gate 110. As electrons are accelerated within a channel region between source and drain, some of them will gather enough energy to be injected upward and trapped in charge-trapping dielectric 114. This is known as hot electron injection.

[0027] In one example of a charge-trapping dielectric 114, the electrons are trapped within a nitride layer of the charge-trapping dielectric 114. This nitride layer is also commonly referred to as the charge-trapping layer. The charge trapped within the charge-trapping dielectric 114 stores the "high" bit within the memory cell 100, even after the various supply voltages have been removed.

[0028] To "erase" the stored charge within memory cell 100 and reset the state of memory cell 100 to a "low" bit, a positive voltage, for example, on the order of 5 volts, is applied to region 106 while region 104 is floating or at some bias, and select gate 108 and substrate 102 are typically grounded. A high negative voltage, on the order of -8 volts, for example, is applied to memory gate 110. The bias conditions between memory gate 110 and region 106 generate holes through band-to-band tunneling. The generated holes receive sufficient energy from the strong electric field under memory gate 110 and are injected upward into charge-trapping dielectric 114. The injected holes effectively erase memory cell 100 to the "low" bit state.

[0029] To "read" the stored bit of memory cell 100, a low voltage ranging, for example, between zero and 3 volts is applied to each of the select gate, the store gate, and region 104, while region 106 and substrate 102 are typically grounded. The low voltage applied to the store gate is selected to be substantially equidistant between the threshold voltage necessary to turn on the transistor when a "high" bit is stored and the threshold voltage necessary to turn on the transistor when a "low" bit is stored, in order to clearly distinguish between the two states.For example, if the application of the low voltage during the "read" operation causes a significant current to flow between regions 104 and 106, the memory cell holds a "low" bit, and if the application of the low voltage during the "read" operation does not cause a significant current to flow between regions 104 and 106, the memory cell holds a "high" bit.

[0030] Fig. 2 illustrates an exemplary circuit diagram 200 including a memory cell 100, including connections to various metal layers in a semiconductor device. Only a single memory cell 100 is illustrated, however, as shown by the ellipses in both the X and Y directions, a grouping of memory cells may be connected by the various lines extending in both the X and Y directions. In this way, one or more memory cells 100 may be selected for reading, writing, and erasing bits based on the bit line (BL) and source line (SL) used.

[0031] An exemplary source line (SL) runs along the X-direction and is formed in a first metal layer (M1). The source line (SL) can be used to electrically connect to the doped region 106 of each memory cell 100 along a row running in the X-direction.

[0032] An exemplary bit line (BL) runs along the Y-direction and is formed in a second metal layer (M2). The bit line (BL) can be used to establish an electrical connection to the doped region 104 of each memory cell 100 along a column running in the Y-direction.

[0033] It should be understood that the Fig. 2 are merely exemplary, and various connections may be formed in metal layers other than those illustrated. Furthermore, although not illustrated, memory cells 100 may be grouped in the Z-direction and formed within multiple stacked layers.

[0034] Fig. 3 illustrates an exemplary semiconductor device 300 that includes both a memory circuit 302 and a peripheral circuit 304 in the same substrate 102. In this example, the substrate 102 includes a core region 302 and a peripheral region 304. The core region 302 includes a plurality of memory cells 100 that may operate similarly to those previously described. It should be understood that the cross section of Fig. 3 is merely exemplary, and that the core region 302 and the peripheral region 304 may be located in any area of ​​the substrate 102 and may be composed of various different regions. Furthermore, the core region 302 and the peripheral region 304 may exist in the same general area of ​​the substrate 102.

[0035] The substrate 302—and indeed substrates in general, as used in the description—may be silicon according to various embodiments. However, the substrate 302 may also be any of a wide group of semiconductor materials, such as germanium, gallium arsenide, indium phosphide, etc. In other embodiments, the substrate 302 may be electrically non-conductive, such as a glass or sapphire wafer.

[0036] The peripheral region 304 can include integrated circuit components, such as resistors, capacitors, inductors, etc., as well as transistors. In the illustrated embodiment, the peripheral region 304 includes a plurality of high-voltage transistors 306 and low-voltage transistors 308. In one example, the high-voltage transistors 306 exist in a separate region of the substrate 102 from the low-voltage transistors 308. High-voltage transistors 306 can handle voltages as high as, for example, 20 volts, while low-voltage transistors 308 operate at a faster speed but cannot operate at the same high voltages as high-voltage transistors 306. In one embodiment, low-voltage transistors 308 are designed to have a shorter gate length than high-voltage transistors 306.High voltage transistors 306 typically feature a thicker gate dielectric 310 than the gate dielectric of low voltage transistors 308. As shown in . Fig. As shown in Figure 3, low-voltage transistors 308 have a narrower width than high-voltage transistors 306, but this need not be the case. According to some embodiments, low-voltage transistors 308 may be wider than high-voltage transistors 306, or, alternatively, low-voltage transistors 308 and high-voltage transistors 306 may have the same width.

[0037] Throughout the descriptions herein, various regions of the substrate are mentioned on which the field effect devices are fabricated. For example, with reference to Fig. 3, core region 302 and peripheral region 304 were described. It should be understood that these regions may exist anywhere on the substrate, and further, the regions may not be mutually exclusive. That is, in some embodiments, portions of one or more regions may overlap. Although up to three distinct regions are described herein, it should be understood that any number of regions may exist on the substrate and may denote areas with certain types of devices or materials. In general, the regions are used to conveniently describe areas of the substrate that include similar devices.

[0038] Fig. 4 is a functional block diagram of a memory device according to various embodiments of the present invention. As shown, the memory device 402 includes a memory array 404, high-voltage control logic 406, and low-voltage control logic 408. According to various embodiments, the memory array 404 may include a number of memory cells 100 and may be physically located within a core region 302 of the memory device 402. The high-voltage control logic 406 may include a number of high-voltage transistors 306 that may be used to control and / or drive portions of the memory array 404. Additionally, the high-voltage control logic 406 may be located within the periphery 304 of the memory device 402.Similar to high-voltage control logic 406, low-voltage control logic 408 may include a number of low-voltage transistors 308 that may be used to control and / or drive portions of memory array 404. Low-voltage control logic 408 may also be located in the periphery 304 of the memory device. According to various embodiments, high-voltage control logic 406 and low-voltage control logic 408 are located in different portions of the periphery region 304.

[0039] Fig. 5A- Fig. 5J illustrate a cross-section of a semiconductor device 500 at various points during its manufacture according to various embodiments of the present invention. Fig. 5A illustrates 500 after a number of structural features have been formed. As in Fig. 5A, the device 500 includes a substrate 502 that includes three distinct regions 504, 506, and 508.

[0040] A first or memory region 504 of the substrate may be used for memory components. According to various embodiments, the first region 504 comprises a memory core region in which a plurality of memory cells (e.g., memory cell 100) may be formed. For example, according to some embodiments, the first region may be used to form a number of select gate / memory gate pairs.

[0041] Logic and / or control circuitry may be formed in the periphery, which includes second and third regions 506 and 508, respectively, according to various embodiments. The second region 506 may include the high-voltage control logic region 406, and the third region 508 may include the low-voltage control logic (e.g., region) 408.

[0042] As in Fig. 5A, a gate dielectric 512b was formed in the second region 506, and a different gate dielectric 512c was formed in the third region 508. The gate dielectric 512a (not shown in this figure) may be formed at a different time according to various embodiments. Each of the gate dielectrics 512a, 512b, and 512c may include a suitable dielectric material, such as, for example, an oxide. According to various embodiments, the gate dielectrics 512b and 512c may have different thicknesses, but this need not be the case. The gate dielectrics 512b and 512c may be formed by a well-known method. For example, the dielectrics may be grown on the substrate 502 and include an oxide of the substrate material (e.g., silicon oxide). However, it is also possible that the gate dielectrics 512b and 512c are arranged on the substrate and include an oxide made of a different material than the substrate.Additionally, dielectrics 512b and 512c may include the same or different materials and may be formed at the same time or at different times according to various embodiments. A gate dielectric 512a (not shown in this figure) may also be later disposed in first region 504 according to various embodiments. Gate dielectric 512a may be thinner than one of gate dielectrics 512a and 512b, according to some embodiments, but may also have the same thickness as one or both of gate dielectrics 512a and 512b.

[0043] A charge trapping dielectric 514 was disposed over the substrate 502 in the first region 504, as shown in Fig. 5A. According to various embodiments, the charge-trapping dielectric includes one or more layers of dielectric, such as ONO, as described above. For example, the charge-trapping dielectric 514 may include a first dielectric layer 514a, a charge-trapping layer 514b, and a second dielectric layer 514c. Regardless of the specific composition of the charge-trapping dielectric 514, it preferably includes at least one charge-trapping layer 514b. The charge-trapping dielectric may be formed from a nitride or silicon-rich nitride, and may include multiple layers of different nitrides, according to some embodiments.

[0044] A gate conductor layer 516 was formed over all three regions 504, 506, and 508 of device 500. According to various embodiments, gate conductor layer 516 may be disposed or deposited according to a corresponding well-known method, such as deposition. Deposition may include any process in which material is grown on, coated with, or transferred to a substrate. Some well-known technologies include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), and plasma-enhanced CVD (PECVD).

[0045] A cap layer 518 has been formed over all three regions 504, 506, and 508 of device 500. According to various embodiments, cap layer 518 may include a layer of nitride 518a disposed over a layer of dielectric 518b. A mask 520 is disposed over second region 506 and third region 508. Mask 520 may additionally be patterned in first region 504. Both masks 520 may include a suitable material that allows selective removal (e.g., etching) of the unmasked portion of gate conductor layer 516. According to some embodiments, masking structures may include a photoresist, such as poly(methyl methacrylate) (PMMA), poly(dimethylglutarimide) (PMGI), a phenol-formaldehyde resin, a suitable epoxy, etc.

[0046] Fig. 5B illustrates a cross-section of device 500 after gate conductor 516 has been removed from the unmasked portion of the first region. Additionally, charge-trapping dielectric 514 disposed between memory gates 522a and 522b is removed. According to some embodiments, the removed portion of gate conductor layer 514 and charge-trapping dielectric 514 are removed by a number of corresponding etching processes. Gate conductor layer 516 may be etched, for example, using Cl2, KOH, TMAH (tetramethylaminohydroxyl), or using gas-phase etching with, for example, H2, HCl, O2, H2O (vapor or gas), O3, HF, F2, and carbon-fluorine compounds with Cl2 and XeF2. Additionally, according to some embodiments, a combination of etching products may be used.

[0047] As in Fig. 5B, the remaining portions of the gate conductor 516 in the first region 504 form the memory gates 522a / 522b. Additionally, a dielectric 524 has been formed on the sidewalls of the memory gates and the charge-trapping dielectric 514. According to various embodiments, the dielectric may include a single-layer dielectric or a multi-layer dielectric, such as ONO described above. Additionally, a select gate dielectric 512a may be grown in the first region 504 according to various embodiments.

[0048] In Fig. 5C, a second gate conductor layer 526 has been formed over the memory gates 522 in the first region 504. According to some embodiments, the second gate conductor layer 526 may be substantially conformal to the other structures formed in the first region, but this may not be the case in all embodiments. A second gate conductor layer 526 has been formed over the second region 506 and the third region 508, as shown in Fig. 5C shown.

[0049] Fig. Figure 5D illustrates the partial removal of the second gate conductor layer 526. As can be seen, a portion of the second gate conductor layer 526 remains disposed on the sidewalls of the memory gates 522a and 522b. The gate conductor portions 528a and 528b will eventually include the select gates for the memory cells to be formed using the memory gates 522a and 522b. However, portions 530a and 530b are redundant. The redundant portions 530a and 530b can be removed by masking the portions 528a and 528b with the mask 532, as shown in Fig. 5E. After being masked, the redundant portions 530a and 530b as well as the unmasked portion of the dielectric 524 can be removed. The result of this removal is shown in Fig. 5F illustrates.

[0050] Fig. 5G illustrates a cross-section of the device 500 after several additional steps have been performed according to various embodiments. In Fig. 5G, the first and second regions 504 and 508 are masked with the mask 536. In addition, the mask 536 may be patterned over the second region 506 over the cap layer 518. The portion of the cap layer 518 and the second gate conductor 516 that is not under the patterned mask 536 is removed from the second region 506, as shown. After the gate 544 has been defined in the second region, the lightly doped drain and source masks and implants are performed to form the junctions adjacent to the gates 544. After the Fig. 5G, the mask 536 may be removed from the device 500 and the nitride portion 518a may be removed from the cap layer 518 in all three regions, for example, using a nitride wet stripping process.

[0051] Fig. 5H illustrates a cross-section of device 500 after gate 544 has been defined by removing a portion of second gate conductor 516 from second region 506. Additionally, a mask 546 has been disposed in second region 506 to protect gate 544 from the process steps of forming logic gates in third region 508. Additionally, mask 546 has been patterned in third region 508 to enable the formation of a gate 548 in third region 508.

[0052] Fig. Figure 5l illustrates a cross-section of device 500 after a second logic gate 548 has been defined in third region 508. Additionally, mask 546 is removed from first region 504 and second region 506. Any remaining portions of cap layer 518 are also shown removed. At this point, device 500 therefore includes a pair of memory cells 550a and 550b disposed in first region 504 of device 500. Each of memory cells 550a and 550b includes a memory gate 522a and 522b, respectively (referred to generally herein as "memory gate 522") and a select gate 534a and 534b, respectively. A dielectric 524a and 524b, disposed on the sidewall of the memory gate, electrically isolates the select gates 534a and 534b from their associated memory gates 522a and 522b. Charge-trapping dielectrics 514a and 514b are disposed beneath the memory gates 522a and 522b.As discussed above, charge-trapping dielectrics 514a and 514b may include one or more dielectric layers comprising a charge-trapping layer. Additionally, charge-trapping dielectrics 514a and 514b are formed separately and independently from sidewall dielectrics 524a and 524b.

[0053] In addition to the memory cells 550a and 550b, the device 500 includes a first gate 544 disposed in the second region 506 and a second gate 548 disposed in the third region 508. According to various embodiments, the second region may be configured to accommodate high-voltage circuitry and logic, and accordingly, the gate 544 may be designed to handle high voltage. For example, the gate 544 may be longer than the gate 548 to enable the use of higher current in the second region 506. The third region 508 may be configured to accommodate relatively low-voltage logic and / or circuitry. Accordingly, the gate 548 may be thinner than the gate 544, according to various embodiments.

[0054] It should be understood that Fig. 5A- Fig. 5l illustrates a simplified version of the device 500 for ease of explanation, with only a pair of memory cells 550a and 550b and a single logic gate 544 and 548 in each of the second region 506 and the third region 508. However, one skilled in the art would understand that the device 500 may include a large number of memory cells, logic cells, and other components in each of the first region 504, second region 506, and third region 508.

[0055] Fig. 6A- Fig. 6D illustrate an alternative to the method of forming the Fig. 5A- Fig. 5l illustrates select gates 534a and 543b on the sidewalls of memory gates 522a and 522b. As in Fig. 6A, the device 600 may include a substrate 602 and memory gates 610a and 610b. A charge-trapping dielectric 603a and 603b is disposed between each of the memory gates 610a and 610b. In this case, the charge-trapping dielectrics 603a and 603b each include an upper dielectric 604a and 604b, a nitride layer 606a and 606b, and a lower dielectric 608a and 608b. According to some embodiments, the lower dielectric 608a and 608b may be in addition to an additional gate dielectric (not shown). According to various embodiments, the upper dielectrics 604a and 604b and the lower dielectrics 608a and 608b may include oxides of a suitable material, such as silicon oxide. Additionally, the charge-trapping dielectric may include additional layers. For example, it may be desirable to include multiple nitride layers 606a and 606b to act as charge-trapping layers.Dielectric layers 604a, 604b, 608a, and 608b may include dielectrics of the substrate or another material and may be formed according to a number of conventional means. Nitride layers 606a and 606b may include silicon nitride, silicon-rich nitride, or any material suitable for acting as a charge-trapping layer.

[0056] Fig. 6A also illustrates dielectrics 620a and 620b (collectively referred to herein as dielectric 620) disposed on the sidewall memory gate structures 610a and 610b. The dielectric may include a single-layer dielectric or a multi-layer dielectric, such as ONO, described above. A layer of gate conductor 612 is disposed over the dielectric 620 and the memory gate structures 610a and 610b. Additionally, a mask 614 has been formed over a portion of the second gate conductor 612 disposed on the sidewalls of the memory gates 610a and 610b.

[0057] As in Fig. As shown in Figure 6B, a portion of the gate conductor layer 612 may be removed from the unmasked area of ​​the device 600. However, a portion of the gate conductor in the unmasked portion was intentionally left unremoved at the outer sidewalls of the memory gates 610a and 610b. The retained portion of the gate conductor 612 at the outer sidewalls of the memory gates 610a and 610b will form the select gates 616a and 616b.

[0058] As in Fig. 6C, the mask 614 is removed, leaving the gate conductor 612 exposed. Additionally, new masks 618a and 618b have been formed over the select gates 616a and 616b and a portion of the memory gates 610a and 610b. The remaining gate conductor 612 can then be removed from the inner sidewall portion of the memory gates 610a and 610b, as shown in Fig. 6D shown.

[0059] Fig. Figure 6D illustrates two split-gate memory cells 622a and 622b formed according to the Fig. 6A- Fig. 6D, with the cover layer 518 on 610a and 610b removed. In addition, as shown in Fig. 6D, the dielectric 620 is removed from the sidewalls between the memory gates 610a and 610b. As shown in Fig. As shown in Figure 6D, each of the split-gate memory cells includes a memory gate 610a and 610b disposed over a charge-trapping dielectric 603a and 603b. The charge-trapping dielectric 603a and 603b itself consists of multiple dielectric layers. For example, the charge-trapping dielectric may include a top dielectric layer 604a and 604b, a nitride layer 606a and 606b, and a bottom dielectric layer 608a and 608b, as shown.

[0060] A select gate 616a and 616b was formed on a sidewall of each of the memory gates 610a and 610b. A dielectric 620a and 620b electrically isolates the select gates 616a and 616b from the memory gates 610a and 610b. According to various embodiments, the dielectric 620a and 620b may include one or more dielectric layers, but was formed independently of the charge-trapping dielectric 603a and 603b.

[0061] For simplicity, Fig. 5A- Fig. 5l and Fig. 6A- Fig. 6D does not explicitly depict the source and drain regions in devices 500 and 600. However, it should be understood that corresponding source and drain regions (e.g., regions 104 and 106) in devices 500 and 600 may be formed during the manufacturing process by an appropriate method, such as, for example, ion implantation.

[0062] Fig. 7 is a flowchart illustrating a method 700 for forming a semiconductor device according to various embodiments. In discussing Fig. 7 is on Fig. 5A- Fig. 5l, however, it should be understood that the method 700 is not limited to the specific embodiment shown in Fig. 5A- Fig. 5l, but is more generally applicable.

[0063] As in Fig. 7, the method 700 may begin by masking a peripheral region of the device 500 in step 702. The peripheral region may include any portion of the device 500 other than the memory region or first region 504. For example, in device 500, the peripheral region may include the second region 506 and the third region 508.

[0064] According to various embodiments, step 702 may occur after the gate dielectrics 512a, 512b, and 512c have been formed in each of the first region 504, the second region 506, and the third region 508. Additionally, prior to performing step 702, a charge-trapping dielectric may be formed in the first region 504. As described above, the charge-trapping dielectric may include one or more layers of dielectric, such as ONO. For example, the charge-trapping dielectric 514 may include a first dielectric layer 514a, a nitride layer 514b, and a second dielectric layer 514c. In addition to the charge-trapping layer, a first gate conductor layer 516 may be formed in each of the first region 504, the second region 506, and the third region 508 prior to performing step 702.

[0065] In step 704, a memory gate 522 may be formed from a first gate conductor 516. This may be accomplished by masking a portion of the gate conductor 516 in the first region 504 and etching the unmasked gate conductor 516 to define a memory gate 522. Additionally, it should be noted that the portion of the charge-trapping layer that does not underlie the memory gate 522 may also be removed from the first region 504, for example, by etching, during the process of forming the memory gate 522.

[0066] In step 706, a dielectric 524 is disposed on a sidewall of the memory gate 522. The dielectric 524 may include one or more dielectric layers. For example, the dielectric 524 may comprise a nitride layer and one or two dielectric layers. The dielectric may be disposed on the sidewall of the memory gate 522, for example, by forming a dielectric layer over the memory gate, then dry etching to remove all of the dielectric 524 that is not on the sidewall of the memory gate 522. Additionally, at this time, a select gate dielectric 512a may be formed in the first region 504 according to various embodiments.

[0067] In step 708, a second gate conductor layer 526 is disposed over the dielectric 524. According to some embodiments, the second gate conductor layer 526 may be substantially conformal to the other structures formed in the first region, but this may not be the case in all embodiments.

[0068] In step 710, a select gate 534 is formed from the second gate conductor 526. According to some embodiments, the select gate 534 may be formed by removing gate conductors from the first region 504 while leaving a portion of the second gate conductor layer 526 disposed on the sidewalls of the memory gate 522. An excess portion 530 of the gate conductor 526 may be removed from one of the sidewalls of the memory gate by masking a select gate portion 534 and etching the remainder. In step 712, the first region, now containing a predominantly completed memory cell, may be masked to allow the formation of a logic gate in the second region 506 in step 714.

[0069] Fig. 8 is a flowchart illustrating a method 800 for forming a select gate according to various embodiments. In discussing Fig. 8 is on Fig. 6A- Fig. 6D, however, it should be understood that the method 800 is not limited to the specific embodiment shown in Fig. 6A- Fig. 6D, but is more generally applicable.

[0070] According to method 800, a source side of the memory gate 610 is masked in step 802. However, prior to performing step 802, a device 600 may be formed. Device 600 may include a substrate 602 and memory gates 610a and 610b (referred to generally herein as "memory gate 610"). A charge-trapping dielectric 603 is disposed between each of the memory gate 610 and the substrate. The charge-trapping dielectrics 603 may include a top dielectric 604, a nitride layer 606, and a bottom dielectric 608. According to some embodiments, the bottom dielectric 608 may be in addition to an additional gate dielectric. Additionally, the charge-trapping dielectric may include additional layers. For example, it may be desirable to include multiple nitride layers 606 to act as charge-trapping layers.Dielectric layers 604 and 608 may include oxides of the substrate or another material and may be formed according to a number of conventional means. Nitride layer 606 may include silicon nitride, silicon-rich nitride, or any material suitable for acting as a charge-trapping layer.

[0071] A dielectric 620 may also have been disposed over the memory gate structure 610 prior to step 802. The dielectric may include a single-layer dielectric or a multi-layer dielectric, such as ONO, described above. A layer of gate conductor 612 is disposed over the dielectric 620. Additionally, a gate conductor layer 612 of the memory gate structure 610 may be disposed before step 802 is performed.

[0072] In step 804, a drain (unmasked in this case) is removed (e.g., etched) to define a select gate 616 on the sidewall of the memory gate 610. The select gate 616 may be defined by removing a portion of the gate conductor 612 from the unmasked region. However, a portion of the gate conductor 612 is intentionally left on the sidewall of the memory gate 610 to form the select gate 616.

[0073] In step 806, the drain side of the memory gate may be masked to protect the select gate 616. Next, the remaining gate conductor 612 may be removed from the source side of the memory gate in step 808.

[0074] Fig. 9 is a flowchart illustrating a method 900 for forming a charge-trapping dielectric in a first region 504 of a semiconductor device 500 according to various embodiments. The device 500 may include a first region 504, a second region 506, and a third region 508, such as in Fig. 5A- Fig. 5l illustrates.

[0075] In step 902, the charge-trapping dielectric 514 is formed in each of the first region 504, the second region 506, and the third region 508. The charge-trapping dielectric may include one or more dielectric layers according to various embodiments. For example, according to some embodiments, the charge-trapping dielectric may include an upper dielectric layer 514a, a nitride layer 514b, and a lower dielectric layer 514c. Additionally, the step of forming the charge-trapping dielectric may include separately depositing each of the upper dielectric 514a, the nitride layer 514b, and the lower dielectric 514c.

[0076] In step 904, the first region 504 is masked to protect it from the process steps performed in the second region 506 and the third region 508. In step 906, the charge-trapping dielectric 514 is removed from the second region, and in step 908, a gate dielectric 512b may be formed.

[0077] In step 910, the charge-trapping dielectric 514 may be removed from the third region, and in step 912, a gate dielectric 512c may be formed in the third region. After step 912, the device 500 includes a charge-trapping dielectric in the first region and separately formed gate dielectrics 510b and 510c in the second region 506 and the third region 508.

[0078] As mentioned above, according to some embodiments, silicon-rich nitride (SiRN) may be used for the charge-trapping layer 514b. SiRN may be advantageous for use as a charge-trapping layer in a split-gate memory cell because it has been found to have better reliability, faster erase speed, and lower erase current. While SiRN has some properties that make it well-suited for use as the charge-trapping layer 514b, it also has some properties that make it difficult to use. For example, unlike other nitrides, SiRN is slightly conductive. Accordingly, it is important to ensure that the charge-trapping layer 514b of each memory cell (e.g., 550a or 550b) is isolated from the other memory cells to avoid leakage currents. Fig. 10 is a flowchart illustrating a method 1000 for isolating the charge trapping layers in each of the memory cells from each other according to various embodiments. Fig. 11A- Fig. 11E illustrate a semiconductor device 1100 at various points during the method 1000. Accordingly, Fig. 10 in connection with Fig. 11A- Fig. 11E discussed.

[0079] Fig. 11A illustrates a semiconductor device 1100. The device 1100 includes a substrate 1102 and shallow trench isolation (STI) regions 1104a and 1104b (collectively referred to herein as STI regions 1104). STI regions 1104 cause adjacent semiconductor components (not shown) to be electrically isolated from each other. According to method 1000, in step 1002, a nitride layer 1106 is formed over the STI regions 1104 of the semiconductor device 1100 after the bottom dielectric. The result of this step is shown in Fig. 11B. The nitride layer 1106 may include SiRN or any other suitable nitride. As shown in Fig. As shown in Figure 11B, the nitride layer 1106 is conformal to the top surface of the semiconductor device 1100.

[0080] In step 1004, a sacrificial layer 1108 may be formed over the nitride layer 1106. The sacrificial layer 1108 may include any suitable material. For example, according to some different embodiments, the sacrificial layer 1108 may include an oxide, BARC, photoresist, etc. The device 1100 is Fig. 11C illustrates.

[0081] In step 1006, portions of the sacrificial layer 1108, the nitride layer 1106, and the STI regions 1104 may be removed. As in Fig. As shown in Figure 11D, the removed portions of the sacrificial layer 1108, the nitride layer 1106, and the STI regions 1104 cause a discontinuity in the nitride layer 1106. According to various embodiments, the removed portions 1108, 1106, and 1104 may be removed by dry or wet etching or other appropriate means. In step 1008, the remaining portion of the sacrificial layer 1108 may be removed from the device 1100, as shown in Fig. 11E illustrates.

[0082] It is to be understood that the Detailed Description section, and not the Summary and Abstract sections, should be used to interpret the claims. The Summary and Abstract sections may set forth one or more, but not all, exemplary embodiments of the present invention as contemplated by the inventor(s), and thus are not intended to limit the present invention and the appended claims in any way.

[0083] Embodiments of the present invention have been described above with the aid of functional blocks that illustrate the implementation of specified functions and relationships thereof. The boundaries of these functional blocks have been arbitrarily defined here for convenience of description. Alternative boundaries may be defined as long as the specified functions and relationships thereof are adequately implemented.

[0084] The above description of the specific embodiments so fully discloses the general characteristics of the invention that others, by using the knowledge of the prior art, can easily modify and / or adapt these specific embodiments for various applications without departing from the general concept of the present invention. Therefore, such modifications and changes are intended to be included within the meaning and scope of equivalents of the disclosed embodiments based on the teachings and guidance presented herein. It is to be understood that the phraseology or terminology used herein is for the purpose of description and not of limitation, so that the terminology or phraseology of this specification should be interpreted by those skilled in the art in light of the teachings and guidance presented herein.

Claims

[1] A semiconductor device (500) comprising: a first memory gate (522a) disposed in a first region (504) of the semiconductor device, the first memory gate (522a) comprising a first gate conductor layer (516) disposed over a charge trapping dielectric (514); a first select gate (534a) disposed in the first region adjacent a sidewall of the first memory gate (522a); a second select gate (534b) disposed adjacent to the first select gate (534a) in the first region (504) such that the first select gate (534a) is disposed between the first memory gate (522a) and the second select gate (534b); a sidewall dielectric (524) disposed between the sidewall of the first memory gate (522a) and the first select gate (534a); a logic gate (544) disposed in a second region (506) of the semiconductor device (500) and comprising the first gate conductor layer (516); a select gate dielectric (512a) disposed between the first memory gate (522a) and a second memory gate (522b) and below the first select gate (534a) and the second select gate (534b) such that the select gate dielectric (512a) is continuous. [2] The semiconductor device according to claim 1, wherein the first select gate (534a) comprises a second gate conductor layer (526). [3] The semiconductor device according to claim 1 or 2, further comprising a second logic gate (548) disposed in a third region (508) of the semiconductor device (500). [4] The semiconductor device according to claim 3, wherein the second logic gate (548) comprises the first gate conductor layer (516). [5] The device of any preceding claim, wherein the charge trapping dielectric (514) is electrically isolated from one or more other charge trapping dielectrics. [6] The device of any preceding claim, wherein the charge trapping dielectric (514) comprises a nitride layer and a dielectric layer. [7] The device of claim 6, wherein the nitride layer comprises a silicon-rich nitride. [8] The device of any preceding claim, further comprising: a storage dielectric disposed in the first region (504); a first gate dielectric (512b) disposed in the second region (506); and a second gate dielectric (512c) disposed in the third region (508), wherein two of the storage dielectric, the first gate dielectric (512a), and the second gate dielectric (512b) have different thicknesses. [9] The device of any preceding claim, wherein the select gate dielectric (512a) comprises a nitride layer discontinuous from the charge trapping dielectric (514). [10] The device of claim 9, wherein the nitride layer comprises a separate layer from the charge trapping dielectric (514). [11] A semiconductor device according to any preceding claim, wherein the first (534a) and second select gates (534b) include a second gate conductor layer (526). [12] A semiconductor device according to any preceding claim, wherein the second memory gate (522b) is arranged adjacent to the second selection gate (534b). [13] The semiconductor device according to claim 12, wherein the second selection gate (534b) is arranged on a sidewall of the second memory gate (522b). [14] The semiconductor device according to claim 12 or 13, wherein the second memory gate (522b) includes the first gate conductor layer (516). [15] A semiconductor device according to any preceding claim, wherein the select gate dielectric (512a) is arranged so as not to overlap with the charge trapping dielectric (514). [16] A semiconductor device (500) comprising: a first memory cell (550a) including a first memory gate (522a) and a first select gate (534a) arranged on a sidewall of the first memory gate (522a), wherein the first memory gate (522a) is arranged to overlap a first charge trapping dielectric (514), and wherein a sidewall dielectric (524) is disposed between the first memory gate (522a) and the first select gate (534a); a second memory cell (550b) including a second memory gate (522b) and a second select gate (534a), wherein the second select gate (534b) is arranged on a sidewall of the second memory gate (522b) and adjacent to the first select gate (534a), wherein the second memory gate (522b) is arranged to overlap a second charge trapping dielectric (514), and wherein the first (534a) and second select gates (534b) are arranged between the first memory gate (522a) and the second memory gate (522b); a select gate dielectric (512a) disposed between the first memory gate (522a) and the second memory gate (522b) and below the first select gate (534a) and the second select gate (534b) such that the select gate dielectric (512a) is continuous, the select gate dielectric (512a) being separated from the first charge trapping dielectric (514) and the first memory gate (522a) by the sidewall dielectric (524). [17] The semiconductor device according to claim 16, wherein the first memory gate (522a) and the second memory gate (522b) include a first gate conductor layer (516). [18] The semiconductor device according to claim 16 or 17, wherein the first select gate (534a) and the second select gate (534b) include a second gate conductor layer (526). [19] A semiconductor device according to any one of claims 16 to 18, wherein the first and second memory cells are arranged in a memory region. [20] A semiconductor device according to any one of claims 16 to 19, further including a logic region comprising a logic gate. [21] The semiconductor device of claim 20, wherein the logic region (506) includes a logic dielectric. [22] A semiconductor device according to claim 21, wherein the logic dielectric has a different thickness than the select gate dielectric (512a). [23] A semiconductor device according to any one of claims 16 to 22, further comprising a first sidewall dielectric disposed between the first memory gate (522a) and the first select gate (534a), and a second sidewall dielectric disposed between the second memory gate (522b) and the second select gate (534b). [24] A semiconductor device according to any one of claims 16 to 23, wherein the first and second charge trapping dielectrics (514) do not overlap with the select gate dielectric (512a).

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