Tunnel field effect transistors with winding areas

Abstract

Tunnel field effect transistor, TFET (400, 500, 1400, 1500, 1600), comprising: an active homotransition region formed above a substrate, wherein the active homotransition region comprises: a doped source region, an undoped channel region, a wrapped drain underlap region, and a doped drain region; and a gate electrode (602, 604, 606, 702, 704, 706, 802, 804, 806, 902, 904, 906, 1002, 1004, 1006, 1102, 1104, 1106, 1202, 1204, 1206, 1304, 1404, 1520a, 1520b, 1620a, 1620b) and a gate dielectric layer formed on the undoped channel area between the source area and the wound drain overlap area.

Description

SPECIALIZATION

[0001] Embodiments of the invention are in the field of semiconductor devices and in particular tunnel field effect transistors (TFETs) with undoped drain overlap winding regions. BACKGROUND

[0002] In recent decades, the scaling of features in integrated circuits has been a driving force behind the ever-expanding semiconductor industry. Scaling down to ever smaller features enables increased densities of functional units on the limited footprint of semiconductor chips. For example, reducing transistor size allows for a greater number of memory devices to be placed on a single chip, leading to the production of products with increased capacity. However, the pursuit of ever-greater capacity is not without its challenges. The need to optimize the performance of each device is becoming increasingly significant.

[0003] In the fabrication of integrated circuit devices, the subthreshold slope of a metal-oxide-semiconductor field-effect transistor (MOSFET) has a theoretical lower limit of kT / q (60 mV / dec at room temperature), where k is the Boltzmann constant, T is the absolute temperature, and q is the charge strength of an electron. For low active power applications, it is very advantageous to operate at lower supply voltages due to the strong dependence of the active power on the supply voltage (e.g., a dependence of approximately capacitance (C) * voltage (V)). 2However, if a MOSFET is operated at low supply voltages, the on-current would be significantly lower due to the limited (kT / q) rate of rise from off-current to on-current, as it could operate close to its threshold voltage. It has been shown that a different type of transistor—the tunnel FET (TFET)—achieves a sharper turn-on behavior (steeper subthreshold slope) than MOSFETs. This allows for higher on-currents than MOSFETs at low supply voltages, as in Fig. 1 shown. Fig. Figure 1 illustrates drain current (Id) versus gate voltage (Vg) for a low-power MOSFET and an InAs TFET for a gate length of 20 nanometers (nm). A heterojunction TFET, which uses a combination of two semiconductor materials to enable a higher tunneling current, allows for better TFET characteristics, as shown in Fig. 2 illustrated. Fig. Figure 2 also illustrates a low-power MOSFET and a homojunction InAs TFET for a gate length of 15 nm, a gate oxide thickness of 0.8 nm, a drain-source voltage of 0.3 volts and an off-current of 1 nA / µm.

[0004] However, TFET devices require a long drain underlap - an undoped area between the gate edge and the doped drain area - to maintain their steep subthreshold slope and low off-current leakage at short gate lengths. Fig. Figure 3 shows an InAs TFET curve 302 with drain overlap and an InAs TFET curve 306, which has symmetrical source / drain spacers without drain overlap. Without drain overlap, the leakage current is high and the subthreshold slope is not steep for curve 306. When drain overlap is introduced, the leakage decreases and a subthreshold slope steeper than 60 mV / dec can be achieved. Curve 304 shows the device characteristics for a low-power MOSFET.

[0005] Fig. Figure 4 shows sectional drawings for a TFET device 400 with drain overlap and a TFET device 450 without drain overlap. Although the TFET device 400 with drain overlap achieves better device characteristics, including lower leakage and a steeper subthreshold slope, it requires a longer device, which consumes additional area for transistor layout. Furthermore, a longer drain overlap area 410 likely necessitates different spacer machining, increasing machining complexity and cost.

[0006] The publication US 2008 / 0067607A1 discloses tunnel-effect transistors based on elongated monocrystalline nanostructures with a heterostructure. Tunnel field-effect transistors (TFETs) are considered successors to metal-oxide-semiconductor field-effect transistors (MOSFETs). However, silicon-based TFETs typically suffer from low inrush currents, which is attributed to the high resistance of the tunnel barrier. To achieve higher inrush currents, an elongated monocrystalline TFET based on a nanostructure with a heterostructure made of another semiconductor material (e.g., germanium (Ge)) is used. An elongated monocrystalline nanostructure made of another semiconductor material is introduced, serving as the source (or alternatively, the drain) region of the TFET. The heterosection is introduced in such a way that the lattice mismatch between silicon and germanium does not result in a highly defective interface.Compared to conventional MOSFET configurations, both dynamic and static power reduction can be achieved. These elongated monocrystalline Si / Ge TFETs with nanostructure therefore enable multiple logic layers, leading to ultra-high transistor densities on the chip.

[0007] German patent application DE 37 88 253 T2 discloses a controllable tunnel diode. This patent application specifically relates to a three-terminal tunnel FET in which a tunnel current is induced by applying an external gate field to a double heterojunction semiconductor layer. SUMMARY OF THE INVENTION

[0008] The present invention is defined by the independent claims. Advantageous embodiments are described in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates the turn-on behavior for a TFET device compared to a low-power MOSFET device using a conventional approach. Fig. Figure 2 illustrates the turn-on behavior for homo- and hetero-transition TFET devices compared to a low-power MOSFET device using a conventional approach. Fig. Figure 3 illustrates the turn-on behavior for TFET devices with drain overlap, without drain overlap, and for a low-power MOSFET device using a conventional approach. Fig. Figure 4 illustrates cross-sections of TFET devices with and without drain overlap using a conventional approach. Fig. Figure 5 illustrates a tunnel path of an electron at a source side of a heterojunction TFET device with drain overlap. Fig. Figure 6a illustrates a top-down view 600 of a multigate device architecture according to an embodiment of the present invention. Fig. Figure 6b illustrates a cross-sectional view 650 through a cross-section 610 of the active area 620 of the multigate device architecture of Fig. 6a according to an embodiment of the present invention. Fig. Figure 7a illustrates a top-down view 700 of a multigate device architecture during a lithography operation according to an embodiment of the present invention. Fig. Figure 7b illustrates a cross-sectional view 750 through a cross-section 710 of the active area 720 of the multigate device architecture of Fig. 7a according to an embodiment of the present invention. Fig. Figure 8a illustrates a top-down view 800 of a multigate device architecture according to an embodiment of the present invention. Fig. Figure 8b illustrates a cross-sectional view 850 through a cross-section 810 of an active area of ​​the multigate device architecture of Fig. 8a according to an embodiment of the present invention. Fig. Figure 9a illustrates a top-down view 900 of a multigate device architecture according to an embodiment of the present invention. Fig. Figure 9b illustrates a cross-sectional view 950 through a cross-section 910 of the active area 920 of the multigate device architecture of Fig. 9a according to an embodiment of the present invention. Fig. Figure 10a illustrates a top-down view 1000 of a multigate device architecture according to an embodiment of the present invention. Fig. Figure 10b illustrates a cross-sectional view 1050 through a cross-section 1010 of an active area 1020 of the multigate device architecture of Fig. 10a according to an embodiment of the present invention. Fig. Figure 11a illustrates a top-down view 1100 of a multigate device architecture with wrapped and symmetrical spacers according to an embodiment of the present invention. Fig. Figure 11b illustrates a cross-sectional view 1150 through a cross-section 1110 of the active area 1120 of the multigate device architecture of Fig. 11a according to an embodiment of the present invention. Fig. Figure 12a illustrates a top-down view 1200 of a multigate device architecture with wrapped drain overlap comprising symmetrical spacers, according to an embodiment of the present invention. Fig. Figure 12b illustrates a cross-sectional view 1250 through a cross-section 1210 of the active area 1220 of the multigate device architecture of Fig. 12a according to an embodiment of the present invention. Fig. Figure 13 illustrates a cross-sectional view 1300 through a cross-section 1212 of the active area 1220 of the multigate device architecture of Fig. 12b according to an embodiment of the present invention. Fig. Figure 14 illustrates a cross-sectional view 1400 through a cross-section of an active region of a conventional long TFET. Fig. Figure 15 illustrates a device cross-section for the wound TFET according to an embodiment of the present invention. Fig. Figure 16 illustrates a device cross-section for the conventional long, horizontal TFET. Fig. 17 and Fig. Figure 18 illustrates potential profiles for the conventional long horizontal TFET and the wound TFET according to an embodiment of the present invention. Fig. Figure 19 illustrates a computer device according to an implementation of the invention. DESCRIPTION OF THE EXECUTION FORMS

[0009] Tunnel field-effect transistors (TFETs) with undoped drain overlap winding regions are described. Numerous specific details, such as specific integration and materials used, are presented in the following description to provide a thorough understanding of embodiments of the present invention. It should also be noted that the various embodiments shown in the figures are for illustrative purposes only and are not necessarily to scale.

[0010] In one embodiment, TFETs are used to achieve a steeper subthreshold slope (SS) and lower leakage compared to a corresponding metal-oxide-semiconductor field-effect transistor (MOSFET) with a thermal peak load of about 60 mV / decade. In general, embodiments described herein may be suitable for high-power or scaled transistors for logic devices with low-power applications.

[0011] To provide background context, a conventional TFET design requires an undoped region between the gate edge and the n+-doped drain region, the drain overlap region, as shown in Fig. Figure 4 illustrates this. This prevents deterioration of a steep subthreshold slope of a TFET device and keeps the leakage current low. The leakage and subthreshold deterioration are due to ambipolar leakage and a short-channel effect. Ambipolar leakage is caused by band-band tunneling between the channel and drain regions. A short-channel effect involves tunneling from source to either channel or drain due to a drain effect on the channel potential and a short source-drain distance.

[0012] Fig. Figure 5 illustrates an electron tunneling path at the source side of a heterojunction TFET device with a drain underlap region. The TFET device 500 comprises a gate 520, a source region 522 (e.g., p+-doped), a channel 524 (e.g., undoped channel), a drain underlap region 526 (e.g., undoped), and a drain region 528 (e.g., n+-doped). An energy band structure 544 for the TFET device is shown below the TFET device. The energy band structure 544 includes a conduction band 540 and a valence band 542. Electrons within the conduction band are mobile charge carriers in semiconductor devices. The energy band structure shows electron energy in units of eV on a vertical axis and a position within the TFET device in units of nanometers on a horizontal axis.

[0013] Leakage is dominated by the tunneling distance from the source to a point in the drain of the TFET device. A longer tunneling distance reduces leakage. The shortest path to the other side of the band gap, illustrated by arrow 550, along with the barrier height, semiclassically explains the magnitude of the tunneling current. Therefore, it is desirable to keep this tunneling distance longer during an off-condition of the TFET device and shorter during an on-condition.

[0014] In general, it illustrates Fig. Figure 6a shows a top-down view 600 of a multi-gate device architecture according to an embodiment of the present invention. In one embodiment, the device architecture (e.g., tri-gate, FinFET) comprises gate electrodes 602, 604, 606, an active region or rib 620, and an isolation region 630. In general, the illustration Fig. 6b a cross-sectional view 650 through a cross-section 610 of the active area 620 of the multigate device architecture of Fig. 6a according to an embodiment of the present invention. The device architecture comprises the gates 602, 604, 606, the dielectric layers 660-662, gate spacers 640-645, the active area 620 and a substrate 690. This design architecture includes a design of a wrapped drain underlap, as shown in the Fig. Figures 6A-13 and 15 illustrate TFET devices without thick gate spacers or a longer device layout, such as a horizontal drain underlap design, which is described in Fig. 14 illustrates how to obtain.

[0015] In general, it illustrates Fig. Figure 7a shows a top-down view 700 of a multi-gate device architecture during a lithography operation according to an embodiment of the present invention. In one embodiment, the device architecture (e.g., tri-gate, FinFET) comprises a blocking layer 712 with an opening that exposes the gate electrodes 702, 704, and an active region 720. The opening has a length 708, which corresponds approximately to a polysilicon division spacing, and a width 709. In general, the illustration Fig. 7b a cross-sectional view 750 through a cross-section 710 of the active area 720 of the multigate device architecture of Fig. 7a according to an embodiment of the present invention. The device architecture comprises the gate electrodes 702, 704, 706 and corresponding gate spacers 740-745 and gate dielectric layers 760-762. The device architecture also includes the blocking layer 712, the active region 720, and the substrate 790. The blocking layer 712 provides an opening to the active region in a source region. The exposed active region is subsequently either implanted with a p+ doping or etched and a p + - The in-situ doped source area is allowed to grow, as in the Fig. 8a and Fig. 8b illustrates.

[0016] In general, it illustrates Fig. Figure 8a shows a top-down view 800 of a multi-gate device architecture according to an embodiment of the present invention. In one embodiment, the device architecture (e.g., tri-gate, finFET) comprises a blocking layer 812 with an opening that exposes the gate electrodes 802 and 804 and a source region 808 (p+ source region). In general, the illustration Fig. 8b a cross-sectional view 850 through a cross-section 810 of an active area of ​​the multigate device architecture of Fig. 8a according to an embodiment of the present invention. The device architecture comprises the gate electrodes 802, 804, 806 and corresponding gate spacers 840-845 and gate oxide layers 860-862. The device architecture also includes the blocking layer 812, the active region 820, and the substrate 890. The p+ source region is formed in the active region 820 by implantation or partially in the active region by etching and in situ doped source growth. After a photoresist and blocking layer 812 (or hard mask) has been removed, a new lithography operation is performed to create the drain regions, as shown in the Fig. 9a and Fig. 9b illustrates how to open it.

[0017] In general, it illustrates Fig. Figure 9a shows a top-down view 900 of a multi-gate device architecture according to an embodiment of the present invention. In one embodiment, the device architecture (e.g., tri-gate, finFET) comprises a blocking layer 912 with an opening that exposes the gate electrodes 902 and 904 and an active region 920 to form a drain region. In general, the illustration Fig. 9b a cross-sectional view 950 through a cross-section 910 of the active area 920 of the multigate device architecture of Fig. 9a according to an embodiment of the present invention. The device architecture comprises the gate electrodes 902, 904, 906 and corresponding gate spacers 940-945 and gate dielectric layers 960-962. The device architecture also includes the blocking layer 912, the active region 920, and the substrate 990. A drain region is formed on the undoped active region 920 by growing a thin layer of additional undoped material and subsequently growing in-situ n-doped material or by implanting the region with a low-dose, low-energy n-type doping, as described in the Fig. 10a and Fig. 10b illustrates.

[0018] In general, it illustrates Fig. Figure 10a shows a top-down view 1000 of a multi-gate device architecture according to an embodiment of the present invention. In one embodiment, the device architecture (e.g., tri-gate, finFET) comprises a blocking layer 1012 with an opening that exposes the gates 1004 and 1008 and an active region 1020 to form a drain region with n+ doping. In general, the illustration Fig. 10b a cross-sectional view 1050 through a cross-section 1010 of an active area of ​​the multigate device architecture of Fig. 10a according to an embodiment of the present invention. The device architecture comprises the gate electrodes 1002, 1004, 1006 and corresponding gate spacers 1040-1045 and gate oxide layers 1060-1062. The device architecture also includes the blocking layer 1012, the active region 1020, and the substrate 1090. A drain region 1072 is formed on the undoped active region 1020 by growing a thin layer 1071 of additional undoped material and subsequently growing in-situ n-doped material 1070 or by implanting the region with a low-dose, low-energy n-type doping. After the photoresist and blocking layer 1012 (or hard mask) has been removed, a TFET with a wrapped drain underlap having symmetrical spacers, as shown in the Fig. 11a and Fig. 11b illustrates, educates.

[0019] In general, it illustrates Fig. Figure 11a shows a top-down view 1100 of a multi-gate device architecture with wrapped drain overlap and symmetrical spacers according to an embodiment of the present invention. In one embodiment, the device architecture (e.g., trigate, FinFET) comprises the gates 1102, 1104, and 1106 and an active region 1120 (e.g., rib or body) to form a source region 1108 (e.g., p+ source region) and a drain region 1160 (e.g., n+ drain region). In general, the following is illustrated: Fig. 11b a cross-sectional view 1150 through a cross-section 1110 of the active area 1120 of the multigate device architecture of Fig. 11a according to an embodiment of the present invention. The device architecture comprises the gate electrodes 1102, 1104, 1106 and corresponding gate spacers 1140-1145 and gate dielectric layers 1160-1162 (e.g., gate oxide layers). The device architecture also comprises the active region 1120 and the substrate 1190. A drain region is formed on the undoped active region 1120 by growing a thin layer 1171 of additional undoped material and subsequently growing in-situ n-doped material 1170 or by implanting the region, including the layer 1171, with a low-dose, low-energy n-type doping. A source region 1108 (e.g., p+ source region) is also formed on the undoped active region 1120. A similar method approach described in the Fig. As illustrated in 6a-11b, this can be applied to a heterojunction TFET device design to provide enhanced TFET performance.

[0020] In general, it illustrates Fig. Figure 12a shows a top-down view 1200 of a multi-gate device architecture with wound drain overlap, comprising symmetrical spacers, according to an embodiment of the present invention. In one embodiment, the device architecture (e.g., tri-gate, finFET) comprises gate electrodes 1202, 1204, and 1206 and an active region 1220 to form a source region (e.g., p+ source region) and a drain region (e.g., n+ drain region) for a small TFET transistor 1270. In general, the following is illustrated: Fig. 12b a cross-sectional view 1250 through a cross-section 1210 of the active area 1220 of the multigate device architecture of Fig. 12a according to an embodiment of the present invention. The device architecture comprises the gate electrodes 1202, 1204, 1206 and corresponding symmetrical gate spacers 1240-1245 and gate dielectric layers 1260-1262. The device architecture also includes the active region 1220 (e.g., undoped InAs), the substrate 1290, a source region 1208 with p+ doping (e.g., GaSb), and a drain region 1273. The drain region 1273 is formed on the undoped active region 1220 by growing a thin layer 1271 of additional undoped material (e.g., InAs) and subsequently growing in-situ n-doped material 1272 (e.g., n-type InAs), or by implanting the region, including the layer 1271, with low-dose, low-energy n-type doping. Fig. 12a and Fig. Figure 12b illustrates various views of an n-type TFET using GaSb in the source region and InAs in the active region, including channel regions below the gate regions and also the drain region. In one embodiment, a p-type TFET can be constructed with Si, Ge, Sn, or any alloy of these materials in the source region and Si, Ge, Sn, or any alloy of these materials in the active region, including the channel regions below the gate regions and also drain regions. In another embodiment, a TFET can be constructed with In, Ga, Al, As, Sb, P, N, or any alloy of these materials in the source region and In, Ga, Al, As, Sb, P, N, or any alloy of these materials in the active region, including the channel regions below the gate regions and also drain regions. Including the contacts (e.g.,(with a source contact 1280 and a drain contact 1281) the TFET device can be constructed as small as a counterpart MOSFET device.

[0021] In general, it illustrates Fig. 13 a cross-sectional view 1300 through a cross-section 1212 of the active area 1220 of the multigate device architecture of Fig. 12b according to an embodiment of the present invention. The device architecture comprises the gate electrode 1304 and corresponding gate spacers 1340-1343 and gate oxide layers 1360-1361. The device architecture also includes the active region 1320 (e.g., undoped InAs), a source region 1308 with p+ doping (e.g., GaSb), and a drain region 1325. The drain region 1325 is formed on the undoped active region 1320 by growing a thin layer 1321, 1324 of additional undoped material (e.g., InAs) and subsequently growing in-situ n-doped material 1322, 1323 (e.g., n-type InAs), or by implanting the region, including the layer 1321, 1324, with low-dose, low-energy n-type doping. Arrows 1380 and 1381 indicate paths of electrons from the source region to the drain region.

[0022] In general, it illustrates Fig. Figure 14 shows a cross-sectional view 1400 through a cross-section of an active region of a conventional multigate device architecture. The device architecture comprises the gate electrode 1404 and corresponding asymmetric gate spacers 1420, 1421, 1440, 1441 and gate dielectric layers. The device architecture also includes the active region 1430 (e.g., undoped InAs), a source region 1408 with p+ doping (e.g., GaSb), a drain overlap region 1431, and a drain region 1410 (e.g., n-type InAs). Fig. Figure 14 illustrates the conventional long, horizontal drain-lap TFET, while Fig. Figure 13 illustrates a TFET with a wound drain overlap. Arrow 1422 shows the path of an electron from the source region to the drain region.

[0023] Although the wound TFET from Fig. 13 compared to the TFET of Fig. Although the wrapped TFET has a shorter device length (14), it still exhibits good electrostatic properties to keep the leakage current low.

[0024] The Fig. 15 and Fig. Figure 16 illustrates device cross-sections for the wound TFET 1500 and the conventional long, horizontal TFET, respectively. In general, they illustrate Fig. 15 a device cross-section for the wound TFET according to an embodiment of the present invention. The wound TFET 1500 comprises gate electrodes 1520a, 1520b, a gate spacer 1560 and gate dielectric layers 1522 and 1523. An additional symmetrical gate spacer and an additional drain section are shown in Fig. Figure 15 is not shown, wherein the additional symmetrical gate spacer is symmetrical with respect to the spacer 1560, and the additional drain portion is symmetrical with respect to a drain electrode 1540 and a drain region 1542. The TFET comprises an active region 1525 or body (e.g., undoped InAs), a source electrode 1510, a p+-doped source region 1511 (e.g., GaSb), the drain electrode 1540 with the drain region 1542, and a drain overlap region 1530. In one embodiment, the active region 1525 or body has a width of 5 nm, as illustrated by the double arrows 1531 and 1532. The source has a length of 30 nm (1512), an active region channel has a length of 20 nm (1524), a drain overlap has a first length of 5 nm (1532) and a second length of 10 nm (1533), and a drain region has a length of 15 nm (1541). The gate dielectric layers can have a thickness of approximately 1 nm (1526).A spacer 1560 has a thickness 1561 of approximately 3 nm. The first length 1532 and second length 1533 of the drain underlap 1530 run approximately perpendicular to a device length in order to contribute only a width 1531 of the drain underlap 1530 in one direction of the device length, but provide a length 1532 and 1533 for improved leakage characteristics.

[0025] In general, it illustrates Fig. 16 a device cross-section for the conventional long horizontal TFET. The conventional long horizontal TFET 1600 corresponds to the TFET 1400 of Fig. 14. The TFET 1600 comprises gate electrodes 1620a and 1620b, gate spacers 1626 and 1627, and gate oxide layers 1660a and 1660b. The TFET device also includes an active region 1622 or body (e.g., undoped InAs), a source electrode 1610, a p+-doped source region 1612 (e.g., GaSb), a drain electrode 1640 with an n+-doped drain region 1642, and a drain overlap region 1625. The active region 1622 or body has a width of 5 nm, as illustrated by the double arrows in 1641. The drain has a length of 1665 by 20 nm, a channel has a length of 1623 by 20 nm, a drain overlap has a length of 1624 by 10 nm and a source area has a length of 1611 by 30 nm.

[0026] The Fig. 17 and Fig. Figure 18 illustrated potential profiles for the conventional long horizontal TFET and the wound TFET according to an embodiment of the present invention. Fig. Figure 17 illustrates potential profiles for the conventional long horizontal TFET and the wound TFET for a state in which, according to one embodiment of the present invention, the gates of the TFET device are ON. Diagram 1700 shows energy (eV) versus position within the respective TFET device. The conduction band (upper band) and valence band (lower band) of the conventional long horizontal TFET 1730 are nearly identical to the conduction band (upper band) and valence band (lower band) of the wound TFET 1740, wherein the gate bias is sufficient to switch the device ON.

[0027] Fig. Figure 18 illustrates potential profiles for the conventional long horizontal TFET and the wound TFET for a state in which, according to one embodiment of the present invention, the TFET devices are OFF. Diagram 1800 shows energy (eV) versus position within the respective TFET device. The conduction band (upper band) and valence band (lower band) of the conventional long horizontal TFET 1830 are nearly identical to the conduction band (upper band) and valence band (lower band) of the wound TFET 1840 for a position (nm) from zero to 40. The conduction band and valence band of these devices diverge from a position of about 40 to 80, with the devices biased for the OFF state. A tunnel path 1850 of the wound TFET of an electron from the valence band to the conduction band is significantly longer than a tunnel path 1852 of the conventional long horizontal TFET.The tunnel path is related to the leakage current, which is why the wound TFET produces lower leakage currents.

[0028] Therefore, the wound TFET has a shorter fixture length for a smaller area and lower costs, and does not require a complex spacer method compared to the conventional long, horizontal TFET. The wound TFET also exhibits a better controlled potential profile, resulting in lower off-state tunneling currents and therefore a TFET with less leakage compared to the conventional long, horizontal TFET.

[0029] In the embodiments described above, an underlying substrate used for the fabrication of TFET devices, whether formed on virtual substrate layers or on volume substrates, can consist of a semiconductor material capable of accommodating a fabrication process. In one embodiment, the substrate is a volume substrate, such as a p-type silicon substrate commonly used in the semiconductor industry. In another embodiment, the substrate consists of a layer of crystalline silicon, silicon / germanium, or germanium doped with a charge carrier, such as, but not limited to, phosphorus, arsenic, boron, or a combination thereof. In yet another embodiment, the substrate consists of an epitaxial layer grown above a pronounced crystalline substrate, e.g.,a silicon epitaxy layer that is grown above a boron-doped bulk silicon monocrystalline substrate.

[0030] The substrate may instead comprise an insulating layer formed between a bulk crystal substrate and an epitaxial layer, for example, to form a silicon-on-insulator substrate. In one embodiment, the insulating layer consists of a material such as, but not limited to, silicon dioxide, silicon nitride, silicon oxynitride, or a high-k dielectric layer. Alternatively, the substrate may consist of a material from groups III-V. In one embodiment, the substrate consists of a group III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof.In another embodiment, the substrate consists of a III-V material and charge carrier dotante impurity atoms such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.

[0031] In the above embodiments, TFET devices comprise source-drain regions that may be doped with charge carrier impurity atoms. In one embodiment, the Group IV material source and / or drain regions comprise N-type dopants such as, but not limited to, phosphorus or arsenic. In other embodiments, the Group IV material source and / or drain regions comprise P-type dopants such as, but not limited to, boron.

[0032] Although not always shown, it is understood that the TFETs in the above embodiments comprise a gate stack with a gate dielectric layer and a gate electrode layer. In one embodiment, the gate electrode of the gate electrode stack is a metal gate, and the gate dielectric layer is a high-k material. For example, in one embodiment, the gate dielectric layer is a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc cniobate, or a combination thereof. Furthermore, part of a gate dielectric layer may comprise a layer of intrinsic oxide formed from the top few layers of the corresponding channel region.In one embodiment, the gate dielectric layer consists of an upper high-k portion and a lower portion composed of an oxide of a semiconductor material. In another embodiment, the gate dielectric layer consists of an upper portion of hafnium oxide and a lower portion of silicon dioxide or silicon oxynitride.

[0033] In one embodiment, the gate electrode consists of a metal layer such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In a specific embodiment, the gate electrode consists of a non-output work setting filler material formed above a metal output work setting layer. In another embodiment, the gate electrode consists of a T-type or N-type material. The gate electrode stack may also include dielectric spacers.

[0034] The TFET semiconductor devices described above cover both planar and non-planar devices, including gate-to-gate devices. Therefore, the semiconductor devices can more generally be a semiconductor device containing a gate, a channel region, and a source / drain region pair. In one embodiment, the semiconductor device is, but is not limited to, a MOSFET. In another embodiment, the semiconductor device is a planar or three-dimensional MOSFET and is either a single device or a device within a plurality of nested devices. As is typical for an integrated circuit, both N-channel and P-channel transistors can be fabricated on a single substrate to form a CMOS integrated circuit.Furthermore, additional interconnection wiring can be provided to integrate such devices into an integrated circuit.

[0035] In general, one or more embodiments described herein are directed towards tunnel field-effect transistors (TFETs) with undoped drain-lap winding regions. Active layers of group IV or III-V for such devices can be formed by techniques such as, but not limited to, chemical vapor deposition (CVD) or molecular beam epitaxy (MBE) or similar methods.

[0036] Fig.Figure 19 illustrates a computer device 1900 according to one implementation of the invention. The computer device 1900 includes a disk 1902. The disk 1902 can comprise a number of components, including, but not limited to, a processor 1904 and at least one communication chip 1906. The processor 1904 is physically and electrically coupled to the disk 1902. In some implementations, the at least one communication chip 1906 is also physically and electrically coupled to the disk 1902. In other implementations, the communication chip 1906 is part of the processor 1904.

[0037] Depending on its applications, the computer device 1900 may include additional components, which may or may not be physically and electrically coupled to the disk 1902. These additional components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a satellite navigation system (GPS) device, a compass, an accelerometer, a gyroscope, a loudspeaker, a camera, and a mass storage device (such as a hard disk drive, compact disc (CD), digital versatile disc (DVD), and so on).

[0038] The 1906 communication chip enables wireless transmission for data transfer to and from the 1900 computer device. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data through a non-solid medium by using modulated electromagnetic radiation. The term does not imply that the connected devices do not contain any wires, although they may not in some embodiments. The 1906 communication chip can implement any number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), and IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G, and higher. The 1900 computing device can incorporate a variety of 1906 communication chips. For example, a first 1906 communication chip can be used for shorter-range wireless transmissions such as Wi-Fi and Bluetooth, and a second 1906 communication chip can be used for longer-range wireless transmissions such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0039] The processor 1904 of the computer device 1900 comprises an integrated circuit bare chip 1910 located within the package of the processor 1904. In some embodiments of the invention, the integrated circuit bare chip of the processor comprises one or more devices 1912, such as tunnel field-effect transistors (TFETs), constructed according to the embodiments of the invention. The term "processor" may refer to any device or any part of a device that processes electronic data from registers and / or memories in order to convert such electronic data into other electronic data that can be stored in registers and / or memories.

[0040] The communication chip 1906 also includes an integrated circuit bare chip 1920, which is located within the package of the communication chip 1906. According to a further implementation of the invention, the integrated circuit bare chip of the communication chip comprises one or more devices 1921, such as tunnel field-effect transistors (TFETs), which were constructed according to the implementations of the invention.

[0041] In further implementations, another component located within the computer device 1900 can include an integrated circuit naked chip comprising one or more devices, such as tunnel field effect transistors (TFETs), constructed according to implementations of the invention.

[0042] In various implementations, the computer device 1900 can be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In other implementations, the computer device 1900 can be any other device that processes data.

[0043] Therefore, embodiments of the present invention include tunnel field effect transistors (TFETs) with undoped drain overlap winding regions.

[0044] In one embodiment, a tunnel field-effect transistor (TFET) comprises an active homojunction region formed (e.g., placed, arranged, positioned, or arranged) above a substrate. The active homojunction region includes a doped source region, an undoped channel region, a wound region, and a doped drain region. A gate stack is formed on the undoped channel region, between the source and wound regions. The gate stack comprises a gate dielectric portion and a gate electrode portion. The TFET has a length in a first direction and a width in a second direction, while the wound region has a width in the second direction that is greater than its length in the first direction. The length and width of the TFET can be designed to have similar dimensions to those of a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0045] In one embodiment, the TFET is a device based on Finfet or Trigate.

[0046] In one embodiment, the TFET device further comprises symmetrical gate spacers, each adjacent to the gate electrode. The wound area can be grown on an exposed portion of the active area and borders one of the gate spacers of the gate electrode.

[0047] In one embodiment, a doped drain region is formed by allowing an in situ doped material to grow on an exposed part of the wrapped area.

[0048] In one embodiment, the TFET device is an N-type TFET comprising the source region, which has a p+ dopant, and the drain region, which has an N-type dopant.

[0049] In one embodiment, a tunnel field-effect transistor (TFET) comprises an active heterojunction region formed above a substrate. The active heterojunction region includes a doped source region, an undoped channel region, a wound region, and a doped drain region. A gate electrode and a gate dielectric layer are formed on the undoped channel region, between the source and wound regions. A gate stack comprises a gate dielectric portion and a gate electrode portion.

[0050] In one embodiment, the TFET has a length in a first direction and a width in a second direction, and the wrapped area has a width in the second direction that is greater than a length in the first direction.

[0051] In one embodiment, the length and width of the TFET are similar to those of a metal-oxide-semiconductor field-effect transistor (MOSFET). The TFET can be a FinFET or Trigate-based device.

[0052] In one embodiment, the TFET device further comprises symmetrical gate spacers that have approximately the same thickness and each adjoin the gate electrode.

[0053] In one embodiment, the wrapped area is allowed to grow on an exposed part of the active area and borders one of the gate spacers of the gate electrode.

[0054] A doped drain area is formed by allowing in situ doped material to grow on an exposed part of the wrapped area.

[0055] In one embodiment, the TFET device is an N-type TFET comprising the source region which has gallium antimony (GaSb), the channel region which has indium arsenide (InAs), and the drain region which has InAs.

[0056] In one embodiment, a computing device comprises a memory for storing electronic data and a processor coupled to the memory. The processor processes electronic data. The processor includes an integrated circuit bare chip comprising tunnel field-effect transistors (TFETs). At least one TFET comprises an active heterojunction formed above a substrate. The active heterojunction comprises a doped source region, an undoped channel region, a wound region, and a doped drain region. A gate electrode and gate dielectric layer are formed on the undoped channel region, between the source and wound regions. A gate stack comprises a gate dielectric portion and a gate electrode portion.

[0057] In one embodiment, the TFET has a length in a first direction and a width in a second direction, and the wrapped area has a width in the second direction that is greater than a length in the first direction.

[0058] In one embodiment, the length and width of the TFET are similar to those of a metal-oxide-semiconductor field-effect transistor (MOSFET). The TFET can be a FinFET or Trigate-based device.

[0059] In one embodiment, the TFET device further comprises symmetrical gate spacers that have approximately the same thickness and each adjoin the gate electrode.

[0060] In one embodiment, the wrapped area is allowed to grow on an exposed part of the active area and borders one of the gate spacers of the gate electrode.

[0061] A doped drain area is formed by allowing in situ doped material to grow on an exposed part of the wrapped area.

[0062] In one embodiment, the TFET device is an N-type TFET comprising the source region which has gallium antimony (GaSb), the channel region which has indium arsenide (InAs), and the drain region which has InAs.

Claims

[1] Tunnel field effect transistor, TFET (400, 500, 1400, 1500, 1600), comprising: an active homotransition region formed above a substrate, wherein the active homotransition region comprises: a doped source region, an undoped channel region, a wrapped drain underlap region, and a doped drain region; and a gate electrode (602, 604, 606, 702, 704, 706, 802, 804, 806, 902, 904, 906, 1002, 1004, 1006, 1102, 1104, 1106, 1202, 1204, 1206, 1304, 1404, 1520a, 1520b, 1620a, 1620b) and a gate dielectric layer formed on the undoped channel area between the source area and the wound drain overlap area. [2] TFET (400, 500, 1400, 1500, 1600) according to claim 1, wherein the TFET (400, 500, 1400, 1500, 1600) has a length in a first direction and a width in a second direction and the wrapped area has a width in the second direction which is greater than a length in the first direction. [3] TFET (400, 500, 1400, 1500, 1600) according to claim 1, wherein the length and width of the TFET (400, 500, 1400, 1500, 1600) are similar to the length and width of a metal oxide semiconductor field-effect transistor, MOSFET. [4] TFET (400, 500, 1400, 1500, 1600) according to claim 1, wherein the TFET (400, 500, 1400, 1500, 1600) is a Finfet or Trigate-based device. [5] TFET (400, 500, 1400, 1500, 1600) according to claim 1, wherein the TFET (400, 500, 1400, 1500, 1600) further comprises: symmetrical gate spacers, each adjacent to the gate electrode (602, 604, 606, 702, 704, 706, 802, 804, 806, 902, 904, 906, 1002, 1004, 1006, 1102, 1104, 1106, 1202, 1204, 1206, 1304, 1404, 1520a, 1520b, 1620a, 1620b). [6] TFET (400, 500, 1400, 1500, 1600) according to claim 5, wherein the wound area is allowed to grow on an exposed part of the active area and is adjacent to one of the gate spacers of the gate electrode (602, 604, 606, 702, 704, 706, 802, 804, 806, 902, 904, 906, 1002, 1004, 1006, 1102, 1104, 1106, 1202, 1204, 1206, 1304, 1404, 1520a, 1520b, 1620a, 1620b). [7] TFET (400, 500, 1400, 1500, 1600) according to claim 1, wherein a doped drain region is formed by growing in situ doped material on an exposed part of the wrapped region. [8] TFET (400, 500, 1400, 1500, 1600) according to claim 1, wherein the TFET (400, 500, 1400, 1500, 1600) is an n-type TFET comprising the source region (522, 808, 1108, 1208, 1308, 1408, 1511, 1612) having a p+ dopant and the drain region (528, 1072, 1160, 1273, 1325, 1410, 1542, 1642) having an n-type dopant. [9] Tunnel field effect transistor, TFET (400, 500, 1400, 1500, 1600), comprising: an active heterojunction region formed above a substrate, wherein the active heterojunction region comprises a doped source region, an undoped channel region, a wrapped region, and a doped drain region; and a gate electrode (602, 604, 606, 702, 704, 706, 802, 804, 806, 902, 904, 906, 1002, 1004, 1006, 1102, 1104, 1106, 1202, 1204, 1206, 1304, 1404, 1520a, 1520b, 1620a, 1620b) and a gate dielectric layer formed on the undoped channel area between the source area and the wound area. [10] TFET (400, 500, 1400, 1500, 1600) according to claim 9, wherein the TFET (400, 500, 1400, 1500, 1600) has a length in a first direction and a width in a second direction and the wrapped area has a width in the second direction which is greater than a length in the first direction. [11] TFET (400, 500, 1400, 1500, 1600) according to claim 9, wherein the length and width of the TFET (400, 500, 1400, 1500, 1600) is similar to the length and width of a metal oxide semiconductor field-effect transistor, MOSFET. [12] TFET (400, 500, 1400, 1500, 1600) according to claim 9, wherein the TFET (400, 500, 1400, 1500, 1600) is a Finfet or Trigate-based device. [13] TFET (400, 500, 1400, 1500, 1600) according to claim 9, wherein the TFET (400, 500, 1400, 1500, 1600) further comprises: symmetrical gate spacers of approximately the same thickness, each adjacent to the gate electrode (602, 604, 606, 702, 704, 706, 802, 804, 806, 902, 904, 906, 1002, 1004, 1006, 1102, 1104, 1106, 1202, 1204, 1206, 1304, 1404, 1520a, 1520b, 1620a, 1620b). [14] TFET (400, 500, 1400, 1500, 1600) according to claim 13, wherein the wound area is allowed to grow on an exposed part of the active area and is adjacent to one of the gate spacers of the gate electrode (602, 604, 606, 702, 704, 706, 802, 804, 806, 902, 904, 906, 1002, 1004, 1006, 1102, 1104, 1106, 1202, 1204, 1206, 1304, 1404, 1520a, 1520b, 1620a, 1620b). [15] TFET (400, 500, 1400, 1500, 1600) according to claim 9, wherein a doped drain region is formed by growing in situ doped material on an exposed part of the wrapped region. [16] TFET (400, 500, 1400, 1500, 1600) according to claim 9, wherein the TFET (400, 500, 1400, 1500, 1600) is an n-type TFET comprising the source region (522, 808, 1108, 1208, 1308, 1408, 1511, 1612) comprising gallium antimony, GaSb, the channel region comprising indium arsenide, InAs, and the drain region (528, 1072, 1160, 1273, 1325, 1410, 1542, 1642) comprising InAs. [17] Computer device (1900), comprising: Storage for storing electronic data; and a processor (1904) coupled to the memory, wherein the processor (1904) processes electronic data and comprises an integrated circuit comprising a plurality of tunnel field effect transistors, TFET (400, 500, 1400, 1500, 1600), wherein at least one TFET (400, 500, 1400, 1500, 1600) comprises: an active heterojunction region formed above a substrate, wherein the active heterojunction region comprises a doped source region, an undoped channel region, a wrapped region, and a doped drain region; and a gate electrode (602, 604, 606, 702, 704, 706, 802, 804, 806, 902, 904, 906, 1002, 1004, 1006, 1102, 1104, 1106, 1202, 1204, 1206, 1304, 1404, 1520a, 1520b, 1620a, 1620b) and a gate dielectric layer formed on the undoped channel area between the source area and the wound area. [18] Computer device (1900) according to claim 17, wherein the TFET (400, 500, 1400, 1500, 1600) has a length in a first direction and a width in a second direction and the wrapped area has a width in the second direction which is greater than a length in the first direction. [19] Computer device (1900) according to claim 17, wherein the length and width of the TFET (400, 500, 1400, 1500, 1600) are similar to the length and width of a metal oxide semiconductor field-effect transistor, MOSFET. [20] Computer device (1900) according to claim 17, wherein the TFET (400, 500, 1400, 1500, 1600) is a Finfet or Trigate-based device. [21] Computer device (1900) according to claim 17, wherein the TFET (400, 500, 1400, 1500, 1600) further comprises: symmetrical gate spacers of approximately the same thickness, each adjacent to the gate electrode (602, 604, 606, 702, 704, 706, 802, 804, 806, 902, 904, 906, 1002, 1004, 1006, 1102, 1104, 1106, 1202, 1204, 1206, 1304, 1404, 1520a, 1520b, 1620a, 1620b). [22] Computer device (1900) according to claim 17, wherein the wound area is allowed to grow on an exposed part of the active area and is adjacent to one of the gate spacers of the gate electrode (602, 604, 606, 702, 704, 706, 802, 804, 806, 902, 904, 906, 1002, 1004, 1006, 1102, 1104, 1106, 1202, 1204, 1206, 1304, 1404, 1520a, 1520b, 1620a, 1620b). [23] Computer device (1900) according to claim 17, wherein a doped drain area is formed by growing in situ doped material on an exposed part of the wrapped area. [24] Computer device (1900) according to claim 17, wherein the TFET (400, 500, 1400, 1500, 1600) is an n-type TFET comprising the source region (522, 808, 1108, 1208, 1308, 1408, 1511, 1612) comprising gallium antimony, GaSb, the channel region comprising indium arsenide, InAs, and the drain region (528, 1072, 1160, 1273, 1325, 1410, 1542, 1642) comprising InAs.

Images