Storage cell having isolated charge points, and methods for its manufacture

Abstract

Non-volatile charge capture storage device (200'), comprising: a substrate (208) comprising a channel region, a source region (204) and a drain region (206); and a gate stack arranged above the substrate (208) over the channel region, wherein the gate stack comprises: a first dielectric tunnel layer region (210') and a second dielectric tunnel layer region (210') located above the channel region and separated by a distance; a first charge-capture region (212A') and a second charge-capture region (212B'), wherein the first charge-capture region is located above the first dielectric tunnel layer region and the second charge-capture region is located above the second dielectric tunnel layer region and are separated by the distance; a dielectric insulating layer (218') located above the channel region between the first charge-trapping region (212A') and the second charge-trapping region (212B') and between the first dielectric tunnel layer region and the second dielectric tunnel layer region; a dielectric gate layer (214) located above the first charge-trapping region (212A'), the second charge-trapping region (212B') and the dielectric isolation layer (218'); and a gate electrode (216) arranged above the dielectric gate layer (214), wherein part of the gate electrode (216) is arranged above a vertical sidewall part of the first dielectric tunnel layer region and a vertical sidewall part of the second dielectric tunnel layer region, wherein the first dielectric tunnel layer region (210') further extends along an outer side wall of the first charge trapping region (212A') and the second dielectric tunnel layer region (210') further extends along an outer side wall of the second charge trapping region (212B').

Description

SUBJECT AREA

[0001] Embodiments of the invention lie in the field of semiconductor devices and processing, and in particular memory cells having isolated charge points, and methods for manufacturing memory cells having isolated charge points. BACKGROUND

[0002] In recent decades, the scaling of elements in integrated circuits has been a driving force behind the ever-expanding semiconductor industry. Scaling down to ever smaller elements enables increased densities of functional units on the limited area of ​​semiconductor chips. For example, shrinking the transistor size allows for a greater number of memory or logic devices to be placed on a single chip, leading to the production of products with increased capacity. However, the pursuit of ever greater capacity brings its own set of challenges. The need to optimize the performance of each device becomes increasingly significant. Furthermore, space constraints can also impact efficiency in terms of the semiconductor bare-chip area.

[0003] US 2004 / 0232470A1 discloses a non-volatile charge-capture storage device comprising a substrate having a channel region, a source region, and a drain region, and a gate stack arranged above the substrate over the channel region, wherein the gate stack comprises: a dielectric tunnel layer arranged above the channel region, a first charge-capture region and a second charge-capture region, the regions being arranged above the dielectric tunnel layer and separated by a spacer, a dielectric isolation layer arranged above the dielectric tunnel layer and between the first charge-capture region and the second charge-capture region, a dielectric gate layer arranged above the first charge-capture region, the second charge-capture region, and the dielectric isolation layer, and a gate electrode arranged above the dielectric gate layer.

[0004] US 2006 / 0035433A1 discloses a non-volatile charge-trapping storage device comprising a substrate having a channel region, a source region, and a drain region, and a gate stack arranged above the substrate above the channel region, wherein the gate stack comprises: a first dielectric tunnel layer region and a second dielectric tunnel layer region arranged above the channel region and separated by a space, a first charge-trapping region and a second charge-trapping region, wherein the regions above the first dielectric tunnel layer region and the second dielectric tunnel layer region are respectively arranged by a space.a dielectric insulating layer arranged above the channel region between the first charge-trapping region and the second charge-trapping region and between the first dielectric tunnel region and the second dielectric tunnel region, and a gate electrode.

[0005] US 2009 / 0134444A1 discloses a method for manufacturing a non-volatile charge-trapping storage device, the method comprising: removing a placeholder gate electrode to form a trench above a substrate having a channel region, a source region, and a drain region, all self-aligned with the trench; forming a dielectric tunnel layer in the trench; forming a first charge-trapping region and a second charge-trapping region above the dielectric tunnel layer, separated by a gap; forming a dielectric gate layer above the first charge-trapping region and the second charge-trapping region; and forming a gate electrode.

[0006] US 2003 / 0034518A1 and US 6178113B1 disclose further non-volatile storage devices. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates a cross-sectional view of a conventional storage cell having electrically isolated charge trapping sites, according to the state of the art. Fig. Figure 2 illustrates a cross-sectional view of a storage cell having both physically and electrically isolated charge trapping sites according to the present invention. Fig. 3A illustrates a cross-sectional view of a memory cell made of Fig. 2, which has both physically and electrically isolated charge trapping points and is operated in a program mode, according to an embodiment of the present invention. Fig. 3B illustrates a cross-sectional view of a memory cell made of Fig. 2, which has both physically and electrically isolated charge trapping points and is operated in a reading mode, according to an embodiment of the present invention. Fig. 3C illustrates a cross-sectional view of a memory cell made of Fig. 2, which has both physically and electrically isolated charge trapping points and is operated in an extinguishing mode, according to an embodiment of the present invention. The Fig. Figures 4A-4D illustrate cross-sectional views of various operations in a method for manufacturing a storage cell having both physically and electrically isolated charge trapping sites according to the present invention. The Fig. Figures 5A-5D illustrate cross-sectional views of various operations in a further method for manufacturing a storage cell having both physically and electrically isolated charge trapping sites according to the present invention. Fig. Figure 6 illustrates a computer device according to an implementation of the invention. DESCRIPTION OF THE EXECUTION FORMS

[0007] This document describes memory cells having isolated charge points and methods for manufacturing memory cells having isolated charge points. Numerous specific details, such as specific integration and material states, are presented in the following description to provide a thorough understanding of embodiments of the present invention. In other cases, well-known features, such as the design layouts of integrated circuits, are not described in detail to avoid unnecessarily obscuring embodiments of the present invention. It should also be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0008] One or more embodiments described herein relate to isolated structures for charge storage / capture in flash memory cells. In one embodiment, the memory cells described herein can be implemented as embedded memory for a single-chip system (SoC) architecture, e.g., as embedded flash memory.

[0009] In general, in one embodiment, isolated charge-trapping / storage sites for non-volatile memory cells, as described herein, can be used to double the corresponding bit density of flash memory cells. Additionally, approaches described herein can be implemented to overcome scaling limitations associated with conventional continuous charge-trapping layers (e.g., nitride layers). Scaling limitations associated with such continuous charge-trapping layers can result from crosstalk and scattering loss problems between localized trapping sites that are typically separated by a very short distance. Furthermore, embodiments described herein can enable fabrication compatibility with high-k and / or metal-gate processing, along with flexibility in material selection for each layer / structure of the described devices.

[0010] More specifically, the embodiments described herein relate to the fabrication of capture / storage sites that are not only electrically isolated (e.g., as in continuous nitride layers) but also physically isolated. Such physical isolation can enable the elimination or at least reduction of crosstalk between the two bits of a single memory cell, which can be advantageous for scaling. In one embodiment, physically separating the charge capture / storage sites allows for the fabrication of a flash device with two bits per cell that is easily compatible with high-k and / or metal-gate technologies.

[0011] To provide context, conventional devices employ continuous nitride layers for charge trapping. While charge trapping is localized, the two trapping sites cannot be in close proximity, which can hinder further scaling. In contrast, according to one embodiment of the present invention, the physically isolated charge trapping / storage structures described herein can be integrated using CMOS techniques without additional masks. Furthermore, the approaches described herein can accommodate a wide selection of tunneling, trapping / storage, and gate materials, allowing for precise customization of each performance factor of the resulting device (e.g., program / erase / read voltage, program / erase / read speed, retention, durability).

[0012] As further explained and illustrated below in conjunction with the drawings, embodiments described herein may include one or more features: (1) the use of physical separation of capture / storage sites for improved scaling and performance; (2) freedom of material selection for charge capture / storage sites, tunnel / gate oxide, and gate material for improved performance (e.g., force, velocity, retention, and durability); (3) self-alignment with and compatibility with high-k and metal-gate (HKMG) complementary metal-oxide semiconductor (CMOS) processes; and (4) operation in combination with multi-level capture / storage capacity.

[0013] For comparison purposes, illustrated Fig. 1 A cross-sectional view of a conventional storage cell having electrically isolated charge traps, according to the prior art. With regard to Fig. 1 comprises an N-type semiconductor oxide-nitride oxide semiconductor device 100 (SONOS NROM) comprising a gate stack 102, a source region 104, and a drain region 106 as configured in and above a substrate 108. The source region 104 and the drain region 106 are N-type regions that can be used as the first (BL1) and second (BL2) bit lines, respectively. The gate stack 102 comprises a dielectric tunnel layer 110, a charge-trapping layer 112, and a dielectric gate layer 114. The gate stack 102 also includes a gate electrode 116, e.g., an N-type gate electrode, which can be used as a word line (WL) for the device 100. The charge-trapping layer 112 is a non-conductive nitride layer that traps charges at electrically isolated locations 120. The charge-trapping layer 112 is a continuous material between the electrically isolated locations 120.

[0014] As opposed to Fig. 1 illustrates Fig. 2 A cross-sectional view of a storage cell having both physically and electrically isolated charge trapping sites according to the present invention. With regard to Fig. Figure 2 comprises a semiconductor device 200 comprising a gate stack 202, a source region 204, and a drain region 206 as configured in and above a substrate 208. The source region 204 and the drain region 206 can be used as the first (BL1) and second (BL2) bit lines, respectively. The gate stack 202 comprises a dielectric tunnel layer 210, a charge-trapping layer 212 (shown as 212A and 212B), and a dielectric gate layer 214. A physically isolated dielectric layer 218 is arranged vertically between the dielectric tunnel layer 210 and the dielectric gate layer 214. The physically isolated dielectric layer 218 is arranged horizontally between regions 212A and 212B of the charge-trapping layer 212. In one embodiment, the charge-trapping layer 212 is a non-conductive dielectric layer that traps charges at physically and electrically isolated locations 220.Thus, the charge-trapping layer 212 (shown as 212A and 212B) is not continuous material between the electrically isolated sites 220. According to one embodiment of the present invention, the electrically isolated sites 220 are self-aligning charge sites that provide physically isolated structures for charge trapping and / or charge storage. The gate stack 202 also includes a gate electrode 216, which can be used as a word line (WL) for the device 200. The gate electrode 216 is electrically isolated from the substrate 208.

[0015] Again, in relation to Fig. 2. In one embodiment, the device 200 can be viewed or described as a SONOS-type storage device. SONOS conventionally stands for "semiconductor-oxide-nitride-oxide-semiconductor," where the first "semiconductor" refers to the gate layer, the first "oxide" refers to the dielectric gate layer, "nitride" refers to the dielectric charge-trapping layer, the second "oxide" refers to the dielectric tunnel layer, and the second "semiconductor" refers to the channel region material. However, a SONOS-type device is not limited to these specific materials, as described below. In one embodiment, the SONOS device is an N-type SONOS device (SONOS NROM). In another embodiment, the SONOS device is a P-type SONOS device (SONOS PROM). In one embodiment, devices comprising a metal gate electrode may be referred to as MONOS devices.

[0016] Again, in relation to Fig. 2 In one embodiment, the substrate 208 can consist of a material suitable for fabricating a semiconductor device. In another embodiment, the substrate 208 is a bulk substrate consisting of a single crystal of a material that may, but is not limited to, silicon, germanium, silicon-germanium, or a III-V compound semiconductor material. In a further embodiment, the substrate 208 comprises a bulk layer with an epitaxial top layer.In one specific embodiment, the mass layer consists of a single crystal of a material that may include, but is not limited to, silicon, germanium, silicon-germanium, a III-V compound semiconductor material, or quartz, while the epitaxial top layer consists of a single crystal layer that may include, but is not limited to, silicon, germanium, silicon-germanium, or a III-V compound semiconductor material. In another embodiment, the substrate 208 comprises an epitaxial top layer on a middle insulating layer located above a lower mass layer. The epitaxial top layer consists of a single crystal layer that may include, but is not limited to, silicon (i.e., to form a SOI (silicon-on-an-insulator) semiconductor substrate), germanium, silicon-germanium, or a III-V compound semiconductor material.The insulating layer consists of a material that may, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride. The lower bulk layer consists of a single crystal that may, but is not limited to, silicon, germanium, silicon-germanium, a III-V compound semiconductor material, or quartz. The substrate 208 may include dopants. In one specific embodiment, at least a portion of the substrate 208 is P-type doped, and in an alternative embodiment, at least a portion of the substrate 208 is N-type doped.

[0017] Again, in relation to Fig. 2 In one embodiment, a source region 204 and a drain region 206 are formed in the substrate 208 and can be regions exhibiting opposite conductivity for the respective part of the substrate 208 (e.g., opposite to a channel region 207 formed in the substrate 208). For example, in one embodiment, the source and drain regions 204 and 206 are N-type doped regions, while the channel region 207 is a P-type doped region. In one embodiment, the substrate 208, and therefore the channel region 207, consists of boron-doped single-crystal silicon with a boron concentration approximately in the range of 1 × 10⁻⁶ 15 - 1 × 10 19 atoms / cm² 3 The source and drain regions 204 and 206 consist of phosphorus- or arsenic-doped regions exhibiting a concentration of N-type dopants approximately in the range of 5 × 10 16 - 5 × 10 19 atoms / cm² 3exhibit. In an alternative embodiment, the source and drain regions 204 and 206 are P-type doped regions, while the channel region 207 is an N-type doped region.

[0018] Again, in relation to Fig. 2 In one embodiment, the dielectric tunneling layer 210 can be made of a material and have a thickness suitable to allow charge carriers to tunnel into the charge-trapping layer under an applied gate bias, while maintaining a suitable barrier layer to prevent stray losses when the device is unbiased. In one embodiment, the dielectric tunneling layer 210 is formed by a thermal oxidation process and consists of silicon dioxide or silicon oxynitride, or a combination thereof. In another embodiment, the dielectric tunneling layer 210 is formed by chemical vapor deposition or atomic layer deposition and consists of a dielectric layer comprising, but not limited to, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, hafnium silicate, zirconium silicate, hafnium oxynitride, hafnium zirconium oxide, or lanthanum oxide.In another embodiment, the dielectric tunneling layer 210 is a dielectric bilayer region comprising a bottom layer of a material such as, but not limited to, silicon dioxide or silicon oxynitride, and a top layer of a material that includes, but is not limited to, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, hafnium silicate, zirconium silicate, hafnium oxynitride, hafnium zirconium oxide, or lanthanum oxide. In one embodiment, the dielectric tunneling layer 210 therefore includes a high-K dielectric region. In a specific embodiment, the dielectric tunneling layer 210 has a thickness approximately in the range of 1–10 nanometers.

[0019] Again, in relation to Fig. 2 In one embodiment, the charge-trapping layer 212 (e.g., as regions 212A and 212B) can be made of a material and have a thickness suitable for storing charge and thus increasing the threshold voltage of the gate stack 202. In one embodiment, the charge-trapping layer 212 is formed by a chemical vapor deposition process and consists of a dielectric material that includes, but is not limited to, stoichiometric silicon nitride, silicon-rich silicon nitride, or silicon oxynitride. In one embodiment, the charge-trapping layer 212 has a thickness approximately in the range of 5–10 nanometers.

[0020] Again, in relation to Fig. 2 In one embodiment, the physically insulating dielectric layer 218 can consist of a material and have a thickness suitable for isolating regions 212A and 212B of the charge-trapping layer 212 to prevent crosstalk between the two regions. In one embodiment, the physically insulating dielectric layer 218 is formed by a chemical vapor deposition process and consists of a dielectric material such as silicon dioxide (SiO₂). x) or stoichiometric silicon dioxide (SiO2), but is not limited to these. In an alternative embodiment, a dielectric low-k material (e.g., a material whose dielectric constant is less than 4) is used to form the physically insulating dielectric layer 218. In one embodiment, the physically insulating dielectric layer 218 has a thickness approximately equal to the thickness of the charge-trapping layer 212. In another embodiment, however, the physically insulating dielectric layer 218 has a thickness less than the thickness of the charge-trapping layer 212. In yet another embodiment, the physically insulating dielectric layer 218 has a thickness greater than the thickness of the charge-trapping layer 212. In one embodiment, the width of the physically insulating dielectric layer 218 (e.g.,The distance between regions 212A and 212B of the charge-trapping layer 212 is approximately in the range of 3–20 nanometers. It should be understood that the lower end of this range represents a minimum of a few nanometers, while the upper limit can depend on the actual gate length used.

[0021] Again, in relation to Fig. 2 In one embodiment, the dielectric gate layer 214 can be made of a material and have a thickness suitable to provide a barrier layer against charge leakage loss without significantly reducing the capacitance of the gate stack 202. In one embodiment, the dielectric gate layer 214 is formed by a chemical vapor deposition process. In such a specific embodiment, the dielectric gate layer 214 consists of silicon dioxide, silicon oxynitride, silicon nitride, or a combination thereof. In another embodiment, the dielectric gate layer 214 is formed by atomic layer deposition. In such a specific embodiment, the dielectric gate layer 214 consists of a high-k dielectric layer, which may include, but is not limited to, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxynitride, hafnium zirconium oxide, or lanthanum oxide.In a specific embodiment, the dielectric gate layer 214 has a thickness approximately in the range of 1-20 nanometers.

[0022] Again, in relation to Fig. 2 In one embodiment, the gate electrode 216 can be made of a conductor or semiconductor material suitable for accepting a bias voltage during the operation of a SONOS-type transistor. In another embodiment, the gate electrode 216 is formed by a chemical vapor deposition process. In such a specific embodiment, the gate electrode 216 is made of doped polycrystalline silicon. In a further embodiment, the gate electrode 216 is formed by physical vapor deposition and is made of a metal-containing material that may include, but is not limited to, metal nitrides, metal carbides, metal silicides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, or nickel. In one embodiment, the gate electrode 216 has an N-type work function. In an alternative embodiment, the gate electrode 216 has a P-type work function.

[0023] The device, which is associated with Fig. The device described in section 2 can be operated as a non-volatile storage device. Fig. 3A-3C illustrate a cross-sectional view of a memory cell made of Fig. 2, which has both physically and electrically isolated charge trapping sites and operates in a program mode ( Fig. 3A), a reading mode ( Fig. 3B) and a deletion mode ( Fig. 3C) is operated according to an embodiment of the present invention. It should be understood that for operations for the mirrored bit, the BL1 and BL2 voltages described below are reversed.

[0024] In relation to Fig. Section 3A comprises the programming of the device for hot charge carrier channel injection. In an exemplary embodiment, a 9 V bias voltage is applied to the gate electrode 216 of the gate stack 202. The source region 204 (BL1) is connected to ground (GND). Finally, the drain region 206 (BL2) is biased with a 5 V voltage. A path 300A of charge carriers (e.g., electrons) leads from the source region 204 (BL1) to region 212B of the charge-trapping layer 212. The resulting electric field between the gate and the substrate causes electrons to tunnel from the substrate through the thin tunnel oxide layer, where they are trapped in the charge-trapping layer. When the programming voltage is removed, the electrons trapped in the nitride layer repel electrons from the channel and induce a positive space charge in the P-type channel. The electron-depleted channel forms PN junctions with the N+ source and drain diffusions.In such a state, the transistor cannot conduct current from drain to source when a drain-source voltage is applied. The programmed state can be assigned to a logical state (e.g., a logical "1").

[0025] In relation to Fig. 3B includes a reversal mode for reading the device 200 to enrich a reading window. In one exemplary embodiment, a 3 V bias is applied to the gate electrode 216 of the gate stack 202. The drain region 206 (BL2) is connected to ground (GND). Finally, the source region 204 (BL2) is biased with a 1.5 V bias. A path 300B of charge carriers (e.g., electrons) is provided from the drain region 206 (BL2) to the channel region 207 of the device 200. In one embodiment, greater sensitivity is achieved with trapped electrons near the source region 204 than near the drain region 206. It should be understood that in one embodiment, greater sensitivity is achieved when the trapped electrons are close to the "source" of electrons in the channel, in this case 206.

[0026] In relation to Fig. 3C comprises the quenching of the device 200 band-to-band hot hole tunneling. In an exemplary embodiment, a -5 V bias is applied to the gate electrode 216 of the gate stack 202. The source region 204 (BL1) is biased to 5 V. Finally, the drain region 206 (BL2) is biased to ground (GND, 0 V). A path 300C of charge carriers (e.g., holes) leads from the channel region 207 to region 212B of the charge-trapping layer 212. The resulting electric field between the gate and the substrate causes holes to tunnel from the substrate through the thin tunnel oxide layer, where they are trapped in the charge-trapping layer. When the quenching voltage is removed, the holes trapped in the nitride layer attract electrons to the channel, reversing the normally P-type channel. The reversed channel then allows the transistor to conduct current between drain and source when a voltage is applied.

[0027] In another aspect, a device such as the device 200 from Fig. 2. can be formed by using a replacement gate or Damascene type process. As an example, the following illustrate... Fig. 4A-4D Cross-sectional views of various operations in a method for manufacturing a storage cell having both physically and electrically isolated charge trapping sites according to the present invention.

[0028] In relation to Fig. 4A A trench 250 is formed in a dielectric intermediate layer 260. In one embodiment, the trench 250 is formed in a substitute gate processing scheme (described in detail below), wherein the source and drain regions 204 and 206, respectively, remain self-aligned with the trench 250. The dielectric tunnel layer 210 is then formed in the trench 250. Regions 212A and 212B of the charge-trapping layer are then formed in the trench 250 on the dielectric tunnel layer 210. In one embodiment, regions 212A and 212B of the charge-trapping layer are formed by deposition and etching (e.g., in a spacer-forming process) of the charge-trapping material.

[0029] In relation to Fig. 4B a material layer 270, which is a precursor of the dielectric insulating layer 218, is deposited in the remaining parts of the trench 250 from Fig. 4A and on the dielectric tunnel layer 210 and the regions 212A and 212B of the charge-trapping layer. A dielectric spin-on layer, such as a lower antireflection coating layer 272 (BARC layer), is then formed on the material layer 270, which is a precursor to the dielectric insulating layer 218. Subsequently, an angle implementation process 274 is carried out to cure regions of the dielectric spin-on layer 270 near the center of the layer.

[0030] In relation to Fig. In step 4C, the corners of the dielectric spin-on layer 270 (e.g., the unhardened parts) and the material layer 270 are removed by an etching process to preserve the structured dielectric insulating layer 218. Parts of the dielectric spin-on layer 270 (e.g., the hardened parts) are also retained, as shown in Fig. 4C shown.

[0031] In relation to Fig. In step 4D, the portions of the dielectric spin-on layer 270 that remain are removed, for example, by a dry or wet etching process. The dielectric gate layer 214 is then formed on the dielectric insulating layer 218 and on exposed portions of the charge-trapping layer (shown, for example, as regions 212A and 212B). The gate electrode 216 is then deposited to complete the filling of the trench 250. It should be understood that chemical-mechanical planarization (CMP) operations can be used to confine the materials described above to the trench 250. It should also be understood that subsequent processing, such as dielectric back-end and metallization, can be used to fabricate an integrated circuit based on a variety of devices, such as device 200. Fig. to train in 4D.

[0032] As a further example, the Fig. 5A-5D Cross-sectional views of various operations in a method for manufacturing a storage cell having both physically and electrically isolated charge trapping sites according to the present invention.

[0033] In relation to Fig. In 5A, a trench 250 is formed in a dielectric intermediate layer 260. In one embodiment, the trench 250 is formed in a substitute gate processing scheme (described in detail below), wherein the source and drain regions 204 and 206, respectively, remain self-aligned with the trench 250. A dielectric tunnel layer 210' is then formed in the trench 250. Regions 212A' and 212B' of the charge-trapping layer are then formed in the trench 250 on the dielectric tunnel layer 210'. In one embodiment, the dielectric tunnel layer 210' and the regions 212A' and 212B' of the charge-trapping layer are formed by deposition and etching (e.g. in a spacer-forming approach), wherein the dielectric tunnel layer 210' is provided under and along the side walls of the regions 212A' and 212B' of the charge-trapping layer.In one embodiment, the part of the dielectric tunnel layer 210' between regions 212A' and 212B' of the charge-trapping layer is also removed, as in . Fig. 5A is shown.

[0034] In relation to Fig. 5B, an angle implementation method 274' is optionally used to damage the exposed portion of the substrate 208 between regions 212A' and 212B' of the charge-trapping layer. In one embodiment, the angle implementation method 274' is used to damage exposed silicon from a bulk silicon substrate.

[0035] In relation to Fig. In step 5C, the damaged part of the substrate 208 between regions 212A' and 212B' is oxidized to form a dielectric insulating layer 218'. In one embodiment, a damaged part of a silicon substrate is oxidized to form a dielectric silicon oxide or silicon dioxide insulating layer 218'.

[0036] In relation to Fig. In step 5D, the dielectric gate layer 214 is subsequently formed on the dielectric insulating layer 218' and on exposed portions of the charge-trapping layer (e.g., shown as regions 212A' and 212B') and on exposed portions of the dielectric tunneling layer 210' (e.g., the exposed sidewall portions). The gate electrode 216 is then deposited to complete the filling of the trench 250. It should be understood that chemical-mechanical planarization (CMP) operations can be used to confine the materials described above to the trench 250. It should also be understood that subsequent processing, such as dielectric back-end and metallization, can be used to fabricate an integrated circuit based on a variety of devices, such as device 200'. Fig. to train in 5D.

[0037] Again, in relation to the Fig. 4A and Fig. 5B A replacement gate method can be used to provide the initial structures for final device fabrication. In such a scheme, placeholder gate material, such as polysilicon or silicon nitride column material, can be removed, allowing replacement with the final (permanent) materials of device 200. In one embodiment, placeholder gates are removed by a dry etching or wet etching process. In one embodiment, placeholder gates consist of polycrystalline silicon or amorphous silicon and are removed by a dry etching process that includes the use of SF6. In another embodiment, placeholder gates consist of polycrystalline silicon or amorphous silicon and are removed by a wet etching process that includes the use of aqueous NH4OH or tetramethylammonium hydroxide.In one embodiment, placeholder gates consist of silicon nitride and are removed using wet processes with aqueous phosphoric acid. In another embodiment, a dielectric placeholder layer (e.g., a silicon dioxide layer) is also included and is removed for replacement with a dielectric tunneling layer, e.g., by treatment with aqueous or vaporous hydrofluoric acid.

[0038] In one embodiment, flash memory cells using localized capture with electrical and physical separation between the capture sites were described. By appropriately biasing the terminals of such a device, charge capture / storage can occur near the edge of the capture / storage layer. Embodiments can enable the enrichment of bit cell density compared to that of conventional flash cells using high-k and metal-gate methods at scaled-down generation nodes. Embodiments can allow flexibility in tunneling, capture / storage, and gate material selection for adjusting, for example, program / erase / read voltage, speed, retention, and persistence.

[0039] The embodiments described herein may be applicable to designs requiring flash memory embedded in a multifunctional chip, such as a system-on-a-chip (SoC) product. Current flash memory cells cannot be scaled to smaller device sizes. In contrast, in one embodiment, flash memory cells incorporating isolated charge points as described herein enable a smaller device and therefore a smaller circuit design and footprint.

[0040] Fig.Figure 6 illustrates a computer device 600 according to one implementation of the invention. The computer device 600 houses a circuit board 602. The circuit board 602 can comprise a number of components, including, but not limited to, a processor 604 and at least one communication chip 606. The processor 604 is physically and electrically coupled to the circuit board 602. In some implementations, the at least one communication chip 606 is also physically and electrically coupled to the circuit board 602. In other implementations, the communication chip 606 is part of the processor 604.

[0041] Depending on its applications, the computer device 600 may include additional components, which may or may not be physically and electrically coupled to the circuit board 602. These additional components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a screen, a touchscreen screen, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a GPS (global positioning system) device, a compass, an accelerometer, a gyroscope, a loudspeaker, a camera, and a mass storage device (such as a hard disk drive, a compact disc (CD), a DVD (digital versatile disc), and so on).

[0042] The 606 communication chip enables wireless communication for the transmission of data to and from the 600 computer device. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through a non-solid medium by using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain wires, although in some embodiments they may indeed not. The 606 communication chip can implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.11, and IEEE 802.11.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols referred to as 3G, 4G, 5G, and beyond. The computing device 600 can include a variety of communication chips 606. For example, a first communication chip 606 can be provided for shorter-range wireless communication, such as Wi-Fi and Bluetooth, and a second communication chip 606 can be provided for longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0043] The processor 604 of the computer device 600 comprises a bare chip of an integrated circuit enclosed within the processor 604. In some implementations of the invention, the bare chip of an integrated circuit of the processor comprises one or more devices, such as memory cells, having isolated charge points, constructed according to implementations of the invention, e.g., as part of a system-on-a-chip (SoC) architecture. The term "processor" can refer to any device or any part of a device that processes electronic data from registers and / or memory in order to convert this electronic data into other electronic data that can be stored in registers and / or memory.

[0044] The communication chip 606 also includes a bare chip of an integrated circuit enclosed within the communication chip 606. According to another implementation of the invention, the bare chip of an integrated circuit of the communication chip comprises one or more devices, such as memory cells, having isolated charge points, constructed according to implementations of the invention, e.g., as part of a system-on-a-chip (SoC) architecture.

[0045] In further implementations, another component housed within the computer device 600 can contain a bare chip of an integrated circuit comprising one or more devices, such as memory cells, having isolated charge points, constructed according to implementations of the invention, e.g. as part of a system-on-a-chip (SoC) architecture.

[0046] In various implementations, the Computing Device 600 can be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultramobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In other implementations, the Computing Device 600 can be any other electronic device that processes data.

[0047] Thus, embodiments of the present invention comprise memory cells having isolated charge points and methods for manufacturing memory cells having isolated charge points.

[0048] In one embodiment, a non-volatile charge-trapping storage device comprises a substrate having a channel region, a source region, and a drain region. A gate stack is arranged above the substrate, above the channel region. The gate stack comprises a dielectric tunnel layer located above the channel region, a first charge-trapping region, and a second charge-trapping region. The regions are located above the dielectric tunnel layer and separated by a gap. The gate stack also includes a dielectric isolation layer located above the dielectric tunnel layer and between the first and second charge-trapping regions. A dielectric gate layer is located above the first charge-trapping region, the second charge-trapping region, and the dielectric isolation layer. A gate electrode is located above the dielectric gate layer.

[0049] In one embodiment, the dielectric insulating layer isolates the first charge-trapping region both physically and electrically from the second charge-trapping region.

[0050] In one embodiment, the distance between the first charge-trapping region and the second charge-trapping region is approximately in the range of 3-20 nanometers.

[0051] In one embodiment, the dielectric insulating layer consists of silicon oxide or silicon dioxide.

[0052] In one embodiment, the dielectric gate layer consists of a high-k dielectric material.

[0053] In one embodiment, the gate electrode is a metal gate electrode.

[0054] In one embodiment, the non-volatile charge capture storage device is a SONOS-type device.

[0055] In one embodiment, the source region, the drain region and the gate electrode are N-type, and the SONOS-type device is an N-type SONOS-type device.

[0056] In one embodiment, a non-volatile charge-trapping storage device comprises a substrate having a channel region, a source region, and a drain region. A gate stack is arranged above the substrate, above the channel region. The gate stack comprises a first dielectric tunnel region and a second dielectric tunnel region, which are arranged above the channel region and separated by a gap. The gate stack also comprises a first charge-trapping region and a second charge-trapping region, the regions being arranged above the first and second dielectric tunnel regions, respectively, and separated by the gap.The gate stack also includes a dielectric isolation layer located above the channel region between the first and second charge-trapping regions and between the first and second dielectric tunnel regions. A dielectric gate layer is located above the first charge-trapping region, the second charge-trapping region, and the dielectric isolation layer. A gate electrode is located above the dielectric gate layer.

[0057] In one embodiment, the dielectric insulating layer isolates the first charge-trapping region both physically and electrically from the second charge-trapping region.

[0058] In one embodiment, the distance between the first charge-trapping region and the second charge-trapping region is approximately in the range of 3-20 nanometers.

[0059] In one embodiment, the dielectric insulating layer consists of silicon oxide or silicon dioxide.

[0060] In one embodiment, the dielectric gate layer consists of a high-k dielectric material.

[0061] In one embodiment, the gate electrode is a metal gate electrode.

[0062] In one embodiment, the non-volatile charge capture storage device is a SONOS-type device.

[0063] In one embodiment, the source region, the drain region and the gate electrode are N-type, and the SONOS-type device is an N-type SONOS-type device.

[0064] In one embodiment, the first dielectric tunnel layer region further extends along an outer side wall of the first charge-trapping region, and the second dielectric tunnel layer region further extends along an outer side wall of the second charge-trapping region.

[0065] In one embodiment, a method for fabricating a non-volatile charge-trapping storage device comprises removing a placeholder gate electrode to form a trench above a substrate having a channel region, a source region, and a drain region, all aligned with the trench. The method also includes forming a dielectric tunnel layer within the trench. Furthermore, the method includes forming a first charge-trapping region and a second charge-trapping region above the dielectric tunnel layer, separated by a gap. Finally, the method includes forming a dielectric isolation layer between the first and second charge-trapping regions. Finally, the method includes forming a dielectric gate layer above the first charge-trapping region, the second charge-trapping region, and the dielectric isolation layer.The process also includes the formation of a gate electrode that is positioned above the dielectric layer.

[0066] In one embodiment, the formation of the dielectric insulating layer further comprises the formation of the dielectric insulating layer above the dielectric tunnel layer.

[0067] In one embodiment, the formation of the dielectric insulating layer further comprises the formation of the dielectric insulating layer between the first and second regions of the dielectric tunnel layer.

[0068] In one embodiment, the formation of the dielectric insulating layer comprises both physical and electrical isolation of the first charge-trapping region from the second charge-trapping region.

[0069] In one embodiment, the formation of the dielectric insulating layer includes the formation of a silicon oxide or silicon dioxide layer.

[0070] In one embodiment, forming the dielectric gate layer includes forming a dielectric high-k material.

[0071] In one embodiment, forming the gate electrode includes forming a metal gate electrode.

Claims

[1] A non-volatile charge trapping storage device (200') comprising: a substrate (208) having a channel region, a source region (204) and a drain region (206); and a gate stack disposed above the substrate (208) over the channel region, wherein the gate stack comprises: a first dielectric tunnel layer region (210') and a second dielectric tunnel layer region (210') disposed above the channel region and separated by a distance; a first charge trapping region (212A') and a second charge trapping region (212B'), wherein the first charge trapping region is disposed above the first dielectric tunnel layer region and the second charge trapping region is disposed above the second dielectric tunnel layer region and are separated by the distance; a dielectric isolation layer (218') disposed above the channel region between the first charge trapping region (212A') and the second charge trapping region (212B') and between the first dielectric tunnel layer region and the second dielectric tunnel layer region; a gate dielectric layer (214) disposed above the first charge trapping region (212A'), the second charge trapping region (212B'), and the dielectric isolation layer (218'); and a gate electrode (216) disposed above the gate dielectric layer (214), wherein a portion of the gate electrode (216) is disposed above a vertical sidewall portion of the first dielectric tunnel layer region and a vertical sidewall portion of the second dielectric tunnel layer region, wherein the first dielectric tunnel layer region (210') further extends along an outer sidewall of the first charge trapping region (212A') and the second dielectric tunnel layer region (210') further extends along an outer sidewall of the second charge trapping region (212B'). [2] The non-volatile charge-trapping memory device (200') of claim 1, wherein the dielectric isolation layer (218') both physically and electrically isolates the first charge-trapping region (212A') from the second charge-trapping region (212B'). [3] The non-volatile charge-trapping memory device (200') of claim 1, wherein the distance between the first charge-trapping region (212A') and the second charge-trapping region (212B') is approximately in the range of 3-20 nanometers. [4] The non-volatile charge-trapping memory device (200) of claim 1, wherein the dielectric insulating layer (218') is made of silicon oxide or silicon dioxide. [5] The non-volatile charge-trapping memory device (200') of claim 1, wherein the gate dielectric layer (214) is made of a high-k dielectric material. [6] The non-volatile charge trapping memory device (200') of claim 1, wherein the gate electrode (216) is a metal gate electrode. [7] The non-volatile charge-trap memory device (200') of claim 1, wherein the non-volatile charge-trap memory device (200') is a SONOS type device. [8] The non-volatile charge-trapping memory device (200') of claim 7, wherein the source region (204), the drain region (206) and the gate electrode (216) are N-type and the SONOS-type device is an N-type SONOS-type device. [9] A method of manufacturing a non-volatile charge trapping storage device (200), the method comprising: removing a placeholder gate electrode to form a trench above a substrate (208) having a channel region (207), a source region (204), and a drain region (206), all self-aligned with the trench; forming a dielectric tunnel layer (210') in the trench; forming a first charge trapping region (212A') and a second charge trapping region (212B') above the tunnel dielectric layer (210') separated by a distance; forming a dielectric insulation layer (218') between the first charge trapping region (212A') and the second charge trapping region (212B'); forming a gate dielectric layer (214) above the first charge trapping region (212A'), the second charge trapping region (212B'), and the dielectric isolation layer (218'); and forming a gate electrode disposed above the gate dielectric layer (214). [10] The method of claim 9, wherein forming the dielectric isolation layer further comprises forming the dielectric isolation layer (218') above the tunnel dielectric layer (210'). [11] The method of claim 9, wherein forming the dielectric isolation layer (218') further comprises forming the dielectric isolation layer (218') between first and second regions of the tunnel dielectric layer. [12] The method of claim 9, wherein forming the dielectric isolation layer (218') comprises both physically and electrically isolating the first charge trapping region (212A') from the second charge trapping region (212B'). [13] The method of claim 9, wherein forming the dielectric insulation layer (218') comprises forming a silicon oxide or silicon dioxide layer. [14] The method of claim 9, wherein forming the gate dielectric layer (214) comprises forming a high-k dielectric material. [15] The method of claim 9, wherein forming the gate electrode (216) comprises forming a metal gate electrode.

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