Memory bus management

Abstract

Method for managing a memory bus (BUS 1; BUS 2), comprising: Receiving (101) multiple memory access instructions addressed to multiple non-volatile memory dies (Die A, Die B; Die C, Die D) connected to the memory bus; Identifying (102) sub-operations required to execute the multiple memory access instructions, wherein execution of a single memory access instruction requires execution of two or more sub-operations; Maintaining an initial list of suboperations required to execute the multiple memory access instructions, wherein the initial list includes unreleased unexecuted suboperations directed to individual dies that are not identified as available, and unexecuted suboperations directed to individual dies that are identified as available and for which a gate switching condition applies; Maintaining a second list of suboperations required to execute the multiple memory access instructions, wherein the second list contains only released unexecuted suboperations directed to individual dies identified as available; Accessing the multiple memory dies via the memory bus by performing (107) only sub-operations from the second list until the second list is empty; Then, if the second list is empty, queries (111) of the multiple non-volatile dies to identify individual non-volatile dies of the multiple non-volatile dies that are available; Moving one or more suboperations from the first list to the second list when one or more available non-volatile memory dies are identified; and Then, resuming access to the multiple non-volatile memory dies via the memory bus by executing only sub-operations from the second list until the second list is empty.

Description

[0001] The present application relates to the functioning of reprogrammable non-volatile memory, such as semiconductor flash memory.

[0002] Semiconductor memory with the ability to store data non-volatilely, particularly in the form of EEPROM and Flash EEPROM, encapsulated as a small form factor card, has become the preferred choice in a wide variety of mobile and handheld devices, especially information technology and consumer electronics products. Unlike RAM (random access memory), which is also semiconductor memory, flash memory is non-volatile and retains its stored data even after power is turned off. Furthermore, unlike ROM (read-only memory), flash memory is rewritable, similar to a disk storage device.

[0003] Flash EEPROM is similar to EEPROM (electrically erasable and programmable read-only memory) in that it is a non-volatile memory that can be erased and into which new data can be written or "programmed." Both use a conductive floating (unconnected) gate in a field-effect transistor structure, positioned over a channel region in a semiconductor substrate between the source and drain regions. A control gate is then placed over the floating gate. The transistor's threshold voltage curve is controlled by the amount of charge retained on the floating gate. That is, for a given value of charge on the floating gate, a corresponding voltage (threshold) must be applied to the control gate before the transistor is "switched on" to allow conduction between its source and drain regions.Flash memory such as Flash EEPROM allows the simultaneous erasure of entire blocks of memory cells.

[0004] The floating gate can hold a range of charges and can therefore be programmed to any threshold voltage value within the threshold voltage window. The size of the threshold voltage window is defined by the device's minimum and maximum thresholds, which in turn correspond to the range of charges that can be programmed onto the floating gate. The threshold window generally depends on the storage device's characteristics, operating conditions, and history. In principle, any distinct, resolvable threshold voltage range within the window can be used to designate a definitive storage state of the cell.

[0005] Non-volatile memory devices are also constructed from memory cells with a dielectric layer for storing charge. Instead of the previously described conductive floating-gate elements, a dielectric layer is used. A dielectric ONO layer extends across the channel between the source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is implemented by separately reading the binary states of the spatially separated charge storage regions in the dielectric.

[0006] Many non-volatile memories are formed along the surface of a substrate (e.g., a silicon substrate) as two-dimensional (2D) or planar memories. Other non-volatile memories are three-dimensional (3D) memories, formed monolithically in one or more physical layers of memory cells with active areas arranged across a substrate.

[0007] German patent application DE 20 2010 017 667 U1 relates to a data storage device and a method for storing data in a data storage device containing a plurality of memory chips. German patent application DE 10 2011 086 098 A1 relates to parallel memory read and write operations in a memory with a serial interface. German patent application DE 11 2009 004 900 T5 relates to the delay of memory operations to reduce read latency in memory arrays. German patent application DE 203 21 101 U1 relates to a storage device and a system that allows an early read operation after one or more write operations. SUMMARY

[0008] According to the invention, methods for managing a memory bus and a non-volatile memory system with the features of the independent claims are provided; dependent claims relate to preferred embodiments.

[0009] In some non-volatile memory systems, two or more memory dies can communicate with a memory controller over a shared bus. Such a bus can become a bottleneck if it is not managed efficiently. In particular, if a memory bus is occupied by polling a die to identify when that die is ready, the memory bus becomes unavailable for other purposes, even if other dies might be ready and could be used. One example of a memory bus management scheme parses received instructions into sub-instructions, each of which then occupies the memory bus for a continuous period (i.e., they have uninterrupted use of the memory bus). The sub-operations are only released for execution when their corresponding dies are ready. Thus, when a sub-operation is released, it can be executed immediately without polling the corresponding die.Queries only occur when there are no more released suboperations to be executed. As long as there are suboperations with corresponding dies identified as ready, the execution of the suboperations continues without delays for queries. Queries only occur when there are no more suboperations with corresponding dies identified as ready, thus preventing execution opportunities from being lost due to queries.

[0010] An example of a method for managing a memory bus includes receiving multiple memory access instructions directed to multiple non-volatile memory dies connected to the memory bus; identifying suboperations required to execute the multiple memory access instructions, wherein execution of a single memory access instruction requires the execution of two or more suboperations; maintaining an initial list of suboperations required to execute the multiple memory access instructions, wherein the initial list includes unreleased, unexecuted suboperations directed to individual dies that are not identified as available, and unexecuted suboperations directed to individual dies that are identified as available and for which a gate-switching condition holds.Maintaining a second list of suboperations required to execute the multiple memory access instructions, wherein the second list contains only released, unexecuted suboperations directed to individual dies identified as available; accessing the multiple memory dies via the memory bus by executing only suboperations from the second list until the second list is empty; thereafter, when the second list is empty, querying the multiple non-volatile memory dies to identify individual non-volatile memory dies of the multiple non-volatile memory dies that are available; moving one or more suboperations from the first list to the second list when one or more available non-volatile memory dies of the multiple non-volatile memory dies are identified;and then resuming access to the multiple non-volatile memory dies via the memory bus by executing only sub-operations from the second list until the second list is empty.

[0011] Queries of the multiple non-volatile memory dies can occur when the second list becomes empty, and no queries can occur if at least one suboperation is in the second list. The operation can alternate between querying and accessing the multiple non-volatile memory dies via the memory bus until all suboperations required to execute the multiple memory access instructions have been completed. Access to the multiple non-volatile memory dies can resume as soon as a new entry is added to the second list. Execution of a single suboperation can be atomic, occupying the memory bus without interruption for a continuous period.The multiple memory access commands can include a move command to copy data from a first physical location to a second physical location. The one or more sub-operations can include one or more read operations from the first location and one or more write operations to the second location. Moving the one or more writes from the first list to the second list can only occur after the one or more read operations are complete. Unexecuted sub-operations can be moved from the first list to the second list according to an order specified by a host for executing the multiple memory access commands.Unexecuted write suboperations relating to memory management data can be moved from the first list to the second list according to an order specified by a memory controller. When moving one or more suboperations from the first list to the second list in response to the identification of one or more available non-volatile memory dies, the move of one or more suboperations from the first list to the second list can be delayed to keep power consumption below a power consumption limit. Suboperations can also be prioritized according to a prioritization scheme when moving one or more suboperations from the first list to the second list in response to the identification of one or more available non-volatile memory dies.The prioritization scheme can prioritize read capture sub-operations over read transfer sub-operations.

[0012] An example of a non-volatile memory system comprises multiple non-volatile memory dies; a memory bus connected to the multiple non-volatile memory dies; an interface designed to receive multiple memory access instructions directed to the multiple non-volatile memory dies; an instruction parser designed to identify suboperations required to execute the multiple memory access instructions, wherein execution of a single memory access instruction requires execution of two or more suboperations; an initial list of suboperations required to execute the multiple memory access instructions, wherein the initial list includes unreleased, unexecuted suboperations;a second list of suboperations required to execute the multiple memory access instructions, wherein the second list contains only released unexecuted suboperations directed to individual non-volatile memory dies identified as available, the multiple non-volatile memory dies being accessed via the memory bus by executing only suboperations from the second list until the second list is empty; a die query unit designed to query the multiple non-volatile memory dies to identify individual non-volatile memory dies of the multiple non-volatile memory dies that are available;and a list update unit designed to update the second list by releasing a suboperation for a single non-volatile memory die in response to the identification of the single non-volatile memory die of the multiple non-volatile memory dies as available.

[0013] The die query unit can be configured to remain inactive whenever there is at least one unexecuted suboperation in the second list. The instruction parser can be configured to identify suboperations that are atomic, such that a single suboperation occupies the memory bus without interruption for a continuous period. The list update unit can move individual unexecuted suboperations directed to individual non-volatile memory dies identified as available by the query unit from the first list to the second list, according to an order specified by a host or a storage controller.The list update unit can be designed to move individual unexecuted suboperations directed to individual non-volatile memory dies identified as available by the query unit from the first list to the second list, such that the number of occupied memory dies does not exceed a maximum number that is less than the total number of memory dies of the multiple memory dies. A single non-volatile memory die of the multiple non-volatile memory dies can be a three-dimensional non-volatile memory die monolithically formed in one or more physical layers of arrays of memory cells with an active region arranged over a silicon substrate.The non-volatile memory system may include: an additional memory bus connected to additional non-volatile memory dies; wherein the first list may contain unexecuted suboperations directed to individual non-volatile memory dies of the multiple non-volatile memory dies and the additional non-volatile memory dies, and the second list may contain only unexecuted suboperations directed to individual non-volatile memory dies of the multiple non-volatile memory dies.

[0014] An example of a method for managing a memory bus includes: receiving multiple memory access instructions directed to multiple non-volatile memory dies connected to the memory bus; identifying suboperations required to execute the multiple memory access instructions, wherein executing a single memory access instruction requires executing two or more suboperations, each suboperation being an atomic operation that occupies the memory bus without interruption for a continuous period of time; maintaining an initial list of unreleased suboperations required to execute the multiple memory access instructions, wherein the initial list includes unexecuted suboperations directed to individual dies not identified as available and unexecuted suboperations directed to dies that already have a released suboperation.Maintaining a second list of released suboperations required to execute the multiple memory access instructions, wherein the second list contains only unexecuted suboperations directed to individual dies identified as available, with a maximum of one unexecuted suboperation per non-volatile die identified as available; accessing the multiple memory dies via the memory bus by executing only released suboperations from the second list until the second list is empty; thereafter, when the second list is determined to be empty, querying the multiple non-volatile dies to identify individual non-volatile dies of the multiple non-volatile dies that are available;When one or more available non-volatile memory dies are identified among the multiple non-volatile memory dies, one or more suboperations are released from the first list to the second list; then, accessing the multiple non-volatile memory dies via the memory bus is resumed by executing only released suboperations from the second list until the second list is empty, with no querying of the multiple non-volatile memory dies occurring from the resumption until the second list is empty; and thereafter, the process alternates between querying and accessing the multiple non-volatile memory dies until all suboperations required to execute the multiple memory access instructions have been performed.

[0015] Releasing one or more sub-operations from the first list to the second list can be performed according to an order specified by a host, a memory controller, and / or a power requirement. A single non-volatile memory die or multiple non-volatile memory dies can be a three-dimensional non-volatile memory die monolithically formed in one or more physical layers of arrays of memory cells with an active region arranged over a silicon substrate.Identifying suboperations can include: identifying a read capture suboperation and a read transfer suboperation for each received read command; identifying a write transfer suboperation and a write status check suboperation for each received write command; and identifying a delete initiation suboperation and a delete status check suboperation for each received delete command. The procedure can also include: receiving multiple no-access commands, where executing a single no-access command involves executing one or more suboperations.

[0016] Various aspects, advantages, features and embodiments are included in the following description of exemplary embodiments, the description being to be understood in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 schematically shows the main hardware components of a storage system. Fig. Figure 2 schematically shows a non-volatile memory cell. Fig. Figure 3 shows the relationship between a source-drain stream I D and the control gate voltage V CG for four different charges Q1-Q4 that a floating gate can store. Fig. Figure 4A schematically shows a chain of memory cells organized into a NAND chain. Fig. Figure 4B shows an example of a NAND array 210 of memory cells, consisting of NAND chains 50 like the one in Fig. 4A is shown. Fig. Figure 5 shows a side of memory cells organized in a NAND configuration, which are captured or programmed in parallel. Fig. Figure 6A-6C shows an example of programming a population of memory cells. Fig. Figure 7 shows an example of a physical structure of a 3-D NAND chain. Fig. Figure 8 shows an example of a physical structure of a U-shaped 3-D NAND chain. Fig. Figure 9 shows an example of a cross-section of a 3-D NAND memory array with U-shaped NAND chains in the yz plane. Fig. Figure 10 shows an example of a cross-section of a 3D NAND memory with straight NAND chains in the yz plane. Fig. Figure 11 shows an example of memory bus management. Fig. Figure 12 shows an example of how commands can be processed. Fig. Figure 13 shows an example of steps in memory bus management. Fig. Figure 14 shows a storage system with two storage buses. DETAILED DESCRIPTION STORAGE SYSTEM

[0017] Semiconductor memory devices include volatile memory devices, such as DRAM (dynamic random access memory) or SRAM (static random access memory); non-volatile memory devices, such as ReRAM (resistive random access memory), EEPROM (electrically erasable programmable read-only memory), flash memory (which can also be considered a subset of EEPROM), FRAM (ferroelectric random access memory), and MRAM (magnetoresistive random access memory); and other semiconductor elements capable of storing information. Each type of memory device can have various configurations. For example, flash memory devices can be configured in either a NAND or a NOR configuration.

[0018] The memory devices can be composed of passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments may include a specific resistance switching memory element, such as an anti-melt compound, phase-change material, etc., and optionally a control element, such as a diode, etc. As another non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a dielectric charge storage material.

[0019] Multiple memory elements can be configured to be cascaded or to allow individual access to each element. As a non-restrictive example, flash memory devices in a NAND configuration (NAND memory) typically contain cascaded memory elements. A NAND memory array can be configured to consist of multiple chains of memory, with each chain comprising multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured to allow individual access to each element, such as a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0020] The semiconductor memory elements located in and / or above a substrate can be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure.

[0021] In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device plane. Typically, in a two-dimensional memory structure, memory elements are arranged in a plane (e.g., in an xz-direction plane) that extends substantially parallel to a major surface of a substrate supporting the memory elements. The substrate can be a wafer over or in which the layer of memory elements is formed, or it can be a support substrate that is attached to the memory elements after they have been formed. As a non-restrictive example, the substrate can include a semiconductor, such as silicon.

[0022] The memory elements can be arranged in a single storage device level in an ordered array, such as in multiple rows and / or columns. However, the memory elements can also be arranged in irregular or non-orthogonal configurations. Each memory element can have two or more electrodes or contact lines, such as bit lines and word lines.

[0023] A three-dimensional storage array is arranged such that storage elements occupy multiple levels or multiple storage device levels to form a structure in three dimensions (i.e. in the x, y and z directions, with the y direction being essentially perpendicular to the main surface of the substrate and the x and z directions being essentially parallel).

[0024] As a non-restrictive example, a three-dimensional memory structure can be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-restrictive example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), with each column containing multiple memory elements. The columns can be arranged in a two-dimensional configuration, e.g., in an xz-plane, resulting in a three-dimensional array of memory elements with elements on multiple vertically stacked memory levels. Other configurations of memory elements in three dimensions can also constitute a three-dimensional memory array.

[0025] As a non-restrictive example, in a three-dimensional NAND memory array, the memory elements can be coupled to form a NAND chain in single horizontal (e.g., xz) memory device levels. Alternatively, the memory elements can be coupled to form a vertical NAND chain that traverses multiple horizontal memory device levels. Other three-dimensional configurations can be considered, where some NAND chains contain memory elements in a single memory level, while other chains contain memory elements that span multiple memory levels. Three-dimensional memory arrays can also be designed in a NOR configuration and in a ReRAM configuration.

[0026] Typically, in a monolithic three-dimensional storage array, one or more storage device layers are formed on top of a single substrate. Optionally, the monolithic three-dimensional storage array may also have one or more storage layers at least partially embedded in the single substrate. As a non-restrictive example, the substrate may be a semiconductor, such as silicon. In a monolithic three-dimensional array, the layers representing each storage device layer of the array are typically formed on top of the layers of the underlying storage device layers of the array. However, layers of adjacent storage device layers of a monolithic three-dimensional storage array may be shared between storage device layers or may include intervening layers.

[0027] Nevertheless, two-dimensional arrays can be formed separately and then encapsulated together to create a non-monolithic storage device with multiple layers of memory. For example, non-monolithic stacked memories can be constructed by forming memory layers on separate substrates and then stacking the memory layers on top of each other. The substrates can be thinned or removed from the memory device layers prior to stacking, but because the memory device layers are initially formed over separate substrates, the resulting memory arrays are non-monolithic three-dimensional memory arrays. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then encapsulated together to create a stacked-chip memory device.

[0028] Associated circuitry is typically required to operate and communicate with memory elements. Non-restrictive examples include circuitry used to control and manage memory elements to perform functions such as programming and reading. This associated circuitry may reside on the same substrate as the memory elements and / or on a separate substrate. For example, a memory read / write controller may reside on a separate controller chip and / or on the same substrate as the memory elements.

[0029] In other embodiments, other types of storage can be used besides the exemplary two-dimensional and three-dimensional structures described here.

[0030] Fig. Figure 1 schematically shows the main hardware components of a storage system suitable for implementing some of the techniques described here. The storage system 90 typically operates with a host 80 via a host interface. The storage system can be in the form of removable storage, such as a memory card, or it can be in the form of an embedded storage system. The storage system 90 comprises a memory 102, the operations of which are controlled by a controller 100. The memory 102 comprises one or more arrays of non-volatile memory cells distributed across one or more integrated circuit chips. The controller 100 can include interface circuits 110, a processor 120, ROM (read-only memory) 122, RAM (random access memory) 130, programmable non-volatile memory 124, and additional components.The controller is typically implemented as an ASIC (application-specific integrated circuit), and the components included in such an ASIC generally depend on the specific application. Storage systems can be used with a wide variety of hosts in a wide variety of environments. For example, a host might be a mobile device such as a mobile phone, laptop, music player (e.g., MP3 player), GPS (Global Positioning System) device, tablet computer, or the like. Such storage systems may be inactive and without power for extended periods and may be subject to various conditions, such as high temperatures, vibration, electromagnetic fields, etc. Storage systems for such hosts, whether removable or embedded, can be designed for low power consumption, high data retention, and reliability in a wide range of environmental conditions (e.g.,(a wide temperature range) can be selected. Other hosts can be stationary. Servers used for internet applications, for example, can use non-volatile storage systems to store data sent and received over the internet. Such systems can remain powered on without interruption for long periods (e.g., a year or more), and can be accessed frequently during such periods. Individual blocks can be written to and erased frequently, so uptime can be a significant issue. Physical storage structure

[0031] Fig. Figure 2 schematically shows a non-volatile memory cell. The memory cell 10 can be implemented by a field-effect transistor having a charge storage unit 20, such as a floating gate or a (dielectric) charge trap layer. The memory cell 10 also includes a source terminal 14, a drain terminal 16, and a control gate 30.

[0032] Many commercially successful non-volatile semiconductor storage devices are in use today. These storage devices can use different types of memory cells, each type having one or more charge storage elements.

[0033] In practice, the stored state of a cell is usually read by measuring the conduction current across the cell's source and drain electrodes when a reference voltage is applied to the control gate. For any given charge at the cell's floating gate, a corresponding conduction current can thus be detected relative to a fixed reference control gate voltage. Similarly, the charge range programmable on the floating gate defines a corresponding threshold voltage window or conduction current window.

[0034] Instead of detecting the power current under a partitioned current window, an alternative approach is to set the threshold voltage for a given tested memory state at the control gate and detect whether the line current is less than or greater than a threshold current (cell-read reference current). In one implementation, the detection of the line current relative to a threshold current is achieved by examining the rate at which the line current discharges through the capacitance of the bit line.

[0035] Fig. Figure 3 shows the relationship between the source-drain current I D and the control gate voltage V CG for four different charges Q1-Q4, which the floating gate can selectively store at any given time. With a fixed drain bias, the four solid curves of I represent D as a function of V CGFour of the seven possible charge levels that can be programmed onto a floating gate of a memory cell, each corresponding to four possible memory states. For example, the threshold voltage window of a population of cells can range from 0.5 V to 3.5 V. Seven possible programmed memory states "0", "1", "2", "3", "4", "5", "6", and one (not shown) erased state can be defined by partitioning the threshold window into regions at intervals of 0.5 V each. For example, if a reference current IREF of 2 µA is used as shown, the cell programmed with Q1 can be considered to be in a memory state "1" because its curve lies within a region of the threshold window delimited by VCG = 0.5 V and 1.0 V, where I REF It cuts. Similarly, Q4 is in a memory state of "5".

[0036] As can be seen from the description above, the more states a memory cell is forced to store, the finer its threshold voltage window becomes. For example, a memory device might have memory cells with a threshold voltage window ranging from -1.5 V to 5 V. This provides a maximum width of 6.5 V. If the memory cell is to store 16 states, each state within the threshold window could range from 200 mV to 300 mV. This necessitates higher accuracy in programming and read operations to achieve the required resolution. NAND structure

[0037] Fig. Figure 4A schematically shows a chain of memory cells organized into a NAND chain. A NAND chain 50 comprises a series of storage transistors M1, M2, ... Mn (e.g., n = 4, 8, 16 or higher) connected via their source and drain terminals. Two selection transistors S1 and S2 control the connection of the storage transistor chain to the outside world via the source terminal 54 and drain terminal 56 of the NAND chain, respectively. In a memory array, when the source selection transistor S1 is switched on, the source terminal is coupled to a source line (see Figure 4A). Fig. 4B). Similarly, when the drain selection transistor S2 is switched on, the drain terminal of the NAND chain is coupled to a bit line of the memory array. Each storage transistor 10 in the chain acts as a memory cell. It has a charge storage element 20 to store a given amount of charge to represent an intended memory state. A control gate 30 of each storage transistor allows control over read and write operations. As in Fig. As can be seen in Figure 4B, the control gates 30 of the corresponding storage transistors of a row of NAND flash memory are all connected to the same word line. Similarly, a control gate 32 of each select transistor S1, S2 ensures control access to the NAND flash memory via its source terminal 54 or drain terminal 56, respectively. Similarly, the control gates 32 of the corresponding select transistors of a row of NAND flash memory are all connected to the same select line.

[0038] When an addressed storage transistor 10 in a NAND chain is read or verified during programming, a corresponding voltage is applied to its control gate 30. Simultaneously, the remaining unaddressed storage transistors in the NAND chain 50 are fully switched on by applying sufficient voltage to their control gates. In this way, a conductive path is effectively created from the source terminal of the individual storage transistor to the source terminal 54 of the NAND chain, and similarly for the drain terminal of the individual storage transistor to the drain terminal 56 of the cell.

[0039] Fig. Figure 4B shows an example of a NAND array 210 of memory cells formed from NAND chains 50, such as the one in Fig. As shown in Figure 4A. Along each column of NAND chains, a bit line, such as bit line 36, is coupled to the drain terminal 56 of each NAND chain. Along each bank of NAND chains, a source line, such as source line 34, is coupled to the source terminals 54 of each NAND chain. Additionally, the control gates along a row of memory cells in a bank of NAND chains are connected to a word line, such as word line 42. The control gates along a row of select transistors in a bank of NAND chains are connected to a select line, such as select line 44. By applying suitable voltages to the word lines and select lines of the bank of NAND chains, an entire row of memory cells in a bank of NAND chains can be addressed.

[0040] Fig. Figure 5 shows a page of memory cells, organized in NAND configuration, which are captured or programmed in parallel. Fig. Figure 5 essentially shows a bank of NAND chains 50 in the memory array 210 of Fig. 4B, while the details of each NAND chain are explicitly described as in Fig. Figure 4A shows that a physical page, such as page 60, is a group of memory cells that can be read or programmed in parallel. This is achieved by a corresponding page of read amplifiers 212. The read results are temporarily stored in a corresponding set of latches 214. Each read amplifier can be coupled to a NAND chain via a bit line. The page is released by the control gates of the cells of the page, which are connected together by a word line 42, and each cell is accessible by a read amplifier via a bit line 36. For example, when reading or programming the page of cells 60, a read voltage or a programming voltage is applied to the common word line WL3 together with appropriate voltages on the bit lines. Physical organization of the storage

[0041] One difference between flash memory and other types of memory is that a flash memory cell is generally programmed from a cleared state. That is, the floating gate is generally first cleared of charge. Programming then adds a desired amount of charge back to the floating gate. Flash memory generally does not support removing part of the charge from the floating gate to transition from a more programmed state to a less programmed state. This means that updated data cannot overwrite existing data and is instead written to a previously blank location.

[0042] Furthermore, erasure is intended to empty all charges from the floating gate and generally takes a considerable amount of time. For this reason, erasing cell by cell or even page by page is cumbersome and very slow. In practice, the array of memory cells is divided into a large number of blocks of memory cells. As is common with flash EEPROM systems, the block is the unit of erasure. That is, each block contains the minimum number of memory cells that are erased together. Although aggregating a large number of cells into a block to be erased in parallel will improve erasure efficiency, a large block also means having to deal with a greater amount of update and outdated data.

[0043] Each block is typically divided into a number of physical pages. A logical page is a unit of programming or reading that contains a number of bits equal to the number of cells in a physical page. In a memory that stores one bit per cell (a single-level cell, or SLC, memory), a physical page stores one logical page of data. In memories that store two bits per cell, a physical page stores two logical pages. The number of logical pages stored in a physical page thus reflects the number of bits stored per cell. The term multi-level cell, or "MLC," generally refers to memories that store more than one bit per cell, including memories that store three bits per cell (TLC), four bits per cell, or more bits per cell.In one embodiment, the individual pages can be divided into segments, and the segments can contain the smallest number of cells that can be written at once as a basic programming operation. Typically, one or more logical pages of data are stored in a row of memory cells. A page can store one or more sectors. A sector includes user data and overhead data. MLC programming

[0044] Fig. Figures 6A - 6C show an example of programming a population of 4-state memory cells. Fig. Figure 6A shows the population of memory cells that can be programmed into four distinct distributions of threshold voltages, each representing memory states “E”, “A”, “B” and “C”. Fig. Figure 6B shows the initial distribution of "erased" threshold voltages for an erased memory. Fig. Figure 6C shows an example of the memory after many of the memory cells have been programmed. Essentially, a cell initially has a "cleared" threshold voltage, and programming shifts it to a higher value into one of three zones, delimited by the verification levels vV1, vV2, and vV3. In this way, each memory cell can be programmed to one of the three programmed states "A," "B," and "C," or remain unprogrammed in the "cleared" state. As the memory receives more programming, the initial distribution of the "cleared" states changes as shown in Figure 6C. Fig. 6B is shown narrower, and the deleted state is represented by the "0" state.

[0045] Each of the four memory states can be represented using a 2-bit code, which has a lower bit and an upper bit. For example, the states "E", "A", "B", and "C" are represented by "11", "01", "00", and "10", respectively. The 2-bit data can be read from memory by acquiring it in "full sequence" mode, where the two bits are acquired together by acquiring them in three partial passes relative to the read thresholds rV1, rV2, and rV3. 3-D NAND structure

[0046] An alternative to a conventional two-dimensional (2D) NAND array is a three-dimensional (3D) array. Unlike 2D NAND arrays, which are formed along the planar surface of a semiconductor wafer, 3D arrays extend upwards from the wafer surface and generally comprise stacks or columns of memory cells. Several 3D configurations are possible. In one configuration, a NAND chain is formed vertically with one end (e.g., source) at the wafer surface and the other end (e.g., drain) at the top. In another configuration, a NAND chain is formed in a U-shape, so that both ends of the NAND chain are accessible at the top, thus allowing connections between such chains.

[0047] Fig. Figure 7 shows a first example of a NAND flash memory 701 extending vertically in the z-direction, perpendicular to the xy-plane of the substrate. Memory cells are formed where a vertical bit line (local bit line) 703 passes through a word line (e.g., WL0, WL1, etc.). A charge-trap layer between the local bit line and the word line stores charge, which affects the threshold voltage of the transistor formed by the word line (gate) coupled to the vertical bit line (channel) it encircles. Such memory cells can be formed by stacking word lines and then etching memory holes where memory cells are to be created. Memory holes are then lined with a charge-trap layer and filled with a suitable local bit line / channel material (with appropriate dielectric layers for insulation).

[0048] As with planar NAND chains, selection gates 705 and 707 are located at each end of the chain to allow selective connection to, or isolation from, external elements 709 and 711 of the NAND chain. Such external elements are generally conductive lines, such as common source lines or bit lines, that supply large numbers of NAND chains. Vertical NAND chains can be operated similarly to planar NAND chains, and both SLC (single-level cell) and MLC (multi-level cell) operation are possible. Fig. Figure 7 shows an example of a NAND chain with 32 (0-31) cells connected in series; the number of cells in a NAND chain can be any suitable number. For clarity, not all cells are shown. It is understood that additional cells are formed where word lines 3-29 (not shown) intersect the local vertical bit line.

[0049] Fig. Figure 8 shows a second example of an 815 NAND flash memory extending in the vertical (z-direction). In this case, the 815 NAND flash memory forms a U-shape for connection to external elements (source line "SL" and bit line "BL") located on the upper part of the structure. At the lower part of the 815 NAND flash memory is a controllable gate (back gate "BG") that connects the two wings 816A and 816B of the 815 NAND flash memory. This creates a total of 64 cells where word lines WL0–WL63 intersect with the vertical local bit line 817 (although other numbers of cells may be provided in other examples). The select gates SGS and SGD are located at each end of the 815 NAND flash memory to control the connection / isolation of the 815 NAND flash memory.

[0050] Vertical NAND chains can be arranged in various ways to form a 3D NAND array. Fig. Figure 9 shows an example where several U-shaped NAND flash memory arrays are connected in a block by a bit line. In this case, there are n flash memory arrays (flash 1 - flash n) in a block connected by a bit line (“BL”). The value of “n” can be any suitable number, for example, 8, 12, 16, 32, or more. The orientation of the flash memory arrays, with the source connection of odd-numbered flash memory arrays on the left and the source connection of even-numbered flash memory arrays on the right. This arrangement is convenient but not essential, and other patterns are possible.

[0051] Common source lines (SL) are connected to one end of each NAND chain (opposite the end connected to the bit line). This can be considered the source end of the NAND chain, with the bit line end being considered the drain end. Multiple common source lines can be connected so that all source lines for a block can be controlled together by a single peripheral circuit. Thus, the NAND chains of a block extend in parallel between the bit lines at one end and the common source lines at the other.

[0052] Fig. Figure 10 shows a memory structure in which straight vertical NAND chains extend from common source connections in or near a substrate to global bit lines (BL0–BL3) that span the physical layers of memory cells. Word lines in a given physical layer within a block are formed from a layer of conductive material. Down through these conductive layers, memory hole structures extend to form memory cells. Within a given block, there are multiple NAND chains connected to a given bit line. NAND chains are grouped into sets of chains that share a common selection gate. For example, NAND chains selected by SGS0 and SGD0 can thus be considered a single set and referred to as chain 0, while NAND chains selected by SGS1 and SGD1 can be considered a single set and referred to as chain 1, as shown.A block can consist of any number of such sets of chains. It is understood that the cross-section of . Fig. The 10 parts of BL0 - BL3 show that these bit lines extend further in the y-direction. Furthermore, additional bit lines extend parallel to BL0 - BL3 (e.g., at various locations on the x-axis before or after the point of the cross-section). Fig. 10) Other three-dimensional storage devices are not based on charge storage elements, but on resistive elements. memory bus

[0053] In some non-volatile memory systems, two or more non-volatile memory dies can be connected to a memory bus. For example, four, eight, or more NAND flash memory dies can be connected to a NAND controller via a memory bus. Such a multi-die bus can be used with any form of non-volatile memory, including planar, 3D, charge storage memory (such as flash), resistive memory (such as ReRAM), and other forms of memory. In some cases, a memory controller can manage more than one memory bus, and each such memory bus can supply multiple non-volatile memory dies.

[0054] Although using a memory bus to communicate with multiple memory dies over a shared communication channel can provide significant savings compared to using dedicated communication channels for each memory die, a memory bus can become a bottleneck, reducing storage system performance in some situations. For example, in some scenarios, the execution of a memory access command (read, write, or erase) may be delayed because the memory bus is occupied.

[0055] An example of a task that can occupy a memory bus and prevent other tasks from executing is querying memory dies to identify when a memory die becomes available (ready). In some cases, a storage system may query a specific die while waiting for that die to become available because there is another task to be performed using that die. For example, if a die is occupied (unavailable) because it is writing data, the storage system may wait for the die to become ready to send more data to it. During the query, there may be one or more other dies on the memory bus that are available to write more data. However, data is not transferred to these dies because the memory bus is occupied with the query operation.

[0056] An alternative to querying individual dies is to link blocks of multiple dies into metablocks, which are then operated together in parallel. This allows all dies on a given memory bus to become available essentially at the same time (or at least in a predictable sequence), so that little or no time is spent querying one die while other dies are ready.

[0057] Another alternative is to use one or more timers to estimate when a die will be ready. When a die begins a specific task, such as writing the first part of data (e.g., a page), a timer can be initiated for that die. No queries can be executed until the timer indicates that the write has likely finished (e.g., based on a comparison of elapsed time with a certain previous write time). This minimizes time wasted on queries. However, such a system can be relatively complex because it requires multiple timers and tracking average times for different tasks across multiple dies (or smaller units, such as blocks), and may involve updating these times as memory ages. Such an estimate can be inaccurate.There may be cases where the estimated time is too short, causing queries to begin significantly before a die is ready, thus wasting time on queries. In other cases, the estimated time is too long, unnecessarily delaying queries and leaving the die idle.

[0058] An efficient scheme for managing a memory bus is described in Fig. Figure 11 illustrates this. Commands are received, for example, from a host via a host interface (Figure 101). Commands can also originate from a memory controller (e.g., commands relating to internal operations such as garbage collection, updating memory management data, or block reclaiming). Suboperations are then identified (Figure 103).

[0059] Identifying suboperations can involve parsing individual instructions into suboperations that are executed when the instruction is run. Suboperations can be tasks that occupy the memory bus and can be executed as atomic operations without interruption. Suboperations should generally be relatively short and should not unnecessarily combine tasks that can be performed more efficiently as separate suboperations. For example, it would be inefficient to consider a read capture and a read transfer as a single suboperation because the memory bus would have to be idle during the memory capture portion of the suboperation. Writing to multi-level cell or "MLC" memory cells (e.g., three-level cells or "TLC") can be considered multiple suboperations, so that between such suboperations within a die, the memory bus can be used for other purposes (i.e., other dies can be accessed).Memory access commands such as read, write, and erase generally require at least two such suboperations. For example, a read command may require at least one read capture suboperation to transfer physical address information into a memory die and initiate capture of the addressed cells, and at least one read transfer to transfer the captured data from the die over the memory bus. Reading multiple logical pages from a single physical page and reading multiple dies can require many such suboperations. A write command may require at least one write transfer suboperation to transfer data and address information to a destination die over the memory bus, and at least one status check to determine whether the write was successful.A delete command may require at least one first suboperation to identify a block to be deleted and initiate the deletion, and at least one second suboperation to verify that the deletion was successful. In some cases, a command may consist of only a single suboperation. For example, a command to modify NAND parameters (e.g., to change parameters associated with reading, writing, and / or deleting a block, level, or die) may require only a single suboperation to transfer the new NAND parameters.

[0060] Suboperations are released (made available for execution) in a manner that ensures efficient use of the memory bus. Suboperations are generally scheduled for execution in the order in which they receive corresponding instructions. In some cases, some reordering may occur. Suboperations are released only when a corresponding die is available. In some cases, only one suboperation is released for a given die, so the list of released suboperations may be one suboperation deep. In some cases, more than one suboperation may be released for a die at a time, allowing two suboperations to be executed efficiently in succession. For example, a read-transfer suboperation for previously acquired data may be released with a read-acquire suboperation for the next data to be read from the same die.The release of sub-operations may be subject to gate switching conditions, so that in some cases a sub-operation cannot be released immediately if a corresponding die is available.

[0061] In some cases, queries can indicate that a die is ready, and a corresponding suboperation is immediately released and executed. In other cases, the release of a corresponding suboperation is not immediate but is instead delayed due to a gate-switching condition. For example, to keep power consumption below a certain limit, the release of a suboperation can be delayed until another suboperation has finished. For instance, a memory bus might have eight memory dies, but power consumption might limit the number of dies performing a write operation to, say, six. Thus, if six dies are already performing write suboperations when another die becomes ready, releasing the newly ready die could cause seven dies to perform write operations concurrently.In this situation, releasing the suboperation could be delayed until another die has finished writing. Power consumed during read, erase, and other operations can also be considered when deciding whether to delay release. For example, an erase might be performed on one or more dies while read operations are performed on other dies and write operations on yet others. The total current power consumption can be tracked and used to determine the difference between the current power consumption and the power consumption limit. If the additional power consumption caused by releasing another suboperation is within the power consumption limit, the suboperation can be released. If the additional power consumption is outside the limit, release can be delayed.The type of suboperation can be taken into account, as different suboperations result in different power consumption. Thus, a read / capture suboperation could be enabled immediately, whereas an erase / initiate suboperation, which initiates an erase and requires more power than writing, could not be enabled immediately. Therefore, various gate switching conditions can be applied to determine whether a particular suboperation should be enabled.

[0062] Releasing a suboperation transfers the suboperation to another list for execution. Fig. Figure 11 shows upper steps 101-105 regarding suboperation release and lower steps 107-113 regarding suboperation execution. These two operations can largely run independently and can be asynchronous. Only released suboperations are executed (Figure 107). While released suboperations are executing, no queries can be performed. In some cases, there can be exceptions; for example, a multilevel MLC write can be considered a single suboperation rather than multiple atomic suboperations. In this case, some queries can be performed within the multilevel write to determine when the next page can be transferred. For example, after transferring lower-level page data across two levels, queries can be used to determine when the lower-level page data is written and the die is ready to receive middle-level page data.When a suboperation completes and the memory bus becomes available, the system determines whether the list of released suboperations is empty. If at least one suboperation remains in the list, execution continues. If the list of released suboperations is empty, the memory dies are queried to identify any ready dies. Queries are thus performed only when there are no more suboperations that can be executed immediately (i.e., suboperations for dies that are known to be ready). No querying occurs as long as at least one suboperation remains in the list, so suboperation execution continues until the list is empty. Queries can be limited to dies that are active (i.e., querying inactive dies may be unnecessary). If all dies are inactive, no querying can be performed.If no sub-operations need to be executed, the system can enter a low-power state without executing sub-operations or querying dies. Execution and querying can then resume when a new command is received. If queries indicate that one or more dies are ready (113), this information is passed for use in identifying sub-operations for release (dashed line), and the corresponding sub-operations are released (105) and executed (107). Generally, querying and release, and execution, end as soon as a ready die is identified, so querying does not continue for an extended period. For example, the next sub-operation can be released for all dies identified as ready.When query 113 ends, the list of released suboperations is checked 109 to determine if any newly released suboperations exist, and if so, to execute them 103. It is evident that this scheme alternates between executing suboperations (during which no query occurs) when the list is not empty, and querying the list, which only occurs when the list becomes empty.

[0063] The release of suboperations can also be triggered by events other than queries, such as releasing a suboperation that was held up because a gate condition was in effect. For example, if a suboperation is held up due to a power consumption limit, the suboperation can always be released when the power consumption decreases to a value that allows the suboperation to execute without exceeding the power consumption limit (i.e., when the gate condition is no longer in effect, the suboperation can be released without additional querying). In some cases, a "virtually occupied" condition can be used to specify that a die that sets a ready signal should not be treated as ready (i.e., no suboperation should be released for such a die).Thus, gate switching conditions can be implemented by setting a virtual occupied condition, which is then released when the gate switching conditions are met. For example, a virtual occupied condition can be used during read data transfers when a die sets a ready signal to manage the release of subsequent sub-operations.

[0064] In some cases, there may be two or more suboperations that can be released from the list of unreleased suboperations because their dies are ready. The order in which such suboperations are released and executed can be determined according to a prioritization scheme, which may be based on performance optimization rules. For example, if a read capture suboperation is ready to be released to one die while a read transfer suboperation is ready to be released to another die, the read capture would generally be released first. This allows the capture operation to proceed in parallel with the read transfer operation. A prioritization scheme may include delaying and / or ordering suboperations based on power requirements, as discussed above. In some cases, a host or controller may specify a particular order for release and / or execution.Data read from memory can be returned to a host in a specific order (e.g., in logical address order). To facilitate this, read / acquire and read / transfer suboperations can also be ordered by logical address. In some cases, a memory controller may perform an operation that requires a specific order. For example, moving data from one block to another (e.g., during garbage collection) may require read / acquire suboperations to be performed on all dies before any write suboperations are executed.

[0065] Fig. Figure 12 shows an example of instruction handling that ensures efficient memory bus utilization. Instructions to be executed are received and can be queued 221 (e.g., in the order in which they were received). An instruction parser 223 identifies suboperations corresponding to the instructions. The identified suboperations are placed in a pool of pending (unreleased) suboperations 225. A release controller 227 then releases suboperations only to dies that are determined to be ready, subject to any gate switching conditions that may apply. Released suboperations are held in a queue 229. Suboperations are executed by the memory bus controller, with each such suboperation occupying the memory bus for an uninterrupted period.If there are no more released sub-operations in queue 229, the memory bus controller 231 queries the dies to identify any available dies and identifies available dies to the release controller 227, which can then release further sub-operations into queue 229 so that the memory bus controller 231 can return to executing sub-operations.

[0066] The functionality of a memory bus controller (e.g., the memory bus controller 231) is described in Fig. Figure 13 shows that it is determined whether there is a released suboperation in the queue of released suboperations. If there are no suboperations in the queue, the next suboperation in the queue is executed. If no released suboperations remain in the queue, these are queried to identify ready ones. If there are ready ones, the memory bus controller informs the release controller so that the corresponding suboperations can be released.

[0067] In some storage systems, a single storage controller can manage more than one storage bus. Fig. Figure 14 shows an example of a Memory System 451 that manages two memory buses, Bus 1 and Bus 2. Bus 1 supplies dies A and dies B, while Bus 2 supplies dies C and dies D. In this example, all dies span two levels (Level 0 and Level 1). It is understood that various other configurations can be implemented. For example, each bus can have more than two dies (e.g., four, eight, sixteen, or more dies), and a controller can have more than two buses.

[0068] The memory controller 453 includes a host interface 455, which receives host commands via a communication channel 457. Additional commands can be generated in the memory controller 453. Commands (from a host or elsewhere) are sent to a command analyzer 459, which analyzes commands into constituent sub-operations. The sub-operations are placed in a queue of unreleased sub-commands 461. A release controller 463 releases sub-commands from the queue of unreleased sub-commands 461 and releases them to an appropriate queue of released sub-commands, either a queue 465 of released sub-commands for bus 1 or a queue 467 of released sub-commands for bus 2. Thus, bus 1 and bus 2 share a queue 461 of unreleased sub-commands, while each bus has its own queue of released sub-commands: queue 465 for bus 1 and queue 467 for bus 2.Each bus can thus operate separately based on its queue of released suboperations. A query circuit 469 is provided to query the This of a given bus whenever the queue of released suboperations for that bus is empty. Although a single query circuit is shown, separate query circuits can be provided for each bus, so that each bus has its own dedicated query circuit. Although... Fig. 14. Where the memory controller 453 is presented as specific circuits, it is understood that additional circuits may be provided in the memory controller. It is also understood that circuits in such a memory controller may be provided as dedicated circuits, programmable logic circuits, or general-purpose physical circuits that are configured by software. The in Fig.The 14 components shown are therefore not necessarily physically separate circuits, but can be functional parts of a memory controller configured by controller firmware for specific purposes. In some cases, a combination of dedicated circuits and software-configurable circuits within an ASIC (application-specific integrated circuit) can form such a memory controller. Concluding remarks

[0069] The above detailed description is for illustrative and descriptive purposes only. It is not intended to be exhaustive or to limit the attached claims. Many modifications and variations of the above teachings are possible.

Claims

[1] Method for managing a memory bus (BUS 1; BUS 2), comprising: Receiving (101) multiple memory access instructions addressed to multiple non-volatile memory dies (Die A, Die B; Die C, Die D) connected to the memory bus; Identifying (102) sub-operations required to execute the multiple memory access instructions, wherein execution of a single memory access instruction requires execution of two or more sub-operations; Maintaining an initial list of suboperations required to execute the multiple memory access instructions, wherein the initial list includes unreleased unexecuted suboperations directed to individual dies that are not identified as available, and unexecuted suboperations directed to individual dies that are identified as available and for which a gate switching condition applies; Maintaining a second list of suboperations required to execute the multiple memory access instructions, wherein the second list contains only released unexecuted suboperations directed to individual dies identified as available; Accessing the multiple memory dies via the memory bus by performing (107) only sub-operations from the second list until the second list is empty; Then, if the second list is empty, queries (111) of the multiple non-volatile dies to identify individual non-volatile dies of the multiple non-volatile dies that are available; Moving one or more suboperations from the first list to the second list when one or more available non-volatile memory dies are identified; and Then, resuming access to the multiple non-volatile memory dies via the memory bus by executing only sub-operations from the second list until the second list is empty. [2] Method according to claim 1, wherein queries (111) of the multiple non-volatile memory dies occur in response to the second list becoming empty and no querying occurs if there is at least one suboperation in the second list. [3] The method of claim 2, further comprising switching between querying the multiple non-volatile memory dies and accessing the multiple non-volatile memory dies via the memory bus until all sub-operations required to execute the multiple memory access instructions have been performed. [4] Method according to claim 1, wherein resuming access to the multiple non-volatile memory dies occurs as soon as a new entry is added to the second list. [5] Method according to claim 1, wherein execution of a single suboperation is an atomic execution that occupies the memory bus without interruption for a continuous period of time. [6] Method according to claim 1, wherein the multiple memory access instructions comprise a relocation instruction for copying data from a first physical location to a second physical location, and wherein the one or more sub-operations comprise one or more read operations from the first location and one or more write operations to the second location, and wherein the relocation of the one or more write operations from the first list to the second list only occurs when the one or more read operations have been completed. [7] Method according to claim 1, wherein unexecuted sub-operations are moved from the first list to the second list according to a sequence for executing sub-operations in accordance with a sequence specified by a host (80) for executing the multiple memory access instructions. [8] Method according to claim 1, wherein unexecuted write sub-operations with respect to memory management data are moved from the first list to the second list according to a sequence specified by a memory controller (100, 453). [9] The method of claim 1, further comprising, when moving one or more sub-operations from the first list to the second list in response to identifying one or more available non-volatile memory dies of the multiple non-volatile memory dies, delaying the movement of one or more sub-operations from the first list to the second list in order to keep a power consumption value below a power consumption limit. [10] The method of claim 1, further comprising prioritizing suboperations according to a prioritization scheme when moving one or more suboperations from the first list to the second list in response to the identification of one or more available non-volatile memory dies of the multiple non-volatile memory dies. [11] Method according to claim 10, wherein the prioritization scheme prioritizes read capture sub-operations over read transfer sub-operations. [12] Non-volatile storage system, comprising: several non-volatile memory dies (Die A, Die B; Die C, Die D); a memory bus (BUS 1; BUS 2) connected to the multiple non-volatile memory dies; an interface (110, 455) designed to receive (101) multiple memory access commands directed to the multiple non-volatile memory dies; an instruction analysis unit (459) designed to identify (103) sub-operations required for the execution of the multiple memory access instructions, wherein the execution of a single memory access instruction requires the execution of two or more sub-operations; a first list of suboperations required to execute the multiple memory access instructions, wherein the first list contains unreleased, unexecuted suboperations; a second list of sub-operations required to execute the multiple memory access instructions, wherein the second list contains only released unexecuted sub-operations directed to individual non-volatile memory dies identified as available, wherein the multiple non-volatile memory dies are accessed via the memory bus by executing only sub-operations from the second list until the second list is empty; a die query unit (469) designed to query (111) the multiple non-volatile memory dies to identify individual non-volatile memory dies of the multiple non-volatile memory dies that are available; and A list update unit designed to update the second list by releasing a suboperation for a single non-volatile memory die in response to the identification of the single non-volatile memory die of the multiple non-volatile memory dies as available. [13] Non-volatile memory system according to claim 12, wherein the die query unit (469) is designed to remain inactive whenever there is at least one unexecuted suboperation in the second list. [14] Non-volatile memory system according to claim 12, wherein the instruction analysis unit (459) is designed to identify sub-operations that are atomic, such that a single sub-operation occupies the memory bus without interruption for a continuous period of time. [15] Non-volatile memory system (451) according to claim 12, wherein the list update unit moves individual unexecuted sub-operations directed to individual non-volatile memory dies identified as available by the query unit (469) from the first list to the second list according to an order specified by a host (80) or by a memory controller (100, 453). [16] Non-volatile memory system according to claim 12, wherein the list update unit is designed to move individual unexecuted sub-operations directed to individual non-volatile memory dies identified as available by the query unit (469) from the first list to the second list in such a way that the number of occupied memory dies does not exceed a maximum number that is less than the total number of memory dies of the multiple memory dies. [17] Non-volatile memory system according to claim 12, wherein a single non-volatile memory die of the multiple non-volatile memory dies is a three-dimensional non-volatile memory die formed monolithically in one or more physical layers (layer 0, layer 1) of arrays of memory cells with an active area arranged over a silicon substrate. [18] Non-volatile storage system according to claim 12, further comprising: an additional memory bus connected to additional non-volatile memory dies; wherein the first list contains unexecuted suboperations directed to individual non-volatile memory dies of the multiple non-volatile memory dies and the additional non-volatile memory dies, and the second list contains only unexecuted suboperations directed to individual non-volatile memory dies of the multiple non-volatile memory dies. [19] Method for managing a memory bus, comprising: Receiving (101) multiple memory access instructions directed to multiple non-volatile memory dies connected to the memory bus; Identifying (103) sub-operations required to execute the multiple memory access instructions, wherein execution of a single memory access instruction requires execution of two or more sub-operations, each sub-operation being an atomic operation that occupies the memory bus without interruption for a continuous period of time; Maintaining an initial list of unshared suboperations required to execute the multiple memory access instructions, wherein the initial list includes unexecuted suboperations directed to individual dies that are not identified as available and unexecuted suboperations directed to dies that already have a shared suboperation; Maintaining a second list of released suboperations required to execute the multiple memory access instructions, wherein the second list contains only unexecuted suboperations directed to individual dies identified as available, with a maximum of one unexecuted suboperation per non-volatile memory die identified as available; Accessing the multiple memory dies via the memory bus by executing (107) only allowed suboperations from the second list until the second list is empty; Then, if the second list is determined to be empty, queries (111) of the multiple non-volatile dies are performed to identify individual non-volatile dies of the multiple non-volatile dies that are available; If one or more available non-volatile memory dies are identified among the multiple non-volatile memory dies, release one or more suboperations from the first list to the second list; then resuming access to the multiple non-volatile memory dies via the memory bus by executing only released suboperations from the second list until the second list is empty, whereby from the resumption until the second list is empty, no querying of the multiple non-volatile memory dies occurs; and Then, switching between querying and accessing the multiple non-volatile memory dies until all sub-operations required to execute the multiple memory access instructions have been performed. [20] Method according to claim 19, wherein the release of one or more sub-operations from the first list to the second list is performed according to a sequence specified by a host (80) and / or a sequence specified by a storage controller (100, 453) and / or a power request. [21] Method according to claim 19, wherein a single non-volatile memory die of the multiple non-volatile memory dies is a three-dimensional non-volatile memory die formed monolithically in one or more physical layers (layer 0, layer 1) of arrays of memory cells with an active region arranged over a silicon substrate. [22] Method according to claim 19, wherein identifying (103) sub-operations comprises: Identify a read capture sub-operation and a read transfer sub-operation for each received read command; Identifying a write transfer suboperation and a write status check suboperation for each received write command; and Identify a delete initiation sub-operation and a delete status check sub-operation for each received delete command. [23] The method of claim 22, further comprising: Receiving multiple no-access commands, where the execution of a single no-access command includes the execution of one or more sub-operations.

Images