Switching element driver circuit

Abstract

Switching element driver circuit (1) which controls a main switching element (TR) by providing a control terminal of the main switching element (TR) with a driver signal (SP) having asymmetric positive and negative potentials with respect to a reference potential (Vref), wherein the main switching element (TR) has a ground terminal which is a source terminal or an emitter terminal and to which the reference potential (Vref) is connected, wherein the switching element driver circuit (1) comprises: a power source circuit comprising a positive and negative bipolar power source, and a positive power source providing a positive potential that is positive with respect to the reference potential (Vref), and a negative power source providing a negative potential that is negative with respect to the reference potential (Vref) and whose absolute value differs from an absolute value of the positive potential, wherein the positive and negative potentials are asymmetric with respect to the reference potential (Vref); an inductor, one terminal of which is connected to a control terminal side and the other terminal of which is connected to a reference potential (Vref) side; a first current path (41) in which a first rectification element (D1), whose forward direction is from the control terminal side to the reference potential (Vref) side, and a first switch (S1) are connected in series; and a second current path (42) in which a second rectification element (D2), whose forward direction is a direction from the reference potential (Vref) side to the control terminal side, and a second switch (S2) are connected in series, wherein: a resonance control circuit (3) formed by connecting in series a rectification circuit (4) in which the first current path (41) and the second current path (42) are connected in parallel with each other, and the inductor; the resonant control circuit (3) is connected between the control terminal and the reference potential (Vref) such that a parasitic capacitance (PC) between the control terminal and the ground terminal of the main switching element (TR) and the resonant control circuit (3) form a resonant circuit (3); and the switching element driver circuit (1) additionally includes a bias circuit (5) which sets a potential of a terminal of the resonance control circuit (3) on the opposite side from the control terminal side to a bias potential (Vb) that differs from the reference potential (Vref).

Description

TECHNICAL AREA

[0001] The present invention relates to a switching element driver circuit which provides a control terminal of a switching element with a driver signal for controlling the switching element. STATE OF THE ART

[0002] A switching element, such as a FET (Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor), operates when a driver signal is applied such that a potential difference is created between a gate terminal (control terminal) and a source terminal. A parasitic capacitance exists between the gate and source terminals of the switching element, and power dissipation occurs as this capacitance is charged. The power dissipation is proportional to the switching frequency. Therefore, as the switching frequency increases, the power dissipation for the driver circuit that controls the switching element also increases, which can lead to disadvantages such as the need for larger circuit dimensions or a larger power source for the driver circuit.

[0003] Japanese patent application number 3-60360 (patent document 1) discloses a gate driver circuit incorporating a parallel resonant circuit to suppress the influence of parasitic capacitance. The gate driver circuit includes an inductor forming a parallel resonant circuit with the parasitic capacitance and a rectification circuit that determines the direction of current application, causing a charge to flow back and forth between the inductor and the parasitic capacitance. The rectification circuit includes a switch (switching element) that controls the application and blocking of the current (see above). Fig. 1 etc. of patent document 1). A similar configuration is also described in US patent application 2012 / 0176176 A1 (patent document 2). In such gate driver circuits, energy is generally exchanged between the parasitic capacitance and the inductor to reduce power loss.

[0004] The driver signal according to patent document 1 is a positive and negative bipolar signal exhibiting symmetrical positive and negative potentials with respect to a reference potential. However, in some elements, such as a MOSFET using silicon carbide (SiC), the dielectric strength against a negative potential with respect to a reference potential is lower than the dielectric strength against a positive potential. Therefore, when driving a SiC MOSFET using such a positive and negative bipolar driver signal, a positive and negative bipolar signal exhibiting asymmetrical positive and negative potentials with respect to a reference potential may be required.Since the driver signal according to patent document 1 is a positive and negative bipolar signal having symmetrical positive and negative potentials with respect to the reference potential, a current flowing back and forth between the parasitic capacitance and the inductor is essentially equal (see for example . Fig. 3 of the patent document 1). In addition, the power and current consumed by a positive power source and a negative power source, which form a power source for driver pulses, are also essentially the same.

[0005] In the case where the driver signal is a positive and negative bipolar signal exhibiting asymmetrical positive and negative potentials with respect to the reference potential, the current flowing back and forth between the parasitic capacitance and the inductor is also not equal. Furthermore, if the power source for the driver pulses is a positive and negative bipolar power source, the power and current consumed by the positive and negative power sources are also not equal. Therefore, while a certain reduction in power dissipation can be achieved, the load on a driver circuit that drives the switching element or on a power source supplying power to the driver circuit may be increased.Additionally, it may be necessary to use a component with a high yield strength corresponding to the magnitude of the current draw, or procurement costs may be increased due to the use of components with different specifications on the positive and negative sides. Furthermore, an unintended undertone or similar waveform may be introduced into the waveform of the driver signal for the switching element, and this may exceed the voltage rating of the gate terminal (control terminal) of the switching element being driven. [Applications of the same type][Patent documents] [Patent document 1] Japanese patent application with publication number 3-60360 (JP 3-60360 A) [Patent document 2] US patent application with publication number 2012 / 0176176 A1 SUMMARY [Problem to be solved by the invention]

[0006] In view of the prior art described above, it is desirable to provide a technique configured to reduce power loss for a driver circuit that drives a switching element using a positive and negative bipolar signal having asymmetric positive and negative potentials with respect to a reference potential as a driver signal, and to reduce load distribution deviations in the driver circuit. [Means to solve the problem]

[0007] With regard to what has been described above, a switching element driver circuit is, according to one aspect a switching element driver circuit that controls a main switching element by providing a control terminal of the main switching element with a driver signal, the main switching element having a ground terminal which is a source terminal or an emitter terminal, and to which the reference potential is connected, wherein the switching element driver circuit comprises: an inductor, one terminal of which is connected to a control terminal side and the other terminal of which is connected to a reference potential side; a first current path in which a first rectification element, whose forward direction is from the control terminal side to the reference potential side, and a first switch are connected in series; and a second current path in which a second rectification element, whose forward direction is a direction from the reference potential side to the control terminal side, and a second switch are connected in series, wherein: a resonant control circuit formed by connecting in series a rectification circuit, in which the first current path and the second current path are connected in parallel, and the inductor; the resonant control circuit is connected between the control terminal and the reference potential in such a way that a parasitic capacitance between the control terminal and the ground terminal of the main switching element and the resonant control circuit form a resonant circuit; and The switching element driver circuit additionally has a bias circuit that sets a potential of a terminal of the resonance control circuit on the opposite side from the control terminal side to a bias potential that differs from the reference potential.

[0008] The driver signal for the main switching element reduces power loss due to parasitic capacitance through energy exchange via the parallel resonant circuit formed by the parasitic capacitance and the inductor. The parallel resonant circuit is highly effective when the driver signal is a positive and negative bipolar signal symmetrical with respect to the reference potential. However, when the driver signal is an asymmetrical positive and negative bipolar signal, a DC component, resulting from the asymmetry of the driver signal's amplitude relative to the reference potential, affects the resonant circuit. In the configuration described above, however, the DC component can be canceled out by the bias potential.As a result, it is possible to reduce power loss for the driver circuit that drives the main switching element using a positive and negative bipolar signal that has asymmetrical positive and negative potentials with respect to the reference potential as the driver signal, and to reduce a deviation of the load distribution in the driver circuit.

[0009] Further features and advantages of the switching element driver circuit will become apparent from the following description of an exemplary embodiment with reference to the drawing. BRIEF DESCRIPTION OF THE DRAWING [ Fig. 1] Fig. Figure 1 is a schematic block diagram representing the basic configuration of a gate driver circuit. [ Fig. 2] Fig. Figure 2 is a schematic circuit diagram that shows an example of the configuration of the gate driver circuit. [ Fig. 3] Fig. Figure 3 is a waveform diagram that shows an example of the waveform of a driver signal. [ Fig. 4] Fig. Figure 4 is a waveform diagram that shows an example of the waveform of a current flowing through a resonant coil. [ Fig. 5] Fig. Figure 5 is a waveform diagram that shows an example of the waveform of a current flowing through a power source. [ Fig. 6] Fig. Figure 6 is a waveform diagram that shows another example of the waveform of the driver signal. [ Fig. 7] Fig. Figure 7 is a waveform diagram that shows another example of the waveform of the current flowing through the resonant coil. [ Fig. 8] Fig. Figure 8 illustrates the principle for setting a preload potential. [ Fig. 9] Fig. Figure 9 is a schematic circuit diagram that represents another example of the configuration of the gate driver circuit. [ Fig. 10] Fig. Figure 10 is a waveform diagram that shows an example of fluctuations in the waveform of a gate driver signal. [ Fig. 11] Fig. Figure 11 is a waveform diagram that shows an example of fluctuations in the waveform of a current flowing through the resonant coil. [ Fig. 12] Fig. Figure 12 is a schematic circuit diagram that represents another example of the configuration of the gate driver circuit. [ Fig. 13] Fig. Figure 13 is a schematic circuit diagram that represents another example of the configuration of the gate driver circuit. [ Fig. 14] Fig. Figure 14 is a schematic circuit diagram that represents another example of the configuration of the gate driver circuit. [ Fig. 15] Fig. Figure 15 is a schematic circuit diagram that represents a comparative example of the gate driver circuit. WAYS TO IMPLEMENT THE INVENTION

[0010] A switching element driver circuit according to an embodiment of the present invention is described below with reference to the drawing. Fig. Figure 1 is a schematic block diagram that represents the basic configuration of a gate driver circuit (switching element driver circuit). Fig. Figure 2 is a schematic circuit diagram that shows an example of the configuration of the gate driver circuit, which corresponds to the basic configuration. Fig. 15 is a schematic block diagram that provides a comparative example according to the Fig. 1 represents. A gate driver circuit 1 is a circuit that provides a control terminal of a main switching element TR with a driver signal SP for controlling the main switching element TR.

[0011] In this embodiment, a MOS (Metal Oxide Semiconductor)-type FET is shown as an example of the main switching element TR, and the control terminal is a gate terminal. In one aspect of a source-grounded circuit, the main switching element TR is connected to a source terminal, which serves as the ground terminal. In the case where the main switching element TR is an IGBT, in one aspect of an emitter-grounded circuit, the main switching element TR is connected to an emitter terminal, which serves as the ground terminal. A reference potential Vref, commonly referred to as "ground," is connected to either the source terminal or the emitter terminal. In the following description, the ground terminal is simply referred to as the "source terminal." Of course, in the case where the main switching element TR is an IGBT or the like, the "source terminal" in the description can be read as the "emitter terminal."

[0012] In the Fig. 1 and Fig. The aspect shown in Figure 2 is that the driver signal SP is a bipolar signal exhibiting potentials in both the positive and negative directions relative to the reference potential Vref. The main switching element TR transitions from an off state to an on state when a specified voltage is applied between the gate and the source. However, if the threshold voltage for a state transition is close to the reference potential Vref connected to the source terminal, the main switching element TR may transition to the on state due to an external noise signal or similar disturbance. In this case, if a bipolar signal is used as the driver signal SP, the main switching element TR can be stably switched to the off state by providing a potential lower than the reference potential Vref. For example, a MOSFET using silicon carbide (SiC) has a relatively low threshold voltage.Thus, such a bipolar signal is preferably used as the driver signal SP in the case where the main switching element TR is a SiC MOSFET or the like.

[0013] The in the Fig. 1 and Fig. The gate driver circuit 1 shown in Figure 2 has a power source circuit PS, which is a bipolar power source, to generate the driver signal SP, which is also a bipolar signal. In the power source circuit PS, a positive power source BP and a negative power source BN are connected in series, with the junction between them at the reference potential Vref. That is, the positive power source BP provides the gate driver circuit 1 with a potential (positive potential Vcc) that is positive with respect to the reference potential Vref, and the negative power source BN provides the gate driver circuit 1 with a potential (negative potential Vee) that is negative with respect to the reference potential Vref. Here, the reference potential Vref is zero, and the power source circuit PS provides the gate driver circuit 1 with a voltage of "|Vcc|+|Vee|".In this embodiment, the absolute value (|Vcc|) of the positive potential Vcc differs relative to the reference potential Vref, and the absolute value (|Vee|) of the negative potential Vee differs relative to the reference potential Vref. Furthermore, in this embodiment, the condition "|Vcc|>|Vee|" is satisfied, meaning that the absolute value (|Vcc|) of the positive potential Vcc is greater relative to the reference potential Vref than the absolute value (|Vee|) of the negative potential Vee relative to the reference potential Vref. This means that the power source circuit PS comprises a positive and negative bipolar power source with asymmetrical positive and negative potentials.

[0014] As previously discussed, the driver signal SP is preferably a bipolar signal if the main switching element TR is a SiC MOSFET or the like. However, it should be noted that the voltage withstand capability to a negative potential is lower in some SiC MOSFETs than the voltage withstand capability to a positive potential. In the embodiment where SiC MOSFETs with such characteristics are assumed, the driver signal SP, which is a bipolar signal, is generated by a positive and negative bipolar power source (power source circuit PS) in which the absolute value (|Vcc|) of the positive potential Vcc relative to the reference potential Vref is greater than the absolute value (|Vee|) of the negative potential Vee relative to the reference potential Vref.

[0015] A driver signal generation circuit 2 generates the driver signal SP, which has a voltage amplitude within a range provided by the power source circuit PS, based on a clock signal TP from a control device (not shown), such as a microcomputer. The driver signal generation circuit 2 is formed by connecting in series an upper switch 21, connected to the positive terminal of the power source circuit PS, and a lower switch 22, connected to the negative terminal of the power source circuit PS. When either the upper switch 21 or the lower switch 22 is exclusively in the ON state, the driver signal SP is generated, which has a state in which the signal level is at the positive potential Vcc and a state in which the signal level is at the negative potential Vee.The driver signal SP is fed into the gate terminal of the main switching element TR via a current limiting resistor R3.

[0016] Fig. Figure 2 represents a specific example of the circuit configuration of the driver signal generation circuit 2. Here, the two switches (21, 22) of the driver signal generation circuit 2 are each formed by a bipolar transistor. The upper switch 21 is an NPN-type transistor, and the lower switch 22 is a PNP-type transistor. One of the NPN-type transistors and one of the PNP-type transistors is switched to the ON state only according to the state of the clock signal TP (depending on whether the signal level of the clock signal TP is high or low). As will be discussed later, the clock signal TP is fed into the base terminals of the two transistors via an integrated circuit, and therefore the two transistors are controlled such that they are not switched to the ON state simultaneously.A resistor R21 and a resistor R22 are each a resistor acting as a switch (21, 22) that switches a current flowing between a collector and an emitter of the transistor.

[0017] A resistor R20 and a capacitor C20 form an integrated circuit. An output from the integrated circuit is fed into the control terminals of switches (21, 22) (the base terminals of the transistors). Capacitor C20 is charged via a path through resistor R21. A time, corresponding to a time constant (τ = resistance × capacitance), determined according to the resistance of resistor R20 and the capacitance of capacitor C20, is then elapsed before the potential of capacitor C20 is raised from the reference potential Vref (= 0) to the positive potential Vcc or the negative potential Vee. Conversely, capacitor C20 is discharged via a point between the base and emitter of the transistor controlled by either the upper switch 21 or the lower switch 22.Thus, the time before the potential of capacitor C20 is brought from the positive potential Vcc or from the negative potential Vee to the reference potential Vref (= 0) is short. Due to the effect of the integrated circuit, the time at which the potential of the driver signal SP is brought to the positive potential Vcc in response to a rise in the clock signal TP is delayed by a time equal to the time constant τ. Additionally, due to the effect of the integrated circuit, the time at which the potential of the driver signal SP is brought to the negative potential Vee in response to a fall in the clock signal TP is also delayed by a time equal to the time constant τ.

[0018] On the other hand, the time at which the potential of the driver signal SP is varied from the positive potential Vcc is essentially synchronized with a fall in the clock signal TP. Additionally, the time at which the potential of the driver signal SP is varied from the negative potential Vee is essentially synchronized with a rise in the clock signal TPP. As discussed previously, the time at which the potential of the driver signal SP is brought to the positive potential Vcc and the time at which the potential of the driver signal SP is brought to the negative potential Vee in response to fluctuations in the clock signal TP are delayed by a time equal to the time constant τ. Thus, the potential of the driver signal SP is brought from the positive potential Vcc into a high-impedance (Hi-Z) state essentially in sync with a fall in the clock signal TP.Similarly, the potential of the driver signal SP is brought from the negative potential Vee into the Hi-Z state, essentially in synchronization with a rise in the clock signal TP. In the Hi-Z state, the gate driver circuit 1, according to the exemplary embodiment, creates a resonant circuit to generate an electrical oscillation, as described below.

[0019] A parasitic capacitance PC in the range of [nF] to [pF] is located between the gate and the source of the switching element, such as a FET. An n-channel type FET, such as the one in the Fig. 1 and Fig. The device shown in section 2 is brought into the ON state by applying a voltage in the forward direction relative to the source terminal to the gate terminal. This means that the driver signal SP rises from a low potential state to a high potential state. During this process, energy from the driver signal SP is used to charge the parasitic capacitance PC, resulting in power loss. Additionally, the rise of the driver signal SP is delayed, for example, by the charging of the parasitic capacitance PC. If the switching frequency for turning the main switching element TR on and off increases, the power loss due to the parasitic capacitance PC is not negligible.

[0020] To suppress the influence of the parasitic capacitance PC, the gate driver circuit 1 includes a resonant coil L1 (inductor) to form a parallel resonant circuit with the parasitic capacitance PC. One terminal of the resonant coil L1 is connected to the gate terminal (control terminal), and the other terminal is connected to the reference potential Vref. The parallel resonant circuit is formed by connecting a resonant control circuit 3, which includes the resonant coil L1, and the parasitic capacitance PC in parallel. The resonant control circuit 3 is formed by connecting a rectification circuit 4 and the resonant coil L1 in series.

[0021] The rectification circuit 4, which allows currents to flow in opposite directions, is formed by connecting a first current path 41 and a second current path 42 in parallel. The first current path 41 is formed by connecting a first rectification circuit D1, whose forward direction is from the gate terminal (control terminal) to the reference potential Vref, and a first switch S1 in series. That is, the first current path 41 is a current path that allows energy to flow from the parasitic capacitance PC to the resonant coil L1. The second current path 42 is formed by connecting a second rectification circuit D2, whose forward direction is from the reference potential Vref to the gate terminal (control terminal), and a second switch S2 in series.That is, the second current path 42 is a current path that allows a movement of energy from the resonant coil L1 to the parasitic capacitance PC.

[0022] In the first current path 41 and the second current path 42, the switches (S1, S2) connected in series with the rectification elements (D1, D2) are formed from FETs. The clock signal TP is applied to the gate terminals of the FETs forming the first switch S1 and the second switch S2 via a current-limiting resistor. The first switch S1 is a p-channel type FET and the second switch S2 is an n-channel type FET. One of the p-channel type FETs and one of the n-channel type FETs is switched to the ON state according to the state of the clock signal TP (whether high or low).

[0023] When the clock signal TP rises from the low state to the high state, the n-channel FET forming the second switch S2 is switched to the ON state, allowing current to flow through the second current path 42. This second current path 42 allows energy to flow from the resonant coil L1 to the parasitic capacitance PC. Thus, the parasitic capacitance PC is charged by the energy from the resonant coil L1, increasing the potential of the gate terminal of the main switching element TR. After the clock signal TP rises, the driver signal SP is in the Hi-Z state until a time corresponding to the previously discussed time constant τ has elapsed. Thus, the main switching element TR is driven by the energy of the resonant coil L1 after the clock signal TP rises and until the time corresponding to the time constant τ has elapsed. After the time corresponding to the time constant τ has elapsed, power is supplied from the power source circuit PS (in this case the positive power source BP) via the driver signal generation circuit 2 to drive the main switching element TR.

[0024] When the clock signal TP falls from the high state to the low state, the p-channel FET forming the first switch S1 is switched ON, allowing current to flow through the first current path 41. This first current path allows energy from the parasitic capacitance PC to be transferred to the resonant coil L1. Thus, the energy stored in the parasitic capacitance PC is transferred to the resonant coil L1. After the clock signal TP falls off, the driver signal SP is in the Hi-Z state until a time equal to the previously discussed time constant τ has elapsed. Therefore, the potential of the gate terminal of the main switching element TR is reduced by the transfer of energy to the resonant coil L1 after the clock signal TP falls off and until the time equal to the time constant τ has elapsed.After the time corresponding to the time constant τ has elapsed, the gate terminal is connected via the driver signal generation circuit 2 to the power source circuit PS (in this case the negative power source BN) and the potential of the gate terminal is reduced to bring the main switching element TR into the OFF state.

[0025] In this embodiment, the gate driver circuit 1 is configured to include an additional bias circuit 5. The bias circuit 5 sets a potential of a terminal of the resonant control circuit 3 on the opposite side from the gate terminal to a bias potential Vb that differs from the potential of the source terminal of the main switching element TR. In this embodiment, as discussed previously, the condition "|Vcc|>|Vee|" is satisfied, and the bias potential Vb is a positive potential relative to the potential (reference potential Vref) of the source terminal of the main switching element TR.In the case where the power source circuit PS, which is a positive and negative bipolar power source, is an asymmetrical power source with different positive and negative absolute values, the effect of the resonant circuit can be enhanced in this way by setting a suitable bias potential Vb.

[0026] A block diagram in Fig. Figure 15 shows a circuit 100 according to a comparative example as per the Fig. 1, which represents the block diagram according to the exemplary embodiment. The circuit 100 according to the comparative example is an aspect that is achieved by removing the bias circuit 5 from the one in Fig. The gate driver circuit 1 shown in Figure 1 is obtained by connecting the resonant control circuit 3 to the reference potential Vref. Such a circuit configuration of circuit 100 according to the comparison example can be derived from the analogy of Fig. 2 can be easily explained and is therefore not shown. Differences between the gate driver circuit 1 according to the exemplary embodiment and the circuit 100 according to the comparative example, i.e., differences due to the presence and absence of the bias circuit 5, are explained below with regard to the Fig. 3 to 7 described.

[0027] The waveform diagrams of Fig. Figures 3 to 5 show the simulation results for a case where the specifications of the power source circuit PS are set as “|Vcc|:|Vee| ≈ 3:2”. Meanwhile, the Fig. 6 and Fig. Figure 7 presents the simulation results for a case in which the specifications of the power source circuit PS are defined as “|Vcc|:|Vee| ≈ 2:1”. The reference potential Vref is zero. Fig. 3 and Fig. Figure 6 represents the waveform of the driver signal SP. Fig. 4 and Fig. Figure 7 represents the waveform of a current flowing through the resonant coil L1. Fig. Figure 5 represents the waveform of a current flowing through the power source circuit PS. In the Fig. 3 and Fig. Figure 6 shows the solid line as the driver signal SP for the gate driver circuit 1 in the Fig. 1 and Fig. The aspect shown in Figure 2 is shown, and the dashed line indicates the driver signal SP for circuit 100 according to the comparison example in Figure 2. Fig. The aspect shown in section 15. In the Fig. 4 and Fig. 7 The solid line indicates the current flowing through the resonant coil L1 of the gate driver circuit 1 in the Fig. 1 and Fig. The aspect shown in section 2 shows the flow, and the dashed line indicates the current flowing through the resonant coil L1 of circuit 100 according to the comparative example in the Fig. The aspect shown in 15 flows. Fig. Item 5 will be discussed at a later date.

[0028] As in Fig. As shown in Figure 3, a delay of the driver signal SP has been better resolved, particularly during an increase in the driver signal SP, and the waveform has a shape that is closer to a square wave for the gate driver circuit 1, which features the bias circuit 5. Here, with respect to Fig. 4. As indicated by the dashed line, the magnitudes of the positive and negative currents flowing through the resonant coil L1 of circuit 100 according to the comparison example are not equal. That is, the current (positive current) flowing from the parasitic capacitance PC to the resonant coil L1 is greater than the current (negative current) flowing from the resonant coil L1 to the parasitic capacitance PC. Therefore, when the driver signal SP increases, there is insufficient energy to charge the parasitic capacitance PC, resulting in a delay during an increase. When the driver signal SP decreases, the energy of the parasitic capacitance PC is sufficiently discharged, and therefore no delay occurs. Consequently, the driver signal SP for circuit 100 according to the comparison example exhibits a distorted waveform with broken symmetry.Energy that is insufficient to charge the parasitic capacity PC is supplemented with energy from the power source circuit PS.

[0029] In the gate driver circuit 1 according to the exemplary embodiment, as indicated by the solid line in Fig. As shown in Figure 4, the magnitudes of the positive and negative currents flowing through the resonant coil L1 are essentially equal. That is, the energy used to charge the parasitic capacitance PC and the energy discharged from the parasitic capacitance PC are essentially equal. Therefore, the delay on a rise has been resolved, and a delay is caused on a rise compared to the driver signal SP for circuit 100 according to the comparison example. However, it should be noted that the driver signal SP for the gate driver circuit 1 according to the embodiment has a waveform that is less distorted and without broken symmetry. A charge flowing back and forth between the parasitic capacitance PC and the resonant coil L1 is reduced by an impedance in the circuit. Energy that is insufficient due to such a reduction in charge is supplemented by energy from the power source circuit PS.

[0030] Fig. Figure 5 represents the waveform of a current flowing through the power source circuit PS. Waveforms shown in the upper and second diagrams indicate currents flowing through the power source circuit of the gate driver circuit 1 according to the embodiment. The solid line indicates a current flowing through the negative power source BN, and the dashed line indicates a current flowing through the positive power source BP. Waveforms shown in the third and lower diagrams indicate currents flowing through the power source circuit of circuit 100 according to the comparison example. The dash-dot line in the third diagram indicates a current flowing through the negative power source BN, and the double-dashed line in the third diagram indicates a current flowing through the positive power source BP.

[0031] In circuit 100 according to the comparative example, as discussed previously, the energy available to charge the parasitic capacitance PC is insufficient when the driver signal SP increases and is supplemented by energy from the positive power source BP. Thus, a large current flows through the positive power source BP. Conversely, the energy is not insufficient when the driver signal SP decreases, and therefore almost no current flows through the negative power source BN. In gate driver circuit 1 according to the embodiment, as discussed previously, the energy available to charge the parasitic capacitance PC and the energy discharged from the parasitic capacitance PC are essentially equal. Therefore, the currents flowing through the positive power source BP and the negative power source BN are also essentially equal.In the gate driver circuit 1 according to the exemplary embodiment, the current flowing through the resonant coil L1 is additionally not deflected in either the positive or negative directions as in the circuit 100 according to the comparative example. Thus, the maximum amplitude of the current flowing through the positive power source BP and the negative power source BN for the gate driver circuit 1 according to the exemplary embodiment is approximately half that of the circuit 100 according to the comparative example.

[0032] The difference between gate driver circuit 1 according to the exemplary embodiment and circuit 100 according to the previously discussed comparison example is even more remarkable when the ratio between the voltages of the positive power source BP and the negative power source BN in the power source circuit PS becomes higher. As discussed previously, the Fig. 6 and Fig. Figure 7 presents the simulation results for a case where the ratio between the voltages of the positive power source BP and the negative power source BN, i.e., "|Vcc|:|Vee|", is "2:1". As indicated by the dashed line in Fig. As indicated in Figure 6, the driver signal SP for circuit 100, according to the comparison example, exhibits a waveform with an even more broken symmetry than that shown in Figure 6. Fig. 3, and this exhibits a large underoscillation (overvoltage) and a large oscillation due to the underoscillation. Additionally, this underoscillation increases the loss of the main switching element TR. As shown by the solid line in Fig. As indicated in Figure 6, the driver signal SP for the gate driver circuit 1 according to the exemplary embodiment has a waveform with good symmetry, and this is close to a square wave like the one in Figure 6. Fig. 3.

[0033] This is related to Fig. 7, as indicated by the dashed line, the difference between the orders of magnitude of the positive and negative currents flowing through the resonant coil L1 of circuit 100 according to the comparison example is greater than in Fig. 4. Therefore, when the driver signal SP increases, there is still insufficient energy to charge the parasitic capacitance PC, resulting in a significant delay during the increase. When the driver signal SP decreases, the energy of the parasitic capacitance PC is discharged more than necessary, which not only prevents the occurrence of a delay but also reduces the potential of the driver signal SP more than necessary to cause an undershoot. Therefore, according to the comparison example, the driver signal SP for circuit 100 exhibits a distorted waveform with broken symmetry.

[0034] In this way, in the gate driver circuit 1 according to the embodiment, the waveform of the driver signal SP is close to a square wave, which has symmetry, and enables stable control of the main switching element TR. Additionally, a stable electrical oscillation can be achieved between the resonant coil L1 and the parasitic capacitance PC, which can reduce the load on the power source circuit PS. If the power source circuit PS is formed using a positive and negative bipolar power source, loads on the positive power source BP and the negative power source BN can be balanced. Thus, it is not necessary to improve the specifications of either the positive or negative power source, which can prevent an increase in component procurement costs. Furthermore, it is less likely that the load on either the positive or negative power source will be increased, thereby reducing its lifespan and preventing a decrease in the reliability of the gate driver circuit 1.

[0035] The bias potential Vb, which is set by the bias circuit 5, is preferably a potential at which the charge in the parasitic capacitance PC, which is varied along with potential changes of the control terminal due to the driver signal SP, is balanced. Fig. Figure 8 represents the bias potential Vb, which is set in this way. In the case where the main switching element TR is to be switched on, the gate voltage of the main switching element TR transitions from Vee to Vcc, as shown in Fig. Figure 8 illustrates this process. During this process, the charge in the parasitic capacitance PC moves from "-Q1" to "Q2". In the diagram, "Qc" denotes a point at which the charge in the parasitic capacitance PC, oscillating between "-Q1" and "Q2", is balanced. That is, "Qc = (|-Q1|+|Q2|) / 2" is satisfied. The bias potential Vb is preferably the gate voltage at the time when the charge in the parasitic capacitance PC is "Qc". When an electrical oscillation is generated around this potential, the current flowing through the resonant coil L1 is balanced in both the positive and negative directions.

[0036] One in the Fig. 1 and Fig. The voltage divider circuit 6 shown in Figure 2 sets the bias potential Vb in accordance with the voltages divided by a resistor R1 and a resistor R2. The voltage divider circuit 6 establishes an initial value of the bias potential Vb. In the voltage divider circuit 6, the values ​​of resistors R1 and R2 are set such that a divided potential of the resistor "(R1·|Vee|+R2·Vcc) / (R1+R2)" is a potential corresponding to the midpoint "Qc" of the previously discussed charge Vb. Resistors R1 and R2 preferably have a large resistance value of approximately 100 kΩ or more to suppress power dissipation. In the case where the bias circuit 5 includes a bias capacitor C1, as in the Fig. 1 and Fig. As shown in Figure 2, the bias potential Vb is additionally moved to an optimal point after the main switching element TR begins switching. To move the bias potential Vb directly to the optimal point, without being dependent on the divided potential of the resistor, the impedance of the voltage divider circuit 6 is preferably high. Therefore, for this reason as well, resistors R1 and R2 preferably have a large resistance value of approximately 100 kΩ or more.

[0037] As previously discussed, after the main switching element TR is switched on, the bias potential Vb is moved to the optimal point by the action of the bias capacitor C1. Therefore, it is not necessary for the voltage divider circuit 6 to adjust the divided potential of the resistor exactly in accordance with the values ​​in Fig. The conditions shown in Figure 8 are set. The main switching element TR is subject to individual variations, and therefore the capacitance of the parasitic capacitance PC also differs in accordance with the main switching element TR. The inductance of the resonant coil L1 is also subject to individual variations. Thus, ideally, the potential set by the voltage divider circuit 6 can differ from the bias potential Vb. If the potential is set to a value more or less close to the bias potential Vb, the time for convergence to an optimal potential can be reduced by the bias capacitor C1. Therefore, the potential set by the voltage divider circuit 6 can, for example, be the midpoint between Vcc and Vee.In any case, the preload potential Vb is set such that the ratio (|Vcc-Vb|:|Vb-Vee|) between the absolute value (|Vcc-Vb|) of the potential difference between the positive potential Vcc and the preload potential Vb, and the absolute value (|Vb-Vee|) of the potential difference between the negative potential Vee and the preload potential Vb, is closer to 1:1 than the ratio (|Vcc|:|Vee|) between the absolute value (|Vcc|) of the positive potential Vcc and the absolute value (|Vee|) of the negative potential Vee.

[0038] With regard to such an effect of the bias capacitor C1, it is clear that the gate driver circuit 1 can assume other circuit configurations. Fig. Figure 9 represents another example of the configuration of the gate driver circuit 1. In the Fig. In the gate driver circuit 1 shown in Figure 2, the bias circuit 5 is configured to include the voltage divider circuit 6 and the bias capacitor C1. In the Fig. However, in the gate driver circuit 1 shown in Figure 9, the bias circuit 5 is configured such that it only has the bias capacitor C1.

[0039] As discussed previously, the voltage divider circuit 6 establishes an initial value for the bias potential Vb. If the voltage divider circuit 6 is present, the potential of the resonant coil L1 on the reference potential Vref side can be set to the bias potential Vb immediately after switching on. If the voltage divider circuit 6 is not present, as described in Fig. Figure 10 shows that the potential of the resonant coil L1 on the reference potential Vref side moves to an optimal value of the bias potential Vb due to the action of the bias capacitor C1 after the gate driver circuit 1 starts operation. Similarly, the current flowing through the resonant coil L1 is unbalanced between the positive and negative directions immediately after the power source is switched on. However, along with the movement of the bias potential Vb, the current between the positive and negative directions becomes balanced. In the Fig. In the configuration shown in Figure 9, the power source circuit PS is a symmetrical power source in which “Vcc=|Vee|” is satisfied, or an asymmetrical power source in which the difference between “Vcc” and “|Vee|” is relatively small, and can be a particularly effective circuit in the case where the accuracy of the power source voltage is high.

[0040] As previously described, the gate driver circuit 1 (switching element driver circuit) controls the main switching element TR by supplying the gate terminal (control terminal) of the main switching element TR with the driver signal SP. The source terminal or emitter terminal of the main switching element serves as the ground terminal, and the reference potential Vref is connected to the ground terminal. The gate driver circuit 1 is configured to reduce power dissipation of the gate driver circuit 1 due to the parasitic capacitance PC of the gate terminal of the main switching element TR and to minimize load distribution deviations in the circuit. Specifically, the gate driver circuit 1 includes the resonant coil L1 (inductor), the first current path 41, and the second current path 42. One terminal of the resonant coil L1 (inductor) is connected to the gate terminal side, and the other terminal of the resonant coil L1 is connected to the reference potential Vref side.The first current path 41 is formed by connecting in series a first rectification circuit D1, whose forward direction is from the gate terminal side to the reference potential Vref side, and a first switch S1. The second current path 42 is formed by connecting in series a second rectification circuit D2, whose forward direction is from the reference potential Vref side to the gate terminal side, and a second switch S2. The "reference potential Vref side" is also satisfied in the case where the target of the circuit connection is changed from the "reference potential Vref" to the "bias potential Vb". The bias potential Vb is used to set an offset from a target potential. The bias potential Vb is used to set an offset from the reference potential Vref, which serves as the target potential.Thus, the "preload potential Vb side" is equivalent to the "reference potential Vref side".

[0041] The resonant control circuit 3 is formed by connecting a rectification circuit 4, in which the first current path 41 and the second current path 42 are connected in parallel, and the resonant coil L1 in series. The resonant control circuit 3 is connected between the control terminal and the reference potential Vref such that the parasitic capacitance PC between the gate terminal and the ground terminal of the main switching element and the resonant control circuit 3 form a resonant circuit. The gate driver circuit 1 additionally includes the bias circuit 5, which sets a potential at a terminal of the resonant control circuit 3 on the opposite side from the gate terminal to the bias potential Vb, which differs from the reference potential Vref.One of the first switch S1 and the second switch S2 are exclusively set to the on state, so that one of the first current path 41 and the second current path 42 exclusively allows current to flow. The first switch S1 and the second switch S2 are switched in accordance with the clock signal when the signal level of the driver signal SP crosses, causing resonance between the resonant coil L1 and the parasitic capacitance PC. [Further examples]

[0042] Further embodiments of the switching element driver circuit (gate driver circuit (1)) are described below. The configuration of each embodiment described below is not limited to its independent application and can be used in combination with the configuration of other embodiments, provided no contradiction occurs.

[0043] (1) The gate driver circuit 1 is not limited to the aspect discussed above and can be implemented in a variety of variations. Fig. Figure 12 provides another example of the configuration of the gate driver circuit 1. As in Fig. As shown in Figure 12, the bias circuit 5 can be formed by connecting parallel circuits in series, each circuit having a resistor and a capacitor between the positive potential Vcc and the negative potential Vee. In particular, the bias circuit 5 can be formed by a series connection of a parallel connection of resistor R1 and capacitor C11 and a parallel connection of resistor R2 and capacitor C12.

[0044] (2) Additionally, the gate driver circuit 1 can be configured as shown in Fig. Figure 13 shows how it can be configured. That is, the bias circuit 5 can only consist of the voltage divider circuit 6, which is made up of resistors. As discussed previously, the voltage divider circuit 6, which consists of resistors, cannot be able to set an exact bias potential Vb. However, if it is possible to provide a bias with a value as close as possible to the bias potential Vb, which is ideal, an imbalance in the current flowing through the resonant coil L1 can be corrected. The asymmetry of the driver signal SP can also be reduced.

[0045] (3) In the example described above, the driver signal SP is a bipolar signal, exhibiting a potential in both the positive and negative directions with respect to the reference potential Vref, and the power source circuit PS, which is a bipolar power source, is configured to generate the driver signal SP, which is a bipolar signal. However, even if the driver signal SP is a unipolar signal, exhibiting a potential in either the positive or negative direction with respect to the reference potential Vref, and the power source circuit PS is a unipolar power source, the parasitic capacitance PC at the gate terminal of the main switching element TR can still affect the driver signal SP.Thus, the gate driver circuit 1 is preferably configured to have the bias circuit 5 as discussed previously, even if the driver signal SP is a unipolar signal and the power source circuit PS is a unipolar power source. Fig. Figure 14 presents an example of the configuration of the gate driver circuit 1 according to the Fig. 2 dar.

[0046] (4) In the example described above, the bias potential Vb is provided in the positive direction with respect to the reference potential Vref. However, the bias potential Vb is not restricted to being in the positive direction with respect to the reference potential Vref, but can also be in the negative direction. The direction of the bias potential Vb with respect to the reference potential Vref is determined by the relationship between the difference between the reference potential Vref and the positive potential Vcc, the difference between the reference potential Vref and the negative potential Vee, and the potential at which a charge charged into the parasitic capacitance PC and a charge discharged from it are balanced. [Overview of implementation examples]

[0047] The overview of the switching element driver circuit (1), which was previously described as an example, is briefly described below.

[0048] In one aspect, the switching element driver circuit (1) a switching element driver circuit (1) which drives a main switching element (TR) by providing a control terminal of the main switching element (TR) with a driver signal (SP) having asymmetric positive and negative potentials with respect to a reference potential, wherein the main switching element (TR) has a ground terminal which is a source terminal or an emitter terminal and to which the reference potential (Vref) is connected, wherein the switching element driver circuit (1) comprises: an inductor (L1) whose one terminal is connected to a control terminal side and whose other terminal is connected to a reference potential (Vref) side; a first current path (41) in which a first rectification element (D1), whose forward direction is from the control terminal side to the reference potential (Vref) side, and a first switch (S1) are connected in series; and a second current path (42) in which a second rectification element (D2), whose forward direction is a direction from the reference potential (Vref) side to the control terminal side, and a second switch (S2) are connected in series, wherein: a resonance control circuit (3) formed by connecting in series a rectification circuit (4) in which the first current path (41) and the second current path (42) are connected in parallel with each other, and the inductor (L1); the resonant control circuit (3) is connected between the control terminal and the reference potential (Vref) such that a parasitic capacitance (PC) between the control terminal and the ground terminal of the main switching element (TR) and the resonant control circuit (3) form a resonant circuit; and the switching element driver circuit (1) additionally includes a bias circuit (5) which sets a potential of a terminal of the resonance control circuit (3) on the opposite side from the control terminal side to a bias potential (Vb) that differs from the reference potential (Vref).

[0049] The driver signal (SP) for the main switching element (TR) reduces power loss due to parasitic capacitance (PC) through energy exchange via the parallel resonant circuit formed by the parasitic capacitance (PC) and the inductor (L1). The parallel resonant circuit is highly effective when the driver signal (SP) is a positive and negative bipolar signal that is symmetrical with respect to the reference potential (Vref). However, when the driver signal (SP) is an asymmetrical positive and negative bipolar signal, a DC component affects the resonant circuit due to the asymmetry of the driver signal's (SP) amplitude relative to the reference potential (Vref). In the configuration described above, this DC component can be canceled out by the bias potential (Vb).As a result, it is possible to reduce power loss for the driver circuit (1) which drives the main switching element (TR) using a positive and negative bipolar signal which has asymmetric positive and negative potentials with respect to the reference potential (Vref) as the driver signal (SP) and to reduce a deviation of the load distribution in the driver circuit (1).

[0050] Here, the bias potential (Vb) is preferably set such that the ratio (|Vcc-Vb|:|Vb-Vee|) between an absolute value (|Vcc-Vb|) of the potential difference between the positive potential (Vcc) and the bias potential (Vb) and an absolute value (|Vb-Vee|) of the potential difference between the negative potential (Vee) and the bias potential (Vb) is closer to 1:1 than the ratio (|Vcc|:|Vee|) between an absolute value (|Vcc|) of the positive potential (Vcc) and an absolute value (|Vee|) of the negative potential (Vee). The bias potential (Vb) corresponds to the electrical midpoint between the positive potential (Vcc) and the negative potential (Vee), as can be seen from the resonant circuit.Therefore, if the ratio between the absolute value of the positive potential (Vcc) and the absolute value of the negative potential (Vee) with respect to the bias potential (Vb) is close to 1:1, a DC component that affects the resonant circuit can be reduced.

[0051] In one aspect, the bias circuit (5) preferably includes a bias capacitor (C1) connected between a ground-side terminal of the resonant control circuit (3) and the reference potential. A DC component is absorbed by the bias capacitor (C1) due to the asymmetry of the amplitude of the driver signal (SP) relative to the reference potential (Vref). The midpoint of the amplitude of the driver signal (SP) is shifted relative to the reference potential (Vref) by an amount corresponding to the bias potential (Vb), thus canceling out the DC component.

[0052] In one aspect, the biasing circuit (5) preferably includes a voltage divider circuit (6) that generates the bias potential (Vb). The bias potential (Vb) can be directly adjusted using the voltage divider circuit (6).

[0053] In one aspect, the bias potential (Vb) is preferably a potential at which a charge in the parasitic capacitance (PC) is varied along with potential changes of the control terminal due to the driver signal (SP). By determining the bias potential (Vb) in this way, it is possible to adjust the bias potential (Vb) appropriately, matching the characteristics of the main switching element (TR), i.e., the parasitic capacitance (PC). Description of the reference symbols 1 GATE DRIVER SWITCHING (SWITCHING ELEMENT DRIVER SWITCHING) 3 RESONANCE CONTROL CIRCUIT 4 RECTIFICATION CIRCUIT 5 PRE-VOLTAGE CIRCUIT 6 Voltage divider switch 41 FIRST POWER PATH 42 SECOND POWER PATH C1 PRE-VOLTAGE CAPACITOR D1 FIRST RECTIFICATION ELEMENT D2 SECOND RECTIFICATION ELEMENT L1 RESONANCE COIL (INDUCTOR) PC PARASITIC CAPACITY S1 FIRST SWITCH S2 SECOND SWITCH SP DRIVER SIGNAL TR MAIN SWITCHING ELEMENT Vb PRE-VOLTAGE POTENTIAL Vref REFERENCE POTENTIAL

Claims

[1] Switching element driver circuit (1) which controls a main switching element (TR) by providing a control terminal of the main switching element (TR) with a driver signal (SP) having asymmetric positive and negative potentials with respect to a reference potential (Vref), wherein the main switching element (TR) has an earth terminal which is a source terminal or an emitter terminal and to which the reference potential (Vref) is connected, wherein the switching element driver circuit (1) comprises: a power source circuit comprising a positive and negative bipolar power source, and a positive power source providing a positive potential that is positive with respect to the reference potential (Vref), and a negative power source providing a negative potential that is negative with respect to the reference potential (Vref) and whose absolute value differs from an absolute value of the positive potential, wherein the positive and negative potentials are asymmetric with respect to the reference potential (Vref); an inductor, one terminal of which is connected to a control terminal side and the other terminal of which is connected to a reference potential (Vref) side; a first current path (41) in which a first rectification element (D1), whose forward direction is from the control terminal side to the reference potential (Vref) side, and a first switch (S1) are connected in series; and a second current path (42) in which a second rectification element (D2), whose forward direction is a direction from the reference potential (Vref) side to the control terminal side, and a second switch (S2) are connected in series, wherein: a resonance control circuit (3) formed by connecting in series a rectification circuit (4) in which the first current path (41) and the second current path (42) are connected in parallel with each other, and the inductor; the resonant control circuit (3) is connected between the control terminal and the reference potential (Vref) such that a parasitic capacitance (PC) between the control terminal and the ground terminal of the main switching element (TR) and the resonant control circuit (3) form a resonant circuit (3); and the switching element driver circuit (1) additionally includes a bias circuit (5) which sets a potential of a terminal of the resonance control circuit (3) on the opposite side from the control terminal side to a bias potential (Vb) that differs from the reference potential (Vref). [2] Switching element driver circuit according to claim 1, wherein the bias potential is set such that a ratio between an absolute value of a potential difference between the positive potential and the bias potential and an absolute value of a potential difference between the negative potential and the bias potential is closer to 1:1 than a ratio between an absolute value of the positive potential and an absolute value of the negative potential. [3] Switching element driver circuit according to claim 1 or 2, wherein the biasing circuit has a bias capacitor connected between an earth-side terminal of the resonant control circuit and the reference potential. [4] Switching element driver circuit according to one of claims 1 to 3, wherein the biasing circuit comprises a voltage divider circuit that generates the biasing potential. [5] Switching element driver circuit according to one of claims 1 to 4, wherein the bias potential is a potential at which a charge in the parasitic capacitance, which is varied together with potential changes of the control terminal due to the driver signal, is balanced.

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