Method for producing a semiconductor device and semiconductor device

Abstract

Method for producing a plurality of semiconductor components (100), each having a semiconductor body (2), comprising the following method steps: A) applying a semiconductor layer sequence (200) with a first semiconductor layer (21), a second semiconductor layer (22) and an active region (23) arranged between the first semiconductor layer and the second semiconductor layer to a substrate (9); B) forming a contact structure (7) for electrically contacting the first semiconductor layer (21) and the second semiconductor layer (22); C) structuring the semiconductor layer sequence (200) by forming at least one trench (20) which separates the semiconductor bodies (2); D) applying an insulation layer (6) covering the trench (20) and vertical surfaces of the semiconductor bodies (2); E) forming a plurality of anchor elements (63) by structuring the insulation layer (6) in a region covering the trench (20); F) Locally detaching the substrate (9) from the semiconductor bodies (2), wherein the anchor elements (63) remain attached to the substrate (9); and G) Selectively picking up at least one semiconductor body (2) with a first semiconductor layer (21), a second semiconductor layer (22) and an active region (23) together with an associated contact structure (7) by separating the anchor elements (63) from the substrate (9).

Description

[0001] The invention relates to a method for producing a semiconductor component and a semiconductor component.

[0002] Area lighting using LEDs requires a large number of small LEDs to be attached to a substrate using chip bonding. This is time-consuming and expensive when using standard LED manufacturing processes and standard chip bonding techniques.

[0003] Document US 2014 / 0 203 314 A1 describes a light-emitting semiconductor device comprising a semiconductor layer, a p-side electrode, an n-side electrode, and a fluorescent layer. A p-side electrode is provided on a first surface of the semiconductor layer. The n-side electrode is located on a further surface of the semiconductor layer. The fluorescent layer is provided on the first surface of the semiconductor layer and contains a plurality of fluorescent bodies configured to convert radiation emitted during operation of the semiconductor device.

[0004] An object of the invention is to provide a particularly flexible method for producing a semiconductor component or a plurality of semiconductor components, and further to provide a semiconductor component which can be produced in a simple and cost-effective manner.

[0005] This problem is solved by the subject matter of the independent patent claims. The dependent patent claims relate to further developments and further embodiments.

[0006] A substrate is provided for producing a semiconductor component or a plurality of semiconductor components. The substrate can be structured or flat. For example, the substrate is radiation-permeable, in particular transparent. The substrate is, for example, a growth substrate, which in this case can consist of, among other things, sapphire or silicon or can contain sapphire or silicon.

[0007] A semiconductor layer sequence comprising a first semiconductor layer, a second semiconductor layer and an active region is applied to the substrate, for example epitaxially grown.

[0008] The semiconductor layer sequence has a first main surface facing the substrate and a second main surface facing away from the substrate. The first main surface faces, for example, a surface of the substrate. The surface of the substrate can be structured, such that the first main surface is also structured. In particular, the first main surface replicates the structured surface of the substrate facing the semiconductor layer sequence. In particular, the first and second main surfaces delimit the semiconductor layer sequence in a vertical direction. A vertical direction is understood to be a direction that runs transversely, for example perpendicularly, to a main extension plane of the active region. A lateral direction runs parallel to the main extension plane of the active region. In particular, the lateral direction and the vertical direction are perpendicular to one another.

[0009] For example, the first semiconductor layer is formed as an n-type layer, and the second semiconductor layer is formed as a p-type layer, or vice versa. For example, the active region is arranged between the first semiconductor layer and the second semiconductor layer. In particular, the active region is a pn junction region configured to generate or detect electromagnetic radiation during operation of the semiconductor component.

[0010] The semiconductor layer sequence is based, for example, on a group III-V compound semiconductor material which comprises at least one element from main group III, such as Al, Ga, In, and one element from main group V, such as N, P, As. In particular, the term “III-V semiconductor compound material” encompasses the group of binary, tertiary, and quaternary compounds which contain at least one element from main group III and at least one element from main group V, for example nitride and phosphide compound semiconductors. N-conducting and p-conducting layers can each be produced by suitable doping of the semiconductor material. The semiconductor layer sequence can also be based on a group II-VI compound semiconductor material.

[0011] A contact structure comprising at least a first contact region, a second contact region, and a via is formed on the side of the second main surface. The via is electrically connected, for example, to the first contact region. For electrically contacting the first semiconductor layer, the via can extend from the second main surface through the second semiconductor layer and the active region into the first semiconductor layer. It is also possible for the via to extend through the first semiconductor layer. The second contact region is electrically connected, for example, to the second semiconductor layer.

[0012] The semiconductor layer sequence is structured into a plurality of semiconductor bodies. The semiconductor layer sequence can be divided into a plurality of semiconductor bodies, for example, by forming at least one or a plurality of trenches that separate the semiconductor bodies from one another in the lateral direction.

[0013] The structuring of the semiconductor layer sequence can be carried out, for example, by an etching process and / or a laser separation process to form the mesa trench or the plurality of trenches. The trench can extend from the second main surface of the semiconductor layer sequence facing away from the substrate to the first semiconductor layer or to the substrate or into the substrate. The trench can be formed such that a bottom surface of the trench is formed by surfaces of the first semiconductor layer and / or the substrate. After the structuring of the semiconductor layer sequence, the semiconductor bodies are in particular electrically insulated from one another.

[0014] An insulating layer is applied to the structured semiconductor layer sequence, wherein the insulating layer covers the trench or the plurality of trenches and vertical surfaces of the semiconductor bodies. The insulating layer can be a dielectric layer containing, for example, silicon such as silicon oxide or silicon nitride. The insulating layer can be applied to the semiconductor bodies, for example, by sputtering or coating, such as chemical or physical vapor deposition.

[0015] A plurality of anchor elements are formed by patterning the insulation layer in the region covering the trench. In particular, the anchor elements are formed within the trench or trenches. In this case, the anchor elements are arranged laterally from the active regions of the semiconductor bodies in plan view.

[0016] The substrate is locally detached from the semiconductor bodies. The local detachment of the substrate from the semiconductor bodies means that the substrate then no longer has direct physical contact with the semiconductor bodies, in particular at least in regions covered by the active regions or the first semiconductor layers of the semiconductor bodies. However, the semiconductor bodies can still be indirectly connected to the substrate, for example, by the anchor elements arranged laterally of the semiconductor bodies.

[0017] The local detachment of the substrate can occur after the formation of the anchor elements. During or after the step of locally detaching the substrate from the semiconductor bodies, the anchor elements remain attached to the substrate, in particular directly or indirectly. In this case, the semiconductor bodies can be held in place at least during the step of locally detaching the substrate. After the step of locally detaching the substrate from the semiconductor bodies, the substrate is detached from the semiconductor bodies and / or from the semiconductor layer sequence, in particular at least in those regions covered by the active regions of the semiconductor bodies. However, the substrate is preferably attached to the anchor elements and / or parts of the first semiconductor layer covered by the anchor elements. In this case, the semiconductor bodies are preferably only indirectly connected to the substrate via the anchor elements.The detachment of the substrate from the semiconductor bodies can be achieved, for example, using an etching process or a laser lift-off process. Using a laser lift-off process, radiation is introduced through the substrate, for example, so that a separation area can be decomposed and the semiconductor bodies can be detached from the substrate.

[0018] A semiconductor body having a first semiconductor layer, a second semiconductor layer, and an active region, together with an associated contact structure, is optionally picked up by separating the anchor elements from the substrate. The anchor elements can be separated from the substrate by mechanically breaking the anchor elements or by releasing or dissolving the anchor elements from the substrate. The at least one semiconductor body can then be completely detached from the substrate and placed on a carrier, such as an intermediate storage device or a final circuit board. The semiconductor body, which is mechanically connected to the substrate, in particular only by the anchor elements, can optionally be removed by a stamp attached to the semiconductor body on the side of its second main surface.By lifting the semiconductor body away from the substrate, the anchor elements that secure the semiconductor body to the substrate can be mechanically broken or released, so that the semiconductor body is completely separated from the substrate. It is also possible for a plurality of semiconductor bodies to be removed from the substrate either simultaneously or sequentially.

[0019] According to at least one embodiment of a method for producing a plurality of semiconductor components, each comprising a semiconductor body, a semiconductor layer sequence is applied to a substrate, wherein the semiconductor layer sequence comprises a first semiconductor layer, a second semiconductor layer, and an active region arranged between the first and second semiconductor layers. A contact structure is formed for electrically contacting the first semiconductor layer and the second semiconductor layer. For electrically contacting the first semiconductor layer, the contact structure comprises, for example, at least one via or a plurality of vias extending through the second semiconductor layer and the active region.The semiconductor layer sequence is patterned into a plurality of semiconductor bodies by forming at least one trench or a plurality of trenches separating the semiconductor bodies. An insulation layer is applied to the semiconductor layer sequence to cover the trench or the plurality of trenches and vertical surfaces of the semiconductor bodies. In a next step, a plurality of anchor elements are formed by patterning the insulation layer in regions covering the trench or the plurality of trenches. After forming the anchor elements, the substrate is locally detached from the semiconductor bodies, while the anchor elements remain attached to the substrate.Each individual semiconductor body or a plurality of semiconductor bodies can then be selectively picked up from the substrate by separating the anchor elements from the substrate, wherein the semiconductor body comprises a first semiconductor layer, a second semiconductor layer and an active region together with an associated contact structure.

[0020] By bonding the anchor elements to the growth substrate, wherein the anchor elements connected to the semiconductor bodies are formed after forming a plurality of trenches that separate or isolate the semiconductor bodies from one another, each individual semiconductor body can be held in place by the anchor elements during the step of locally detaching the substrate from the semiconductor bodies. In a subsequent step, the semiconductor bodies can be selectively picked up, for example by a stamp, by breaking or releasing the anchor elements from the substrate. The semiconductor bodies can be transferred to a carrier, such as an intermediate tray or a final circuit board, one after the other or in large numbers at the same time.

[0021] According to at least one embodiment of the method, the semiconductor body or a plurality of semiconductor bodies is printed in a downward-radiating configuration onto a transparent carrier. A downward-radiating configuration means that the semiconductor body is arranged on the carrier such that its radiation passage surface faces the carrier. For example, the semiconductor body is applied to a connecting layer arranged on the carrier. The connecting layer can be an adhesive layer and / or an epoxy layer that is cured, for example, after the semiconductor body has been printed. The anchor elements or remnants of the broken anchor elements can serve as lateral anchor structures, which further improve the mechanical stability of the connection between a semiconductor body and the carrier.

[0022] According to at least one embodiment of the method, the insulation layer is structured such that the anchor elements belonging to different semiconductor bodies are separated. It is also possible for at least one anchor bar to be formed between the semiconductor bodies by structuring the insulation layer in the region covering the trench or the plurality of trenches, wherein the semiconductor bodies are connected to the anchor bar by the anchor elements. The anchor bar extends, for example, along at least one trench separating the semiconductor bodies. The anchor bar additionally contributes to holding the semiconductor bodies in place during the step of separating the substrate from the semiconductor bodies.

[0023] According to at least one embodiment of the method, at least one trench is formed through the second semiconductor layer and the active region into the first semiconductor layer of the semiconductor layer sequence, such that a bottom surface of the trench is at least partially formed by a surface of the first semiconductor layer. The insulation layer can be formed within the trench to cover the first semiconductor layer. In this case, the anchor elements can be formed by structuring the insulation layer and in particular also the first semiconductor layer such that, in a plan view, the anchor elements cover the first semiconductor layer within the trench or trenches. It is also possible for the insulation layer within the trench or trenches to be structured into a plurality of anchor elements and anchor bars, wherein the anchor bars can also cover the first semiconductor layer within the trench or trenches.In this way, the first semiconductor layer within the trench or trenches increases the mechanical strength of the anchor elements and anchor bars.

[0024] According to at least one embodiment of the method, at least one trench or a plurality of trenches are formed through the semiconductor layer sequence such that a surface, in particular a structured surface, of the substrate is partially exposed within the trench or trenches. By applying the insulation layer covering the trench or the plurality of trenches, the insulation layer can penetrate into the structured substrate such that the insulation layer and the anchor elements to be formed are anchored to the substrate. An interface between the substrate and the insulation layer is enlarged due to the structured surface of the substrate, so that an adhesion surface for the anchor elements and / or for the anchor bars on the structured surface is enlarged.

[0025] According to at least one embodiment of the method, the substrate is locally detached from the semiconductor bodies by means of a laser lift-off method. The substrate is formed, for example, from a material that is radiation-permeable, in particular transparent to radiation used in the laser lift-off method. The substrate contains, for example, gallium nitride, silicon carbide, or sapphire. The radiation can be directed specifically and precisely onto the semiconductor bodies. Furthermore, due to the different absorption coefficients of the material of the semiconductor bodies and the material of the anchor elements and / or the anchor bars, the semiconductor bodies can be separated from the substrate, while the anchor elements and / or anchor bars remain attached to the substrate. Therefore, by means of a laser lift-off method, the semiconductor bodies can optionally be locally detached from the substrate in a simplified manner.

[0026] According to at least one embodiment of the method, the substrate is locally separated from the semiconductor bodies by means of an etching process. The semiconductor bodies can be undercut using a wet etchant. In particular, a directional etching process is used to separate the substrate from the semiconductor bodies. The anchor elements and anchor bars can be designed to utilize directional etching. The anchor bars can be formed such that the substrate is etched only in a lateral direction parallel to the anchor bars and not along a lateral direction perpendicular to the anchor bars. In this case, the substrate can be formed from silicon. Wet etchants such as KOH can be used for the directional etching. In this way, the substrate can be locally detached from the semiconductor bodies while the anchor elements remain attached to the substrate.

[0027] According to at least one embodiment of the method, a combination of etching methods is used to locally detach the substrate from the semiconductor bodies and to structure the first main surfaces of the semiconductor bodies facing the substrate. In this case, the semiconductor layer sequence can be grown on a non-structured, for example, flat or planar, surface of the substrate, so that the first main surface of the semiconductor layer sequence can initially be substructured. After structuring the semiconductor layer sequence into a plurality of semiconductor bodies, the first main surfaces of the semiconductor bodies facing the substrate can be structured, for example, by means of an etching method.

[0028] In particular, the structuring takes place after the step of forming the plurality of anchor elements and before the step of picking up the semiconductor bodies from the substrate by separating the anchor elements. The structuring of the first main surfaces of the semiconductor bodies can take place during the step of locally detaching the substrate from the semiconductor bodies or after the step of locally detaching the substrate and before the step of separating the anchor elements. It is possible for a single etchant to be used for locally detaching the substrate from the semiconductor bodies and for structuring the main surfaces of the semiconductor bodies. For example, the etchant KOH can be used to detach the substrate, which contains, for example, silicon, and simultaneously be used to structure the first semiconductor layer, which contains, for example, gallium nitride.It is also possible to use a combination of two etching processes in succession, i.e. first to locally dissolve the substrate and then to structure the first main surfaces of the semiconductor bodies while they are connected to the substrate by the anchor elements.

[0029] According to at least one embodiment of a semiconductor component, the semiconductor component comprises a contact structure and a semiconductor body arranged on a light-transmissive carrier, wherein the semiconductor body comprises a first semiconductor layer, a second semiconductor layer, and an active region arranged between the first semiconductor layer and the second semiconductor layer. The semiconductor body has a first structured main surface facing the carrier and a second main surface facing away from the carrier. The contact structure comprises a first contact region and a second contact region arranged on the side of the second main surface, wherein the second contact region is electrically connected to the second semiconductor layer.The contact structure has a via that is electrically connected to the first contact region and extends in the vertical direction, in particular from the second main surface through the second semiconductor layer and the active region into the first semiconductor layer. At least one vertical surface of the semiconductor body is covered by an insulation layer that has an anchor element or a remnant of the anchor element. Furthermore, the semiconductor component is free of a growth substrate. The anchor element or the remnant of the anchor element is arranged laterally of the semiconductor body and embedded in a connecting layer that fixes the semiconductor body to the carrier, wherein the anchor element or the remnant of the anchor element has a structured surface facing the carrier.

[0030] Such a semiconductor component can be manufactured by the methods described here for manufacturing a semiconductor component. Therefore, features described in connection with the methods for manufacturing a semiconductor component or a plurality of semiconductor components can also be applied to the semiconductor component, and vice versa. According to at least one embodiment of the component, the component has a connecting layer that mechanically fixes the semiconductor body to the light-transmissive carrier. The component has at least one or a plurality of anchor elements or remnants of the anchor elements, which are arranged laterally next to the semiconductor body and embedded in the connecting layer. The anchor element or remnants of the anchor element is part of an insulation layer that covers a vertical surface of the semiconductor body.

[0031] According to at least one embodiment of the component, the component has a mirror layer arranged on the side of the second main surface of the semiconductor body. Furthermore, the semiconductor component can have a further mirror layer, which is embedded, for example, in the light-transmissive carrier. In particular, the further mirror is arranged adjacent to the semiconductor body. In plan view, the mirror layer and the further mirror layer are, in particular, free of overlaps. The light-transmissive carrier can have a plurality of such further mirror layers.

[0032] According to a preferred embodiment of the component, the active region is configured to generate electromagnetic radiation during operation of the semiconductor component. The electromagnetic radiation can be coupled out of the semiconductor component at a surface of the transparent carrier. The efficiency of the light coupling can be negatively influenced by the effect of total internal reflection at the surface of the transparent carrier. However, electromagnetic radiation reflected back into the carrier can be reflected back in a forward direction by the further mirror layer, which leads to an increase in the efficiency of the light coupling out.

[0033] According to at least one embodiment of the component, phosphor particles and / or scattering particles are arranged between the semiconductor body and a radiation passage area of the semiconductor component. The radiation passage area of the component can be formed by the surface of the light-transmissive carrier, wherein the surface faces away from the semiconductor body. Phosphor particles can absorb electromagnetic radiation emitted by the active region and re-emit electromagnetic radiation with a longer peak wavelength compared to the electromagnetic radiation absorbed by the phosphor particles, so that the component can emit white light overall. The phosphor particles and / or the scattering particles can be arranged within the light-transmissive carrier.Alternatively, the phosphor particles and / or the scattering particles may be embedded in a layer arranged between the carrier and the semiconductor body or on the side of the surface of the carrier facing away from the semiconductor body.

[0034] A plurality of semiconductor bodies can be arranged on a common, transparent carrier, forming a device comprising a plurality of semiconductor components and a common, transparent carrier. The semiconductor bodies can be arranged in the form of a matrix with columns and rows on the single, common, transparent carrier. The common, transparent carrier can have a plurality of further mirror layers, wherein the further mirror layers can each be arranged between two adjacent columns or rows of semiconductor bodies.

[0035] The method and the semiconductor device described here are described in more detail below using exemplary embodiments and the associated figures, in which: Fig. 1 to 8 show schematic sectional views of various process steps for producing a variety of semiconductor devices, Fig. 9A, Fig. 9B, Fig. 10 and Fig. 11 embodiments of a semiconductor device show, Fig. 12 shows an embodiment of a device comprising a plurality of semiconductor devices, and Fig. 13A to 13E show schematic sectional views of various process stages of further embodiments of a method for manufacturing a plurality of semiconductor devices.

[0036] Identical or similar elements, or elements that have the same effect, are provided with the same reference numerals in the figures. The figures are schematic views and are therefore not necessarily to scale. Rather, comparatively small elements, and in particular layer thicknesses, may be exaggerated for clarity.

[0037] In Fig. 1, a substrate 9 is provided. The substrate 9 has a structured surface 91. It is also possible for the surface 91 of the substrate 9 to be unstructured and to be formed as a flat surface. The substrate 9 is, for example, radiation-permeable, in particular transparent to electromagnetic radiation in the visible, infrared, and / or ultraviolet spectral range. The substrate 9 can comprise gallium nitride, silicon carbide, or sapphire. Alternatively, the substrate 9 can be radiation-opaque. In this case, the substrate 9 can be a silicon substrate.

[0038] A semiconductor layer sequence 200 is applied to the surface 91 of the substrate 9. The semiconductor layer sequence 200 has a first semiconductor layer 21, a second semiconductor layer 22, and an active region 23 arranged between the first semiconductor layer 21 and the second semiconductor layer 22. The first semiconductor layer 21 can be an n-conducting layer, and the second semiconductor layer 22 can be a p-conducting layer, or vice versa. The active region 23 is configured, for example, to generate electromagnetic radiation or to absorb and convert electromagnetic radiation into electrical signals or energy.

[0039] The semiconductor layer sequence 200 can be grown epitaxially on the substrate 9. The semiconductor layer sequence 200 has a first main surface 201 facing the substrate 9 and a second main surface 202 facing away from the substrate 9. The first main surface 201 is structured, which can be formed by a surface of the first semiconductor layer 21 facing the substrate 9. A structured substrate 9 can improve the quality of the epitaxial semiconductor layers of the semiconductor layer sequence 200. Furthermore, the semiconductor layer sequence 200 can be grown on the structured surface 91 of the substrate 9 such that the first structured main surface 201 replicates the structured surface 91 of the substrate 9.

[0040] A mirror layer 3 is deposited on the second main surface 202 facing away from the substrate 9. The mirror layer 3 has a plurality of subregions that are laterally separated from one another. In particular, the mirror layer 3 has a plurality of openings 30. Each of the subregions of the mirror layer 3 can be continuous and has, for example, at least one of the openings 30 of the mirror layer 3.

[0041] The mirror layer 3 is, in particular, electrically conductive. In plan view, the mirror layer 3 is covered by a connecting layer 4, which is also electrically conductive, for example. The mirror layer 3 and / or the connecting layer 4 can contain a metal such as aluminum, rhodium, palladium, silver, gold, or platinum, or alloys of these elements.

[0042] In Fig. 2, a dielectric layer 5, for example a silicon nitride layer or a silicon oxide layer, is applied to the semiconductor layer sequence 200, wherein the dielectric layer 5 completely covers the connection layer 4 and in particular the semiconductor layer sequence 200.

[0043] In Fig. 3, a plurality of recesses 24 are formed in regions of the openings 30 of the mirror layer 3. In the vertical direction, each recess 24 extends through the dielectric layer 5, the second semiconductor layer 22, the active region 23, and into the first semiconductor layer 21. The recess 24 forms a blind hole in the semiconductor layer sequence 200, wherein the recess 24 is, for example, completely surrounded in the lateral direction by the semiconductor layer sequence 200. The recess 24 can be formed by an etching process, for example, by a dry etching process.

[0044] After forming the recesses 24, a passivation layer 61, for example a silicon oxide layer such as SiO2 or a silicon nitride layer, is formed to cover vertical surfaces of the recesses 24. It is possible for the passivation layer 61 to completely cover the recesses 24 and the dielectric layer 5. In a subsequent step, the passivation layer 61 may be partially removed. The passivation layer 61 and the dielectric layer 5 preferably comprise different dielectric materials. For example, the dielectric layer 5 contains or consists predominantly of silicon nitride, and the passivation layer 61 contains or consists predominantly of silicon oxide.

[0045] In Fig. 4, the passivation layer 61 is partially removed, for example by etching, such that the first semiconductor layer 21 is exposed in the regions of the recesses 24. By partially removing the passivation layer 61, the dielectric layer 5 is also at least partially exposed. In a next step, the dielectric layer 5 is removed in places such that, in addition to the first openings 51 in the regions of the recesses 24, the dielectric layer 5 has a plurality of second openings 52 arranged laterally next to the recesses 24. An electrically conductive layer, such as the connecting layer 4, is partially exposed in the second openings 52.

[0046] In Fig. 5, a contact structure 7 comprising a first contact region 71, a second contact region 72, and a via 70 is formed on the side of the second main surface 202 of the semiconductor layer sequence 200. The first contact region 71 and the second contact region 72 are laterally separated and thus electrically insulated from one another. In the vertical direction, the second contact region 72 extends through the second opening 52 of the dielectric layer 5 and is electrically connected to the second semiconductor layer 22 through the mirror layer 3 and the connecting layer 4. The first contact region 71 is deposited outside the recess 24 and is electrically connected to the via 70, wherein the via 70 is arranged within the recess 24.

[0047] In the vertical direction, the via 70 extends at least from the second main surface 202 through the second semiconductor layer 22 and the active region 23 into the first semiconductor layer 21. Particularly for testing purposes, the semiconductor layer sequence 200 can be connected to an external power source by means of the first and second contact regions 71 and 72, which are arranged on the second main surface 202 facing away from the substrate 9. Within the recess 24, the via 70 is electrically insulated laterally from the second semiconductor layer 22 and the active region 23 by the passivation layer 61, which covers vertical surfaces of the recess 24.

[0048] In Fig. 5, the semiconductor layer sequence 200 is structured laterally into a plurality of semiconductor bodies 2. Lateral laser structuring means that the semiconductor layer sequence 200 is divided into a plurality of semiconductor bodies 2 that are laterally spaced from one another. A mesa trench 20 or a plurality of mesa trenches 20 is formed between the semiconductor bodies 2. In the vertical direction, the trench 20 extends through the semiconductor layer sequence 200 into the substrate, so that the surface 91, in particular the structured surface 91, of the substrate 9 is partially exposed within the trench 20 or the trenches 20. A bottom surface or lower surface of the trench 20 can be formed by the structured surface 91 of the substrate 9. The trenches 20 can be formed by an etching process, for example by a dry, wet, or laser etching process, in particular in regions between the partial regions of the mirror layer 3.The trench 20 can also be formed laterally from the semiconductor layer 200.

[0049] In Fig. 6A, an insulation layer 6 is applied to the semiconductor bodies 2 and to the substrate 9, wherein the insulation layer 6 covers vertical surfaces of the semiconductor bodies 2 and the trench or trenches 20 arranged laterally of the semiconductor bodies 2. In particular, the insulation layer penetrates into the structured surface 9 such that the insulation layer 6 is additionally anchored to the substrate 9 due to the structured surface 91 of the substrate. The insulation layer 6 can also be applied to cover the dielectric layer 5 and the contact structure 7, in particular the second contact region 72, such that a backside 102 of the device is formed, wherein the backside 102 is substantially flat, at least outside the recess or recesses 24. The backside is formed, for example, partly by surfaces of the insulation layer 6 and partly by surfaces of the first and second contact regions 71 and 72.On the back side 102, the first contact area 71 and the second contact area 72 are partially exposed and can be electrically contacted.

[0050] After the insulating layer 6 has been applied, a plurality of anchor elements 63 are formed by structuring the insulating layer 6 at least in regions covering the trench 20 or the trenches. The anchor elements 63 are, in particular, parts of the insulating layer 6 that are arranged next to their associated semiconductor body 2. In a plan view of the substrate 9, the semiconductor body 2 preferably has no overlaps with the anchor elements 63. The anchor elements 63 are formed to mechanically fix the semiconductor body 2 to the substrate 9. The anchor elements 63 can contain a dielectric such as silicon nitride or silicon oxide, for example silicon dioxide. A lithography method and / or an etching method can be used to structure the insulating layer 6 covering the trenches 20.

[0051] In Fig. 6B shows the contact structure 7, which has the first contact region 71, the via 70, and the second contact region 72 on the rear side 102. Vertical surfaces of each semiconductor body 2 are covered by the insulation layer 6. The insulation layer 6 is structured into a plurality of laterally spaced insulation layers 6 belonging to different semiconductor bodies 2. Each semiconductor body 2 has at least one or a plurality of anchor elements 63 on its sides. The insulation layer 6 is structured in regions covering the trenches 20 such that the anchor elements belonging to different semiconductor bodies 2 are separated. This simplifies the lifting of an individual semiconductor body 2 without affecting its neighboring semiconductor bodies 2.

[0052] In Fig. 6C, an anchor bar 64 is formed between the semiconductor bodies 2 by patterning the insulation layer 6 in the region covering the trench. By way of example, the anchor bar extends along a row of semiconductor bodies 2 along a lateral direction. A plurality of anchor bars 64 may be formed in regions of the trenches 20 between the semiconductor bodies 2. The anchor elements 63 are connected to the anchor bar 64. In this case, adjacent semiconductor bodies 2 may be mechanically connected to one another by the anchor elements 63 and the anchor bars 64. The anchor elements 63 and the anchor bars 64 may be configured, for example, to utilize a directional etching process used to locally detach the substrate 9 from the semiconductor bodies 2.

[0053] In Fig. 7A, the substrate 9 is separated from the semiconductor bodies 2. This can be done by a laser lift-off method. Radiation S can be introduced into the semiconductor bodies 2, in particular into the first semiconductor layers 21, region-wise through the substrate 9, so that the first semiconductor layers 21 of the semiconductor bodies 2, in particular of all semiconductor bodies 2, are locally detached from the substrate 9. During the step of separating the substrate 9, the semiconductor bodies 2 are held in place by the anchor elements 63, which remain attached to the substrate 9. In addition, a stabilizing carrier 81 can be used, which is attached to the rear side 102 of the semiconductor bodies 2. After the detachment of the substrate 9 from the semiconductor bodies 2, the first semiconductor layers 21 of the semiconductor bodies 2 are preferably completely separated from the substrate 9, while the anchor elements 63 remain at least partially attached to the substrate 9.

[0054] In Fig. 7B, an etching method can be used to detach the substrate 9 from the semiconductor bodies 2. For example, the semiconductor body 2 is undercut by a wet etchant E, which etches the surface 91 of the substrate 9 and / or the first main surface 201 of the semiconductor body 2. For example, a direction-dependent etching method is used, wherein the etchant only etches regions covered by the semiconductor body 2. In particular, the anchor elements 63 and / or the anchor bars 64 are not etched. The substrate 9 is, for example, a silicon substrate. In this case, the anchor elements 63 and 64 are configured such that the substrate 9 is not etched perpendicular to the anchor bars, i.e., is etched only along a lateral direction parallel to the anchor bars 64. For example, a hot-wet etchant such as KOH is used to directional etch the silicon substrate along a direction parallel to the anchor bars 64.In particular, the wet etchant, such as KOH, etches the silicon substrate 9 in a (111) plane selectively along <110> directions and is in <112> directions are blocked. It is also possible to use an etchant that etches the first semiconductor layer 21 or both the first semiconductor layer 21 and the substrate 9. By underetching the semiconductor bodies 2, the substrate 9 can be locally removed from the semiconductor bodies 2, wherein the anchor elements 63 and / or the anchor bars 64 remain at least partially attached to the substrate 9 (. Fig. 7C). Using an etchant such as KOH, the first main surface 201 is structured, resulting in an optimal light-outcoupling surface 201. It is also possible to use a combination of two etchants sequentially, one of which is used to etch the substrate 9, and the other of which is used to etch the first main surface 201 of the semiconductor bodies facing the substrate 9.

[0055] In Fig. 8A, a stamp 82 is attached to the rear side 102 after the stabilization region 81 has been removed. A semiconductor body 2 with a first semiconductor layer 21, a second semiconductor layer 22, and an active region 23, together with the associated contact structure 7 with the through-contact 70, can optionally be picked up by the stamp and lifted off the substrate 9 such that the anchor elements 63 are separated from the substrate 9. For example, the anchor elements 63 are mechanically broken open or detached from the substrate 9. It is possible that the anchor elements 63, or at least a portion of the remains of the anchor elements 63, are detached from the substrate ( Fig. 8B), so that the insulation layer 6 continues to have the anchor elements 63, or at least some of the anchor elements 63, after the semiconductor body 2 has been completely removed from the substrate 9. It is also possible to selectively pick up a plurality of semiconductor bodies 2 simultaneously.

[0056] In Fig. 9A, the semiconductor body 2 is placed onto a carrier 1 together with the associated contact structure 7. The semiconductor body 2 is printed, for example, onto the carrier 1 such that the structured first main surface 201 faces the carrier 1. The first main surface 201 is, in particular, free of electrical contacts. The carrier 1 is designed, for example, as a light-transmitting carrier. The carrier 1 has a connecting layer 13, which is a transparent layer, for example an adhesive or an epoxy layer. After the semiconductor body 2 has been applied to the carrier 1, the connecting layer 13 can be partially removed and cured. The connecting layer 13 fixes the semiconductor body 2 to the carrier 1. The carrier 1 has a further mirror 10 or a plurality of further mirrors 10 that can be embedded in the carrier 1.The semiconductor body 2 is arranged on the carrier 1 such that the further mirror 10 or the further mirrors 10 are arranged laterally of the semiconductor body 2. In plan view of the mirror layer 3, which is arranged on the side of the second main surface 202 of the semiconductor body 2, and the further mirror layers 10 are in particular free of overlaps. After applying the semiconductor body 2 to the carrier 1, the connecting layer 13 can be partially removed and cured. After removing the stamp 82, a semiconductor component 100, as shown in FIG. Fig. 9A, electrically connected to an external power source by means of the first contact area 71 and the second contact area 72 on the back side 102 of the semiconductor device 100. Fig. 9B schematically shows a further embodiment of the semiconductor device 100. This embodiment essentially corresponds to the embodiment of the semiconductor device 100 in Fig. 9A. In contrast, the insulation layer 6 comprises an anchor element 63 or a remnant of the anchor element 63 embedded in the connecting layer 13. The anchor element 63 or the remnant of the anchor element 63 can serve as an additional lateral anchoring structure, which improves the mechanical stability of the connection between the carrier 1 and the semiconductor body 2. It is also possible for the semiconductor device 100 to comprise a plurality of anchor elements 63 or remnants of anchor elements 63 embedded in the connecting layer 13.

[0057] Fig. 10 schematically illustrates another embodiment of the semiconductor device which essentially corresponds to the embodiment in Fig. 9A. In contrast, the contact structure 7 further comprises a first contact layer 710, a second contact layer 720, a first contact path 721, and a second contact path 722, wherein the first contact layer 710 and the second contact layer 720 are arranged adjacent to the semiconductor body 2 on the carrier 1. The first contact layer 710 is electrically connected to the first contact region 71 by the first contact path 721, which covers a vertical surface of the semiconductor body 2. The second contact layer 720 is electrically connected to the second contact region 72 by the second contact path 722, which covers a vertical surface of the semiconductor body 2. It is also possible for the semiconductor device 100 to be covered by an additional passivation layer (not shown), which, for example, covers parts of the contact structure 7.

[0058] In Fig. 11, the semiconductor component 100 comprises phosphor particles 11 and / or scattering particles 12. The phosphor particles 11 and / or the scattering particles 12 can be embedded in a main body of the carrier 1. The carrier 1 has a radiation passage area 101 on a side facing away from the semiconductor body 2. Electromagnetic radiation emitted by the active region 23 can be absorbed and re-emitted by the phosphor particles and scattered by the scattering particles 12 before leaving the semiconductor component 100, for example at the radiation passage area 101. It is also possible for the phosphor particles 11 and / or the scattering particles 12 to be embedded in the connecting layer 13 or a layer arranged between the semiconductor body 2 and the carrier 1 or arranged on the radiation passage region 101 of the carrier.

[0059] Fig. 12 illustrates a device comprising a plurality of semiconductor components 100, wherein the carriers of all of the semiconductor components 100 are formed as a single common light-transmissive carrier 1. The semiconductor bodies 2 can be arranged in a plurality of rows or columns on the common light-transmissive carrier 1. In particular, a plurality of semiconductor bodies 2 can be applied to the common carrier 1 simultaneously or one after the other. The device can comprise a plurality of further mirror layers 10 embedded in the common carrier 1 and arranged between columns and rows of the semiconductor bodies 2. For example, the mirror layers 3 of the semiconductor bodies 2 and the further mirror layers 10 of the common carrier are free of overlaps in plan view. The Fig. 13A to 13E illustrate further steps of a method for manufacturing a semiconductor device 100.

[0060] The Fig. 13A essentially corresponds to the manufacturing step shown in Fig. 1. In contrast, the substrate 9 has a surface 91 that is not structured but flat.

[0061] The Fig. 13B essentially corresponds to the manufacturing step shown in Fig. 6A. In contrast, the anchor elements 63 are formed on the smooth surface 91 of the substrate 9.

[0062] The Fig. 13C essentially corresponds to the manufacturing step described in Fig. 13B. In contrast, the insulation layer 6 covers the first contact region 71, the second contact region 72, and the through contact 70, in particular completely, such that the rear side 102 is formed, in particular, only by an outer surface of the insulation layer 6.

[0063] The rear side 102 can be designed to be particularly flat in a simplified manner, so that in the subsequent manufacturing steps, the stabilizing carrier 81 or the stamp 82 can be easily attached to the semiconductor bodies 2 on the rear side 102. For electrical contacting of the component 100, the insulation layer 6 can be partially removed, so that the first and second contact regions 71 and 72 are at least partially exposed.

[0064] The Fig. 13D essentially corresponds to the manufacturing step shown in Fig. 13D. In contrast, the trench 20 or a plurality of trenches 20 are formed such that their bottom surfaces are partially formed by exposed portions of the first semiconductor layer 21. The anchor elements 63 and / or the anchor bars 64 are in this case formed partially by the insulation layer 6 and partially by the first semiconductor layer 21. This increases the mechanical strength of the anchor elements 63 and the anchor bars 64.

[0065] The Fig. 13E essentially corresponds to the manufacturing step shown in Fig.7B. In contrast, the semiconductor layer sequence 200 was grown on a planar or flat surface 91 of the substrate 9, wherein the first main surfaces 201 of the semiconductor bodies 2 are structured during or after the process of undercutting the semiconductor bodies 2, locally detaching them from the substrate 9. A single etchant or a combination of at least two or more etchants can be used to detach the substrate 9 from the semiconductor bodies 2 and to structure the first main surfaces 201. The structuring of the first main surfaces 201 can be performed while the semiconductor bodies 2 are still connected to the substrate 9 by means of the anchor elements 63.

[0066] Using anchor elements to connect semiconductor bodies to a growth substrate, where the anchor elements are formed within mesa trenches that separate the semiconductor bodies, the semiconductor bodies can be held in place during and after the process of detaching the growth substrate, then selectively picked up and transferred to a carrier without the need for additional release layers. Using the anchor elements, the process for manufacturing a variety of semiconductor devices is simplified, leading to a reduction in manufacturing costs.

Claims

[1] Method for producing a plurality of semiconductor components (100), each having a semiconductor body (2), comprising the following method steps: A) applying a semiconductor layer sequence (200) with a first semiconductor layer (21), a second semiconductor layer (22) and an active region (23) arranged between the first semiconductor layer and the second semiconductor layer to a substrate (9); B) forming a contact structure (7) for electrically contacting the first semiconductor layer (21) and the second semiconductor layer (22); C) structuring the semiconductor layer sequence (200) by forming at least one trench (20) which separates the semiconductor bodies (2); D) applying an insulation layer (6) covering the trench (20) and vertical surfaces of the semiconductor bodies (2); E) forming a plurality of anchor elements (63) by structuring the insulation layer (6) in a region covering the trench (20); F) Locally detaching the substrate (9) from the semiconductor bodies (2), wherein the anchor elements (63) remain attached to the substrate (9); and G) Selectively picking up at least one semiconductor body (2) with a first semiconductor layer (21), a second semiconductor layer (22) and an active region (23) together with an associated contact structure (7) by separating the anchor elements (63) from the substrate (9). [2] The method of claim 1, wherein step E is performed before step F and the semiconductor bodies (2) are held in place by the anchor elements (63) during step F. [3] Method according to claim 1, wherein during step E the insulation layer (6) is structured in a region covering the trench (20) such that the anchor elements (63) belonging to different semiconductor bodies are separated. [4] The method according to claim 1, wherein during step E an anchor bar (64) is formed between the semiconductor bodies (2) by structuring the insulation layer (6) in a region covering the trench (20), and wherein the semiconductor bodies (2) are connected to the anchor bar (64) by the anchor elements (63). [5] The method according to claim 1, wherein - in step C, at least one trench (20) is formed through the second semiconductor layer (22) and the active region (23), so that in step D, within the trench (20), the insulation layer (6) covers the first semiconductor layer (21), and - in step F, the plurality of anchor elements (63) are formed by structuring the insulation layer (6) such that the anchor elements (63) cover the first semiconductor layer (21) within the trench (20). [6] Method according to claim 1, wherein the substrate (9) is provided with a structured surface (91) and the semiconductor layer sequence (200) is grown on the structured surface (91) of the substrate (9) such that the semiconductor layer sequence (200) has a first structured main surface (201) which replicates the structured surface (91) of the substrate (9). [7] Method according to claim 6, wherein - in step C, the at least one trench (20) is formed through the semiconductor layer sequence (200) in such a way that the structured surface (91) of the substrate (9) is partially exposed within the trench (20), and - in step D, the insulation layer (6) penetrates into the structured surface (9) in such a way that the anchor elements (61) are anchored to the substrate (9). [8] Method according to claim 1, wherein in step F the substrate (9) is detached from the semiconductor bodies (2) by a laser lift-off method, and wherein the anchor elements (63) remain at least partially attached to the substrate (9) after step F. [9] Method according to claim 1, wherein in step F the substrate (9) is detached from the semiconductor bodies (2) by means of an etching process, wherein the anchor elements (63) remain at least partially attached to the substrate (9) after step F. [10] Method according to claim 4, wherein the substrate (9) is detached from the semiconductor bodies (2) by a directional etching process using a wet etchant, wherein the anchor elements (63) and the anchor bar (64) are not under-etched. [11] The method of claim 1, wherein - the semiconductor layer sequence (200) is grown on a flat surface (91) of the substrate (9), - after step E and before step G, first main surfaces (201) of the semiconductor bodies (2) facing the substrate (9) are structured by means of an etching process. [12] Method according to claim 1, - wherein the contact structure (7) is formed on a main surface (202) of the semiconductor layer sequence (200) facing away from the substrate (9), and - wherein the contact structure (7) has a first contact region (71), a via (70), and a second contact region (72), wherein the second contact region (72) is electrically connected to the second semiconductor layer (22), wherein the via (70) is electrically connected to the first contact region (71) and extends from the main surface (202) through the second semiconductor layer (22) and the active region (23) into the first semiconductor layer (21). [13] The method of claim 1, wherein - during step E, the insulation layer (6) is structured in regions covering the trench or trenches (20) such that the anchor elements (63) belonging to different semiconductor bodies (2) are connected to anchor bars (64), the anchor bars extending along a lateral direction along a row of semiconductor bodies, and - the anchor bar (64) is formed between the semiconductor bodies (2) by structuring the insulation layer (6) in a region covering the trench (20). [14] Method according to claim 1, wherein a mirror layer (3) and a further mirror layer (10) are formed, wherein - the mirror layer (3) is formed on a side of the semiconductor body (2) facing the second main surface (202), - the further mirror (10) is embedded in a translucent carrier (1), - the further mirror (10) is arranged laterally of the semiconductor body (2), and - the mirror layer (3) and the further mirror layer (10) are free of overlaps. [15] Semiconductor component with a contact structure (7) and a semiconductor body (2) arranged on a light-transmissive carrier (1), wherein - the semiconductor body (2) has a first semiconductor layer (21), a second semiconductor layer (22) and an active region (23) arranged between the first semiconductor layer and the second semiconductor layer, - the semiconductor body (2) has a first structured main surface (201) facing the carrier (1) and a second main surface (202) facing away from the carrier (1), - the contact structure (7) has a first contact region (71) and a second contact region (72) arranged on the second main surface (202), wherein the second contact region (72) is electrically connected to the second semiconductor layer (22), - the contact structure (7) has a through contact (70), wherein the through contact (70) is electrically connected to the first contact region (71) and extends from the second main surface (202) through the second semiconductor layer (22) and the active region (23) into the first semiconductor layer (21), - a vertical surface of the semiconductor body is covered by an insulating layer (6) with an anchor element (63) or a remnant of the anchor element (63), - the component is free of a growth substrate, - the anchor element (63) or the remainder of the anchor element (63) is arranged laterally of the semiconductor body (2) and is embedded in a connecting layer (13) which fixes the semiconductor body (2) to the carrier (1), and - the anchor element (63) or the remainder of the anchor element (63) has a structured surface facing the carrier (1). [16] Semiconductor device according to claim 15, wherein - the anchor element (63) or the remainder of the anchor element (63) serves as an additional lateral anchoring structure which improves a mechanical stability of a connection between the carrier (1) and the semiconductor body (2), and - the translucent carrier (1) is an intermediate shelf or a final board. [17] Semiconductor component according to claim 15, comprising a mirror layer (3) and a further mirror layer (10), wherein - the mirror layer (3) is arranged on a side of the semiconductor body (2) facing the second main surface (202), - the further mirror (10) is embedded in the translucent carrier (1), - the further mirror (10) is arranged laterally of the semiconductor body (2), and - the mirror layer (3) and the further mirror layer (10) are free of overlaps. [18] Semiconductor component according to claim 15, wherein the active region (23) is arranged to generate electromagnetic radiation during operation of the semiconductor component. [19] Semiconductor component according to claim 15, wherein phosphor particles (11) are arranged within the light-transmissive carrier (1) or in a layer arranged on the light-transmissive carrier (1). [20] A device comprising a plurality of the semiconductor devices (100) according to claim 15, wherein the light-transmitting carriers (1) of all the semiconductor devices (100) are formed as a single common light-transmitting carrier.

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