Signal processing device and method for processing a signal

Abstract

Signal processing device, which includes the following: a sampling time control circuit configured to provide a sequence of digital values, wherein each digital value specifies a sampling time from a sequence of sampling times, wherein the sampling time control circuit is configured to provide multiple digital values, wherein each digital value specifies an offset with respect to a respective sampling time of a predetermined grid of multiple points in time; a sampling circuit configured to sample an input signal according to the sequence of sampling times in order to generate a sample value of the input signal for each sampling time of the sequence of sampling times; a processing circuit configured to receive the sampled values ​​and configured to process the sampled values ​​based on the sampled times, wherein the sampled time control circuit is configured to introduce jitter into the sampled times by varying the time intervals between adjacent sampled times, and wherein the processing circuit is configured to generate further sampled values ​​at the times of the previously specified grid of time points by interpolation, extrapolation, or both of the sampled values.

Description

Cross-reference to a related registration

[0001] This application claims priority over US patent application no. 14 / 751,195, filed on June 26, 2015. Technical field

[0002] The embodiments described herein relate generally to signal processing devices and methods for processing a signal. background

[0003] Converting an analog signal to the digital domain, i.e., analog-to-digital conversion, is a typical application in communication systems, for example. An analog signal is typically sampled at a specific frequency to generate samples at regular intervals, which can then be further processed, for example, by a discrete Fourier transform. However, the samples can be affected by noise and interference, making further processing difficult. Therefore, approaches to improve the quality of the samples are desirable.

[0004] The prior art document US 9,000,809 B2 describes a method for sampling an input signal, wherein the method includes providing a single-frequency clock signal, randomly selecting clock pulses from the single-frequency clock signal to generate a spread-spectrum clock signal, and sampling the input signal using the spread-spectrum clock signal.

[0005] The prior art document US 7,424,275 B2 describes a system comprising a digital circuit that is clocked by a digital clock signal with an associated clock period. Summary of the invention

[0006] The present invention is defined in the independent claims. Advantageous embodiments are specified in the dependent claims. Brief description of the drawings

[0007] In the drawings, the same reference numerals generally denote the same parts in the different views. The drawings are not necessarily to scale, and the focus is generally on illustrating the principles of the invention. The following description describes various aspects with reference to the following drawings, in which: Fig. Figure 1 shows a signal processing device. Fig. 2 shows a flowchart that represents a procedure for processing a signal. Fig. Figure 3 shows a signal processing device. Fig. Figure 4 shows a diagram that illustrates an example of sampling times. Fig. Figure 5 shows a device, including the signal processing device. Fig. Figure 6 shows a flowchart illustrating how the sampling time control circuit determines the sequence of sampling times. Description of embodiments

[0008] The following detailed description refers to the accompanying drawings, which illustrate specific details and aspects of this disclosure in which the invention may be carried out. Other aspects may be used, and structural, logical, and electrical modifications may be made without deviating from the scope of protection of the invention. The various aspects of this disclosure are not necessarily mutually exclusive, because some aspects of this disclosure may be combined with one or more other aspects of this disclosure to form new aspects.

[0009] Signals can be processed in a variety of domains, encompassing both continuous and discrete time and amplitude axes. For example, signals can be fully processed in the following domains: • Time-continuous and amplitude-continuous domain, which is usually referred to as the analog domain in technical language. • Time-discrete and amplitude-continuous domain, usually referred to as the sampled data domain. Implementation techniques such as switching capacitor, switching current, CCD (charge-coupled device), and others are typically used here. • Time-discrete and amplitude-discrete domain, widely known as the digital domain.

[0010] A fourth combination is conceivable, as are other pseudodomains such as a sigma-delta domain, although these can be considered of minor importance for the following description.

[0011] Signals in these domains can be represented in time and frequency spaces, linked by a pair of Fourier transforms. In this context, concepts such as aliasing, imaging, Nyquist rate, etc., arise.

[0012] A signal can be transformed between the domains mentioned above by interface blocks such as a sampler (which discretizes time), a quantizer (which discretizes amplitude), a hold circuit (which generates a continuous-time signal from a discrete-time signal), an analog filter (which generates an amplitude-discrete signal or interpolates to generate an amplitude-continuous signal), and so on. All these interface blocks can be implemented in many variations and all correspond to specific and well-defined signal transformations in both time and frequency domains.

[0013] Furthermore, a signal with either a discrete or continuous amplitude can be processed in the discrete-time domain by an interpolator or a decimator. For example, a discrete-time interpolator first generates an additional set of discrete time points between the available discrete time points; that is, it increases the rate. A discrete-time decimator removes values ​​from a discrete-time representation of a signal; that is, it reduces the rate. Rate reducers preceded by a suitable antialiasing filter constitute a decimator, while rate increasers followed by an image removal or smoothing filter constitute an interpolator.

[0014] Typically, a sampling circuit and a holding circuit are operated at fixed frequencies; that is, they are assumed to discretize or generate a continuous-time signal at well-defined and constant time intervals. This makes the mathematics of subsequent transformations, for example, typically quite simple. Furthermore, if constant time intervals are not used, the signal becomes distorted, or more generally, noise is added to the signal.

[0015] Varying the time intervals typically introduces jitter, which adds noise to the sampled signal (for an analog-to-digital conversion – ADC) or the reproduced signal (for a digital-to-analog conversion – DAC). However, noise is typically only relevant if it shares the same frequency band as the signal being processed, or, in the time domain, if its amplitude and position in time are unknown. If known, errors can be subtracted subsequently or corrected beforehand, and, in particular, if the exact time is known, an estimation procedure can be applied to clean the signal of the noise.

[0016] The following describes a signal processing device that can be used, for example, to deliberately introduce jitter over the sampling times, e.g., to avoid aliasing effects, whereby the noise introduced with the jitter can then be removed based on knowledge of the sampling times. In other words, various aspects of this disclosure can modify the deliberate introduction of jitter in response to a measured signal quality (e.g., of the digitized signal).

[0017] Fig. Figure 1 shows a signal processing device 100.

[0018] The signal processing device 100 includes a sampling time control circuit 101 configured to provide a sequence of digital values ​​102, each digital value specifying a sampling time from a sequence of sampling times.

[0019] The signal processing device 100 further comprises a sampling circuit 103 which is configured to sample an input signal 104 according to the sequence of sampling times in order to generate a sample value of the input signal 104 for each sampling time of the sequence of sampling times.

[0020] Furthermore, the signal processing device 100 includes a processing circuit 105 configured to receive the sampled values ​​and to process them based on the sample times. The sample time control circuit is configured to introduce jitter into the sample times by varying the time intervals between adjacent sample times.

[0021] In other words, a sampling time control circuit specifies sampling times individually, and a processing circuit that processes the sampled signal values ​​takes these sampling times into account. This allows the sampling times to be freely chosen (e.g., with certain variations from a predefined sampling grid), which, for example, makes it possible to spread out noise.

[0022] In other words, the signal processing device enables the provision of an interface between the continuous-time domain and the digital processing domain based on a potentially variable positioning of the sampling times (in the ADC direction) and similarly, for example, the holding times (in the DAC direction).

[0023] The processing circuit 105, which processes the sampled values ​​based on the sampling times, can include taking the sampling times into account when processing them. For example, it can consider whether the sampling times differ from a predefined grid and, for instance, how much they differ from the predefined grid. Through interpolation and / or extrapolation, the processing circuit 105 can, for example, generate sampled values ​​at the times specified in the predefined grid from the sampled values ​​provided by the sampling circuit 103.

[0024] The components of the signal processing device (e.g., the sampling timer circuit, the sampling circuit, and the processing circuit) can be implemented by one or more circuits. A "circuit" can be understood as any type of logic-implementing entity, which may be a specialized integrated circuit or a processor that executes software stored in memory, firmware, or any combination thereof. Thus, a "circuit" can be a hard-wired logic circuit or a programmable logic circuit such as a programmable processor, e.g., a microprocessor. A "circuit" can also be a processor that executes software, e.g., any type of computer program. Any other type of implementation of the respective functions, which are described in more detail below, can also be understood as a "circuit."

[0025] It should also be noted that the sampling time control circuit 101 and the processing circuit 105 can be implemented by the same circuit, e.g. a processor such as a DSP (digital signal processor).

[0026] The signal processing device 100, for example, introduces a feature as described in Fig. The procedure described in section 2 was carried out.

[0027] Fig. Figure 2 shows a flowchart 200, which represents a procedure for processing a signal, for example, by a signal processing device.

[0028] In 201, the signal processing device provides a sequence of digital values, each digital value specifying a sampling time from a sequence of sampling times. If desired, and as in 201, the signal processing device can be used to deliberately introduce jitter across the sampling times, for example, to avoid aliasing effects, with the noise introduced with the jitter then being removed based on the knowledge of the sampling times. In other words, various aspects of this disclosure can modify the deliberate introduction of jitter in response to a measured signal quality (e.g., of the digitized signal).

[0029] In 202, the signal processing device samples an input signal according to the sequence of sampling times in order to generate a sample value of the input signal for each sampling time of the sequence of sampling times.

[0030] In section 203, the signal processing device processes the sampled values ​​based on the sampling times. If desired, and as described in section 203, the signal processing can remove the noise introduced with the jitter deliberately introduced in section 201, based on knowledge of the sampling times.

[0031] The following examples relate to further embodiments.

[0032] Examples are described in more detail below.

[0033] Fig. Figure 3 shows a signal processing device 300.

[0034] The signal processing circuit 300 comprises a digital signal processor (DSP) 301, a first digital time converter (DTC) 302, an analog-to-digital converter (ADC) 303, a digital-to-analog converter (DAC) 304 and a second digital time converter (DTC) 305.

[0035] Each of the DTCs 302 and 305 is a functional block that positions the edges of a rectangular waveform (generally a periodic waveform) at a specific point in time according to a digital code. The positioning of the edges is determined, for example, with respect to a predefined underlying grid of fixed and equally spaced discrete-time points. The edges are positioned sequentially and independently at times slightly ahead or behind the grid.

[0036] In this example, the signal processing device receives an analog signal A(t), i.e., a continuous-time signal.

[0037] The signal enters the analog-to-digital converter (ADC) 303, which processes the signal A(t) through an anti-aliasing filter (AAF) 306, a sampler (for time discretization) 307, a quantizer (for amplitude discretization) 308, and an encoder 309. The encoder 309 assigns a digital code to each quantized layer, i.e., each quantized, sampled, anti-aliasing-filtered amplitude value of the signal A(t). The encoder 309 may include a filter, a decimator, etc.

[0038] The first digital time converter 302 triggers the probe 307 at the desired sampling times. These sampling times are determined in the DSP 301. For each sampling time, the first digital time converter 302 receives a code from the DSP 301 specifying the desired sampling time (e.g., in the form of a timestamp). The first digital time converter 302 generates a rectangular waveform with edges corresponding to the specified sampling times and triggers the probe 307 accordingly.

[0039] The ADC 303 provides the DSP 301 with the result of the sampling (after quantization and encoding), i.e., for each sampling time, a value (e.g., represented by a byte) indicating the quantized sampled amplitude. Furthermore, in this example, the ADC 303 provides, for each sampling time, a value (e.g., represented by a byte) indicating the sampling time (i.e., a timestamp of the quantized sampled amplitude). However, the DSP 301 can also be configured to synchronize quantized sampled amplitudes with the corresponding sampling times (and generate timestamps for the quantized sampled amplitudes itself). In this case, the ADC 303 does not need to return any timestamps to the DSP 301.

[0040] The DSP 301 can operate based on a fixed time grid (or several or fractions thereof, but strictly periodic). The interface between the DSP 301 and the first DTC 302 can also be based on a fixed time grid, as can the interface between the ADC 303 and the DSP 301. The interface between the first DTC 302 and the ADC 303 uses a time-variable grid (however, the timestamps are encoded with reference to a fixed time grid, e.g., by means of offsets).

[0041] To allow the DSP 301 to process the digital signal provided by the ADC 303 within a fixed time grid, the DSP 301 can, for example, interpolate or extrapolate the amplitude values ​​to achieve amplitude values ​​for a fixed time grid. The DSP 301 could then, for example, apply a discrete Fourier transform or similar processing.

[0042] The DSP 301 is capable of processing amplitude stamps along with timestamps. For example, the DSP 301 can generate timestamps according to a given pattern, such as sinusoidal, two alternating planes, pseudorandom, etc., and provide them to the first DTC 302 for generation and sampling in the ADC 303. Since the DSP 301 knows which timestamp to apply to each amplitude sample, it can apply filtering for extrapolation, derivatives, or any other suitable algorithm to correct the measurement (i.e., to achieve amplitude values ​​within a fixed time grid). By varying the sampling times, the DSP 301 can generate jitter (i.e., fluctuation) during sampling by the sampler 307, which can, for example, allow the DSP 301 to spread the power of an interference signal located in the aliasing bands of the input signal.

[0043] Fig. Figure 4 shows a diagram 400, which is an example of sampling times determined by the DSP 301 and provided to the first DTC 302 using timestamps.

[0044] The sampling times are given along a time axis 401. In this example, the DSP 301 specifies the sampling times with respect to a predefined grid (i.e., a predefined pattern) of time points. In this example, the DSP 301 has determined sampling times 403 that differ from the time points 402 by a specific time offset Δt in alternating order. This means that the first sampling time differs from the first time point of the predefined grid by -Δt, that the second sampling time differs from the second time point of the predefined grid by +Δt, that the third sampling time differs from the third time point of the predefined grid by -Δt, and so on.

[0045] Other patterns can be used and the differences between the sampling times and the times of the predefined grid can also be randomized (for example, it can be randomly determined whether a sampling time differs from a time of the predefined grid by +Δt or -Δt).

[0046] The period length T of the previously defined grid is, for example, 1 ms and Δt is, for example, 10 ns.

[0047] For example, if the input signal corresponds to a received radio signal, the variation of sampling times by the DSP 301 can be used to spread the power of an interfering signal (e.g., with a narrow spectrum in an aliasing band of the input signal) over a wider spectrum.

[0048] The DSP 301, the first TDC 302, and the ADC 303 could be part of a closed (control) loop that uses a minimization algorithm or, more generally, an algorithm with a cost function (e.g., in terms of disturbances to minimize disturbances by varying the sampling times, e.g., by varying Δt in Fig. 4) executes. Thus, the DSP 301 can, for example, weigh jitter, which is introduced by varying the sampling times from a predetermined grid, against a reduction of disturbances achieved by varying the sampling times from the predetermined grid.

[0049] The DAC 304 can, for example, include a decoder, a code-to-electrical variable converter, a holding circuit, and an anti-imaging or smoothing filter (AIF). To output an analog signal B(t), the DSP 301 sends timestamps of amplitude values ​​to the second DTC 305 and the amplitude values ​​themselves to the DAC 304. In this case, the DSP 301 can apply any suitable algorithm to generate timestamps to fulfill a desired processing goal. With regard to the DSP processing capabilities, the DAC path, due to its open-loop nature, can be considered inherently limited.

[0050] Fig. Figure 5 shows a device 500, including the signal processing device 100. Fig. 1.

[0051] The device 500 can be a radio communication device such as a radio communication terminal device (e.g., a user device (UE)) or a radio base station (e.g., a NodeB or an eNodeB). The device 500 can be an antenna 501 and a radio frequency (RF) circuit 503 coupled to the antenna 501. A radio signal 502 received by the antenna 501 can be applied to the RF circuit 503. The RF circuit 503 can process the radio signal 502 according to one or more radio communication technologies implemented in the RF circuit 503 (e.g., LTE (Long Term Evolution) and / or LTE-A (Long Term Evolution Advanced) or any other type of 3G or 4G radio communication technology). The RF circuit 503 can include one or more circuits that, for example, B. implement filtering, impedance matching, signal amplification, frequency conversion (e.g. using a local oscillator signal) and the like.For example, the radio signal 502 is an analog signal, and the signal processing in the RF circuit 503 can be performed in the analog signal domain. In the example shown, an output signal of the RF circuit 503 can be an analog signal and can be applied to the input signal 104. Fig. The signal processing device 100 can process the analog input signal 104 as described above and can convert the analog input signal 104 into a digitized signal 504. The signal processing device 100 can provide the digitized signal 504 to a baseband circuit 505, which can operate entirely in the digital signal domain. The baseband circuit 505 can include one or more circuits that implement, for example, filtering, impedance matching, signal amplification, and other baseband functions as required. The baseband circuit 505 can output a processed baseband signal 506 to one or more microprocessors 507 for further processing such as channel decoding and the like.

[0052] However, it should be noted that the analog-to-digital conversion, and thus the signal processing device, accounts for 100% of Fig. 1 can be provided within the RF circuit 503 so that some parts of the RF circuit 503 can operate in the analog signal domain, while some other parts of the RF circuit 503 can operate in the digital signal domain.

[0053] Fig. Figure 6 shows a flowchart 600, which illustrates how the sampling time control circuit 101 performs the determination of the sequence of sampling times.

[0054] As described above, the sampling time control circuit 101 can determine the sampling times based on a quality measure of the digitized version of the input signal. For example, the sampling time control circuit 101 can be configured to perform a process, as shown in flowchart 600, to determine the sampling times. After starting the process and initializing the index i to a value of "0" in 601, the sampling time control circuit 101 can determine preliminary sampling times, which may correspond to a (e.g., regular) grid of predefined sampling times that may be stored in a memory of the device. The preliminary sampling time i can be changed by a small offset (e.g., the offset ±ΔT, as described above) or can remain unchanged during the process.In other words, as described in more detail below, the sampling time control circuit 101 may or may not add jitter (e.g., a positive or negative time offset) to a sampling time i. To this end, process 603 determines a digitized version of the input signal 104 at the respective sampling time i. Then, in 604, the process determines the amount of jitter present in the digitized version of the input signal 104 at the respective sampling time i, followed by comparing the determined amount of jitter with a predefined first threshold (in 605). If the determined amount of jitter is less than the predefined first threshold ("Yes" in 605), the process increments the time index i by a predefined value, e.g., by the value "1", and continues in 607 to add jitter to the sampling time of the new time index i.The process can then continue in 603 and is repeated from there. However, if the determined amount of jitter is not less than the previously defined first threshold ("No" in 605), the process can proceed to determine an amount of noise in the digitized version of the input signal 104 at the respective sampling time i (in 608), followed by comparing the determined amount of noise with a previously defined second threshold, which may differ from the first threshold (in 609). If the determined amount of noise is less than the previously defined second threshold ("Yes" in 609), the process increments the time index i by a previously defined value, e.g., by the value "1", and continues in 607 by adding jitter to the sampling time of the new time index i. The process can then proceed in 603 and is repeated from there.However, if the specified amount of disturbances is not less than the previously defined second threshold ("No" in 609), the process can increment the time index i by a previously defined value, e.g., by the value "1", and can continue in 612 without adding any jitter to the sampling time i. In other words, in this case, the respective sampling time i remains unchanged. The process can then continue in 603, and the process is repeated from there.

[0055] It should be noted that the process can dispense with aspects 604, 605, and 606 in alternative ways. In other words, this process can only measure the amount of noise in the digitized version of the input signal, and the change in the addition of jitter to the respective sampling time can only be based on the measured amount of noise.

[0056] Furthermore, the process can omit steps 608, 609, and 610 in alternative aspects. In other words, this process can only measure the amount of jitter in the digitized version of the input signal, and the change in adding jitter to the respective sampling time can only be based on the measured amount of noise.

[0057] Example 1 is like in Fig. 1. Signal processing device shown.

[0058] In Example 2, the subject of Example 1 can optionally include the sampling time control circuit being configured to provide multiple digital values, each digital value specifying an offset with respect to a respective sampling time of a predetermined grid of multiple time points.

[0059] In Example 3, the subject of Example 2 can optionally include the fact that the sampling time control circuit is configured to provide the previously defined grid of multiple time points as a periodic sequence of multiple time points.

[0060] In Example 4, the subject matter can optionally include from any of Examples 2-3 that the processing circuit is configured to generate further samples at the times of the previously specified grid of times by interpolation, extrapolation, or both of the samples.

[0061] In Example 5, the subject matter can optionally include from any of Examples 1-4 that the sampling time control circuit is configured to provide the sampled values ​​as samples of the amplitude of the input signal.

[0062] In Example 6, the subject matter can optionally include from any of Examples 1-5 that the sampling time control circuit is configured to determine the sequence of sampling times.

[0063] In Example 7, the subject of Example 6 can optionally include the fact that the sampling time control circuit is configured to determine the sequence of sampling times by varying the time intervals between adjacent sampling times based on a quality measure of the samples.

[0064] In Example 8, the subject matter can optionally include from any of Examples 6-7 that the processing circuit is configured to generate a digitized version of the input signal based on the samples, and that the sampling time control circuit is configured to determine the sequence of sampling times based on a quality measure of the digitized version of the input signal.

[0065] In Example 9, the subject of Example 8 can optionally include the sampling time control circuit being configured to provide the quality measure based on an amount of jitter in the digitized version of the input signal.

[0066] In Example 10, the subject matter can optionally include from any of Examples 8-9 that the sampling time control circuit is configured to provide the quality measure based on a quantity of disturbances in the digitized version of the input signal.

[0067] In Example 11, the subject matter can optionally include from any of Examples 8-10 that the processing circuit is configured to reconstruct transmission data from the digitized version of the input signal.

[0068] In Example 12, the subject of Example 11 can optionally include the sampling time control circuit being configured to receive the input signal, which includes a modulated carrier signal representing the transmission data.

[0069] In Example 13, the subject matter of any of Examples 1-12 may optionally include the fact that the sampling time control unit is configured to vary a time interval between two successive sampling times of the sequence of sampling times over the sequence of sampling times.

[0070] In Example 14, the subject of Example 13 can optionally include the processing circuit being configured to remove jitter from the samples introduced by varying the time interval between two successive samples of the sequence of samples.

[0071] Example 15 is like in Fig.2. Method for processing a signal shown.

[0072] In Example 16, the subject of Example 15 can optionally include each digital value specifying an offset with respect to a respective sampling time of a previously defined grid of several points in time.

[0073] In Example 17, the subject of Example 16 can optionally include the fact that the previously defined grid of multiple sampling times is a periodic sequence of the multiple times.

[0074] In Example 18, the subject can optionally include from any of Examples 16-17 generating further sample values ​​at the times of the previously defined grid of times by interpolation, extrapolation or both of the sample values.

[0075] In Example 19, the subject can optionally include from any of Examples 15-18 that the sampled values ​​are samples of the amplitude of the input signal.

[0076] In Example 20, the subject can optionally include any of Examples 15-19 to determine the sequence of sampling times.

[0077] In Example 21, the subject of Example 20 can optionally include determining the sequence of sampling times by varying the time intervals between adjacent sampling times based on a quality measure of the samples.

[0078] In Example 22, the subject can optionally include from any of Examples 20-21, generating a digitized version of the input signal based on the sampled values ​​and determining the sequence of sampling times based on a quality measure of the digitized version of the input signal.

[0079] In Example 23, the subject of Example 22 can optionally include the fact that the quality measure is based on an amount of jitter in the digitized version of the input signal.

[0080] In Example 24, the subject matter can optionally include from any of Examples 22-23 that the quality measure is based on a quantity of disturbances in the digitized version of the input signal.

[0081] In Example 25, the subject can optionally comprise any of Examples 22-24, reconstructing transmission data from the digitized version of the input signal.

[0082] In Example 26, the subject of Example 25 can optionally include the input signal comprising a modulated carrier signal representing the transmission data.

[0083] In Example 27, the subject can optionally comprise any of Examples 15-26, varying a time interval between two successive sampling times of the sequence of sampling times over the sequence of sampling times.

[0084] In Example 28, the subject of Example 27 may optionally include removing jitter from the samples introduced by varying the time interval between two successive samples of the sequence of samples.

[0085] Example 29 is a computer-readable medium on which instructions are recorded which, when executed by a processor, cause the processor to perform a procedure for processing a signal according to any one of Examples 15 to 28.

[0086] Example 30 is a signal processing device comprising a sampling time control means for providing a sequence of digital values, wherein each digital value specifies a sampling time of a sequence of sampling times, a sampling means for sampling an input signal according to the sequence of sampling times in order to produce a sample of the input signal for each sampling time of the sequence of sampling times, and a processing means for receiving the samples and processing the samples based on the sampling times, wherein the sampling time control means is configured to introduce jitter into the sampling times by varying the time intervals between adjacent sampling times.

[0087] In Example 31, the subject of Example 30 may optionally include the sampling time control means being configured to provide multiple digital values, each digital value specifying an offset with respect to a respective sampling time of a predetermined grid of multiple time points.

[0088] In Example 32, the subject of Example 31 may optionally include the fact that the sampling time control means is configured to provide the predetermined grid of sampling times as a periodic sequence of time points.

[0089] In Example 33, the subject of any of Examples 31-32 may optionally include the processing means being configured to generate further samples at the times of the previously specified grid of times by interpolation, extrapolation, or both of the samples.

[0090] In Example 34, the subject matter can optionally include from any of Examples 30-33 that the sampling time control means is configured to provide the samples as samples of the amplitude of the input signal.

[0091] In Example 35, the subject matter can optionally include from any of Examples 30-34 that the sampling time control is configured to determine the sequence of sampling times.

[0092] In Example 36, the subject of Example 35 may optionally include the fact that the sampling time control means is configured to determine the sequence of sampling times based on a quality measure of the samples.

[0093] In Example 37, the subject of any of Examples 35-36 may optionally include the processing means being configured to generate a digitized version of the input signal based on the samples, and the sampling time control means being configured to determine the sequence of sampling times based on a quality measure of the digitized version of the input signal.

[0094] In Example 38, the subject of Example 37 may optionally include the sampling time control means being configured to provide the quality measure based on an amount of jitter in the digitized version of the input signal.

[0095] In Example 39, the subject matter can optionally include from any of Examples 37-38 that the sampling time control means is configured to provide the quality measure based on a quantity of disturbances in the digitized version of the input signal.

[0096] In Example 40, the subject matter can optionally include from any of Examples 37-39 that the processing means is configured to reconstruct transmission data from the digitized version of the input signal.

[0097] In Example 41, the subject of Example 40 may optionally include the scanning means being configured to receive the input signal which includes a modulated carrier signal representing the transmission data.

[0098] In Example 42, the subject matter of any of Examples 30-41 may optionally include the fact that the sampling time control unit is configured to vary a time interval between two successive sampling times of the sequence of sampling times over the sequence of sampling times.

[0099] In Example 43, the subject of Example 42 may optionally include the processing means being configured to remove jitter from the samples introduced by varying the time interval between two successive samples of the sequence of samples.

[0100] It should be noted that one or more of the features from any of the above examples can be combined with any of the other examples.

[0101] Although specific aspects have been described, it is apparent to those skilled in the art that various changes to form and detail can be made without altering the essence and scope of protection of the aspects of this disclosure as defined by the attached claims. The scope of protection is thus specified by the attached claims, and all modifications that fall within the meaning and scope of equivalence of the claims are therefore intended to be included.

Claims

[1] Signal processing device comprising: a sampling time control circuit configured to provide a sequence of digital values, wherein each digital value specifies a sampling time from a sequence of sampling times, wherein the sampling time control circuit is configured to provide multiple digital values, wherein each digital value specifies an offset with respect to a respective sampling time of a predetermined grid of multiple points in time; a sampling circuit configured to sample an input signal according to the sequence of sampling times in order to generate a sample value of the input signal for each sampling time of the sequence of sampling times; a processing circuit configured to receive the sampled values ​​and configured to process the sampled values ​​based on the sampled times, wherein the sampled time control circuit is configured to introduce jitter into the sampled times by varying the time intervals between adjacent sampled times, and wherein the processing circuit is configured to generate further sampled values ​​at the times of the previously specified grid of time points by interpolation, extrapolation, or both of the sampled values. [2] Signal processing device according to claim 1, wherein the sampling time control circuit is configured to provide the predetermined grid of multiple time points as a periodic sequence of multiple time points. [3] Signal processing device according to claim 1, wherein the sampling time control circuit is configured to provide the sampled values ​​as sampled values ​​of the amplitude of the input signal. [4] Signal processing device according to claim 1, wherein the sampling time control circuit is configured to determine the sequence of sampling times. [5] Signal processing device according to claim 4, wherein the sampling time control circuit is configured to determine the sequence of sampling times by varying the time intervals between adjacent sampling times based on a quality measure of the sampled values. [6] Signal processing device according to claim 4, wherein the processing circuit is configured to generate a digitized version of the input signal based on the sampled values, and the sampling time control circuit is configured to determine the sequence of sampling times based on a quality measure of the digitized version of the input signal. [7] Signal processing device according to claim 6, wherein the sampling time control circuit is configured to provide the quality measure based on an amount of jitter in the digitized version of the input signal. [8] Signal processing device according to claim 6, wherein the sampling time control circuit is configured to provide the quality measure based on a quantity of disturbances in the digitized version of the input signal. [9] Signal processing device according to claim 6, wherein the processing circuit is configured to reconstruct transmission data from the digitized version of the input signal. [10] Signal processing device according to claim 9, wherein the sampling time control circuit is configured to receive the input signal comprising a modulated carrier signal representing the transmission data. [11] Signal processing device according to claim 1, wherein the sampling time control unit is configured to vary a time interval between two successive sampling times of the sequence of sampling times over the sequence of sampling times. [12] Signal processing device according to claim 11, wherein the processing circuit is configured to remove jitter from the samples introduced by varying the time interval between two successive sampling times of the sequence of sampling times. [13] Method for processing a signal comprising: Providing a sequence of digital values, wherein each digital value specifies a sampling time from a sequence of sampling times, wherein each digital value specifies an offset with respect to a respective sampling time of a predetermined grid of multiple time points; Sampling an input signal according to the sequence of sampling times to generate a sample value of the input signal for each sampling time of the sequence of sampling times; Processing the sampled values ​​based on the sampling times and introducing jitter into the sampling times by varying the time intervals between adjacent sampling times; and generating further sampled values ​​at the times of the previously defined grid of times by interpolation, extrapolation or both of the sampled values. [14] Method according to claim 13, wherein the predetermined grid of multiple sampling times is a periodic sequence of the multiple sampling times. [15] Method according to claim 13, wherein the sampled values ​​are sampled values ​​of the amplitude of the input signal. [16] Method according to claim 13, comprising determining the sequence of sampling times. [17] Method according to claim 16, comprising determining the sequence of sampling times by varying the time intervals between adjacent sampling times based on a quality measure of the sampled values. [18] Method according to claim 16, comprising generating a digitized version of the input signal based on the sample values ​​and determining the sequence of sampling times based on a quality measure of the digitized version of the input signal. [19] Method according to claim 18, wherein the quality measure is based on an amount of jitter in the digitized version of the input signal. [20] Method according to claim 18, wherein the quality measure is based on a quantity of disturbances in the digitized version of the input signal. [21] Computer-readable medium on which instructions are recorded which, when executed by a processor, cause the processor to perform a method for processing a signal according to any one of claims 13 to 20.

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