SEMICONDUCTOR DEVICE

Abstract

Semiconductor device (100) comprising: - an n-type drift layer (10); - a p-type base layer (7a, 7b) arranged on an upper surface side of the drift layer (10); - an n-type emitter layer (6) selectively arranged on an upper surface side of the base layer (7a, 7b); - a trench gate (1) enabling a trench gate electrode to be in contact with the emitter layer (6), the base layer (7a, 7b) and the drift layer (10) via a gate insulating layer, the trench gate electrode being embedded such that it extends from a surface layer of the emitter layer (6) to the drift layer (10);- a dummy trench gate (2, 3) which allows a dummy trench gate electrode to be in contact with the base layer (7a, 7b) and the drift layer (10) via a gate insulating layer, wherein the dummy trench gate electrode is embedded such that it extends from a surface layer of the base layer (7a, 7b) to the drift layer (10), and wherein the dummy trench gate (2, 3) is a trench gate in which no channel is formed on a lateral surface; - a p-type collector layer (12) arranged on a lower surface side of the drift layer (10);and a diode (21) whose anode and cathode sides are electrically connected to the trench-gate electrode and the dummy trench-gate electrode, respectively, and wherein the semiconductor device has a plurality of dummy trench gates (2, 3), wherein one or some (3) of the plurality of dummy trench-gate electrodes is or are electrically connected to an emitter electrode arranged on the emitter layer (6), and the other(s) (2) of the dummy trench-gate electrodes is / are electrically connected to the cathode side of the diode (21), and wherein the diode (21a) has a plurality of diodes connected in series.

Description

TECHNICAL AREA

[0001] The present invention relates to a semiconductor device comprising a trench gate. STATE OF THE ART

[0002] Inverters for industrial use, household electrical appliances, and the like incorporate a semiconductor device, such as a power module with a power semiconductor element mounted within it. In particular, a semiconductor device incorporating a single-gate IGBT (Insulated Gate Bipolar Transistor) is widely used due to its excellent controllability and energy efficiency.

[0003] The single-trench-gate IGBT has a trench gate formed in strips on the surface of a semiconductor substrate, which has a p-type base layer formed on a surface layer region of an n-type drift layer, and which is formed in such a way that it penetrates the p-type base layer and extends to the n-type drift layer.

[0004] In contact with a lateral surface (side surfaces) of one or some of the trench gates, an n-type emitter layer is configured such that a channel is formed in the p-type base layer at the lateral surface (side surfaces) of the trench gate (trenches) that is in contact with the n-type emitter layer.

[0005] On the lateral surface(s) of the other trench gate(s), no n-type emitter layer is formed to accumulate holes (positive holes) in the p-type base layer(s) in contact with the lateral surface(s) when the trench-gate IGBT is switched on. The so-called dummy trench gate is a trench gate on a lateral surface where no n-type emitter layer is formed and therefore no channel is formed.

[0006] On the other hand, the so-called active trench gate is a trench gate with a channel on its lateral surface to which a gate voltage is applied by a gate driver circuit. Furthermore, the so-called active dummy trench gate is a special type of dummy trench gate to which the gate voltage is applied by the gate driver circuit in the same way as with the active trench gate.

[0007] In a single-trench-gate IGBT, a conventional semiconductor device, one or more dummy trench gates are connected to a gate terminal to make them active dummy trench gates, and the other dummy trench gate(s) are connected to an emitter terminal to make it (them) dummy trench gate(s). This results in increased parasitic capacitance between a gate and a collector compared to a case where the active dummy trench gates are not connected to the gate terminal.

[0008] Therefore, the gate resistance is reduced so that the rate of change of the collector voltage with respect to time (dV / dt) at the time of switching on the IGBT is at the same level as in conventional cases, so that the rate of change of the collector current with respect to time (dI / dt) is reduced, so that turn-on losses at constant dV / dt are reduced (see, for example, patent document 1). STATE OF THE ART Patent document

[0009] Patent document 1: WO 2015 / 162 811 A SHORT DESCRIPTION Problem to be solved with the invention

[0010] In a conventional semiconductor device described in patent document 1, an active dummy trench gate as well as an active trench gate with a channel formed on a lateral surface of the same are connected to a gate terminal, so that it is possible to reduce a gate resistance when an IGBT is switched on, while maintaining the same dV / dt.However, part of the parasitic capacitance between a gate and a collector is a parasitic capacitance that is assigned to the active dummy trench gate in which an electrical charge is accumulated, and a current generated by the electrical charge charges a capacitance between the gate and an emitter without flowing through a gate resistor at the time the IGBT is switched on, so that sometimes the value of dV / dt is excessively increased, which leads to a problem in terms of a deterioration of the controllability of dV / dt by the gate resistor.

[0011] The present invention was designed to solve the problem described above, and the object of the present invention is to provide a semiconductor device that suppresses the current that charges the capacitance between the gate and the emitter without flowing through the gate resistor, and which improves the controllability of dV / dt by the gate resistor. Means to solve the problem

[0012] A semiconductor device according to the present invention has the following features: a drift layer of a first conductivity type; a base layer of a second conductivity type, which is arranged on an upper surface side of the drift layer; an emitter layer of the first conductivity type, which is arranged on an upper surface side of the base layer; a trench-gate which allows a trench-gate electrode to be in contact with the emitter layer, the base layer and the drift layer via a gate insulating layer, wherein the trench-gate electrode is embedded such that it extends from a surface layer of the emitter layer to the drift layer; a dummy trench gate which allows a dummy trench gate electrode to be in contact with the base layer and the drift layer via a gate insulating layer, wherein the dummy trench gate electrode is embedded such that it extends from a surface layer of the base layer to the drift layer; a collector layer of the second conductivity type, arranged on a lower surface side of the drift layer; as well as a diode whose anode side and cathode side are electrically connected to the trench-gate electrode and the dummy trench-gate electrode, respectively. Effects of the invention

[0013] The semiconductor device according to the present invention suppresses the current that charges the capacitance between the gate and the emitter without flowing through the gate resistor, so that it is possible to improve the controllability of the value of dV / dt by the gate resistor. List of characters

[0014] The characters include: Fig. 1 a schematic cross-sectional view representing a semiconductor device according to a first embodiment of the present invention; Fig. 2 a schematic cross-sectional view representing another semiconductor device according to the first embodiment of the present invention; Fig. 3 an enlarged cross-sectional structural view representing an IGBT element forming the semiconductor device according to the first embodiment of the present invention; Fig. 4 An enlarged cross-sectional structural view showing an IGBT element forming a conventional semiconductor device; Fig. 5 Circuit diagrams representing equivalent circuits of the conventional semiconductor device and the semiconductor device according to the first embodiment of the present invention; Fig. 6 diagrams showing a relationship between the gate resistance value and dV / dt in the IGBT element forming the conventional semiconductor device, as well as a measurement result for a waveform of a voltage between the gate and the emitter at the time of switching on the IGBT element; Fig. 7 an enlarged cross-sectional structural view representing an IGBT element forming a semiconductor device with a further configuration according to the first embodiment of the present invention; Fig. 8 an enlarged structural cross-section representing an IGBT element forming a semiconductor device according to a second embodiment of the present invention; Fig. 9 an enlarged structural cross-section representing an IGBT element forming a semiconductor device with a further configuration according to the second embodiment of the present invention; Fig. 10 an enlarged structural cross-sectional view representing an IGBT element forming a semiconductor device according to a third embodiment of the present invention; Fig. 11 an enlarged structural cross-sectional view showing a peripheral element area of ​​the IGBT element forming the semiconductor device according to the third embodiment of the present invention; Fig. 12 an enlarged structural cross-sectional view representing an IGBT element forming a semiconductor device according to a fourth embodiment of the present invention; Fig. 13 an enlarged structural cross-sectional view representing an IGBT element forming a semiconductor device according to a fifth embodiment of the present invention; Fig. 14 an enlarged structural cross-sectional view showing a peripheral element area of ​​an IGBT element forming a semiconductor device according to a sixth embodiment of the present invention; Fig. 15 an enlarged structural cross-sectional view showing a peripheral element area of ​​an IGBT element forming a semiconductor device with a further configuration according to the sixth embodiment of the present invention. DESCRIPTION OF EXECUTION FORMS First embodiment

[0015] First, a configuration of a semiconductor device according to a first embodiment of the present invention is described. Fig. Figure 1 is a schematic cross-sectional view representing the semiconductor device according to the first embodiment of the present invention.

[0016] In the following description, n and p denote the conductivity type of a semiconductor, and the present invention is described such that a first conductivity type and a second conductivity type are defined as an n-type and a p-type, respectively. Furthermore, n - a lower concentration of impurities than n again, and n + This represents a higher concentration of impurities than n. Similarly, p represents - a lower impurity concentration than p again, and p + indicates a higher concentration of impurities than p.

[0017] According to Fig. 1 features a semiconductor device 100 an IGBT element 20 of the trench-gate type, a diode 21 as well as a gate resistor 22 on. The IGBT element 20 , the diode 21 and the gate resistance 22 are connected to the surface of an electrode (not shown) which is structured and formed on a substrate 24. The substrate 24 is attached to the surface of an insulating element 25 formed from a ceramic or resin; the insulating element 25 is attached to the surface of a metal plate 26, such as copper or aluminum, with high thermal conductivity; a housing 28 completely covers these components; and a sealing resin 27 is enclosed in the housing 28.

[0018] Furthermore, the housing 27 is provided with a gate terminal 30, an emitter terminal 31, and a collector terminal 32, which are exposed outside the housing 28 (or to the outside). The IGBT element 20 is connected to the diode by means of a wiring 23a, such as a wire or a plate made of a metallic material, such as copper or aluminium, with high electrical conductivity 21 connected, and the diode 21 is connected to the gate resistor via a wiring connection 23b 22 tied together.

[0019] Furthermore, an emitter electrode 4 of the IGBT element is 20 connected to the emitter terminal 31 by means of a wiring connection 23d, and a collector electrode 5 of the IGBT element 20 The collector terminal 32 is connected via a wire 23e. Furthermore, the gate terminal 30 is connected to the gate resistor via a wire 23c. 22 tied together.

[0020] The wiring 23a to 23e is not limited to wiring made from a wire or a plate, as shown in FIG. 1, but can also consist of wiring formed by a structuring on the substrate 24. Furthermore, a configuration in which the substrate 24, the insulating element 25, and the metal plate 26 are stacked is not limited to this example, but other configurations can also be used, such as a configuration in which the IGBT element 20 directly connected to the metal plate 26 to hold the IGBT element 20 It can be cooled without problems. Furthermore, the semiconductor device 100 a configuration that has no gate resistance 22 exhibits, or may exhibit a configuration that allows a user to connect the gate resistor to the gate connector for use.

[0021] Furthermore, the diode 21 and the gate resistance 22 in the IGBT element 20 be trained. Alternatively, the diode can be 21 in the IGBT element 20 be trained, and the gate resistance 22 can be arranged by connecting it to the gate terminal 30 outside the semiconductor device 100 (or to the outside) is connected.

[0022] Fig. Figure 2 is a schematic cross-sectional view depicting another semiconductor device according to the first embodiment of the present invention. Fig. 2 indicates a component that has the same reference symbol as the reference symbol of a component in Fig. 1, which has the identical configuration to the configuration of the component in Fig. 1 or a configuration that matches this, and the description for the component is omitted. Fig. Figure 2 is a cross-sectional view showing a semiconductor device 100 represents when the diode 21 and the gate resistance 22 in the IGBT element 20 are trained or when the diode 21 in the IGBT element 20 is trained and the gate resistance 22 outside the semiconductor device 100 is arranged.

[0023] The collector electrode of the IGBT element 20 is connected to the metal plate 26, and the IGBT element 20 is attached to the metal plate 26 and arranged in the housing 28. The sealing resin 27 is enclosed in the housing 28. In the IGBT element 20 The diode and gate resistor, or just the diode, are included. This diode and gate resistor can be integrally integrated with the IGBT element in a semiconductor process. 20 be formed.

[0024] For example, it is possible to form a diode by placing a pn junction at a gate wiring position in the IGBT element. 20 is formed, and it is possible to form a gate resistance by increasing the impurity concentration of the gate wiring area in the IGBT element. 20 is being discontinued.

[0025] Fig. Figure 3 is an enlarged cross-sectional structural view representing the IGBT element that forms the semiconductor device according to the first embodiment of the present invention. Fig. Figure 3 primarily shows the structure of IGBT element 20 of the in Fig. 1 Semiconductor device shown 100 in detail and shows the diode 21 and the gate resistance 22 through circuit symbols in a simplified way. Fig. Figure 3 is a cross-sectional view of the IGBT element. 20, especially in an active area of ​​the IGBT element that is orthogonal to the longitudinal lines of the trench gate.

[0026] An area that is in Fig. The 3 sandwich-like arrangement between the dashed lines AA and BB represents a unit IGBT, and the IGBT element 20 is configured to have a plurality of unit IGBTs arranged and formed horizontally along the paper surface.

[0027] According to Fig. 3 indicates the IGBT element 20 a base layer 7 of the p-type and a charge carrier accumulation layer 8 of the n-type, located on an upper surface side of a drift layer 10 from n - -type are formed from a semiconductor substrate of n - -type is formed, and has a plurality of trenches 16 that pass through the base layer 7of the p-type and the charge carrier accumulation layer 8 of the n-type. The charge carrier accumulation layer 8 of the n-type is not strictly necessary, and the IGBT element can also have a configuration that does not have a charge carrier accumulation layer 8 of the n-type.

[0028] On an inner wall of each of the trenches 16 is a gate insulating layer 14 trained, and in each of the trenches 16 is a trench-gate electrode 15 embedded, which is made of polysilicon containing n-type or p-type impurities, wherein the gate insulating layer 14 inserted between the trench and the trench-gate electrode, so that a trench-gate is formed.

[0029] This means that the trench gate is separated from a surface layer of the semiconductor substrate by n - -type through to the interior of the semiconductor substrate from n --type arranged. In the present invention, the surface layer refers to an area located on a surface of the semiconductor substrate from n - -Type is located on a side where the base layer 7 is of the p-type. As in Fig. As shown in Figure 3, the trench gates are connected to a first control electrode. 1 as an active trench gate and a second control electrode 2 subdivided into an active dummy trench gate.

[0030] In the present invention, a dummy trench gate refers to a trench gate that does not function as a gate, since no channel is formed on a lateral surface of the gate, and a special dummy trench gate, i.e. the active dummy trench gate, refers to a dummy trench gate to which a gate voltage from a gate driver circuit is applied in the same way as to the active trench gate.

[0031] On the other hand, a trench gate with a channel formed on its lateral surface, functioning as a gate, is in some cases simply referred to as a trench gate; however, it is referred to as an active trench gate when it is clearly distinct from the dummy trench gate and the active dummy trench gate, since the gate voltage is applied by the gate driver circuit.

[0032] Furthermore, if it is necessary to use the trench-gate electrode 15 To distinguish specifically between the active trench gate and the dummy trench gate, reference is made to the trench gate electrode. 15 of the active trench gate as an active trench gate electrode, and to the trench gate electrode 15 The dummy trench gate is referred to as a dummy trench gate electrode. Furthermore, the trench gate electrode is also referred to. 15of the active dummy trench gate, to which the gate voltage is applied, is referred to as an active dummy trench gate electrode when a distinction is necessary.

[0033] In a sub-area of ​​a surface layer region of the base layer 7 of the p-type, which comes into contact with the first control electrode 1 The emitter layer 6 of the n is located there + -type and a contact layer 9 from p + -type formed, and for the active trench gate is the emitter layer 6 from n + -Type in contact with a lateral surface of the trench 16 trained. That is, in the case of a trench gate that spans the trench 16 exhibits, one or both of whose lateral surfaces are in contact with the n + -Emitter layer 6 is the active trench gate, and the active trench gate is the first control electrode. 1 in the first embodiment.

[0034] On the other hand, for the active dummy trench gate, a lateral surface of the trench is required. 16 no emitter layer 6 from n + -Type trained. That means, in the case of a trench gate that has no trench 16 in contact with the n + -Emitter layer 6, this is the active dummy trench gate, and the active dummy trench gate is the second control electrode. 2 in the first embodiment.

[0035] Furthermore, the base layers are 7 from the p-type into a first base layer 7a of the p-type, which come into contact with the first control electrode 1 than the active trench gate, and a second base layer 7b subdivided from the p-type, which do not come into contact with the first control electrode 1 located and those of the second control electrodes 2 is surrounded by the active dummy trench gates.

[0036] The contact layer 9 from p + -Type is in contact with the emitter layer 6 from n + -type arranged. The emitter electrode 4 is located on partial surfaces of the contact layer 9 from p + -type and the emitter layer from n + -type arranged and is in contact with the contact layer 9 from p + -type and emitter layer 6 of n + -Type.

[0037] On the other partial surfaces of the contact layer 9 from p + -type and emitter layer 6 of n + -Type, an insulating intermediate layer 13 is formed to protect the contact layer 9 from p + -type and the emitter layer 6 from n + -Type to be isolated from the emitter electrode 4. In addition, the insulating intermediate layer 13 is located at the trench gates as the first control electrode. 1 and the second control electrode 2 as well as the second base layer7b designed of the p-type to isolate it from the emitter electrode 4.

[0038] On a lower surface side of the drift layer 10 from n - -type, which is made from the semiconductor substrate of the n - The -type consists of a buffer layer 11 of n-type and a collector layer. 12 The collector layer 12 is of the p-type. Furthermore, the collector electrode 5 is formed on the collector layer 12 of the p-type.

[0039] The first control electrode 1 is connected to a first gate contact point (not shown) located on a surface of the IGBT element 20 is arranged, and the second control electrode 2 is connected to a second gate contact point (not shown) located on a surface of the IGBT element 20 is arranged to form the IGBT element 20.

[0040] The diode 21is connected between the first gate contact and the second gate contact, with one anode and one cathode of the diode corresponding to the first gate contact and the second gate contact, respectively. That is, the anode and the cathode of the diode 21 are connected to the first control electrode 1 or the second control electrode 2 connected, as in Fig. 3 shown.

[0041] Furthermore, the first gate contact point is connected to one end of the gate resistance. 22 connected. The other end of the gate resistor 22 is connected to the gate terminal 30, which is located on the housing 28 of the semiconductor device 100 is arranged. If the semiconductor device 100 a configuration that has no gate resistance 22 The first gate contact point is connected to the gate terminal 30.

[0042] The emitter electrode 4 is connected to the emitter terminal 31, which is located on the housing 28 of the semiconductor device. 100 is arranged, and the collector electrode 5 is connected to the collector terminal 32, which is attached to the housing 28 of the semiconductor device 100 is arranged.

[0043] The semiconductor device 100 is configured as described above.

[0044] Next, the operation of the semiconductor device will be described. 100 described.

[0045] A main voltage Vce is applied between the emitter terminal 31 and the collector terminal 32 of the semiconductor device. 100 configured in such a way that the collector terminal 32 has a higher voltage. If the gate driver circuit is located outside the semiconductor device 100When a positive voltage is applied to the gate terminal 30 of the semiconductor device 100, a ion is formed in the first base layer. 7a of the p-type, which are in contact with a lateral surface of the trench 16 for the first control electrode 1 It is located, forming an inversion layer to open a channel.

[0046] Then electrons are released from the emitter layer. 6 from n + -Type into drift layer 10 from n - -type injected, passing through the n-type buffer layer 11 and the collector layer 12 of the p-type. In this process, holes (positive holes) are created in the collector layer. 12 from the p-type into the drift layer 10 from n - -Type injected to meet charge neutrality conditions. Some of the holes are from the collector layer. 12 injected from the p-type, runs from the first basal layer7a of the p-type through the contact layer 9 of the p + -Type through to the emitter electrode 4, from which the part of the holes from the IGBT element 20 flows out.

[0047] On the other hand, another part of the holes, which is not from the emitter electrode 4 of the IGBT element, reaches 20 flows out, the second base layer 7b of the p-type and is located in the second basal layer 7b accumulated of the p-type. Some of the holes that are in the second base layer 7b They accumulate of the p-type and flow as a hole current into the first base layer. 7a from the p-type. This increases the charge carrier density in a channel region of the first base layer. 7a The p-type increases and amplifies a conductivity modulation effect, thus reducing conduction losses of the IGBT element. 20 be reduced.

[0048] The one in the second base layer 7bHowever, the number of holes accumulated by the p-type increases at the time the IGBT element is switched on. 20 temporarily an electrical potential of the second base layer 7b of the p-type. The second base layer 7b of the p-type and the trench-gate electrode. 15 The second control electrode 2 form an electrostatic capacitance, since the trench 16 the second control electrode 2 the gate insulating layer 14 exhibits a feature that is formed on the inner wall of the same.

[0049] Therefore, a displacement current is caused by the increase in the electrical potential of the second base layer. 7b caused by the p-type, striving to reach the second control electrode 2 into the first control electrode 1 to flow in. However, diode 21 is located between the second control electrode. 2 and the first control electrode 1 is switched, with the cathode of the diode of the second control electrode2 corresponds, so that the displacement current, which tends to flow via the second control electrode 2 into the first control electrode 1 to flow in, through the diode 21 is prevented and does not enter the first control electrode 1 can flow into it.

[0050] This causes the current entering the first control electrode to 1 only a current flows in, which is supplied by the external gate driver circuit through the gate terminal 30, so that it is possible to control the turn-on time of the IGBT element. 20 by a resistance value of the gate resistor 22 to control the collector voltage, thus increasing its controllability. This means it is possible to control the rate of change of the collector voltage with respect to time (dV / dt) in the IBGT element. 20 to increase at the time the IGBT element is switched on.

[0051] Next, the operating principle of the semiconductor device will be explained. 100 The present invention is described in detail by comparing the semiconductor device according to the present invention with a conventional semiconductor device that does not contain a diode. 21 exhibits, which are located between the first control electrode 1 and the second control electrode 2 is switched on.

[0052] Fig. Figure 4 is an enlarged cross-sectional view representing an IGBT element that forms the conventional semiconductor device. A semiconductor device 200 according to Fig. 4 has a configuration where the diode 21 from the in Fig. 3 shown semiconductor device removed, the first control electrode 1 with the second control electrode 2 is connected and the gate resistance 22is connected to this connection between the first control electrode and the second control electrode. The semiconductor device 200 is identical to the semiconductor device 100 in Fig. 3, with the exception of the removal of the diode 21 .

[0053] At Fig. 5. These are circuit diagrams representing equivalent circuits of the conventional semiconductor device and the semiconductor device according to the first embodiment of the present invention. Fig. 5(a) to Fig. Figures 5(d) each show a lower branch in a half-bridge circuit. Fig. Figure 5(a) shows an equivalent circuit configured to have the conventional semiconductor device 200 as the lower branch in the half-bridge circuit, and Fig. 5(c) shows an equivalent circuit configured to replace the semiconductor device 100according to the present invention as having the lower branch in the half-bridge circuit.

[0054] Furthermore, Fig. 5(b) a circuit diagram showing the generation of the increase of the electrical potential in the second base layer 7b of the p-type at the time of switching on the conventional semiconductor device 200, and Fig. 5(d) is a circuit diagram that shows the generation of the increase in the electrical potential in the second base layer. 7b of the p-type at the time the semiconductor device is switched on 100 according to the present invention.

[0055] In the Fig. 5(a) to Fig. 5(d) is the IGBT element 20A freewheeling diode 40 is connected in parallel, and an anode and a cathode of the freewheeling diode 40 are connected to the emitter terminal 31 and the collector terminal 32, respectively. The main voltage Vce is applied between the emitter terminal 31 and the collector terminal 32 of the semiconductor device. 100 designed in such a way that the collector terminal 32 has a higher electrical potential.

[0056] A gate voltage Vge is applied between the emitter terminal 31 and the gate terminal 30 by the gate driver circuit outside the semiconductor devices 200 and 100 in such a way that the gate terminal 30 has a higher electrical potential. The gate voltage Vge is applied via the gate resistor 22 between the emitter and the gate of the IGBT element. 20 created.

[0057] In the Fig. 5(a) to Fig. 5(d) is a parasitic capacitance component of the IGBT element 20, represented by a dashed line. Cgc1 represents an electrostatic capacitance between the first control electrode. 1 and the collector electrode 5. Cgc2 represents an electrostatic capacitance between the second control electrode. 2 and the collector electrode 5 again.

[0058] Cge provides an electrostatic capacitance between the first control electrode 1 and the emitter electrode 4 again. A symbol ΔVdp, which appears in the Fig. 5(b) and Fig. Figure 5(d) shows the increase in electrical potential caused by an accumulation of holes in the second base layer. 7b of the p-type at the time the IGBT element is switched on 20 is generated.

[0059] First, according to Fig. 5(a) a conventional semiconductor device 200 is described. When the gate voltage Vge is applied by the gate driver circuit outside the semiconductor device 200, holes are extruded from the collector layer. 12 of the p-type in Fig. 4 are injected, which are not from the emitter electrode 4 of the IGBT element 20 have been removed, in the second base layer 7b of the p-type and generate the increase of the electrical potential ΔVdp in the same way as in the semiconductor device 100 according to the present invention, which is in Fig. 3 is shown.

[0060] As in Fig. As shown in 5(b), ΔVdp is equivalent to a DC voltage source that is connected in such a way between the parasitic capacitance Cgc2 and the collector electrode 5 of the IGBT element. 20 The circuit is such that the collector electrode 5 has a lower electrical potential.

[0061] As in Fig. 5(b) shows the flow from the collector of the IGBT element. 20 A displacement current Id is generated that charges the parasitic capacitance Cgc2 when the rise in the electrical potential ΔVdp occurs at the time the IGBT element 20 is switched on. The displacement current Id flows through the parasitic capacitance Cgc2 and the wiring, charges the parasitic capacitance Cge, and flows out of the emitter of the IGBT element. 20 out of here.

[0062] An increase in the amount of current flowing into the parasitic capacitance Cge due to the displacement current Id quickly opens the channel of the first p-type basal layer 7a, which comes into contact with the first control electrode. 1 located to switch on the IGBT element 20 to accelerate. The displacement current Id flows into the parasitic capacitance Cge without passing through the gate resistor. 22to flow through, making it difficult to determine the turn-on time of the IGBT element. 20 to control by adjusting the resistance value of the gate resistor 22.

[0063] That is, those in the second base layer 7b The p-type accumulated holes charge the parasitic capacitance Cge between the gate and the emitter of the IGBT element 20 and cause the displacement current Id to flow, which accelerates the turn-on, causing a problem in that the controllability of the rate of change of the collector voltage with respect to time (dV / dt) by the gate resistance 22 in the IGBT element 20 The value is reduced. An excessively high dV / dt value causes noise and overvoltage, so it is necessary to reduce the dV / dt value using the gate resistor. 22 to control it in a suitable manner.

[0064] At Fig. Figure 6 represents a relationship between the gate resistance value and dV / dt in the IGBT element forming the conventional semiconductor device, and a measurement result for a waveform of a voltage between the gate and the emitter at the time of switching on the IGBT element. Fig. Figure 6(a) shows a measurement result of dV / dt when the gate resistance value of the IGBT element is increased from 0 Ω compared to the conventional semiconductor device, and Fig. Figure 6(b) shows a measurement result for a waveform of a voltage between the gate and the emitter at the time of switching on the IGBT element at a gate resistance value greater than a gate resistance value at which the Fig. 6(a) shows a minimum value for dV / dt, that is, at a gate resistance value at which dV / dt begins to increase from the minimum value.

[0065] As in Fig. As shown in Figure 6(a), dV / dt decreases as the resistance of the gate resistor 22 increases from 0 Ω. However, dV / dt exhibits a minimum value for a given gate resistance value, and thereafter it increases as the gate resistance value increases. As described above, for the conventional semiconductor device 200, it has been found that it is impossible to adequately control dV / dt, even when the resistance of the gate resistor increases. 22 is being discontinued. As in Fig. As shown in Figure 6(b), the voltage between the gate and the emitter increases gradually from the beginning of the switch-on process, along with the charging of the parasitic capacitance between the gate and the emitter.

[0066] With a gate resistance value of the gate resistance 22However, where dV / dt does not decrease even with an increased gate resistance value, it was confirmed that an abrupt increase in voltage between the gate and the emitter is generated, as in Fig. 6(b) represented by an area surrounded by a dashed line.

[0067] This phenomenon is generated due to the charging of the parasitic capacitance Cge by the displacement current Id, as described above, and it is considered that this sudden change in the voltage between the gate and the emitter generates a high dV / dt. That is, in the conventional semiconductor device 200, it is impossible to prevent the charging of the parasitic capacitance Cge by the displacement current Id, so the problem with regard to a reduction in the controllability of dV / dt is caused by the gate resistor 22.

[0068] Furthermore, in the conventional semiconductor device, 200 holes flow into the second base layer. 7b of the p-type remain at the time the IGBT element is switched off. 20 in the same way as when the IGBT element is switched on 20 sometimes as the displacement current Id into the parasitic capacitance Cge, so that at the time of switching off the IGBT element 20 This may result in an incorrect power-on.

[0069] On the other hand, in the semiconductor device 100 according to the present invention the diode 21 , as in Fig. 3 shown, between the second control electrode 2 and the first control electrode 1 switched, whereby the anode and the cathode of the diode of the first control electrode 1 or correspond to the second control electrode 2, which is determined by the equivalent circuit in Fig. 5(c) is shown. Even if, at the time the IGBT element is switched on, there are 20 holes in the second base layer. 7b The p-type accumulated and the increase in the electric potential ΔVdp in the second base layer 7b of the p-type allows such a configuration that the diode 21 prevents the displacement current which tends to occur due to ΔVdp, so that the displacement current does not flow.

[0070] As in Fig. As shown in 5(d), the displacement current that charges the parasitic capacitance Cge does not flow, so that controlling the charging current of the parasitic capacitance Cge by means of the gate resistor 22 This is made possible. That is, dV / dt at the time the IGBT element is switched on. 20 can be done using the gate resistor 22 can be controlled.

[0071] This allows a manufacturer or user of the semiconductor device 100, the dV / dt of the IGBT element 20 by means of the gate resistor 22 , which is contained in the semiconductor device 100, or by means of an external gate resistor connected to the gate terminal 30 of the semiconductor device 100 is connected to set to some value so that the usability of the semiconductor device is improved by 100.

[0072] Furthermore, it is unlikely that the second base layer 7b p-type accumulated holes from the second base layer 7b are carried away by the p-type, so that holes are multiplied, forming a hole stream from the second base layer. 7b from the p-type into the first base layer 7a flow in from the p-type and amplify the conductivity modulation effect, thus reducing the conduction losses of the IGBT element. 20 This will be reduced. Furthermore, a displacement current will occur at the time the IGBT element is switched off.20 This prevents the Cge from being charged by the displacement current, thus preventing the generation of an incorrect switch-on.

[0073] To be precise, the diode exhibits a parasitic capacitance between the anode electrode and the cathode electrode when a reverse voltage ΔVdp is applied to the diode. 21 is pending. As a comparison between the Fig. 5(a) and Fig. 5(c) understandable, is the electrostatic capacitance of the IGBT element. 20 on a pathway that exhibits the parasitic capacity Cgc2, in Fig. 5(c) smaller and reduces the displacement current Id, which is due to the increase in the electric potential ΔVdp in the second base layer 7b of the p-type, even if the parasitic capacitance of the diode 21 This is taken into account. In particular, the use of a compact diode with a small parasitic capacitance can be considered as the diode 21cause the parasitic capacitance of the diode to increase 21 is essentially negligible.

[0074] Fig. Figure 7 is an enlarged cross-sectional view representing an IGBT element forming a semiconductor device with a further configuration according to the first embodiment of the present invention. In the Fig. In the semiconductor device shown in Figure 3, a plurality of second control electrodes 2 are connected, and the cathode of the diode 21 is connected to this connection of the second control electrodes.

[0075] During a Fig. 7 semiconductor device shown 100 However, the second control electrodes 2 are each connected to the cathodes of the diodes. 21 connected, and a first control electrode 1 is connected to the connection made by connecting the anodes of the diodes 21 is formed.

[0076] The in Fig. 7 Semiconductor device shown 100 also features the equivalent circuits that are in the Fig. 5(c) and Fig. 5(d) are shown, so that the same mode of operation results as that of the semiconductor device according to the present invention, which is shown in Fig. 3 is shown. As in Fig. Figure 7 shows a configuration in which the diodes 21 each as the second control electrodes 2 are arranged, for example, for a semiconductor device 100 suitable with a configuration where the diodes 21 in the IGBT element 20 formed using a semiconductor process.

[0077] As described above, the diode 21 in the semiconductor device 100 according to the first embodiment between the second control electrode 2 and the first control electrode 1arranged, wherein the anode and the cathode of the diode of the first control electrode 1 or the second control electrode 2 This configuration prevents the displacement current Id, which is caused by the increase in the electric potential ΔVdp in the second base layer, from corresponding. 7b caused by the p-type, into which Cge flows, resulting in an effect that generates an incorrect switch-on at the time of switch-off of the IGBT element. 20 is prevented, while the controllability of dV / dt at the time of switching on the IGBT element. 20 is increased.

[0078] Furthermore, this configuration results in an effect that increases the number of holes in the first base layer. 7a flow of the p-type to compensate for the conduction losses of the IGBT element. 20to reduce. These effects can provide a semiconductor device that is excellent in terms of energy saving, has great usability and high reliability. Second embodiment

[0079] Fig. Figure 8 is an enlarged structural cross-section representing an IGBT element forming a semiconductor device according to a second embodiment of the present invention. Fig. 8 indicates a component that has the same reference symbol as the reference symbol of a component in Fig. 1, which has the identical configuration to the configuration of the component in Fig. 1 on or corresponds to this, and the description for the component is omitted.

[0080] The second embodiment differs from the first embodiment according to the present invention in that the semiconductor device has a configuration in which a plurality of diodes are connected in series. In the second embodiment according to the present invention, a section is described that differs from that of the first embodiment according to the present invention, and a description for the same components or a corresponding component is omitted.

[0081] In Fig. 8 is a diode 21 It is configured to have a plurality of diodes connected unidirectionally in series. That is, the anode of one diode is connected to the cathode of another diode, whose anode is further connected to the cathode of yet another diode. Accordingly, the diode 21, which is configured to have the majority of diodes connected in series, with an anode at one end and a cathode at the other end.

[0082] A plurality of second control electrodes 2 is connected, and the cathode of the diode 21 The diode, which has the majority of diodes connected in series, is connected to this connection of the second control electrodes. Furthermore, the anode of the diode is 21 , which has the majority of diodes connected in series, with a first control electrode 1 tied together.

[0083] Even in a semiconductor device 100 , which in Fig. As shown in Figure 8, diode 21, which has the majority of series-connected diodes, can prevent the displacement current charging the parasitic capacitance Cge in order to control the dV / dt of the IGBT element. 20to increase, as described in the first embodiment, even if the increase in the electrical potential ΔVdp is generated by the holes accumulated in a second base layer 7b of the p type.

[0084] Furthermore, the diode 21 be configured to have the majority of diodes connected in series to minimize the integrated parasitic capacitance of the entire diode 21 to reduce the parasitic capacitance of the diodes, so that it is possible to further suppress the displacement current Id which tends to flow, using the parasitic capacitance of a diode.

[0085] Fig. Figure 9 is an enlarged structural cross-section representing an IGBT element forming a semiconductor device with a further configuration according to the second embodiment of the present invention. Fig. 9 indicates a component that has the same reference symbol as the reference symbol of a component in Fig. 8, which has the identical configuration to the configuration of the component in Fig. 8 or a configuration that corresponds to this, and the description for the component is omitted.

[0086] The semiconductor device in Fig. 9 differs from the semiconductor device in Fig. 8 in that it has a configuration in which a diode 21a is included, which is configured to have a plurality of diodes connected in series, and which also includes diodes 21b are included, each with the second control electrodes 2 are connected.

[0087] In Fig. 9 are the second control electrodes 2 a semiconductor device 100 each with cathodes of the diodes 21b connected, and a cathode of the diode21a , which is configured to have the majority of diodes connected in series, is connected to the connection made by connecting the anodes of the majority of diodes 21b is formed. A first control electrode 1 is with an anode of the diode 21a connected, which is configured to have the majority of diodes connected in series.

[0088] Even in the semiconductor device 100 , which in Fig. As shown in Figure 9, diode 21a, which has the majority of diodes connected in series, as well as the diodes 21b , each connected to the second control electrodes 2 are connected, preventing the displacement current that charges the parasitic capacitance Cge to control the dV / dt of the IGBT element 20to increase, as described in the first embodiment, even if the increase in the electrical potential ΔVdp is due to the presence of a second base layer 7b is generated by p-type accumulated holes.

[0089] Furthermore, the diode 21a in the same way as in Fig. The semiconductor device shown in Figure 8 can be configured to have a majority of diodes connected in series in order to reduce the integrated parasitic capacitance of diode 21a. Furthermore, the diode can 21a in series with the diodes 21b be switched, each connected to the second control electrodes to create an integrated parasitic capacitance of the diode 21a and the diodes 21b to further reduce. This can further suppress the displacement current Id, which tends to flow, utilizing the parasitic capacitance of a diode.

[0090] In semiconductor devices100 According to the second embodiment, one way in which the majority of diodes are placed between the first control electrode 1 and the second control electrodes 2 is switched, not limited to the configurations that are in the Fig. 8 and Fig. 9 are shown. The diode 21 For example, it is configured to have four diodes that are in Fig. 8 are connected in series; however, the number of diodes can also be larger or smaller, as long as the diode 21 has at least two diodes.

[0091] In the same way, the diode 21a configured to have two diodes that are in Fig. 9 are connected in series; however, the number of diodes can also be greater. Furthermore, the diodes can be 21b , which in Fig. 9 each with the second control electrodes 2connected, also refers to a diode configured to have a plurality of diodes connected in series.

[0092] As described above, the majority of diodes according to the semiconductor devices of the second embodiment can be placed between the first control electrode 1 and the second control electrodes. 2 They must be connected in series to increase the ability to prevent the displacement current caused by the increase in electrical potential in the second base layer. 7b is generated of the p-type, resulting in an effect that allows control of the value of dV / dt of the IGBT element. 20 will be increased further. Third embodiment

[0093] Fig. Figure 10 is an enlarged structural cross-sectional view representing an IGBT element forming a semiconductor device according to a third embodiment of the present invention. Fig. Figure 11 is an enlarged cross-sectional view of the structure, representing a peripheral element region of the IGBT element that forms the semiconductor device according to the third embodiment of the present invention. Fig. 10 and Fig. 11 indicates a component that has the same reference symbol as the reference symbol of a component in Fig. 3 has the identical configuration to the configuration of the component in Fig. 3 or a configuration that matches this, and the description for the component is omitted.

[0094] The third embodiment differs from the first embodiment according to the present invention in that the semiconductor device has a configuration in which a built-in gate resistor 33 is located between a first control electrode. 1 and an anode of a diode 21 is arranged. Fig. Figure 11 is a cross-sectional view along the first control electrode 1 .

[0095] In Fig. 10 is the built-in gate resistor 33 in the peripheral element area of ​​a trench-gate electrode. 15 an active trench gate formed, which is the first control electrode 1 forms. In particular, the built-in gate resistor 33 is located between the trench-gate electrode. 15 , which is formed in an active area of ​​the IGBT element, and a first gate contact point connected to the first control electrode 1 to connect by forming an area that has a lower concentration of defects in the trench-gate electrode 15 than in the active area.

[0096] As in Fig. Figure 11 shows the trench-gate electrode. 15 , which is the first control electrode 1 of the IGBT element 20The gate wiring area of ​​the trench-gate electrode 15 is extended upwards to an upper element region in the peripheral element region to form a gate wiring area, and this gate wiring area is connected to a first gate contact point 18. In a portion of the gate wiring area of ​​the trench-gate electrode... 15 A region is formed which has a lower concentration of n-type or p-type impurities contained in polysilicon than that in the active region, and this region with a lower impurity concentration forms the built-in gate resistor 33.

[0097] In Fig. 11 is below the gate wiring area of ​​the trench-gate electrode 15and the integrated gate resistor 33 in the peripheral element region forms a p-type trough layer 17 to perform a limiting function of the IGBT element 20. Thus, the p-type trough layer 17 limits a depletion layer that extends from the active region to the peripheral element region.

[0098] The resistance value of the built-in gate resistor 33 can be set to any value by adjusting the concentration of impurities contained in polysilicon in the trench-gate electrode. 15 is set. Alternatively, the resistance value can be set to any value by adjusting the length of the region forming the built-in gate resistor 33. The resistance value of the built-in gate resistor 33 is set to be equivalent to a resistance component caused by a drop in the forward voltage of the diode. 21 is caused.

[0099] In the semiconductor device according to the in Fig. In the first embodiment shown in 3, the second control electrode is 2 with the cathode of the diode 21 connected, the anode of the diode 21 is connected to the first control electrode 1 connected, which is one end of the gate resistance 22 is connected to this diode 21 and the first control electrode 1 connected, and the other end of the gate resistor 22 is connected to gate terminal 30. Therefore, the resistance components that correspond to the gate resistor are located there. 22 can be assigned, as can the drop in the forward voltage of the diode. 21 between the gate terminal 30 and the second control electrodes 2 to.

[0100] On the other hand, only the gate resistance 22 between the gate terminal 30 and the first control electrode 1switched, so that the charging and discharging rate of the gate voltage applied to gate terminal 30 is controlled at the first control electrode 1 and the second control electrode 2 is different. This causes a concentration of an electric field in one or more of the trenches. 16 on one underside of the gate insulating layer 14 , which is formed on the inner wall of the trench (the trenches), the reliability of the dielectric strength of the gate insulating layer 14 possibly reduced.

[0101] On the other hand, the built-in gate resistor 33 in the semiconductor device 100 According to the third embodiment, the device is manufactured in such a way that the resistance value of the built-in gate resistor 33 is set to a value equivalent to the resistance component caused by the drop in the forward voltage of the diode. 21is caused to control the charging and discharging rate between the first control electrode 1 and to match the second control electrode 2 when the gate voltage is applied to the gate terminal 30, so that the concentration of an electric field in one or more of the trenches 16 on one underside of the gate insulating layer 14 The resistance is reduced, which is formed on the inner wall of the trench (or trenches). This can result in an effect that reduces the reliability of the dielectric strength of the gate insulation layer. 14 is increased. Fourth embodiment

[0102] Fig. Figure 12 is an enlarged cross-sectional view of an IGBT element forming a semiconductor device according to a fourth embodiment of the present invention. Fig. 12 indicates a component that has the same reference symbol as the reference symbol of a component in Fig. 3 has the identical configuration to the configuration of the component in Fig. 3 or a configuration that matches this, and the description for the component is omitted.

[0103] The fourth embodiment differs from the first embodiment according to the present invention in that the semiconductor device has a configuration in which one or more dummy trench gates are connected to an emitter terminal 31, wherein the dummy trench gate (the dummy trench gates) is not made into an active dummy trench gate (to active dummy trench gates).

[0104] In Fig. 12 is a third control electrode 3 than the dummy trench gate that is closest to a first control electrode 1 located, connected to the emitter terminal 31. Therefore, the number of second control electrodes is 2than the active dummy trench gates, which are connected to a cathode of a diode 21 are connected, smaller than those in the semiconductor device according to the first embodiment, which are in Fig. 3 is shown.

[0105] A dummy trench gate, connected to emitter terminal 31, serves as the third control electrode. 3 Reference is made to the third control electrode 3 is not limited to the dummy trench gate, which is located closest to the first control electrode 1 It is not located, but it can also be any dummy trench gate. Regarding the number of third control electrodes 3 The number of dummy trench gates connected to emitter terminal 31 can be any, as long as at least one of them is not connected to emitter terminal 31 and is equal to the second control electrode. 2than the active dummy trench gate to which the gate voltage is applied.

[0106] A semiconductor device 100 According to the fourth embodiment, the electrostatic capacitance between the gate and the collector and the electrostatic capacitance between the gate and the emitter in the IGBT element 20 can be reduced by the third control electrode 3 The emitter terminal 31 is connected, allowing the switching speed to be increased and switching losses to be reduced. Furthermore, the number of control electrodes connected to the gate terminal 30 can be reduced to decrease the gate current required for charging and discharging the control electrodes.

[0107] This can reduce the output capacitance of a gate driver circuit located outside the semiconductor device. 100 is arranged in such a way that an effect results through which the semiconductor device 100and units with a peripheral circuit, such as a gate driver circuit, mounted inside them, are miniaturized. Fifth embodiment

[0108] Fig. Figure 13 is an enlarged cross-sectional view of a structure representing an IGBT element forming a semiconductor device according to a fifth embodiment of the present invention. Fig. 13 indicates a component that has the same reference symbol as the reference symbol of a component in Fig. 3 has the identical configuration to the configuration of the component in Fig. 3 or a configuration that matches this, and the description for the component is omitted.

[0109] The fifth embodiment differs from the first embodiment according to the present invention in that the semiconductor device has a configuration in which a second base layer 7c from n- -type instead of the second basal layer of p-type. A trench gate that is in contact with the second basal layer. 7c from n - The -type is also a dummy trench gate, and this is referred to as an active dummy trench gate when the gate voltage is applied to the trench gate. A role of a second control electrode 2a The active dummy trench gate is the same as that of the second control electrode. 2 , which is described in the first to the fifth embodiments.

[0110] According to Fig. 13 is the second base layer 7c from n - -Type on part of an upper surface side of a drift layer 10 from n - -type arranged from a semiconductor substrate of n - -type is formed, and the second base layer 7c from n - -Type is in contact with the second control electrode2a than the active dummy trench gate. That is, the area of ​​the second base layer. 7b of the p-type, which is in Fig. 3 of the first embodiment corresponds to the second base layer. 7c from n - -Type in Fig. 12.

[0111] The concentration of n-type defects in the second base layer 7c from n - -Type is identical to that of the drift layer 10 from n - -Type. The second base layer 7c of n - -Type can be arranged by performing photogravure and by injecting non-p-type defect ions into the area where the second base layer is located. 7c from n - -type is arranged when a first base layer 7a is formed of the p-type.

[0112] In the fifth embodiment, all base layers that are in contact only with the second control electrode are 2a, however, not in contact with a first control electrode 1 as an active trench gate, to second base layers 7c from n - -type, however, a second base layer 7b of the p-type can also be formed by injecting ions from p-type defects into one or some of the base layers that are only in contact with the second control electrode 2a. That is, at least one base layer of the base layers that is only in contact with the second control electrode. 2a If they are in contact, the second base layer should be 7c from n - -type.

[0113] In a semiconductor device 100 According to the fifth embodiment, as in Fig. 13 shows the second base layer 7c from n - -type arranged by injecting non-p-type defects ions into the area where the second base layer is located. 7c from n --Type is arranged to make it more difficult for holes to be present at the time the IGBT element is switched on. 20 into the second base layer 7c from n - -type. This causes many holes to penetrate the first base layer. 7a p-type currents flow in and increase the conductivity modulation effect, thus reducing the conduction losses of the IGBT element. 20 be reduced.

[0114] Furthermore, the number of holes in the second base layer is reduced. 7c from n - -Type accumulate, which only interact with the second control electrode 2a is in contact to reduce the degree of increase of the electrical potential ΔVdp that occurs at the time the IGBT element is switched on. 20is generated. This allows the magnitude of the displacement current Id, which can be generated by the increase in the electrical potential ΔVdp, to be reduced, thus further increasing the controllability of dV / dt at the time of switching on the IGBT element and preventing incorrect switching on at the time of switching off the IGBT element.

[0115] In a case where one or some of the base layers are only connected to the second control electrode 2aSince the second base layers 7b are of the p-type, the amount of holes accumulated in all base layers that are only in contact with the second control electrode 2a can also be reduced in the same way, so that the controllability of dV / dt at the time of switching on the IGBT element is further increased and incorrect switching on at the time of switching off the IGBT element is further prevented.

[0116] The fifth embodiment describes a configuration that is used in the first embodiment. However, the configurations described in the second through fourth embodiments can be used in the semiconductor device that forms the second base layer. 7c from n --type and the dummy trench gate described in the present embodiment, and such a semiconductor device can produce the same effects as the semiconductor devices described in the second to fourth embodiments. Sixth embodiment

[0117] Fig. Figure 14 is an enlarged cross-sectional view of a structure representing a peripheral element region of an IGBT element forming a semiconductor device according to a sixth embodiment of the present invention. Fig. 14 indicates a component that has the same reference symbol as the reference symbol of a component in Fig. 3 has the identical configuration to the configuration of the component in Fig. 3 or a configuration that matches this, and the description for the component is omitted.

[0118] The sixth embodiment differs from the first embodiment according to the present invention in that the semiconductor device has a configuration in which a diode 21 and an IGBT element 20 are integrally formed. Fig. 14 is unlike Fig. 11 of the third embodiment a cross-sectional view along a second control electrode 2 .

[0119] As in Fig. As shown in 14, the IGBT element 20 a semiconductor device 100 according to the sixth embodiment trench gates, which consist of a first control electrode 1 and the second control electrode 2 are formed in such a way that they are configured to form a trench-gate electrode 15a exhibiting a material made of n-type polysilicon. On the other hand, it is a wiring area. 15b, which is made of p-type polysilicon, in part of a gate wiring area of ​​the peripheral element area of ​​the IGBT element 20 trained.

[0120] This creates a pn junction in the gate wiring area in a transition region between the trench-gate electrode. 15a , which is made from n-type polysilicon, and the wiring area 15b formed, which is made from a p-type polysilicon, and this pn junction forms the diode 21 Furthermore, a second gate contact point 19 is located on the wiring area made of p-type polysilicon. 15b formed in the gate wiring area to protect the wiring area 15b to connect to the second gate contact point 19.

[0121] On the other hand, the p-type polysilicon described above is not used in a gate wiring region of the trench-gate electrode made from n-type polysilicon. 15a the first control electrode 1 formed, and a first gate contact point is located at the wiring area of ​​the trench-gate electrode made of n-type polysilicon. 15a designed to connect the wiring area of ​​the first control electrode to the first gate contact point. The first gate contact point is connected to the second gate contact point 19, and one end of a gate resistor 22 is connected to this link between the first gate contact point and the second gate contact point.

[0122] This results in the same outcome as with the configuration described in Fig. 7 of the first embodiment, the semiconductor device 100with a configuration in which the cathodes of the diodes 21 each is connected to the second control electrodes 2, anodes of the diodes 21 with the first control electrode 1 are connected and represent one end of a gate resistor 22 with this connection between the diodes 21 and the first control electrode 1 is connected.

[0123] Fig. Figure 15 is an enlarged cross-sectional view of a structure representing a peripheral element region of an IGBT element forming a semiconductor device with a further configuration according to the sixth embodiment of the present invention. A semiconductor device 100 in Fig. 15 differs from the semiconductor device in Fig. 14 in that it has a configuration in which a plurality of series-connected diodes are located in a gate wiring area made of polysilicon of a second control electrode 2 is trained. Fig. 15 is like Fig. 14 a cross-sectional view along the second control electrode 2 .

[0124] As in Fig. As shown in 15, the semiconductor device 100 a plurality of (three) wiring areas 15b , which are made from p-type polysilicon, and wiring areas 15c , which are made of n-type polysilicon, formed in a gate wiring area of ​​a trench-gate electrode 15a, which is the second control electrode 2 forms and is made of n-type polysilicon. The wiring areas 15care formed integrally at the same time as the trench-gate electrode 15a made from n-type polysilicon.

[0125] In areas between the wiring areas 15b The wiring regions 15c, which are made of p-type polysilicon, are made of n-type polysilicon. This creates three pn junctions, which are transition regions between the p-type and n-type polysilicon, forming a diode. 21 to form a circuit configured to have three diodes connected in series. At a wiring area 15b , which is made of p-type polysilicon, a second gate contact point 19 is formed to connect the second gate contact point 19 to the wiring area 15b to connect.

[0126] In a gate wiring area of ​​the trench-gate electrode made from n-type polysilicon 15a a first control electrode 1 No p-type polysilicon is formed, so the identical configuration is that of the semiconductor device according to Fig. 14 results.

[0127] This is done in the same way as with the semiconductor device in Fig. 8 the semiconductor device 100 supplied with a configuration in which one cathode of the diode 21 , which has the majority of diodes connected in series, with the second control electrodes 2 connected is an anode of the diode 21 , which has the majority of diodes connected in series, with the first control electrode 1 is connected and is one end of a gate resistor 22 with this connection between the diode 21 and the first control electrode 1is connected. Such a configuration can reduce the parasitic capacitance of diode 21 compared to that of the semiconductor device in Fig. 14 decrease by connecting the majority of diodes in series.

[0128] The in the Fig. 14 and Fig. The semiconductor devices shown in Figure 15 can be fabricated, for example, by the following steps. The trench-gate electrode 15a, which is made of n-type polysilicon, is attached to a semiconductor substrate of the n - -Type deposited and subjected to photogravure to only a predetermined area of ​​the gate wiring area of ​​the second control electrode 2 to open. Into this area, ions from p-type defects, such as boron (B), are injected to form the wiring region 15b, which is made from p-type polysilicon.

[0129] As described above, in the semiconductor devices according to the sixth embodiment it is possible to position the diode 21 , which are between the first control electrode 1 and the second control electrode 2 to be arranged and integrated into the IGBT element 20. This enables an increase in the controllability of dV / dt at the time the IGBT element is switched on. 20 and prevents incorrect switching on at the time of switching off the IGBT element 20, without increasing the number of components. Furthermore, this allows for a miniaturization of the semiconductor device and provides a highly reliable semiconductor device that does not require any interruption in the wiring between the IGBT element. 20 and the diode 21 caused.

[0130] In the first through sixth embodiments, silicon was described as the material for the semiconductor substrate. However, the material for the semiconductor substrate is not limited to silicon; it can be materials such as gallium nitride, silicon carbide, aluminum nitride, diamond, and gallium oxide. Reference symbol list 1 first control electrode 2 second control electrode 2a second control electrode 3 third control electrode 6 Emitter layer from n + -Type 7 p-type base layer 7a first base layer of the p-type 7b second base layer of p-type 7c second base layer from n - -Type 9 Contact layer from p + -Type 10 Drift layer from n - -Type 12 p-type collector layer 14 Gate insulating layer 15 Trench-Gate Electrode 15a Trench-Gate Electrode 15b Wiring area 15c Wiring area 16 trenches 20 IGBT elements 21 Diode 21a Diode 21b Diode 22 Gate resistor 100 semiconductor devices QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] WO 2015 / 162811 A

[0009]

Claims

[1] Semiconductor device comprising: - a drift layer of a first conductivity type; - a base layer of a second conductivity type, which is arranged on an upper surface side of the drift layer; - an emitter layer of the first conductivity type, selectively arranged on an upper surface side of the base layer; - a trench-gate that allows a trench-gate electrode to be in contact with the emitter layer, the base layer and the drift layer via a gate insulating layer, wherein the trench-gate electrode is embedded such that it extends from a surface layer of the emitter layer to the drift layer; - a dummy trench gate which allows a dummy trench gate electrode to be in contact with the base layer and the drift layer via a gate insulating layer, wherein the dummy trench gate electrode is embedded such that it extends from a surface layer of the base layer to the drift layer; - a collector layer of the second conductivity type, arranged on a lower surface side of the drift layer; and - a diode whose anode side and cathode side are electrically connected to the trench-gate electrode and the dummy trench-gate electrode, respectively. [2] Semiconductor device comprising: - a drift layer of a first conductivity type; - a base layer of a second conductivity type, selectively arranged on an upper surface side of the drift layer; - an emitter layer of the first conductivity type, arranged on an upper surface side of the base layer; - a trench-gate that allows a trench-gate electrode to be in contact with the emitter layer, the base layer and the drift layer via a gate insulating layer, wherein the trench-gate electrode is embedded such that it extends from a surface layer of the emitter layer to the drift layer; - a dummy trench gate that allows a dummy trench gate electrode to be in contact with the drift layer via a gate insulating layer, wherein the dummy trench gate electrode is embedded such that it extends from a surface layer of the drift layer to the interior of the drift layer; - a collector layer of the second conductivity type, arranged on a lower surface side of the drift layer; and - a diode whose anode side and cathode side are electrically connected to the trench-gate electrode and the dummy trench-gate electrode, respectively. [3] Semiconductor device according to claim 1 or 2, comprising a plurality of dummy trench gates, wherein one or some of the plurality of dummy trench gate electrodes is or are electrically connected to an emitter electrode arranged on the emitter layer, and the other(s) of the dummy trench gate electrodes is / are electrically connected to the cathode side of the diode. [4] Semiconductor device according to any one of claims 1 to 3, wherein - the dummy trench gate electrode is formed from a first conductivity type semiconductor and has a wiring area connected to a second gate contact point located on the upper surface side of the drift layer, and - the diode is formed from a pn junction of a second conductivity type semiconductor and a first conductivity type semiconductor, which are arranged in part of the wiring area. [5] Semiconductor device according to any one of claims 1 to 4, wherein the diode comprises a plurality of diodes connected in series. [6] Semiconductor device according to any one of claims 1 to 5, wherein the trench-gate electrode is connected to the anode side of the diode via a resistor. [7] Semiconductor device according to claim 6, wherein - the trench-gate electrode is formed from a semiconductor containing impurities and has a wiring area connected to a first gate contact point located on the upper surface side of the drift layer, and - the resistance is formed from an area located in the wiring area and has a lower concentration of defects than that in the trench gate.