Semiconductor device

Abstract

Semiconductor device comprising: - a drift layer (1); - an N-type semiconductor layer (3) and a first P-type semiconductor layer (4) arranged below the drift layer (1) while adjacent to each other in a lateral direction; - a second P-type semiconductor layer (6) arranged on the drift layer (1); - an electrode (7) arranged on the second P-type semiconductor layer (6); and - an electrically insulating layer (8) arranged above the first P-type semiconductor layer (4) while in contact with the second P-type semiconductor layer (6) and the electrode (7), wherein: - each region of the electrically insulating layer (8) overlaps in a vertical direction perpendicular to the lateral direction only with a corresponding region of the first P-type semiconductor layer (4); and - no N-type semiconductor layer is formed between the second P-type semiconductor layer (6) and the electrode (7).

Description

Technical field

[0001] The present invention relates to semiconductor devices such as diodes. State of the art

[0002] A conventional semiconductor device, such as a diode, has a structure on its back surface that is provided with a high-concentration N-type semiconductor layer on the cathode side of the device (hereafter referred to as an "N-type cathode layer") to establish an ohmic contact between an electrode and a drift layer or buffer layer. In such a structure, a sudden voltage spike can damage the device during the final stage of a recovery operation. To address this problem, Patent Document 1, for example, proposes a configuration in which a P-type semiconductor layer is arranged on the cathode side (hereafter referred to as a "P-type cathode layer"). In such a configuration, carriers are injected from the cathode side. This dampens fluctuations in the electric field, thereby preventing the sudden voltage spike. State-of-the-art document (patent document)

[0003] Patent document 1: Published Japanese patent application no. 2010-283132 Summary Problem to be solved by the invention

[0004] Unfortunately, the P-type cathode layer, together with a P-type semiconductor layer on the anode side of the device (hereafter referred to as the "P-type anode layer"), forms a parasitic PNP transistor. This sometimes causes the parasitic PNP transistor to be active during the recovery operation. Consequently, the P-type cathode region exhibits a high current density, resulting in a current concentration associated with heat generation. This heat can damage the device.

[0005] To solve the above problem, one object of the present invention is to provide a technique for preventing a concentration of an electric field in a first P-type semiconductor layer, such as a P-type cathode region, during a recovery operation. Means to solve the problem

[0006] A semiconductor device according to a first aspect of the present invention comprises the following: a drift layer; an N-type semiconductor layer and a first P-type semiconductor layer arranged below the drift layer while adjacent to each other in a lateral direction; a second P-type semiconductor layer arranged on the drift layer; an electrode arranged on the second P-type semiconductor layer; and an insulating layer arranged above the first P-type semiconductor layer while in contact with the second P-type semiconductor layer and the electrode.

[0007] A semiconductor device according to a second aspect of the present invention comprises the following: a drift layer; an N-type semiconductor layer and a first P-type semiconductor layer arranged below the drift layer while adjacent to each other in a lateral direction; a second P-type semiconductor layer arranged on or above the drift layer; an electrode arranged on the second P-type semiconductor layer; a first N-type buffer layer arranged above the N-type semiconductor layer and on the drift layer or arranged on the N-type semiconductor layer and below the drift layer; and a second N-type buffer layer arranged above the first P-type semiconductor layer and on the drift layer or arranged on the first P-type semiconductor layer and below the drift layer while adjacent to the first N-type buffer layer in a lateral direction.The second N-type buffer layer has a higher impurity concentration than the first N-type buffer layer. Effects of the invention

[0008] According to the present invention, the insulating layer or the second N-type buffer layer, which has a higher impurity concentration than the impurity concentration of the first N-type buffer layer, is arranged above the first P-type semiconductor layer. This prevents the concentration of an electric field in the first P-type semiconductor layer during the recovery operation.

[0009] These and other tasks, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when it is carried out in conjunction with the accompanying drawings. List of characters Fig. Figure 1 is a cross-sectional view of the configuration of a related diode. Fig. Figure 2 is a diagram showing the result of a simulation of the current distribution during the recovery operation of the related diode. Fig. Figure 3 is a cross-sectional view of the configuration of a diode according to a first embodiment. Fig. Figure 4 is a cross-sectional view of the configuration of a diode according to a modification of the first embodiment. Fig. Figure 5 is a cross-sectional view of the configuration of a diode according to a modification of the first embodiment. Fig. Figure 6 is a cross-sectional view of the configuration of a diode according to a second embodiment. Fig. Figure 7 is a cross-sectional view of the configuration of a diode according to a modification of the second embodiment. Fig. Figure 8 is a cross-sectional view of the configuration of a diode according to a modification of the second embodiment. Fig. Figure 9 is a cross-sectional view of the configuration of a diode according to a third embodiment. Description of the embodiment(s)<Erste Ausführungsform>

[0010] The following describes in detail semiconductor devices according to the present invention, which are diodes of power modules that are resistant to high voltage and are used at voltages of 600 V or more. The semiconductor devices according to the present invention are not limited to diodes and can be any type of semiconductor device, such as insulated-gate bipolar transistors (IGBTs).

[0011] Before describing a diode according to the first embodiment of the present invention, the following describes a diode related to the diode according to the first embodiment (hereinafter referred to as the “related diode”).

[0012] Fig. Figure 1 is a cross-sectional view of the configuration of the related diode. It is specifically noted that directions such as up and down are specified only for convenience and should therefore correspond, as applicable, to the orientation of the device mounting. Fig. 1 and the rest of the drawings and their description will be changed.

[0013] The related diode in Fig. 1 comprises a drift layer 1 , a cathode buffer layer 2 of N-type, an N-type cathode layer (N-type semiconductor layer) 3 , a P-type cathode layer (first P-type semiconductor layer) 4 , a cathode electrode5 , a P-type anode layer (second P-type semiconductor layer) 6 and an anode electrode (electrode) 7 .

[0014] An example of the drift layer 1 is an N-type semiconductor layer.

[0015] The cathode buffer layer 2 of the N-type is below the drift layer 1 arranged. The cathode buffer layer 2 The N-type layer has a higher contamination concentration than the contamination concentration of the drift layer. 1 on.

[0016] The cathode layer 3 of the N-type and the cathode layer 4 P-type molecules are located under the cathode buffer layer. 2 arranged in an N-type pattern, while being adjacent to each other in a lateral direction. That is, the cathode layer 3 of the N-type and the cathode layer 4 P-type particles are located below the drift layer 1 arranged. The cathode buffer layer3 The N-type layer has a higher impurity concentration than the impurity concentration of the cathode buffer layer. 2 of the N-type.

[0017] The cathode electrode 5 is below the cathode layer 3 of the N-type and the cathode layer 4 arranged of the P-type while they are connected to the cathode layer 3 of the N-type and the cathode layer 4 of the P-type in ohmic contact.

[0018] The anode layer 6 of the P-type is on the drift layer 1 arranged. The anode layer 6 P-type bacteria are formed, for example, through impurity diffusion.

[0019] The anode electrode 7 is on the anode layer 6 arranged of the P-type while they are connected to the anode layer 6 of the P-type in ohmic contact.

[0020] The related diode with such a configuration features a parasitic PNP bipolar transistor that is detached from the cathode layer. 4 of the P-type, the anode layer 6 The P-type diode and the N-type semiconductor layer in between are formed. While the related diode recovers, the related diode here is in a reverse bias state, in which a high voltage is applied to the cathode side of the diode; furthermore, a depletion layer expands from a PN junction on the anode side of the diode to the cathode side according to a voltage applied between the anode electrode. 7 and the cathode electrode 5 is set up.

[0021] The depletion layer is created when it interacts with the cathode layers. 4The p-type diode, on the back surface of the diode, experiences a punch-through effect. During this phase, while the related diode is ON, changes occur in the drift layer. 1 Stored carriers occupy a region of the PNP bipolar transistor where the penetration effect occurs. Consequently, the current density in this region increases, resulting in a current concentration.

[0022] Fig. Figure 2 is a diagram showing the result of a simulation of the current distribution inside the related diode during its recovery. Fig. Figure 2 illustrates the current distribution in such a way that the current is higher the more the density of hatched points increases. As shown from Fig. As can be seen in section 2, the current is in the area of ​​the cathode layer. 4 higher of the P-type.

[0023] A heat increase resulting from such a current concentration can damage the diode. In contrast, the diode according to the first embodiment prevents a heat increase due to current distribution during its recovery operation.

[0024] Fig. Figure 3 is a cross-sectional view of the diode configuration according to the first embodiment. Identical or similar components between the related diode and the diode according to the first embodiment are designated by the same reference numerals. The focus is primarily on describing components that differ between these diodes.

[0025] The diode according to the first embodiment comprises, in addition to the components contained in the related diode, an insulating layer. 8 The insulating layer 8 is above the cathode layer 4 formed of the P-type while it is connected to the anode layer 6of the P-type and the anode electrode 7 is in contact. In the first embodiment, the insulating layer 8 with the upper surface of the anode layer 6 of the P-type in contact while in the lower surface of the anode layer 7 is buried.

[0026] In the diode according to the first embodiment, the insulating layer reduces 8 the tendency of carriers to emerge from the cathode layer 4 of the P-type under the insulating layer 8 to exit. This prevents the unnecessary operation of the parasitic PNP bipolar transistor during the recovery operation; that is, this prevents current concentration in the cathode layer region. 4 of the P-type, which improves dielectric strength.

[0027] It is specifically mentioned that the semiconductor layers, including the drift layer, 1Each semiconductor layer can be made from a wide-bandgap semiconductor (containing, for example, silicon carbide, gallium nitride, or diamond); alternatively, each of these semiconductor layers can be made from any other semiconductor (containing, for example, silicon). Wide-bandgap semiconductors, when used to create the semiconductor layers, including the drift layer, allow for 1 to train a stable operation under high-temperature and high-speed conditions. <modifikation>

[0028] The first embodiment describes an example in which the insulating layer 8 with the upper surface of the anode layer 6 of the P-type is in contact while it is in the lower surface of the anode electrode 7 is buried. The configuration of the insulating layer 8 is not limited to this example.

[0029] For example, in a Fig. 4 illustrated the first modification, the insulating layer. 8 with the lower surface of the anode electrode 7 be in contact while in the upper surface of the anode layer 6 is buried of the P-type. Such a configuration achieves an effect similar to that of the first embodiment.

[0030] For example, in a Fig. 5 illustrated the second modification, the insulating layer 8 with the upper surface of the anode electrode 6 of the P-type be in contact while in a through hole 7a the anode electrode 7 is buried, with the passage hole 7a in the direction of its thickness. Such a configuration achieves an effect similar to that of the first embodiment. <Zweite Ausführungsform>

[0031] Fig. Figure 6 is a cross-sectional view of the configuration of a diode according to the second embodiment of the present invention. Identical or similar components between the first and second embodiments are designated by the same reference numerals. The focus is primarily on describing components that differ between these embodiments.

[0032] In the second embodiment, the diode comprises the insulating layer instead of the insulating layer. 8 Anode buffer layers 11 and 12 of the N-type. The anode layer 6 The P-type is located on the anode buffer layers. 11 and 12 of the N-type and above the drift layer 1 arranged.

[0033] The N-type anode buffer layer (first N-type buffer layer) 11 is above the cathode layer 3 of the N-type and on the drift layer 1 arranged.

[0034] The N-type anode buffer layer (second N-type buffer layer) 12 is above the cathode layer 4 of the P-type and on the drift layer 1 arranged while in a lateral direction of the anode buffer layer 11 is adjacent to the N-type. The anode buffer 12 The N-type buffer has a higher impurity concentration than the anode buffer. 11 of the N-type. For example, the anode buffer layer exhibits 12 The N-type has a contamination concentration more than an order of magnitude higher than the contamination concentration of the anode buffer layer. 11 of the N-type. It is specifically mentioned that in the second embodiment the following inequality of impurity concentration is established: the impurity concentration of the drift layer 1 < the impurity concentration of the anode buffer layer 11 of N-type < the impurity concentration of the anode buffer layer 12 of N-type < the impurity concentration of the anode layer 6 of the P-type.

[0035] The diode according to the second embodiment, which is the anode buffer layer 12 of the N-type above the cathode layer 4 The presence of a P-type transistor with a higher impurity concentration reduces the tendency of a depletion layer in this region to extend towards the cathode. This prevents the penetration effect in the parasitic PNP bipolar transistor during the diode's recovery operation and consequently prevents current concentration in the cathode layer region. 4 of the P-type, which improves dielectric strength. <modifikation>

[0036] The configuration in the second embodiment can be modified in various ways.

[0037] For example, in a Fig. Figure 7 illustrated the first modification instead of the cathode buffer layer. 2 N-type cathode buffer layers 16 and 17 It must be of the N type.

[0038] Here is the N-type cathode buffer layer (third N-type buffer layer) 16 on the cathode layer 3 of the N-type and below the drift layer 1 arranged.

[0039] The N-type cathode buffer layer (fourth N-type buffer layer) 17 is on the cathode layer 4 of the P-type and below the drift layer 1 arranged while in a lateral direction of the cathode buffer layer 16 is adjacent to the N-type. The cathode buffer layer 17 The N-type layer has a higher impurity concentration than the impurity concentration of the cathode buffer layer. 16 of the N-type. For example, the cathode buffer layer exhibits 17 The N-type layer has a contamination concentration more than an order of magnitude higher than the contamination concentration of the cathode buffer layer. 16 of the N-type. It is specifically mentioned that in the first modification the following inequality of impurity concentration is established: the impurity concentration of the drift layer 1 < the contamination concentration of the cathode buffer layer 16 of N-type < the impurity concentration of the cathode buffer layer 17 of the N-type. Such a configuration achieves an effect similar to that of the second embodiment.

[0040] For example, in a Fig. Figure 8 illustrated the second modification, the anode buffer layers. 11 and 12 of the N-type from the configuration of Fig. 7. This means the N-type cathode buffer layer (first N-type buffer layer) is removed. 16 is on the cathode layer 3 of the N-type and below the drift layer 1 arranged; furthermore, the cathode buffer layer is of the N type (second buffer layer of the N type) 17 on the cathode layer 4 of the P-type and below the drift layer 1 arranged while in a lateral direction of the cathode buffer layer 16 is adjacent to the N-type. The cathode buffer layer 17 The N-type layer has a higher impurity concentration than the impurity concentration of the cathode buffer layer. 16 of the N-type. Such a configuration achieves an effect similar to that of the second embodiment. <Dritte Ausführungsform>

[0041] Fig. Figure 9 is a cross-sectional view of the configuration of a diode according to a third embodiment of the present invention. The same or similar components between the first and third embodiments are designated by the same reference numerals. The focus is primarily on describing components that differ between these embodiments.

[0042] The diode according to the third embodiment comprises, instead of the insulating layer, 8 a P-type anode layer (third P-type semiconductor layer) 19 The anode layer 19 of the P-type is above the cathode layer 4 arranged of the P-type while they are connected to the anode layer 6 of the P-type and the anode layer 7 is in contact. The anode layer 19 The P-type electrode has a lifetime τ1 that is shorter than the lifetime τ2 of the anode layer. 6 It is of the P-type. That is, the following inequality is established: τ1 < τ2. It is specifically mentioned that a defect in the semiconductor layer, created by proton irradiation, shortens the lifetime of the semiconductor layer. Of course, such lifetime control can be achieved not only via proton irradiation but also via any other method.

[0043] In the diode according to the third embodiment, a shortening of the lifetime of the anode layer is eliminated. 19 of the P-type above the cathode layer 4 of the P-type in an area of ​​the anode layer 19 In the case of a P-type transistor, a portion of the carriers enter the anode side when a pass-through effect occurs in the parasitic PNP bipolar transistor. This reduces the current concentration in the cathode layer. 4 of the P-type during recovery surgery, thereby improving penetration resistance.

[0044] It is specifically mentioned that in the present invention the individual embodiments and modifications within the scope of the invention can be freely combined or modified and omitted as applicable.

[0045] Although the invention has been presented and described in detail, the preceding description is illustrative in all aspects and not limiting. It is therefore understood that numerous modifications and variants can be developed without deviating from the scope of the invention. Reference symbol list

[0046] 1 drift layer, 3 N-type cathode layer, 4 P-type cathode layer, 6 , 19 P-type anode layer, 7 anode electrode, 7a Through hole, 8 Insulating layer 11 , 12 N-type anode buffer layer, 16 , 17 N-type cathode buffer layer QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2010283132

[0003] < / modifikation> < / modifikation>

Claims

[1] Semiconductor device comprising: a drift layer (1); an N-type semiconductor layer (3) and a first P-type semiconductor layer (4) arranged below the drift layer while being adjacent to each other in a lateral direction; a second P-type semiconductor layer (6) arranged on the drift layer; an electrode (7) arranged on the second P-type semiconductor layer; and an insulating layer (8) arranged above the first P-type semiconductor layer while in contact with the second P-type semiconductor layer and the electrode. [2] Semiconductor device according to claim 1, wherein the insulating layer (8) is buried in a lower surface of the electrode (7). [3] Semiconductor device according to claim 1, wherein the insulating layer (8) is buried in an upper surface of the second P-type semiconductor layer (6). [4] Semiconductor device according to claim 1, wherein the electrode (7) has a through hole (7a), and wherein the insulating layer (8) is buried in the through hole. [5] Semiconductor device according to claim 1, comprising, instead of the insulating layer (8), a third P-type semiconductor layer (19) arranged above the first P-type semiconductor layer (4) while in contact with the second P-type semiconductor layer (6) and the electrode (7), wherein the third P-type semiconductor layer has a shorter lifetime than the lifetime of the second P-type semiconductor layer. [6] Semiconductor device comprising: a drift layer (1); an N-type semiconductor layer (3) and a first P-type semiconductor layer (4) arranged below the drift layer while being adjacent to each other in a lateral direction; a second P-type semiconductor layer (6) arranged on or above the drift layer; an electrode (7) arranged on the second P-type semiconductor layer; a first N-type buffer layer (11, 16) arranged above the N-type semiconductor layer and on the drift layer or arranged on the N-type semiconductor layer and below the drift layer; and a second N-type buffer layer (12, 17) arranged above the first P-type semiconductor layer and on the drift layer or arranged on the first P-type semiconductor layer and below the drift layer, while adjacent to the first N-type buffer layer in a lateral direction, where the second N-type buffer layer has a higher impurity concentration than the first N-type buffer layer. [7] Semiconductor device according to claim 6, wherein the first N-type buffer layer (11) is arranged above the N-type semiconductor layer (3) and on the drift layer (1), wherein the second buffer layer (12) of N-type is arranged above the first semiconductor layer (4) of P-type and on the drift layer, the semiconductor device comprises: a third N-type buffer layer (16) arranged on the N-type semiconductor layer and below the drift layer; and a fourth N-type buffer layer (17) located on top of the first P-type semiconductor layer and below the drift layer, while adjacent in a lateral direction to the third N-type buffer layer, and where the fourth N-type buffer layer has a higher impurity concentration than the third N-type buffer layer.

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