Manufacturing process for a semiconductor device

Abstract

A method for manufacturing a semiconductor device comprising the following steps: forming a first oxide semiconductor film (108) over a substrate (102); forming a gate insulating layer (110) comprising at least one silicon oxynitride film over the first oxide semiconductor film (108) using a plasma CVD apparatus; performing an oxygen plasma treatment using the plasma CVD apparatus after forming the gate insulating layer (110) to supply oxygen to the gate insulating layer (110), wherein no N2O or NO2 is used in the oxygen plasma treatment; and forming a gate electrode (112) on the gate insulating layer (110) after performing the plasma treatment.

Description

Technical area

[0001] One embodiment of the present invention relates to a semiconductor device including an oxide semiconductor film, a method of manufacturing the semiconductor device, a display device including the semiconductor device, and an electronic device including the semiconductor device.

[0002] It should be noted that an embodiment of the present invention is not limited to the above technical field. The technical field of an embodiment of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. An embodiment of the present invention additionally relates to a process, a machine, a product or a composition. In particular, an embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, an energy storage device or a storage device, or a driving method or a manufacturing method thereof.

[0003] In this specification and the like, the semiconductor device generally means a device that can operate by utilizing semiconductor properties. A semiconductor element such as B. a transistor, a semiconductor circuit, an arithmetic device, and a memory device are each an embodiment of a semiconductor device. An imaging device, a display device, a liquid crystal display device, a light emitting device, an electro-optical device, a power generating device (including a thin film solar cell, an organic thin film solar cell, and the like) and an electronic device may each include a semiconductor device. State of the art

[0004] A technique in which a transistor is formed using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is used in a wide range of electronic devices, such as e.g. B. an integrated circuit (IC) or an image display device (display device). A silicon-based semiconductor material is widely known as a material for a semiconductor thin film usable for the transistor. As another material for the same, an oxide semiconductor has attracted attention.

[0005] For example, a transistor whose active layer contains an amorphous oxide containing indium (In), gallium (Ga) and zinc (Zn) and has an electron carrier concentration lower than 10 18 / cm 3 (see Patent Document 1).

[0006] Although a transistor containing an oxide semiconductor can be operated at a higher speed than a transistor containing amorphous silicon and can be manufactured more easily than a transistor containing polycrystalline silicon, it is known that the transistor containing a Oxide semiconductors has a problem of low reliability due to a high possibility of change in electrical properties. For example, the threshold voltage of the transistor could change after a bias-temperature stress test (BT test). It should be noted that, in this description, the threshold voltage denotes a gate voltage required to turn on a transistor. A gate voltage denotes a potential difference between a source potential and a gate potential when the source potential is regarded as a reference potential. [Reference] [Patent Document]

[0007] [Patent Document 1] Japanese Patent Laid-Open No. 2006-165528 Disclosure of the invention

[0008] In a transistor using an oxide semiconductor film in its channel region, oxygen vacancies which may be formed in the oxide semiconductor film negatively affect the transistor characteristics. For example, when oxygen vacancies are formed in the oxide semiconductor film, the oxygen vacancies are bonded to hydrogen to serve as carrier supply sources. The carrier supply sources generated in the oxide semiconductor film cause a change in the electrical properties, typically a shift in the threshold voltage, of the transistor that includes the oxide semiconductor film.

[0009] Too many oxygen vacancies in the oxide semiconductor film shift the threshold voltage of the transistor in the negative direction, which leads, for example, to self-conducting properties. Therefore, the oxide semiconductor film, particularly a channel region, preferably contains only a few oxygen vacancies or a small amount of oxygen vacancies, so that it does not result in self-conductive properties.

[0010] Carrier trapping centers in a gate insulating film cause a shift in the threshold voltage of the transistor. Although the number of carrier trapping centers is preferably small, it could multiply if a treatment such as e.g. A plasma treatment is performed after the formation of the gate insulating film.

[0011] In view of the above problems, an object of an embodiment of the present invention is to prevent the electrical characteristics of a transistor including an oxide semiconductor film from being changed and to improve the reliability of the transistor. Another object of an embodiment of the present invention is to provide a novel semiconductor device. Another object of an embodiment of the present invention is to provide a novel display device.

[0012] It should be noted that the description of the above tasks does not stand in the way of the existence of further tasks. In one embodiment of the present invention, it is unnecessary to achieve all of these objects. Objects other than the above objects will be apparent from the explanation of the description and the like and can be derived therefrom.

[0013] One embodiment of the present invention is a semiconductor device provided with a transistor including an oxide semiconductor film. The transistor includes the oxide semiconductor film over a substrate, a gate insulating layer thereover, and a gate electrode thereover. The gate insulating layer includes a silicon oxynitride film. When the gate insulating layer over the substrate is analyzed by thermal desorption spectroscopy, the highest peak of the amount of discharged gas with a mass-to-charge ratio M / z of 32, which corresponds to one oxygen molecule, appears at a substrate temperature higher than or equal to 150 ° C and lower than or equal to 350 ° C.

[0014] In the above embodiment, the measurement temperature of the thermal desorption spectroscopy is preferably higher than or equal to 80 ° C and lower than or equal to 500 ° C.

[0015] In any of the above embodiments, the oxide semiconductor film preferably contains In, M and Zn, where M is Al, Ga, Y or Sn. In any of the above embodiments, the oxide semiconductor film preferably includes a crystal part having an orientation with respect to the c-axis.

[0016] Another embodiment of the present invention is a display device including the semiconductor device of any of the above embodiments and a display element. Another embodiment of the present invention is a display module that includes the display device and a touch sensor. Another embodiment of the present invention is an electronic device that includes the semiconductor device of any of the above embodiments, the above-described display device or module, and an operation button or a battery.

[0017] Another embodiment of the present invention is a manufacturing method of a semiconductor device provided with a transistor including an oxide semiconductor film. The oxide semiconductor film is formed over a substrate, a gate insulating layer including at least one silicon oxynitride film is formed thereover, and an oxygen plasma treatment is performed on the gate insulating layer. After a gate electrode is formed over the gate insulating layer, heat treatment is performed at a temperature higher than or equal to 150 ° C. and lower than or equal to 450 ° C. in order to make oxygen in the gate insulating layer diffuses into the oxide semiconductor film and that the conductivity of the oxide semiconductor film decreases.

[0018] In the above embodiment, the oxygen plasma treatment is preferably carried out at a substrate temperature lower than or equal to 350 ° C. In any of the above embodiments, the silicon oxynitride film is preferably formed by a plasma CVD method at a substrate temperature lower than or equal to 350 ° C.

[0019] Another embodiment of the present invention is a manufacturing method of a semiconductor device provided with a transistor including an oxide semiconductor film. The oxide semiconductor film is formed over a substrate, and a gate insulating layer including at least one silicon oxynitride film is formed thereover. An oxide semiconductor is deposited over the gate insulating film in an atmosphere containing oxygen by a sputtering method, so that a gate electrode is formed while oxygen is added to the gate insulating film. Thereafter, a heat treatment is performed at a temperature of higher than or equal to 150 ° C. and lower than or equal to 450 ° C. to cause oxygen in the gate insulating layer to diffuse into the oxide semiconductor film and to lower the conductivity of the oxide semiconductor film.

[0020] An embodiment of the present invention can prevent the electrical characteristics of a transistor including an oxide semiconductor film from changing and improve the reliability of the transistor. An embodiment of the present invention can provide a novel semiconductor device. An embodiment of the present invention can provide a novel display device.

[0021] It should be noted that the description of these effects does not prevent the existence of further effects. An embodiment of the present invention does not necessarily have all of the above effects. Further effects are evident from the explanation of the description, the drawings, the patent claims and the like and can be derived therefrom. Figure list Fig. 1A to Fig. 1C are a plan view and cross-sectional views illustrating a semiconductor device. Fig. 2A to Fig. 2C are a plan view and cross-sectional views illustrating a semiconductor device. Fig. 3A and Fig. 3B are cross-sectional views illustrating a semiconductor device. Fig. 4A and Fig. 4B are cross-sectional views illustrating a semiconductor device. Fig. 5A to Fig. 5D are cross-sectional views illustrating a method of manufacturing a semiconductor device. Fig. 6A to Fig. 6C are cross-sectional views illustrating a method of manufacturing a semiconductor device. Fig. 7A to Fig. 7C are cross-sectional views illustrating a method of manufacturing a semiconductor device. Fig. 8A to Fig. 8C each illustrate a range of an atomic ratio of an oxide semiconductor of an embodiment of the present invention. Fig. 9A to Fig. 9C are band diagrams of multilayer oxide semiconductor structures. Fig. 10A to Fig. 10C show evaluation results of silicon oxynitride films of an embodiment of the present invention. Fig. 11A and Fig. 11B show evaluation results of silicon oxynitride films of an embodiment of the present invention. Fig. 12A to Fig. 12C show measurement results of silicon oxynitride films of an embodiment of the present invention. Fig. 13A and Fig. 13B are cross-sectional views illustrating a method of manufacturing a semiconductor device. Fig. 14A to Fig. 14C show effects of oxygen diffusion of an embodiment of the present invention. Fig. 15 is a plan view illustrating one embodiment of a display device. Fig. 16 is a cross-sectional view illustrating one embodiment of a display device. Fig. 17 is a cross-sectional view illustrating one embodiment of a display device. Fig. 18 is a cross-sectional view illustrating one embodiment of a display device. Fig. 19 is a cross-sectional view illustrating an embodiment of a display device. Fig. Figure 20 is a cross-sectional view illustrating one embodiment of a display device. Fig. 21A to Fig. 21D are cross-sectional views illustrating a method of forming an EL layer. Fig. Fig. 22 is a conceptual diagram illustrating a droplet ejector. Fig. 23A to Fig. 23C are a block diagram and circuit diagrams each showing a display device. Fig. 24A to Fig. 24C are circuit diagrams and a timing chart showing an embodiment of the present invention. Fig. 25A to Fig. 25C are a diagram and circuit diagrams showing an embodiment of the present invention. Fig. 26A and Fig. 26B are a circuit diagram and timing chart showing an embodiment of the present invention. Fig. 27A and Fig. 27B are a circuit diagram and a timing chart showing an embodiment of the present invention. Fig. 28A to Fig. 28E are a block diagram, circuit diagrams, and waveform diagrams illustrating an embodiment of the present invention. Fig. 29A and Fig. 29B are a circuit diagram and timing chart showing an embodiment of the present invention. Fig. 30A and Fig. 30B are circuit diagrams illustrating an embodiment of the present invention. Fig. 31A to Fig. 31C are circuit diagrams each illustrating an embodiment of the present invention. Fig. 32 represents a display module. Fig. 33A to Fig. 33E represent electronic devices. Fig. 34A to Fig. 34G represent electronic devices. Fig. 35A and Fig. 35B are perspective views illustrating a display device. Fig. 36A and Fig. 36B show I d -V g -Properties of transistors and shifts in threshold voltage. Fig. 37 shows results of TDS analysis. Fig. 38A to Fig. 38C show results of TDS analysis. Fig. 39A to Fig. 39D show results of SIMS analysis. Fig. 40A to Fig. 40I show results of TDS analysis. Fig. 41 shows results of TDS analysis. Fig. 42A and Fig. 42B show results of TDS analysis. Fig. 43A and Fig. 43B show electrical resistances of IGZO films. Fig. 44 shows results of TDS analysis. Fig. 45 is a cross-sectional view illustrating a semiconductor device. Fig. 46A to Fig. 46C are each a circuit diagram of a semiconductor device of an embodiment of the present invention. Fig. 47A and Fig. 47B are each a circuit diagram of a semiconductor device of an embodiment of the present invention. Fig. 48 is a block diagram showing a structural example of a CPU. Fig. 49 is a circuit diagram showing an example of a memory element. Fig. 50A to Fig. 50F show drain current-gate voltage characteristics of transistors of an embodiment of the present invention. Fig. 51 shows results of GBT tests on transistors of an embodiment of the present invention. Fig. 52A to Fig. 52D show current stress characteristics of transistors of an embodiment of the present invention. Best way to carry out the invention

[0022] Embodiments are described below with reference to the drawings. However, the embodiments can be implemented in many different modes, and it will be readily understood by those skilled in the art that modes and details thereof can be changed in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention should not be construed as being limited to the following description of the embodiments.

[0023] In the drawings, the size, layer thickness, or area is exaggerated in some cases for clarity. Accordingly, the embodiments of the present invention are not limited to such an aspect ratio. Note that the drawings are schematic views showing ideal examples, and embodiments of the present invention are not limited to the forms or values ​​shown in the drawings.

[0024] It should be noted that in this description ordinal numbers, such as. For example, “first”, “second” and “third” can be used to avoid confusion between components, and the terms do not limit the number of components.

[0025] It should be noted that in this description terms to explain the arrangement, such as. For convenience, “above,” “above,” “below,” and “below” may be used when describing a positional relationship between components using drawings. Furthermore, the positional relationship between components is adjusted as necessary according to a direction in which the components are described. Therefore, the positional relationship is not limited to that described by a term used in this specification, and another term may be appropriately explained depending on the circumstances.

[0026] In this specification and the like, a transistor is an element that has at least three terminals, namely a gate, a drain, and a source. In addition, the transistor has a channel region between a drain (a drain terminal, a drain region or a drain electrode) and a source (a source terminal, a source region or a source electrode), and current can flow through the drain region, the channel region and the source region flow. It should be noted that in this specification and the like, a channel area denotes an area through which current mainly flows.

[0027] Furthermore, functions of a source and a drain could be interchanged if, for example, transistors with different polarities are used or if a current flow direction is changed during operation of the circuit. Therefore, the terms “source” and “drain” in this description and the like can be interchanged with one another.

[0028] Note that the term “electrically connected” in this specification and the like includes the case where components are connected through an “object having an electrical function”. There is no particular limitation on an “object having an electrical function” as long as electrical signals can be sent and received between components connected through the object. Examples of an “object with an electrical function” are a switching element such as B. a transistor, a resistor, an inductor, a capacitor and elements with different functions as well as an electrode and a lead.

[0029] In this specification and the like, the term “parallel” means that the angle formed between two straight lines is greater than or equal to -10 ° and less than or equal to 10 °, and therefore also includes the case in which the angle is greater than or equal to -5 ° and less than or equal to 5 °. The term “perpendicular” means that the angle formed between two straight lines is greater than or equal to 80 ° and less than or equal to 100 °, and it therefore also includes the case in which the angle is greater than or equal to 85 ° and less than or equal to 95 °.

[0030] In this description and the like, the terms “film” and “layer” may be interchanged with one another. For example, in some cases the term “conductive layer” can be replaced by the term “conductive film”. Furthermore, the term “insulating film” can in some cases be replaced by the term “insulating layer”.

[0031] Unless otherwise specified, the reverse current in this specification and the like denotes a drain current of a transistor in the reverse state (also referred to as the non-conductive state and cutoff state). Unless otherwise specified, the off-state of an n-channel transistor means that a voltage (V gs) Between its gate and source is lower than the threshold voltage (V th), And the off-state of a p-channel transistor means that the gate-source voltage V gs is higher than the threshold voltage V th . For example, the reverse current of an n-channel transistor sometimes denotes a drain current that flows when the gate-source voltage is V gs is lower than the threshold voltage V th .

[0032] In some cases the reverse current of a transistor depends on V gs from. Consequently, “the reverse current of a transistor is less than or equal to I” can mean that “it is V gs where the reverse current of the transistor is less than or equal to I. " Furthermore, “the reverse current of a transistor” means, for example, “the reverse current in a blocking state at a predetermined V gs "," The reverse current in a blocking state at V gs in a predetermined range ”or“ the reverse current in a blocking state at V gs with which a sufficiently reduced reverse current is obtained ".

[0033] As an example, an n-channel transistor is assumed in which the threshold voltage V th 0.5 V and the drain current at V gs of 0.5 V 1 × 10 -9 A, at V gs of 0.1 V 1 × 10 -13 A, at V gs from -0.5 V 1 × 10 -19 A and at V gs from -0.8 V 1 × 10 -22 A are. The drain current of the transistor is at V gs from -0.5 V or at V gs in the range from -0.8 V to -0.5 V 1 × 10 -19 A or lower; therefore, the reverse current of the transistor can be said to be 1 × 10 -19 Is A or lower. Since it is V gs where the drain current of the transistor is 1 × 10 -22 A or lower, the reverse current of the transistor can be said to be 1 × 10 -22 Is A or lower.

[0034] In this specification and the like, the reverse current of a transistor having a channel width W is sometimes represented by a current value with respect to the channel width W or by a current value per certain channel width (e.g., 1 µm). In the latter case, the reverse current can be represented in the unit with the dimension of current per length (e.g. A / µm).

[0035] In some cases the reverse current of a transistor depends on the temperature. Unless otherwise stated, the reverse current in this description can be a reverse current at room temperature, 60 ° C, 85 ° C, 95 ° C or 125 ° C. Alternatively, the reverse current may be reverse current at a temperature at which the reliability required in a semiconductor device or the like including the transistor is secured, or at a temperature at which the semiconductor device or the like incorporating the includes the transistor (e.g., temperatures in the range of 5 ° C to 35 ° C). The description “a reverse current of a transistor is lower than or equal to I” can denote a situation in which it is V gs at which the reverse current of a transistor is at room temperature, 60 ° C, 85 ° C, 95 ° C, 125 ° C, a temperature at which the reliability required in a semiconductor device or the like including the transistor is ensured or at a temperature at which the semiconductor device or the like including the transistor is used (e.g., temperature in the range of 5 ° C to 35 ° C) is less than or equal to I.

[0036] In some cases the reverse current of a transistor depends on the voltage V ds between its drain and its source. Unless otherwise stated, the reverse current in this description can be a reverse current at V ds be 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or 20V. Alternatively, the reverse current could be a reverse current at V ds at which the required reliability of a semiconductor device or the like including the transistor is ensured, or at V ds in which the semiconductor device or the like including the transistor is used. The description “a reverse current of a transistor is lower than or equal to I” can denote a situation in which it is V gs where the reverse current of a transistor is at V ds of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V or 20 V, at V ds at which the required reliability of a semiconductor device or the like including the transistor is ensured, or at V ds in which the semiconductor device or the like including the transistor is used is less than or equal to I.

[0037] In the above description of the reverse current, a drain can be exchanged for a source. That is, the reverse current sometimes denotes a current flowing through a source of a transistor in the reverse state.

[0038] In this specification and the like, the term “leakage current” sometimes has the same meaning as “reverse current”. In this specification and the like, the reverse current sometimes denotes, for example, a current flowing between a source and a drain when a transistor is turned off.

[0039] In this specification and the like, the threshold voltage of a transistor denotes a gate voltage (V g ) At which a channel is formed in the transistor. In particular, in a graph where the horizontal axis is the gate voltage (V g ) And the vertical axis is the square root of the drain current (I d ), The threshold voltage of a transistor can be a gate voltage ( V g ) At the intersection of the square root of the drain current (I d ) Of 0 (I d = 0 A) and an extrapolated straight line that forms a graph (V g -√I d -Properties) with the greatest inclination. Alternatively, the threshold voltage of a transistor may denote a gate voltage (V g ) At which the value of I d [A] × LIW [µm] at 1 × 10 -9 [A] is where L Channel length is and W Channel width is.

[0040] In this specification and the like, a “semiconductor” may have properties of an “insulator” if, for example, the conductivity is sufficiently low. Furthermore, a “semiconductor” and an “insulator” cannot be clearly distinguished from one another in some cases, as a boundary between the “semiconductor” and the “insulator” is not clear. Accordingly, in this specification and the like, a “semiconductor” may be called “insulator” in some cases. Similarly, in this specification and the like, an “insulator” may be called “semiconductor” in some cases. An “insulator” in this specification and the like may be called a “semi-insulator” in some cases.

[0041] In this specification and the like, a “semiconductor” may have properties of a “conductor” if, for example, the conductivity is sufficiently high. Furthermore, a “semiconductor” and a “conductor” cannot be clearly distinguished from one another in some cases, since a boundary between the “semiconductor” and the “conductor” is not clear. Accordingly, in this specification and the like, a “semiconductor” may be called “conductor” in some cases. Similarly, in this specification and the like, a “conductor” may be called “semiconductor” in some cases.

[0042] In this specification and the like, an impurity in a semiconductor denotes an element that is not a main component of the semiconductor film. For example, an element whose concentration is less than 0.1 atomic% is an impurity. For example, when a semiconductor contains an impurity, density of states (DOS) may be formed therein, carrier mobility may be decreased, or crystallinity may be decreased. In the case where the semiconductor contains an oxide semiconductor, examples of the impurity that changes the properties of the semiconductor include elements of the group 1 , Elements of group 2 , Elements of group 14 , Elements of group 15 and transition metals other than the main components; concrete examples are hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon and nitrogen. If the semiconductor is an oxide semiconductor, for example, oxygen vacancies can be caused by the ingress of impurities such as e.g. B. hydrogen are formed. Furthermore, in the case where the semiconductor contains silicon, examples of the impurity that changes the properties of the semiconductor include oxygen, elements of the 1 group. except hydrogen, elements of group 2 , Elements of group 13 and elements of group 15 . (Embodiment 1)

[0043] In this embodiment, a semiconductor device of an embodiment of the present invention including a gate insulating film including an oxygen excess region will be described. A method of manufacturing a semiconductor device of an embodiment of the present invention will also be described. <Structural example 1 of semiconductor device>

[0044] Fig. 1A is a plan view of a transistor 100 a semiconductor device of an embodiment of the present invention. Fig. 1B is a cross-sectional view taken along a chain line X1-X2 in Fig. 1A, and Fig. 1C is a cross-sectional view taken along a chain line Y1-Y2 in Fig. 1A. It should be noted that in Fig. 1A some components of transistor 100 (e.g., an insulating film serving as a gate insulating film) are not shown in order to avoid complexity. Also, the direction of the chain line can be X1-X2 can be referred to as the longitudinal direction of the channel, and the direction of the dash-dot line Y1-Y2 can be referred to as the channel width direction. As in Fig. 1A, some components are in some cases not shown in plan views of the transistors described below.

[0045] With the transistor 100 , which is in Fig. 1A to Fig. 1C, it is a so-called top-gate transistor.

[0046] The transistor 100 includes an insulating film 104 over a substrate 102 , an oxide semiconductor film 108 over the insulating film 104 , an insulating film 110 over the oxide semiconductor film 108 , a conductive film 112 over the insulating film 110 and an insulating film 116 over the insulating film 104 , the oxide semiconductor film 108 and the conductive film 112 .

[0047] The oxide semiconductor film 108 preferably contains In, M (M is Al, Ga, Y or Sn) and Zn.

[0048] The oxide semiconductor film 108 includes a first area 108i that is covered with the conductive film 112 overlapped and in contact with the insulating film 104 and the insulating film 110 is. The oxide semiconductor film 108 also includes a second area 108n in contact with the insulating film 116 . The second area 108n has a higher charge carrier density than the first area 108i . This means that the oxide semiconductor film 108 an embodiment of the present invention comprises two types of regions with different charge carrier densities.

[0049] It should be noted that the carrier density of the first region 108i preferably higher than or equal to 1 × 10 5 cm -3 and lower than 1 × 10 18 cm -3 is, more preferably higher than or equal to 1 × 10 7 cm -3 and less than or equal to 1 × 10 17 cm -3 is, even more preferably higher than or equal to 1 × 10 9 cm -3 and less than or equal to 5 × 10 16 cm -3 is, even more preferably, greater than or equal to 1 × 10 10 cm -3 and less than or equal to 1 × 10 16 cm -3 is and even more preferably higher than or equal to 1 × 10 11 cm -3 and less than or equal to 1 × 10 15 cm -3 is.

[0050] Although referring to Fig. 1A to Fig. 1C and in methods of practicing embodiments of the present invention, an example in which the oxide semiconductor film 108 is a single layer, mainly described, the oxide semiconductor film 108 have a multilayer structure made of films with different charge carrier densities. For example, the oxide semiconductor film can be 108 have a two-layer structure including a first oxide semiconductor film and a second oxide semiconductor film over the first oxide semiconductor film. By making the first oxide semiconductor film have a higher carrier density than the second oxide semiconductor film, the oxide semiconductor film including regions with different carrier densities can be formed.

[0051] The amount of oxygen vacancies or the impurity concentration in the first oxide semiconductor film is slightly higher than that in the second oxide semiconductor film.

[0052] In order to increase the carrier density of the first oxide semiconductor film, an element that forms oxygen vacancies may be added to the first oxide semiconductor film so that hydrogen or the like is bound to the oxygen vacancies. Typical examples of the element that forms oxygen vacancies include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, and a rare gas element. Typical examples of the rare gas element include helium, neon, argon, krypton and xenon. Note that, among the above-mentioned elements, nitrogen is particularly preferable as an element which forms oxygen vacancies in the oxide semiconductor film.

[0053] By using an argon gas and a nitrous oxide gas as deposition gases in forming the first oxide semiconductor film, for example, a nitrogen element can be contained in the first oxide semiconductor film. In this case, the first oxide semiconductor film includes a region with a higher nitrogen concentration than the second oxide semiconductor film.

[0054] Accordingly, the first oxide semiconductor film has a higher carrier density and is slightly n-type. An oxide semiconductor film having an increased carrier density is referred to as “slightly n-type oxide semiconductor film” in some cases.

[0055] For example, in the case where the voltage applied to the gate of the transistor (V g ) Is higher than 0 V and lower than or equal to 30 V, the carrier density of the first oxide semiconductor film is preferably higher than 1 × 10 16 cm -3 and lower than 1 × 10 18 cm -3 and more preferably higher than 1 × 10 16 cm -3 and less than or equal to 1 × 10 17 cm -3 .

[0056] In the case where the carrier density of the first oxide semiconductor film is increased, the crystallinity of the first oxide semiconductor film may be lower than that of the second oxide semiconductor film. In this case, the oxide semiconductor film has 108 has a multilayer structure of an oxide semiconductor film with low crystallinity and an oxide semiconductor film with high crystallinity. The crystallinity of an oxide semiconductor film is correlated with the film density of the oxide semiconductor film, and the oxide semiconductor film having higher crystallinity has a higher film density. Therefore, the oxide semiconductor film 108 consider that it has a multilayer structure of an oxide semiconductor film having a low film density and an oxide semiconductor film having a high film density.

[0057] It should be noted that the crystallinity of the oxide semiconductor film 108 can be determined, for example, by analysis by X-ray diffraction (XRD) or by means of a transmission electron microscope (TEM). The film density of the oxide semiconductor film 108 can for example be measured by means of an X-ray reflectometer (XRR).

[0058] The second area 108n is in contact with the insulating film 116 . The insulating film 116 contains nitrogen or hydrogen. Therefore, the second area becomes 108n Nitrogen or hydrogen in the insulating film 116 added. The charge carrier density of the second area 108n is increased by removing nitrogen or hydrogen from the insulating film 116 is added.

[0059] The transistor 100 can also be an insulating film 118 over the insulating film 116 , a conductive film 120a that is electrically connected to the second area 108n via an opening 141a contained in the insulating films 116 and 118 is provided, is connected, and a conductive film 120b include that is electrically connected to the second area 108n via an opening 141b contained in the insulating films 116 and 118 is provided, is connected.

[0060] In this specification and the like, the insulating film 104 referred to as the first insulating film, the insulating film 110 referred to as the second insulating film, the insulating film 116 can be referred to as the third insulating film, and the insulating film 118 may be referred to as the fourth insulating film. The conductive film 112 serves as the gate electrode, the conductive film 120a serves as a source electrode, and the conductive film 120b serves as a drain electrode.

[0061] The insulating film 110 serves as a gate insulating film. The insulating film further includes 110 an oxygen excess region comprising a silicon oxynitride film. Since the insulating film 110 comprises the oxygen excess area, the first area 108i of the oxide semiconductor film 108 excess oxygen can be supplied. In the present invention, after the insulating film 110 has been formed, the insulating film 110 Oxygen added by an oxygen plasma treatment which is carried out at a substrate temperature of less than or equal to 300 ° C., preferably less than or equal to 250 ° C. Accordingly, the oxide semiconductor film can be made from the insulating film 110 a considerably larger amount of excess oxygen can be supplied compared to the conventional case. It should be noted that in one embodiment of the present invention, an oxygen plasma treatment means a plasma treatment in which oxygen is used. For example, a gas used in plasma treatment may contain a gas other than oxygen which does not prevent an effect of adding oxygen to a film. The gas used in the plasma treatment can contain, for example, oxygen with a percentage of the flow rate of 90% and argon with a percentage of the flow rate of 10%.

[0062] The insulating film 110 One embodiment of the present invention has a single-layer or multi-layer structure including a silicon oxynitride film. When the insulating film 110 is analyzed by thermal desorption spectroscopy (TDS), the highest peak of the amount of released gas with a mass-to-charge ratio M / z of 32, which corresponds to one oxygen molecule, appears within a measurement temperature range at a substrate temperature of higher than or equal to 150 ° C and lower than or equal to 300 ° C, ideally higher than or equal to 150 ° C and lower than or equal to 250 ° C. In the following, emission properties of oxygen molecules that are analyzed by means of TDS are regarded as those of a gas with a mass-to-charge ratio M / z of 32. A typical temperature range analyzed by TDS is from 80 ° C to 500 ° C, and the analysis results at temperatures higher than 500 ° C are not considered to be emission properties of oxygen molecules. Oxygen vacancies in the first area 108i are formed with excess oxygen in the insulating film 110 filled, whereby a highly reliable semiconductor device can be provided. Note that a substrate temperature in the explanation of in this specification means a substrate surface temperature.

[0063] As a conventional method of adding oxygen to a silicon oxynitride film, plasma treatment in which an N 2 O- or NO 2 -Gas used must be specified. However, the present inventors have found that the number of electron capture centers increases when plasma treatment in which an N 2 O- or NO 2 Gas is used on which silicon oxynitride film is passed. One of the factors is an increase in nitrogen oxide (NO x) In the silicon oxynitride film that in the insulating film 110 is included. To a positive shift in the threshold voltage of transistor 100 When performing a bias-temperature stress test (BT test), in particular when applying the positive bias stress to the gate electrode, plasma treatment with an N 2 O- or NO 2 -Gas is used, which leads to an increase in nitrogen oxide (NO x). Therefore, one after the insulating film is formed is 110 oxygen plasma treatment carried out which is an embodiment of the present invention is effective.

[0064] The oxide semiconductor film 108 preferably has a range in which the atomic fraction of In is larger than the atomic fraction of M . When the oxide semiconductor film 108 has a range in which the atomic content of In is higher than the atomic content of M , the transistor 100 have a high field-effect mobility. In particular, the field effect mobility of the transistor 100 10 cm 2 / Vs, preferably 30 cm 2 / Vs, exceed.

[0065] For example, the use of the transistor with a high field effect mobility in a gate driver that generates a gate signal (in particular, in a demultiplexer connected to an output terminal of a shift register included in a gate driver) enables a semiconductor device or a display device has a narrow frame.

[0066] When oxygen vacancies in the oxide semiconductor film 108 are formed, the oxygen vacancies are bound to the hydrogen to serve as charge carrier supply sources. Those in the oxide semiconductor film 108 The generated charge carrier supply sources cause a change in the electrical properties, typically a shift in the threshold voltage, of the transistor 100 containing the oxide semiconductor film 108 includes. Therefore, it is preferable that the amount of oxygen vacancies in the oxide semiconductor film is 108 , especially in the first area 108i , as low as possible.

[0067] Oxygen vacancies in the first area 108i can be filled with excess oxygen that is formed from the insulating film 110 is fed. Therefore, the first area has 108i of the oxide semiconductor film 108 has a low impurity concentration and a low density of defect states. Note that a film having a low impurity concentration and a low density of defect states (or a small amount of oxygen vacancies) is referred to as “high purity intrinsic film” or “substantially high purity intrinsic film”. A high purity intrinsic or substantially high purity intrinsic oxide semiconductor film has only low charge carrier generation sources and can therefore have a low charge carrier density. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film seldom exhibits a negative threshold voltage (it seldom becomes normally on).

[0068] A high purity intrinsic or substantially high purity intrinsic oxide semiconductor film has a low density of defect states and thus a low density of trapped states in some cases. Furthermore, a high purity intrinsic or substantially high purity intrinsic oxide semiconductor film has a very low reverse current; even if an element has a channel width of 1 × 10 6 µm and a channel length L of 10 µm, the reverse current can be less than or equal to the measurement limit of a semiconductor parameter analyzer, i.e. H. less than or equal to 1 × 10 -13 A at a voltage between a source electrode and a drain electrode (drain voltage) of 0.1 V to 10 V.

[0069] A transistor 100A , which is in Fig. 2A to Fig. 2C is different from transistor 100 , which is in Fig. 1A to Fig. 1C in that a conductive film 106 above the substrate 102 is provided. In the transistor that is in Fig. 2A to Fig. 2C, the conductive film 112 and the conductive film 106 can be used as gate electrodes.

[0070] Fig. 36A shows the I d - V g -Properties of a transistor 201 , a transistor 202 and a transistor 203 , each of which is in Fig. 2A to Fig. 2C and in which the conductive films 112 and 106 can be used as gate electrodes at the same potential. The transistors 201 to 203 were obtained by checking the conditions after the formation of the insulating film 110 vary. The I d - V g -Properties were measured under the following conditions: The substrate temperature was room temperature, I d was 0.1 V and 10 V, and V g varies from -15 V to +20 V. Fig. 36A shows the I d - V g -Properties of the transistors operating under conditions 206 and conditions 207 were obtained. With the conditions 206 the channel length was L 2 µm and the channel width was W 50 µm. With the conditions 207 the channel length was L 6 µm and the channel width was W 50 µm. The I d - V g - Properties were determined using the conductive films 112 and 106 measured as gate electrodes. The properties at I d of 0.1 V and 10 V are shown together, and the measurement results of a plurality of transistors on a certain surface of a substrate are shown together.

[0071] The insulating films 110 of transistor 201 , of transistor 202 and the transistor 203 are formed using silicon oxynitride under the same conditions. At the transistor 201 was neither an N 2 O plasma treatment and an oxygen plasma treatment after the formation of the insulating film 110 and the conductive film 112 was made. educated. At the transistor 202 became an N 2 O plasma treatment after the formation of the insulating film 110 and the conductive film 112 was made. educated. At the transistor 203 became an oxygen plasma treatment after the formation of the insulating film 110 was performed, and the conductive film 112 was made. educated. After the conductive film is formed 112 the insulating film became 110 at each of the transistor 201 , of transistor 202 and the transistor 203 subjected to heat treatment at a temperature not higher than 250 ° C.

[0072] With the I d - V g - Properties of transistor 201 the threshold voltage shifts to a large extent in the negative direction. In contrast, I d - V g - Properties of transistor 202 and the transistor 203 the threshold voltage is about 0 V. This indicates that an N 2 O plasma treatment or an oxygen plasma treatment performed after the insulating film 110 is effective for increasing excess oxygen in the insulating film 110 .

[0073] Fig. 36B shows the results of the BT tests performed on transistor 202 and the transistor 203 were carried out. The vertical axis represents the amount of shift of the threshold voltage (ΔV th ) Of the I d - V g Properties, where the unit is V. The channel length L and the channel width W each of the transistors subjected to the BT test were 3 µm and 50 µm, respectively. The BT tests were conducted in an environment exposed to white LED light with an illuminance of 10,000 Ix or in a dark environment with a gate bias of +30 V or -30 V for 60 minutes. This means that four types of BT tests were performed: positive gate bias temperature stress test (PBTS test), negative gate bias temperature stress test (negative gate bias temperature stress test, NBTS test), positive gate bias illumination temperature stress test (PBITS test) and negative gate bias illumination temperature stress test with light exposure (negative gate bias illumination temperature stress test, NBITS- Test). The substrate temperature during the BT tests and during the measurement of the I d - V g -Properties was set to 60 ° C.

[0074] The results of the BT tests show that a shift in the threshold voltage of transistor 202 was approximately +8 V due to the positive gate bias temperature stress test (PBTS test) and a shift in the threshold voltage of transistor 203 was approximately +2 V due to the positive gate bias temperature stress test (PBTS test). This suggests that in the silicon oxynitride film contained in the insulating film 110 included is the transistor 202 more nitrogen oxide (NO x), which serves as electron capture centers, contains than transistor 203 .

[0075] As described above, in the semiconductor device of one embodiment of the present invention, a gate insulating film is formed over an oxide semiconductor layer. Note that the gate insulating film can supply excess oxygen to an oxide semiconductor film while preventing an increase in nitrogen oxide (NO x) In a silicon oxynitride film contained in the gate insulating film. Therefore, a sufficient amount of oxygen is supplied to the oxide semiconductor layer, whereby oxygen vacancies in the oxide semiconductor layer can be reduced, and the reliability of a transistor can be improved. Accordingly, a highly reliable semiconductor device can be provided. <Components of the semiconductor device>

[0076] Next, components of the semiconductor device of this embodiment will be described in detail. [Substrate]

[0077] There is no particular limitation on the property of a material and the like of the substrate 102 as long as the material has a heat resistance sufficient to withstand at least one heat treatment that is carried out later. For example, 102 a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. Alternatively, a monocrystalline semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon germanium, an SOI (silicon on insulator) substrate or the like can be used, or any of these substrates which is provided with a semiconductor element, can be used as substrate 102 be used. In the case where a glass substrate is used as the substrate 102 is used, a glass substrate of one of the following sizes can be used: the sixth generation (1500 mm × 1850 mm), the seventh generation (1870 mm × 2200 mm), the eighth generation (2200 mm × 2400 mm), the ninth generation (2400 mm × 2800 mm) and the tenth generation (2950 mm × 3400 mm). As a result, a large display device can be manufactured.

[0078] Alternatively, a flexible substrate can be used as the substrate 102 are used, and the transistor 100 can be provided directly on the flexible substrate. Alternatively, a separating layer can be used between the substrate 102 and the transistor 100 to be provided. The separation layer can be used when part or all of the semiconductor device formed over the separation layer is removed from the substrate 102 separated and transferred to another substrate. In such a case, the transistor 100 can also be transferred to a substrate with poor heat resistance or a flexible substrate. [First insulating film]

[0079] The insulating film 104 may be formed by a sputtering method, a CVD method, an evaporation method, a laser beam evaporation (pulsed laser deposition, PLD) method, a printing method, a coating method, or the like as required. For example, the insulating film can be 104 can be formed to have a single-layer structure or a multi-layer structure of an oxide insulating film and / or a nitride insulating film. In order to find out the properties of the interface with the oxide semiconductor film 108 to improve, at least a portion of the insulating film becomes 104 that is in contact with the oxide semiconductor film 108 is preferably formed using an oxide insulating film. When the insulating film 104 is formed using an oxide insulating film from which oxygen is released by heating, oxygen contained in the insulating film 104 is contained by heat treatment in the oxide semiconductor film 108 be moved.

[0080] The thickness of the insulating film 104 can be greater than or equal to 50 nm, greater than or equal to 100 nm and less than or equal to 3000 nm, or greater than or equal to 200 nm and less than or equal to 1000 nm. By increasing the thickness of the insulating film 104 can be the amount of oxygen absorbed by the insulating film 104 can be increased, and the interface states at the interface between the insulating film 104 and the oxide semiconductor film 108 and oxygen vacancies formed in the oxide semiconductor film 108 are included.

[0081] For example, the insulating film can be 104 be formed such that it has a single-layer structure or a multilayer structure made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, a Ga-Zn oxide or the like. In this embodiment, the insulating film comprises 104 a multilayer structure of a silicon nitride film and a silicon oxynitride film. By making the insulating film 104 having such a multilayer structure including a silicon nitride film as a lower layer and a silicon oxynitride film as an upper layer, oxygen can efficiently enter the oxide semiconductor film 108 be initiated. [Conductive film]

[0082] The conductive film 112 serving as a gate electrode and the conductive films 120a and 120b that serve as the source electrode and drain electrode can each be made using a metal element composed of chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn) , Molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe) and cobalt (Co), an alloy comprising any of these Contains metal elements as its component, an alloy in which any of these elements are combined, or the like are formed.

[0083] Further, the conductive films 112 , 120a and 120b using an oxide conductor or an oxide semiconductor, such as. B. an oxide containing indium and tin (In-Sn oxide), an oxide containing indium and tungsten (In-W oxide), an oxide containing indium, tungsten and zinc (In-W-Zn Oxide), an oxide containing indium and titanium (In-Ti oxide), an oxide containing indium, titanium and tin (In-Ti-Sn oxide), an oxide containing indium and zinc (In -Zn oxide), an oxide containing indium, tin and silicon (In-Sn-Si oxide), or an oxide containing indium, gallium and zinc (In-Ga-Zn oxide).

[0084] An oxide conductor is described here. In this specification and the like, an oxide conductor may be referred to as OC (Oxide Conductor). For example, the oxide conductor is obtained in the following manner. Oxygen vacancies are formed in an oxide semiconductor, and then hydrogen is added to the oxygen vacancies so that a donor level is formed in the vicinity of the conduction band. This increases the conductivity of the oxide semiconductor; consequently, the oxide semiconductor becomes a conductor. The oxide semiconductor that has become a conductor can be called an oxide conductor. An oxide semiconductor generally allows visible light to pass due to its large energy gap. Since an oxide conductor is an oxide semiconductor having a donor level in the vicinity of the conduction band, an oxide conductor has little influence of absorption due to the donor level, and an oxide conductor has a visible light transmittance comparable to that of an oxide semiconductor .

[0085] Specifically, the above-mentioned oxide conductor is used as the conductive film 112 advantageously used because the insulating film 110 excess oxygen can be added.

[0086] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can be used for the conductive films 112 , 120a and 120b be used. Using a Cu-X alloy film results in lower manufacturing costs because the film can be processed by wet etching.

[0087] Among the metal elements mentioned above, preferably one or more of titanium, tungsten, tantalum and molybdenum in the conductive films is 112 , 120a and 120b contain. In particular, a tantalum nitride film is preferably used for the conductive films 112 , 120a and 120b used. A tantalum nitride film has conductivity and a high barrier property against copper or hydrogen. Since a tantalum nitride film gives off little hydrogen, it can be used advantageously as a conductive film in contact with the oxide semiconductor film 108 or as a conductive film in the vicinity of the oxide semiconductor film 108 be used.

[0088] The conductive films 112 , 120a and 120b can be formed by an electroless plating method. As a material that can be deposited by an electroless plating method, for example, one or more elements selected from Cu, Ni, Al, Au, Sn, Co, Ag, and Pd can be used. It is also advantageous to use Cu or Ag because the electrical resistance of the conductive film can be reduced. [Second insulating film]

[0089] The insulating film 110 used as the gate insulating film of transistor 100 serving, which is an embodiment of the present invention, has a single-layer structure or a multilayer structure including a silicon oxynitride film formed by a plasma-assisted chemical vapor deposition method. The insulating film 110 is subjected to an oxygen plasma treatment.

[0090] When the insulating film 110 According to an embodiment of the present invention is analyzed by TDS, the highest peak of the amount of a discharged gas with a mass-to-charge ratio M / z of 32, which corresponds to an oxygen molecule, appears within a measurement temperature range at a substrate temperature of higher than or equal to 150 ° C and lower than or equal to 300 ° C. The following are the properties of the insulating film 110 an embodiment of the present invention; H. a silicon oxynitride film subjected to oxygen plasma treatment based on Fig. 37, Fig. 38A to Fig. 38C, Fig. 39A to Fig. 39D, Fig. 40A to Fig. 40I, Fig. 41, Fig. 42A and Fig. 42B, Fig. 43A and Fig. 43B and Fig. 44 described.

[0091] Excess oxygen atoms in the silicon oxynitride film are released by thermal excitation. Note that a temperature at which the atoms are released depends on the bonding state of atoms or the like in the film. Many oxygen atoms in the silicon oxynitride film are given off over a wide temperature range. Therefore, if excess oxygen atoms are added to the silicon oxynitride film at low temperatures and then oxygen atoms are supplied to the oxide semiconductor film at high temperatures, a large amount of oxygen atoms can be supplied to the oxide semiconductor film.

[0092] In the case of using a plasma-enhanced chemical vapor deposition (PECVD) method, a silicon oxynitride film formed at high substrate temperatures has high density, high electrical insulation withstand voltage properties and high chemical resistance. In view of these advantages, in the case where the silicon oxynitride film is used in a semiconductor element, the substrate temperature is ideally high during the formation of the silicon oxynitride film. At the same time, in the case of using a silicon oxynitride film as a gate insulating film of a transistor using an oxide semiconductor in a channel, it is important to more effectively supply excess oxygen atoms in the silicon oxynitride film to an oxide semiconductor film in order to increase reliability.

[0093] In this embodiment, in order to increase the amount of excess oxygen atoms, oxygen plasma treatment is performed on a silicon oxynitride film after the silicon oxynitride film is formed. The oxygen plasma treatment is carried out at a substrate temperature lower than or equal to 350.degree. C., preferably lower than or equal to 250.degree. In order to increase the amount of excessive oxygen atoms in the silicon oxynitride film, the substrate temperature is decreased during the formation of the film.

[0094] It should be noted that more oxygen can be supplied to the oxide semiconductor film by varying the conditions of the oxygen plasma treatment performed on the silicon oxynitride film; an example of such a case is described below. Fig. 37 shows the measurement results of the amount of discharged gas having a mass-to-charge ratio M / z of 32, which corresponds to an oxygen molecule, the samples described below being analyzed by TDS. For each sample, a 100 nm thick silicon oxynitride film was formed over an alkali-free glass substrate, and then oxygen plasma treatment was performed on the silicon oxynitride film. In the TDS analysis, the amount of released oxygen molecules was determined using data within the substrate temperature range of 80 ° C to 450 ° C. A gas used for the oxygen plasma treatment was only oxygen. The silicon oxynitride film was made using a SiH 4 Gas and an N 2 O gas is formed by a plasma CVD method at a substrate temperature of 350 ° C. The substrate temperature during the oxygen plasma treatment was 350 ° C.

[0095] Fig. 37 indicates that the smaller the pressure during the oxygen plasma treatment is within a range of 40 Pa to 250 Pa, or the higher the discharge power, the more excess oxygen atoms are released from the silicon oxynitride film as oxygen molecules.

[0096] Fig. 38A to Fig. 38C show the measurement results of the amount of discharged gas having a mass-to-charge ratio M / z of 18, which corresponds to one water molecule, the samples described below being analyzed by TDS. Fig. 38A shows the results of a sample 221 , Fig. 38B shows the results of a sample 222 , and Fig. 38C shows the results of a sample 223 . For each sample, a 100 nm thick IGZO film was formed over an alkali-free glass substrate, and then a 100 nm thick silicon oxynitride film was formed. The silicon oxynitride film was made using an SiH 4 Gas and an N 2 O gas is formed by a plasma CVD method at a substrate temperature of 350 ° C. Thereafter, the sample 222 an oxygen plasma treatment on the silicon oxynitride film at a discharge power of 500 W and on the sample 223 carried out at a discharge power of 3000 W. The vertical axis represents the intensity of a signal, which shows the amount delivered.

[0097] The IGZO film of each sample for TDS analysis was formed by sputtering using an oxide as a target. An atomic ratio of indium to gallium and zinc in the target was 4: 2: 4.1. During the formation of the IGZO film, the substrate temperature was 130 ° C., the flow rate ratio of the gas was Ar: O 2 = 9: 1 and the pressure was 0.6 Pa.

[0098] The results in Fig. 38A to Fig. 38C show that sample 221 emits the largest amount of water molecules at around 120 ° C, followed by sample 222 . The sample 223 gives a small amount of water molecules at around 120 ° C. One of the factors is likely that the oxygen plasma treatment performed on the silicon oxynitride film decreased water adsorbed on a surface.

[0099] Fig. 39A and Fig. 39B each show the measurement results of the hydrogen concentration in the sample 221 , the sample 222 and the sample 223 obtained by secondary ion mass spectrometry (SIMS). In SIMS, profiles were measured from the side of the substrate to a surface of the silicon oxynitride film. An arrow 220 represents the direction of the profile measurements. Fig. 39A to Fig. 39D show a profile 216 in the silicon oxynitride film, a profile 217 in the IGZO film and a profile 218 in the substrate.

[0100] Fig. 39A shows the SIMS results of the hydrogen concentration in the silicon oxynitride films obtained by varying the discharge performance of an oxygen plasma treatment. Fig. 39B shows the SIMS results of the similarly obtained hydrogen concentration in the IGZO films. The sample 221 was produced without oxygen plasma treatment, the sample 222 was made with an oxygen plasma treatment performed at a discharge power of 500 W, and the sample 223 was produced with an oxygen plasma treatment carried out at a discharge power of 3000 W.

[0101] The horizontal axis of each graph in Fig. 39A to Fig. 39D illustrates the depth direction that is perpendicular to the film surface. It should be noted that 0 nm on the horizontal axis represents the position used for the SIMS measurement for convenience, and a range 225 corresponds to the results obtained at a position around the surface of the silicon oxynitride film. In Fig. 39A is the hydrogen concentration in the range 225 in the sample 222 and the sample 223 obtained with oxygen plasma treatment are lower than in the sample 221 obtained without oxygen plasma treatment. The above results suggest that the oxygen plasma treatment performed on the silicon oxynitride film likely decreased water adsorbed on the surface, and therefore differ in Fig. 38A to Fig. 38C shows the amount of water molecules released at about 120 ° C from each other.

[0102] In Fig. 39B, the hydrogen concentration in the IGZO film that has been subjected to the oxygen plasma treatment is decreased. The higher the discharge capacity, the higher the hydrogen concentration of the IGZO film is decreased. Oxygen plasma treatment performed on the silicon oxynitride film is effective for reducing the hydrogen concentration not only on the surface of the silicon oxynitride film but also in the IGZO film, i.e. H. the oxide semiconductor film.

[0103] Fig. 39C and Fig. 39D each show the measurement results obtained by means of SIMS for the hydrogen concentration in a sample 226 , a sample 227 and a sample 228 . The sample 226 is a sample in which no oxygen plasma treatment was performed on a silicon oxynitride film; H. a sample that is under the same conditions as sample 221 was produced. The sample 227 is a sample obtained through the manufacturing process of sample 226 except that oxygen plasma treatment was carried out in a chamber at a gas pressure of 200 Pa. The sample 228 is a sample obtained through the manufacturing process of sample 226 except that oxygen plasma treatment was carried out in a chamber at a gas pressure of 40 Pa. Fig. 39C shows the quantified measurement results of the hydrogen concentration in the silicon oxynitride film, and Fig. 39D shows the quantified measurement results of the hydrogen concentration in the IGZO film. Within a range of the gas pressure in a chamber during the oxygen plasma treatment, namely from 40 Pa to 200 Pa, the hydrogen concentration in the oxide semiconductor film can be decreased as the pressure becomes lower.

[0104] Fig. 40A to Fig. 40I show the measurement results of the amount of a discharged gas having a mass-to-charge ratio M / z of 32 which corresponds to an oxygen molecule, the samples described below being analyzed by TDS. For each sample, a 100 nm thick IGZO film was formed over an alkali-free glass substrate, and then a 100 nm thick silicon oxynitride film was formed. The silicon oxynitride film was made using an SiH 4 Gas and an N 2 O gas is formed by a plasma CVD method at a substrate temperature of 350 ° C. Furthermore, an oxygen plasma treatment was carried out in a chamber at a gas pressure of 200 Pa with a discharge power of 3000 W.

[0105] The samples for TDS analysis were subjected to oxygen plasma treatment for different time periods. Fig. 40A shows the results of the 30 second case, Fig. 40B shows the results of the 60 second case, Fig. 40C shows the results of the case of 100 seconds, Fig. 40D shows the results of the 300 second case, and Fig. 40E shows the results of the 600 second case. These are the results obtained by performing oxygen plasma treatment at a substrate temperature of 220 ° C. Fig. 40F shows the results of the 30 second case, Fig. 40G shows the results of the 60 second case, Fig. 40H shows the results of the case of 100 seconds, and Fig. 40I shows the results of the 300 second case. These are the results obtained by performing oxygen plasma treatment at a substrate temperature of 350 ° C.

[0106] Fig. 40A to Fig. 40I show that the longer the duration of the oxygen plasma treatment performed on the silicon oxynitride film, the greater the amount of oxygen released. Fig. 40A to Fig. 40I also show that the lower the substrate temperature is during the oxygen plasma treatment, the greater the amount of oxygen released.

[0107] Fig. 41 shows the released amounts of oxygen in Fig. 40A to Fig. 40I, where the horizontal axis represents the duration of the oxygen plasma treatment and the vertical axis represents the amount of oxygen released. Dashed line 231 represents values ​​obtained from the results in Fig. 40A to Fig. 40E, which were obtained by performing an oxygen plasma treatment at a substrate temperature of 220 ° C. A solid line 232 represents values ​​obtained from the results in Fig. 40F to Fig. 40I, which were obtained by performing an oxygen plasma treatment at a substrate temperature of 350 ° C. In the case of performing an oxygen plasma treatment at a substrate temperature of 350 ° C., the released amount of oxygen becomes smaller than 2 × 10 14 Molecules / cm 2 saturated when the oxygen plasma treatment time is increased. Meanwhile, in the case of performing oxygen plasma treatment at a substrate temperature of 220 ° C., the amount of oxygen released becomes at least 1.2 × 10 15 Molecules / cm 2 not saturated if the oxygen plasma treatment time is increased. Accordingly, in order to increase the amount of oxygen released, an oxygen plasma treatment is more desirably performed at a substrate temperature of 220 ° C than at a substrate temperature of 350 ° C.

[0108] Fig. 42A and Fig. 42B show the amount of a discharged gas having a mass-to-charge ratio M / z of 32, which corresponds to one oxygen molecule, samples being analyzed by TDS. For each of the samples, a 100 nm thick silicon oxynitride film was formed over an alkali-free glass substrate, and then oxygen plasma treatment was performed on the silicon oxynitride film. The silicon oxynitride film was made using an SiH 4 Gas and an N 2 O gas is formed by a plasma CVD method. Fig. 42A shows the results of the case where the silicon oxynitride film was formed at 350 ° C. The total amount of oxygen released within a measurement temperature range of 80 ° C to 450 ° C is 5.17 × 10 14 Molecules / cm 2 . Fig. 42B shows the results of the case where the silicon oxynitride film was formed at 220 ° C. The total amount of oxygen released within a measurement temperature range of 80 ° C to 450 ° C is 1.47 × 10 15 Molecules / cm 2 .

[0109] One of the reasons that causes the results to be in Fig. 42A and the results in Fig. 42B differ from each other is as follows. The silicon oxynitride film formed at low temperatures (i.e., 220 ° C) has a low film density and contains many voids. Excess oxygen could be added to the vacancies; therefore, there is a possibility that the silicon oxynitride film absorbs or supplies a larger amount of excess oxygen.

[0110] As described above, in order to supply excess oxygen to an oxide semiconductor film from a silicon oxynitride film, it is effective to perform an oxygen plasma treatment on the silicon oxynitride film at low substrate temperatures (a temperature lower than or equal to 350 ° C, e.g. 220 ° C), which To increase discharge capacity, to decrease the pressure in a chamber during discharge, to lengthen the time of oxygen plasma treatment, or to decrease the temperature of the formation of the silicon oxynitride film. It is also effective to increase the thickness of the silicon oxynitride film so long as the silicon oxynitride film is formed to be a source of supply of excess oxygen.

[0111] However, when a silicon oxynitride film is formed over an oxide semiconductor film by a plasma CVD method, the electrical resistance of the oxide semiconductor film may decrease depending on the forming conditions. Fig. 43A and Fig. 43B show the electrical resistance of IGZO films on samples. For each of the samples, a 50 nm thick IGZO film was formed over a quartz glass substrate, and a silicon oxynitride film was formed thereover. In each sample, the substrate was a square with a side of 1 cm, 2 mm square portions of the silicon oxynitride film were removed at the four corners, and 2 mm square electrodes electrically connected to the IGZO film were formed. These electrodes were used as terminals, and the electrical resistance (unit: Ω) between adjacent electrodes was measured.

[0112] The silicon oxynitride films were obtained using an SiH 4 Gas and an N 2 O gas is formed by a plasma CVD method. The thicknesses of the silicon oxynitride films varied between 0 nm (i.e., no film was formed) and 60 nm. For each of the samples, the results of which in Fig. 43A, the silicon oxynitride film was formed at a substrate temperature of 350 ° C. For each of the samples, the results of which are in Fig. 43B, the silicon oxynitride film was formed at a substrate temperature of 220 ° C. Dashed line 235 in each of the Fig. 43A and Fig. 43B shows the electrical resistance of the IGZO film before the silicon oxynitride film is formed.

[0113] When the silicon oxynitride film is formed by a plasma CVD method, hydrogen may diffuse into the IGZO film due to a hydrogen plasma atmosphere in a chamber, and oxygen vacancies and hydrogen or the like may be bonded to each other, resulting in lowering of the electrical resistance of the silicon oxynitride film . The decrease in the electrical resistance of the silicon oxynitride film occurs at a substrate temperature of 350 ° C, which is in Fig. 43A is more evident than at a substrate temperature of 220 ° C, which is shown in Fig. 43B is shown. This is likely because the hydrogen diffusion into the IGZO film and the bonding between oxygen vacancies and hydrogen or the like are improved as the substrate temperature becomes higher. From this point of view, when a silicon oxynitride film is formed by a plasma CVD method, the substrate temperature is ideally low.

[0114] In order to prove the effect of oxygen plasma treatment, the present inventors manufactured display devices each including an oxide semiconductor film and a silicon oxynitride film which had been subjected to oxygen plasma treatment. The display devices were disassembled, and transistors obtained by removing pixel electrodes from the display devices were analyzed by TDS. Fig. 44 shows the results of the amount of discharged gas with a mass-to-charge ratio M / z of 32, which corresponds to one oxygen molecule. An organic resin was removed from each measured sample. A sample 241 was fabricated without oxygen plasma treatment after forming a silicon oxynitride film. A sample 242 was obtained by performing oxygen plasma treatment for 120 seconds. A sample 243 was obtained by performing oxygen plasma treatment for 600 seconds. Although each of the display devices had a structure different from that of an embodiment of the present invention, the silicon oxynitride film was provided over an IGZO film, and the maximum process temperature after the formation of the silicon oxynitride film or the oxygen plasma treatment was 250 ° C.

[0115] Meanwhile, a commercially available display device different from an embodiment of the present invention and including an oxide semiconductor film and a gate insulating film including a silicon oxynitride film was disassembled to obtain a sample 244 from which a pixel electrode has been removed. Fig. 44 shows the results of the analysis of the sample 244 Amount of released gas with a mass-to-charge ratio M / z of 32, which corresponds to an oxygen molecule, obtained by means of TDS.

[0116] Regarding sample 241 , in which the silicon oxynitride film has not been subjected to the oxygen plasma treatment, the highest peak appears within the measurement temperature range of TDS at a temperature lower than or equal to 150 ° C. Regarding each of the sample 242 and the sample 243 in which the silicon oxynitride film has been subjected to the oxygen plasma treatment, the highest peak appears within the measurement temperature range at a temperature between 150 ° C and 350 ° C. In contrast, with respect to the sample obtained from the commercially available display device different from an embodiment of the present invention, the highest peak appears within the measurement temperature range at a temperature between 350 ° C and 450 ° C. Accordingly, the sample obtained from the commercially available display device can be distinguished from the samples each of which has its silicon oxynitride film subjected to the oxygen plasma treatment by the sample temperature at which the highest peak appears.

[0117] The silicon oxynitride film which has been subjected to oxygen plasma treatment contains sufficient excess oxygen. Therefore, even if the silicon oxynitride film subjected to oxygen plasma treatment, which is a feature of the present invention, is analyzed by TDS after supplying oxygen from the silicon oxynitride film to an oxide semiconductor film by a heat treatment performed in a step after the oxygen plasma treatment has been and a semiconductor device or a display device has been completed, the highest peak of the amount of discharged gas having a mass-to-charge ratio M / z of 32, which corresponds to one oxygen molecule, within the measuring temperature range at a temperature between 150 ° C and 350 ° C. The conductivity of an oxide semiconductor film of a transistor included in the finished semiconductor device or display device decreases when heat treatment is performed in the above temperature range.

[0118] In a manufacturing process of the transistor, a heat treatment performed at a temperature higher than or equal to 150 ° C., preferably higher than or equal to 200 ° C., more preferably higher than or equal to 250 ° C., may be performed after an oxygen plasma treatment on the silicon oxynitride film has been performed, supplying oxygen to the oxide semiconductor film. The heat treatment is preferably carried out at a temperature lower than or equal to 450 ° C. because when heat treatment is carried out at a temperature higher than 450 ° C., depending on the atmosphere, oxygen in the oxide semiconductor film is bound to hydrogen and given off as water becomes. Further, in the case where a film containing a metal material is formed, the film absorbs oxygen in the oxide semiconductor film; therefore, in such a case as well, the upper limit of the heat treatment temperature is appropriately set.

[0119] The insulating film 110 may have a multilayer structure of two layers or three or more layers of insulating layers formed by a plasma-assisted chemical vapor deposition method, a sputtering method, or the like in place of the single-layer structure of the silicon oxynitride film. The insulating layers include one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tymantal oxide film, a magnesium oxide film, a lanthanum oxide film, a ceria film, and.

[0120] The insulating film 110 that is in contact with the oxide semiconductor film 108 is used as the channel region of transistor 100 is preferably an oxide insulating film, and preferably includes an area containing more oxygen than the stoichiometric composition (oxygen excess area). In other words, the insulating film 110 is an insulating film that can release oxygen. Around the excess oxygen area in the insulating film 110 For example, the insulating film 110 formed in an oxygen atmosphere, or the deposited insulating film 110 is subjected to heat treatment in an oxygen atmosphere.

[0121] In the case where a multilayer structure containing hafnium oxide is used for the insulating film 110 is used, the following effects are obtained. Hafnium oxide has a higher dielectric constant than silicon oxide and silicon oxynitride. Therefore, by using hafnium oxide, the thickness of the insulating film 110 can be made large compared with the case where silicon oxide is used; thus, leakage current due to tunnel current can be small. That is, it is possible to provide a transistor with a low reverse current. In addition, hafnium oxide with a crystalline structure has a higher dielectric constant than hafnium oxide with an amorphous structure. Therefore, hafnium oxide having a crystalline structure is preferably used in order to obtain a transistor with a low reverse current. Examples of the crystal structure include a monoclinic crystal structure and a cubic crystal structure. It should be noted that an embodiment of the present invention is not limited to the above examples.

[0122] Preferably, the insulating film comprises 110 has only a few defects and typically has as few signals as possible, which are observed by means of electron spin resonance (ESR) spectroscopy. Examples of the signals include a signal attributable to an E 'center observed when the g factor is 2.001. It should be noted that the E 'center is due to the free bonding of silicon. As an insulating film 110 For example, a silicon oxide film or a silicon oxynitride film whose spin density of a signal due to the E 'center is lower than or equal to 3 × 10 17 can be used. Spins / cm 3 and preferably less than or equal to 5 × 10 16 Spins / cm 3 is.

[0123] In addition to the above-described signal, a signal due to nitrogen dioxide (NO 2) May be present in the insulating film 110 to be watched. The signal is divided into three signals according to the N nuclear spin; a first signal, a second signal and a third signal. The first signal is observed when the g-factor is greater than or equal to 2.037 and less than or equal to 2.039. The second signal is observed for a g-factor greater than or equal to 2.001 and less than or equal to 2.003. The third signal is observed for a g-factor greater than or equal to 1.964 and less than or equal to 1.966.

[0124] For example, as an insulating film, 110 is suitably used. an insulating film whose spin density of a signal due to nitrogen dioxide (NO 2) is higher than or equal to 1 × 10 17 Spins / cm 3 and lower than 1 × 10 18 Spins / cm 3 is used.

[0125] It should be noted that nitrogen oxide (NO x) Such as. B. nitrogen dioxide (NO 2), A state in the insulating film 110 forms. The state is in the energy gap of the oxide semiconductor film 108 . When nitrogen oxide (NO x) In the interface between the insulating film 110 and the oxide semiconductor film 108 diffused, therefore, an electron could pass through the state on the insulating film side 110 be captured. As a result, the trapped electron remains in the vicinity of the interface between the insulating film 110 and the oxide semiconductor film 108 which results in a positive shift in the threshold voltage of the transistor. Accordingly, the use of a film having a low nitrogen oxide content as the insulating film 110 reduce a shift in the threshold voltage of the transistor.

[0126] As the insulating film that emits a small amount of nitrogen oxide (NO x), A silicon oxynitride film can be used, for example. The silicon oxynitride film emits more ammonia than nitrogen oxide (NO x) In TDS analysis; the typical amount of ammonia released is greater than or equal to 1 × 10 18 Molecules / cm 3 and less than or equal to 5 × 10 19 Molecules / cm 3 . It should be noted that the amount of ammonia released is the total amount of ammonia released by a heat treatment in a range of 50 ° C to 650 ° C or 50 ° C to 550 ° C in TDS analysis.

[0127] Since nitrogen oxide (NO x) Reacts with ammonia and oxygen upon heat treatment, the use of an insulating film that emits a large amount of ammonia reduces nitrogen oxide (NO x).

[0128] It should be noted that in the case where the insulating film 110 is analyzed by SIMS, the nitrogen concentration in the film is preferably lower than or equal to 6 × 10 20 Atoms / cm 3 is. [Oxide semiconductor film]

[0129] The oxide semiconductor film 108 can be formed using the materials described above.

[0130] In the case where the oxide semiconductor film 108 contains an In-M-Zn oxide, the atomic ratio of the metal elements of a sputtering target which is used to form the In-M-Zn oxide preferably In> M. The atomic ratio between metal elements in such a sputtering target is, for example, In: M : Zn = 2: 1: 3, In: M: Zn = 3: 1: 2 or In: M: Zn = 4: 2: 4.1.

[0131] In the case where the oxide semiconductor film 108 consists of an In-M-Zn oxide, a target containing polycrystalline In-M-Zn oxide is preferably used as the sputtering target. Using a target containing polycrystalline In-M-Zn oxide facilitates the formation of the oxide semiconductor film 108 with crystallinity. It should be noted that the atomic ratio of metal elements in the formed oxide semiconductor film is 108 as a deviation from the above atomic ratios of metal elements of the sputtering target in a range of ± 40%. For example, if a sputtering target with an atomic ratio of In to Ga and Zn of 4:2:4,1 is used, the atomic ratio of In to Ga and Zn in the oxide semiconductor film formed can be 108 at 4:2:3 or in the vicinity of 4:2:3 lie.

[0132] The energy gap of the oxide semiconductor film 108 is 2 eV or more, preferably 2.5 eV or more. By using an oxide semiconductor having such a large energy gap, the reverse current of the transistor 100 be reduced.

[0133] The thickness of the oxide semiconductor film 108 is greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, more preferably greater than or equal to 3 nm and less than or equal to 50 nm.

[0134] Furthermore, the oxide semiconductor film can 108 have a non-monocrystalline structure. Examples of the non-single crystalline structure include a c-axis aligned crystalline oxide semiconductor (CAAC-OS) which will be described below, a polycrystalline structure, a microcrystalline structure, and an amorphous structure. [Third insulating film]

[0135] The insulating film 116 contains nitrogen or hydrogen. As an insulating film 116 For example, a nitride insulating film can be used. In particular, a film containing silicon nitride, silicon nitride oxide, silicon oxynitride or the like can be used as the nitride insulating film. The hydrogen concentration in the insulating film 116 is preferably greater than or equal to 1 × 10 22 Atoms / cm 3 . The insulating film 116 is in contact with the second area 108n of the oxide semiconductor film 108 . Therefore, the concentration of an impurity (nitrogen or hydrogen) in the second area becomes 108n in contact with the insulating film 116 increases, leading to an increase in the charge carrier density of the second region 108n leads. [Fourth insulating film]

[0136] As an insulating film 118 an oxide insulating film can be used. Alternatively, a multilayer film of an oxide insulating film and a nitride insulating film can be used as the insulating film 118 be used. The insulating film 118 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn oxide, for example.

[0137] The insulating film 118 is also used. preferably as a barrier film against hydrogen, water or the like from the outside.

[0138] The thickness of the insulating film 118 can be greater than or equal to 30 nm and less than or equal to 500 nm, or greater than or equal to 100 nm and less than or equal to 400 nm. <Structural example 2 of a transistor>

[0139] Next, a structure of a transistor different from that in Fig. 1A to Fig. 1C differs based on Fig. 2A to Fig. 2C.

[0140] Fig. 2A is a top view of transistor 100A . Fig. 2B is a cross-sectional view taken along a chain line X1-X2 in Fig. 2A. Fig. 2C is a cross-sectional view taken along a chain line Y1-Y2 in Fig. 2A.

[0141] The transistor 100A , which is in Fig. 2A to Fig. 2C includes the conductive film 106 above the substrate 102 , the insulating film 104 over the conductive film 106 , the oxide semiconductor film 108 over the insulating film 104 , the insulating film 110 over the oxide semiconductor film 108 , the conductive film 112 over the insulating film 110 and the insulating film 116 over the insulating film 104 , the oxide semiconductor film 108 and the conductive film 112 .

[0142] The transistor 100A includes the conductive film 106 and an opening 143 in addition to the components of transistor 100 which has been described above.

[0143] It should be noted that the opening 143 in the insulating films 104 and 110 is provided. The conductive film 106 is electrically connected to the conductive film 112 via the opening 143 connected. Therefore, the same potential is applied to the conductive film 106 and the conductive film 112 created. It should be noted that, without the opening 143 to provide different potentials on the conductive film 106 and the conductive film 112 can be created. Alternatively, without the opening 143 to provide the conductive film 106 can be used as an opaque film. For example, when the conductive film 106 is formed using an opaque material, the light irradiation of the first area can be 108i be reduced from below.

[0144] In the case of the structure of transistor 100A the conductive film 106 is used. as the first gate electrode (also referred to as the bottom gate electrode), the conductive film 112 as the second gate electrode (also referred to as the top gate electrode), the insulating film 104 as the first gate insulating film and the insulating film 110 as a second gate insulating film.

[0145] The conductive film 106 can be formed using a material similar to the above-described conductive film materials 112 , 120a and 120b is similar. In particular, a material containing copper is suitably used as the conductive film 106 is used because the electrical resistance can be reduced. It is preferable that, for example, each of the conductive films 106 , 120a and 120b has a multilayer structure in which a copper film is overlaid over a titanium nitride film, a tantalum nitride film, or a tungsten film. In this case, using transistor 100A as a pixel transistor and / or driver transistor of a display device, a parasitic capacitance which occurs between the conductive films 106 and 120a as well as between the conductive films 106 and 120b generated can be reduced. Therefore, the conductive films 106 , 120a and 120b not only as the first gate electrode, source electrode and drain electrode of transistor 100A but also as power source supply lines, signal supply lines, connection lines, or the like of the display device.

[0146] In this way, transistor 100A in Fig. 2A to Fig. 2C in contrast to the transistor 100 described above. has a structure in which a conductive film serving as a gate electrode is above and below the oxide semiconductor film 108 is provided. As with the transistor 100A For example, a semiconductor device of one embodiment of the present invention may have a plurality of gate electrodes.

[0147] As in Fig. 2B and Fig. As shown in Fig. 2C, the oxide semiconductor film is 108 the conductive film 106 serving as the first gate electrode and the conductive film 112 , which serves as the second gate electrode, faces and lies between the two conductive films, which serve as gate electrodes.

[0148] Furthermore, the length of the conductive film is 112 longer than the length of the oxide semiconductor film 108 in the channel width direction. in the channel width direction. In the channel width direction, the entire oxide semiconductor film is 108 with the conductive film 112 covered with the insulating film 110 lies in between. Since the conductive film 112 via the opening 143 contained in the insulating films 104 and 110 is provided with the conductive film 106 is connected, a side surface of the oxide semiconductor film is 108 in the channel width direction, the conductive film 112 facing, the insulating film 110 lies in between.

[0149] In other words, the conductive film 106 and the conductive film 112 are via the opening 143 contained in the insulating films 104 and 110 is provided, and each include a region extending outside an edge portion of the oxide semiconductor film 108 is located.

[0150] With such a structure, electric fields of the conductive film 106 serving as the first gate electrode and the conductive film 112 serving as the second gate electrode, the oxide semiconductor film 108 that is in the transistor 100A is included, electrically enclose. A device structure of a transistor such as that of transistor 100A , in which electric fields of the first gate electrode and the second gate electrode cause the oxide semiconductor film 108 Electrically enclose, in which a channel region is formed, can be referred to as an enclosed channel (S-channel, S-channel) structure.

[0151] Since the transistor 100A has the S-channel structure, an electric field for inducing a channel can be applied through the conductive film 106 or the conductive film 112 effectively to the oxide semiconductor film 108 be created; therefore, the current driving ability of transistor 100A can be improved and high forward current characteristics can be achieved. The high forward current means that it is possible to reduce the size of the transistor 100A to reduce. Furthermore, since the transistor 100A has a structure in which the oxide semiconductor film 108 of the conductive film 106 and the conductive film 112 is enclosed, the mechanical strength of the transistor 100A increase.

[0152] In the channel width direction of the transistor 100A can have an opening that differs from opening 143 differs, on the side of the oxide semiconductor film 108 on which the opening 143 is not trained, trained.

[0153] When a transistor such as transistor 100A , includes a pair of gate electrodes sandwiched by a semiconductor film, one of the gate electrodes can be supplied with a signal A and the other gate electrode can be supplied with a fixed potential V b are supplied. Alternatively, one of the gate electrodes can be supplied with the A signal and the other gate electrode can be supplied with a B signal. Alternatively, one of the gate electrodes may have a fixed potential V a can be supplied, and the other gate electrode can be supplied with the fixed potential V b are supplied.

[0154] The signal A is, for example, a signal for controlling the on / off state. The signal A can be a digital signal with two kinds of potentials, namely a potential V1 and a potential V2 (V1> V2). For example, the potential V1 be a high power supply potential, and the potential V2 can be a low power supply potential. The signal A can be an analog signal.

[0155] The fixed potential V b For example, a potential for controlling a threshold voltage is V thA of the transistor. The fixed potential V b can use the potential V1 or the potential V2 be. In this case, there is no potential generating circuit for generating the fixed potential V b necessary, which is preferable. The fixed potential V b can differ from the potential V1 or the potential V2 distinguish. When the fixed potential V b is low, the threshold voltage can be V thA in some cases high. As a result, the drain current that flows when the gate-source voltage V gs is 0 V, and leakage current in a circuit including the transistor can be reduced in some cases. The fixed potential V b can for example be lower than the low power supply potential. Meanwhile, a high fixed potential V b in some cases the threshold voltage V thA reduce. As a result, in some cases, the drain current that flows when the gate-source voltage can be V gs is a high power supply potential, and the operation speed of the circuit including the transistor can be increased. The fixed potential V b can for example be higher than the low power supply potential.

[0156] The signal B is, for example, a signal for controlling the on / off state. The signal B can be a digital signal with two kinds of potentials, namely a potential V3 and a potential V4 (V3> V4). For example, the potential can be V3 be a high power supply potential, and the potential V4 can be a low power supply potential. The signal B can be an analog signal.

[0157] When both signal A and signal B are digital signals, signal B may have the same digital value as signal A. In this case it may be possible to determine the forward current of the transistor and the speed of operation of the circuit including the transistor to increase. The potential V1 and the potential V2 of the signal A from the potential V3 and the potential V4 of signal B. For example, if a gate insulating film for the gate to which the signal B is inputted is thicker than a gate insulating film for the gate to which the signal A is inputted, the potential amplitude of the signal B (V3 - V4) be greater than the potential amplitude of signal A (V1 - V2). In this way, the influence of signal A and that of signal B on the on / off state of the transistor can in some cases be substantially the same.

[0158] When both signal A and signal B are digital signals, signal B may have a digital value different from that of signal A. In this case, the A signal and the B signal can separately control the transistor, and therefore higher performance can be obtained. The transistor, which is, for example, an n-channel transistor, can serve solely as a NAND circuit, NOR circuit or the like in the following case: The transistor is switched on only when the signal A has the potential V1 and the signal B has the potential V3 or the transistor is switched off only when the signal A has the potential V2 and the signal B has the potential V4 having. The signal B can be a signal for controlling the threshold voltage V thA be. For example, the potential of the signal B in a period in which the circuit including the transistor is operating may differ from the potential of the signal B in a period in which the circuit is not operating. The potential of the signal B may vary depending on the operating mode of the circuit. In this case, in some cases, the potential of the signal B is not changed as often as the potential of the signal A.

[0159] When both the signal A and the signal B are analog signals, the signal B can be an analog signal having the same potential as the signal A, an analog signal whose potential is a constant multiple of the potential of the signal A, an analog one Signal whose potential is higher or lower than the potential of signal A by a constant, or the like. In this case, it may be possible to increase the forward current of the transistor and the speed of operation of the circuit including the transistor. Signal B can be an analog signal that differs from signal A. In this case, the A signal and the B signal can separately control the transistor, and therefore higher performance can be obtained.

[0160] Signal A can be a digital signal and signal B can be an analog signal. Alternatively, signal A can be an analog signal and signal B can be a digital signal.

[0161] When the two gate electrodes of the transistor are supplied with the fixed potentials, the transistor can serve as an element equivalent to a resistor in some cases. For example, in the case where the transistor is an n-channel transistor, the effective resistance of the transistor may sometimes be low (high) when the fixed potential V a or the fixed potential V b is high (low). When both the fixed potential V a as well as the fixed potential V b are high (low), the effective resistance may in some cases be lower (higher) than that of a transistor with only one gate.

[0162] The other components of transistor 100A are those of the above-described transistor 100 similar and have similar effects.

[0163] Furthermore, an insulating film may be provided over the transistor 100A be formed. An example of such a case is in Fig. 3A and Fig. 3B. Fig. 3A and Fig. 3B are cross-sectional views of a transistor 100B . The top view of the transistor 100B is not shown as it is the one on transistor 100A in Fig. 2A is similar.

[0164] The transistor 100B , which is in Fig. 3A and Fig. 3B includes an insulating film 122 over the conductive films 120a and 120b and the insulating film 118 . The other components of transistor 100B are those of transistor 100A similar and have similar effects.

[0165] The insulating film 122 has a function of covering an unevenness and the like caused by the transistor or the like. The insulating film 122 has an insulating property and is formed using an inorganic material or an organic material. Examples of the inorganic material include a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, and an aluminum nitride film. Examples of the organic material include photosensitive resin materials such as. B. an acrylic resin and a polyimide resin. <Structural example 3 of a transistor>

[0166] Next, a structure of a transistor different from that of transistor 100A in Fig. 2A to Fig. 3C differs based on Fig. 4A and Fig. 4B.

[0167] Fig. 4A and Fig. 4B are cross-sectional views of a transistor 100C . The top view of the transistor 100C is not shown because it is the same as that of transistor 100A in Fig. 2A is similar.

[0168] The transistor 100C , which is in Fig. 4A and Fig. 4B is different from transistor 100A by the multilayer structure of the conductive film 112 , the shape of the conductive film 112 and the shape of the insulating film 110 .

[0169] The conductive film 112 in the transistor 100C includes a conductive film 112_1 over the insulating film 110 and the conductive film 112_2 over the conductive film 112_1. For example, a conductive oxide film is used as the conductive film 112_1 so that the insulating film 110 excess oxygen can be added. The conductive oxide film can be formed by a sputtering method in an atmosphere containing an oxygen gas. As the conductive oxide film, for example, an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, an oxide containing indium, gallium and zinc, or the like can be used.

[0170] As in Fig. As shown in Fig. 4B, the conductive film 112_2 is the conductive film 106 via the opening 143 connected. By forming the opening 143 after the formation of a conductive film which becomes the conductive film 112_1, the process shown in Fig. 4B can be obtained. In the case where an oxide conductive film is used as the conductive film 112_1, the structure in which the conductive film 112_2 with the conductive film 106 may be used. is connected, the contact resistance between the conductive film 112 and the conductive film 106 reduce.

[0171] The conductive film 112 and the insulating film 110 in the transistor 100C have a tapered shape. More specifically, the lower edge portion of the conductive film 112 is outside the upper edge portion of the conductive film 112 . The lower edge portion of the insulating film 110 is outside the upper edge portion of the insulating film 110 . In addition, the lower edge portion of the conductive film becomes 112 at substantially the same position as the upper edge portion of the insulating film 110 educated.

[0172] Compared to the transistor 100A where the conductive film 112 and the insulating film 110 have a rectangular shape, the transistor is 100C where the conductive film 112 and the insulating film 110 have a tapered shape due to better coverage with the insulating film 116 preferable.

[0173] The other components of transistor 100C are those of the transistor 100A described above. similar and have similar effects. <Manufacturing method of semiconductor device>

[0174] Next, an example of a method of manufacturing the transistor 100A will be discussed. , which is in Fig. 2A to Fig. 2C based on Fig. 5A to Fig. 5D, Fig. 6A to Fig. 6C and Fig. 7A to Fig. 7C. It should be noted that Fig. 5A to Fig. 5D, Fig. 6A to Fig. 6C and Fig. 7A to Fig. 7C are cross-sectional views in the channel length (L) direction and the channel width (W) direction showing the method of manufacturing the transistor 100A represent.

[0175] First, the conductive film becomes 106 above the substrate 102 educated. Then the insulating film becomes 104 above the substrate 102 and the conductive film 106 is formed, and an island-shaped oxide semiconductor film 108i_0 is formed over the insulating film 104 (see Fig. 5A).

[0176] The conductive film 106 can be formed using a material of the aforementioned materials. In this embodiment, the conductive film is 106 a multilayer film of a 50 nm thick tungsten film and a 400 nm thick copper film is formed by a sputtering device.

[0177] To process the conductive film, which becomes the conductive film 106 a wet etching process and / or a dry etching process can be used. In this embodiment, when the conductive film is processed into the conductive film, 106 the copper film is etched by a wet etching method, and then the tungsten film is etched by a dry etching method.

[0178] The insulating film 104 can be formed by a sputtering method, a CVD method, an evaporation method, a laser beam evaporation (PLD) method, a printing method, a coating method, or the like as required. In this embodiment, a 400 nm thick silicon nitride film and a 50 nm thick silicon oxynitride film as the insulating film become 104 formed by means of a plasma CVD device.

[0179] After the insulating film 104 has been formed, the insulating film 104 Oxygen can be added. As oxygen added to the insulating film 104 is added, an oxygen radical, an oxygen atom, an oxygen atom ion, an oxygen molecular ion or the like can be used. Oxygen can be added by an ion doping method, an ion implantation method, a plasma treatment method, or the like. Alternatively, a film suppressing the release of oxygen may be provided over the insulating film 104 can be formed, and then the insulating film 104 Oxygen can be added through the film.

[0180] The film suppressing release of oxygen can be formed using a conductive film or a semiconductor film consisting of one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt and contains tungsten.

[0181] In the case where oxygen is added by a plasma treatment in which oxygen is excited by a microwave to generate a high-density oxygen plasma, the amount of oxygen added to the insulating film 104 is added.

[0182] The island-shaped oxide semiconductor film 108i_0 may have a single-layer structure, for example. Preferably, the oxide semiconductor film 108i_0 has a multilayer structure of a first oxide semiconductor film and a second oxide semiconductor film. In the case where the oxide semiconductor film 108i_0 has a multilayer structure, the substrate temperature and / or the percentage of oxygen flow rate when forming the first oxide semiconductor film is / are preferably lower than those when forming the second oxide semiconductor film.

[0183] In particular, the conditions for forming the first oxide semiconductor film are set as follows: the substrate temperature is higher than or equal to room temperature and lower than 150 ° C, preferably higher than or equal to 100 ° C and lower than or equal to 140 ° C, and the percentage of Oxygen flow rate is higher than 0% and lower than 30%. Furthermore, the conditions for forming the second oxide semiconductor film are set as follows: The substrate temperature is higher than or equal to 150 ° C and lower than or equal to 350 ° C, preferably higher than or equal to 160 ° C and lower than or equal to 200 ° C, and the percentage of oxygen flow rate is greater than or equal to 30% and less than or equal to 100%.

[0184] Under the above-described conditions, the oxide semiconductor films having different carrier densities can be stacked. It should be noted that it is more advantageous to successively form the first oxide semiconductor film and the second oxide semiconductor film in vacuum because impurities can be prevented from being trapped at the interfaces.

[0185] When the oxide semiconductor film 108i_0 is formed while being heated, the crystallinity of the oxide semiconductor film can be 108 increase. However, in the case where a large glass substrate (e.g. that of the sixth generation to the tenth generation) could be used as the substrate 102 is used and the oxide semiconductor film 108 is formed at a substrate temperature of higher than or equal to 200 ° C. and lower than or equal to 300 ° C., the substrate 102 deformed (distorted or bent). In the case where a large glass substrate is used, the deformation of the glass substrate can be suppressed by making the oxide semiconductor film 108 is formed at a substrate temperature higher than or equal to 100 ° C and lower than 200 ° C.

[0186] In addition, it is necessary to increase the purity of a sputtering gas. For example, as the oxygen gas or argon gas used as the sputtering gas, there is used a gas which is highly purified to have a dew point of -40 ° C or lower, preferably -80 ° C or lower, more preferably -100 ° C or lower , still more preferably -120 ° C or lower, whereby the intrusion of moisture or the like into the oxide semiconductor film can be minimized.

[0187] In the case where the oxide semiconductor film is deposited by a sputtering method, a chamber in a sputtering device is preferably evacuated by evacuation with an adsorption vacuum pump such as a vacuum pump. B. a cryopump, put in a high vacuum state (for example, to a degree of about 5 × 10 -7 Pa to 1 × 10 -4 Pa) to water or the like, which is used as an impurity for the oxide semiconductor film serves to remove as much as possible. In particular, the partial pressure of gas molecules is H 2 O (gas molecules corresponding to M / z = 18), in the chamber in the standby mode of the sputtering device, preferably lower than or equal to 1 × 10 -4 Pa, more preferably less than or equal to 5 × 10 -5 Pa.

[0188] In addition, the first oxide semiconductor film is formed by a sputtering method using a target made of an In-Ga-Zn oxide semiconductor (In: Ga: Zn = 4: 2: 4.1 in atomic ratio). The substrate temperature during formation of the first oxide semiconductor film is 130 ° C, and an oxygen gas with a flow rate of 20 sccm and an argon gas with a flow rate of 180 sccm are used as the deposition gas (percentage of the oxygen flow rate: 10%).

[0189] The second oxide semiconductor film is formed by a sputtering method using a target made of an In-Ga-Zn oxide semiconductor (In: Ga: Zn = 4: 2: 4.1 in atomic ratio). The substrate temperature during formation of the second oxide semiconductor film is 170 ° C, and an oxygen gas with a flow rate of 60 sccm and an argon gas with a flow rate of 140 sccm are used as the deposition gas (the percentage of the oxygen flow rate: 30%).

[0190] It should be noted that, although in the example described above, the multilayer structure was formed from the oxide semiconductor films having different carrier densities by varying the substrate temperature and the percentage of the oxygen flow rate between the first oxide semiconductor film and the second oxide semiconductor film, the method for forming the Structure is not limited to this example. For example, an impurity element may be added when the first oxide semiconductor film is formed in order to make the carrier density of the first oxide semiconductor film different from that of the second oxide semiconductor film. Examples of the impurity element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine and a rare gas element.

[0191] In particular, among the elements described above, nitrogen is preferable as an impurity element to be added to the first oxide semiconductor film. For example, nitrogen may be added to the first oxide semiconductor film using an argon gas and a nitrogen gas as the deposition gas or using an argon gas and nitrous oxide as the deposition gas in forming the first oxide semiconductor film.

[0192] In the case where an impurity element is used to form the first oxide semiconductor film, it is advantageous to separately provide a chamber for forming the first oxide semiconductor film in order to prevent the impurity element from being converted into a film to which the impurity element is preferably not added, z. B. the second oxide semiconductor film occurs.

[0193] After the first oxide semiconductor film is formed, an impurity element may be added to the first oxide semiconductor film. As a method of adding an impurity element after the formation of the first oxide semiconductor film, for example, doping treatment or plasma treatment can be used.

[0194] After the first oxide semiconductor film and the second oxide semiconductor film are formed, the first oxide semiconductor film and the second oxide semiconductor film may be subjected to a heat treatment for dehydration or dehydration. The temperature of the heat treatment is typically higher than or equal to 150 ° C and lower than the stress relief limit of the substrate, higher than or equal to 250 ° C and lower than or equal to 450 ° C or higher than or equal to 300 ° C and lower than or equal to 450 ° C.

[0195] The heat treatment can be carried out in an inert gas atmosphere containing nitrogen or a noble gas such as. B. helium, neon, argon, xenon or krypton contains. Alternatively, the heat treatment can be carried out first in an inert gas atmosphere and then in an oxygen atmosphere. Preferably, the above inert gas atmosphere and the above oxygen atmosphere do not contain hydrogen, water or the like. The treatment time is longer than or equal to 3 minutes and shorter than or equal to 24 hours.

[0196] An electric furnace, an RTA device, or the like can be used for the heat treatment. Using an RTA device, the heat treatment can be carried out at a temperature higher than or equal to the relaxation limit of the substrate if the heating time is short. Therefore, the heat treatment time can be shortened.

[0197] By depositing the oxide semiconductor film while it is being heated or performing heat treatment after the oxide semiconductor film is formed, the hydrogen concentration in the oxide semiconductor film measured by SIMS can become 5 × 10 19 Atoms / cm 3 or lower, 1 × 10 19 Atoms / cm 3 or lower, 5 × 10 18 Atoms / cm 3 or lower, 1 × 10 18 Atoms / cm 3 or lower, 5 × 10 17 Atoms / cm 3 or lower or 1 × 10 16 Atoms / cm 3 or lower.

[0198] Next, an insulating film 110_0 becomes over the insulating film 104 and the oxide semiconductor film (see Fig. 5B).

[0199] As the insulating film 110_0, a silicon oxide film or a silicon oxynitride film can be formed using a plasma-enhanced chemical vapor deposition device (a PECVD device; or simply referred to as a plasma CVD device). In this case, a deposition gas containing silicon and an oxidizing gas are preferably used as the source gas. Typical examples of the silicon-containing deposition gas include silane, disilane, trisilane, and silane fluoride. As examples of the oxidizing gas, oxygen, ozone, nitrous oxide and nitrogen dioxide can be given.

[0200] A silicon oxynitride film having few defects can be formed as the insulating film 110_0 with a plasma CVD device under the following conditions: The flow rate of an oxidizing gas is more than 20 times and less than 100 times, or more than or equal to 40 times and less than or equal to 80 times the flow rate of the deposition gas, and the pressure in a treatment chamber is less than 100 Pa or less than or equal to 50 Pa.

[0201] As the insulating film 110_0, a dense silicon oxide film or a dense silicon oxynitride film can be formed under the following conditions: The substrate placed in an evacuated processing chamber of a plasma CVD apparatus is at a temperature higher than or equal to 280 ° C and lower than or kept equal to 400 ° C; the pressure in the treatment chamber into which a source gas is introduced is set to be higher than or equal to 20 Pa and lower than or equal to 250 Pa, preferably higher than or equal to 100 Pa and lower than or equal to 250 Pa; and high frequency power is supplied to an electrode in the treatment chamber.

[0202] The insulating film 110_0 can be formed by a plasma CVD method using a microwave. A microwave describes a wave in the frequency range from 300 MHz to 300 GHz. In a microwave, the electron temperature and energy are low. Furthermore, in the supplied power, the proportion of the power used to accelerate the electrons is low, and therefore the much more power can be used for dissociation and ionization of molecules. Therefore, a high-density plasma (high-density plasma) can be excited. This method hardly causes plasma damage to the deposition surface or a deposition product, so that the insulating film 110_0 can be formed with few defects.

[0203] Alternatively, the insulating film 110_0 can also be formed by a CVD method using an organosilane gas. The following silicon-containing compound can be used as the organosilane gas: tetraethylorthosilicate (TEOS) (chemical formula: Si (OC 2 H 5) 4), Tetramethylsilane (TMS) (chemical formula : Si (CH 3) 4), Tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH (OC 2 Ha / > 00001165) 3), Trisdimethylaminosilane (SiH (N (CH 3) 2) 3) Or the like. By a CVD method using an organosilane gas, the insulating film 110_0 can be formed with a high coverage.

[0204] In this embodiment, a 100 nm thick silicon oxynitride film is formed as the insulating film 110_0 by means of a plasma CVD device.

[0205] Subsequently, a mask is formed by lithography at a required position over the insulating film 110_0, and then the insulating film 110_0 and the insulating film become 104 partially etched so that the opening 143 that have the conductive film 106 reached, is formed (see Fig. 5C).

[0206] Around the opening 143 to form, a wet etching process and / or a dry etching process can be used. In this embodiment, the opening becomes 143 formed by a dry etching method.

[0207] Next, a conductive film 112_0 becomes over the conductive film 106 and the insulating film 110_0 formed to have the opening 143 covered. For example, in the case where a metal oxide film is used as the conductive film 112_0, oxygen from the conductive film 112_0 may be added to the insulating film 110_0 during the formation of the conductive film 112_0 (see Fig. 5D).

[0208] In Fig. 5D, oxygen added to the insulating film 110_0 is schematically shown by arrows. Furthermore, the conductive film 112_0 formed to have the opening 143 covered electrically with the conductive film 106 connected.

[0209] In the case where a metal oxide film is used as the conductive film 112_0, the conductive film 112_0 is preferably formed by a sputtering method in an atmosphere containing an oxygen gas. Forming the conductive film 112_0 in an atmosphere containing an oxygen gas enables oxygen to be appropriately added to the insulating film 110_0. It should be noted that a method of forming the conductive film 112_0 is not limited to a sputtering method, and other methods such as sputtering. B. an atomic layer deposition (ALD) process can be used.

[0210] In this embodiment, as the conductive film 112_0, a 100 nm thick IGZO film containing an In-Ga-Zn oxide (In: Ga: Zn = 4: 2: 4.1 [atomic ratio]) is formed by a sputtering method. It should be noted that an oxygen addition treatment may be performed on the insulating film 110_0 before or after the formation of the conductive film 112_0. The oxygen addition treatment can be performed in a similar manner to the oxygen addition that is performed after the insulating film 104 is formed. can be carried out.

[0211] Then a mask 140 formed by a lithography process at a required position over the conductive film 112_0 (see Fig. 6A).

[0212] Next, etch from above the mask 140 is performed to process the conductive film 112_0 and the insulating film 110_0. After processing the conductive film 112_0 and the insulating film 110_0, the mask becomes 140 away. As a result of processing the conductive film 112_0 and the insulating film 110_0, the island-shaped conductive film becomes 112 and the island-shaped insulating film 110 (see Fig. 6B).

[0213] In this embodiment, the conductive film 112_0 and the insulating film 110_0 are processed by a dry etching method.

[0214] When processing into the conductive film 112 and the insulating film 110 becomes the thickness of the oxide semiconductor film in an area that does not coincide with the conductive film 112 overlaps, in some cases decreased. In other cases, processing becomes the conductive film 112 and the insulating film 110 the thickness of the insulating film 104 is reduced in an area that does not overlap with the oxide semiconductor film. In processing the conductive film 112_0 and the insulating film 110_0, an etching solution or an etching gas (e.g., chlorine) may be added to the oxide semiconductor film, or the constituent element of the conductive film 112_0 or the insulating film 110_0 may be added to the oxide semiconductor film.

[0215] Next, the insulating film becomes 116 over the insulating film 104 , the oxide semiconductor film and the conductive film 112 is formed, thereby a part of the oxide semiconductor film that is in contact with the insulating film 116 is to the second area 108n becomes. Furthermore, part of the oxide semiconductor film that is in contact with the insulating film becomes 110 is, to the first area 108i . Accordingly, the oxide semiconductor film becomes 108 is formed which has the first area 108i and the second area 108n includes (see Fig. 6C).

[0216] The insulating film 116 can be formed using a material of the aforementioned materials. In this embodiment, the insulating film is 116 a 100 nm thick silicon nitride oxide film was formed by a plasma CVD device. In forming the silicon nitride oxide film, plasma treatment and deposition treatment are performed at 220 ° C. The plasma treatment is carried out before the deposition under the following conditions: an argon gas is introduced into a chamber at a flow rate of 100 sccm, the pressure in the chamber is set to 40 Pa, and a power of 1000 W is supplied to an HF power source ( 27.12 MHz). The deposition treatment is carried out under the following conditions: a silane gas with a flow rate of 50 sccm, a nitrogen gas with a flow rate of 5000 sccm, and an ammonia gas with a flow rate of 100 sccm are introduced into the chamber, the pressure in the chamber becomes 100 Pa is set, and a power of 1000 W is supplied to the HF power source (27.12 MHz).

[0217] When the insulating film 116 includes a silicon nitride oxide film, nitrogen or hydrogen in the silicon nitride oxide film may be the second region 108n in contact with the insulating film 116 are fed. In addition, if the temperature when the insulating film is formed can be 116 the above-mentioned temperature is the release of excess oxygen contained in the insulating film 110 is contained, be suppressed to the outside.

[0218] Next, the insulating film becomes 118 over the insulating film 116 (see Fig. 7A).

[0219] The insulating film 118 can be formed using a material of the aforementioned materials. In this embodiment, the insulating film is 118 a 300 nm thick silicon oxynitride film was formed by a plasma CVD device.

[0220] Then, a mask is made at required positions over the insulating film 118 formed by lithography, and the insulating film 118 and the insulating film 116 are partially etched. Therefore, the openings become 141a and 141b formed, which the second area 108n reach (see Fig. 7B).

[0221] Around the insulating films 118 and 116 To etch, a wet etching process and / or a dry etching process can be used. In this embodiment, the insulating films become 118 and 116 processed by a dry etching process.

[0222] Next, place a conductive film over the second area 108n and the insulating film 118 formed such that it has the openings 141a and 141b covered, and processed into necessary shapes so that the conductive films 120a and 120b (see Fig. 7C).

[0223] The conductive films 120a and 120b can be formed using a material of the aforementioned materials. In this embodiment, the conductive films 120a and 120b a multilayer film including a 50 nm thick tungsten film and a 400 nm thick copper film is formed by a sputtering device.

[0224] In order to process the conductive film that becomes the conductive films 120a and 120b a wet etching process and / or a dry etching process can be used. In this embodiment, when the conductive film is processed into the conductive films, 120a and 120b the copper film is etched by a wet etching method, and then the tungsten film is etched by a dry etching method.

[0225] Through the above process, the transistor 100A in Fig. 2A to Fig. 2C.

[0226] It should be noted that the films included in the transistor 100A are included (the insulating film, the oxide semiconductor film, the conductive film and the like) besides the above methods by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a laser beam evaporation (PLD) method, or an ALD procedure can be trained. Alternatively, a coating method or a printing method can be used. Although the sputtering method and a plasma-enhanced chemical vapor deposition (PECVD) method are typical examples of the film formation method, a thermal CVD method can be used. As an example of a thermal CVD method, a metal organic chemical vapor deposition (metal organic chemical vapor deposition, MOCVD) method can be given.

[0227] The thermal CVD deposition can be performed by adjusting the pressure in a chamber to an atmospheric pressure or a reduced pressure and supplying a source gas and an oxidizer to the chamber at the same time and with each other near the substrate or above the substrate react. Therefore, no plasma is generated in the deposition; therefore, the thermal CVD method has an advantage that no defect due to plasma damage is generated.

[0228] The films, such as B. the conductive films, the insulating films, the oxide semiconductor films and the metal oxide films, which have been described above, can by a thermal CVD method such. B. a MOCVD process can be trained. For example, in the case where an In-Ga-Zn-O film is formed, trimethylindium (In (CH 3) 3), Trimethylgallium (Ga (CH 3) 3) And dimethyl zinc (Zn (CH 3) 2) Are used. Without being limited to the above combination, triethylgallium (Ga (C2H 5) 3) Can be used in place of trimethylgallium, and diethylzinc (Zn (C 2 H 5 ) 2) Can be used instead of dimethyl zinc.

[0229] In the case where a hafnium oxide film is formed with a depositor using an ALD method, two kinds of gases are used, namely, ozone (O 3) As an oxidizer and a source gas obtained by evaporating a liquid containing a solvent and a hafnium precursor (hafnium alkoxide or hafnium amide, such as tetrakis (dimethylamide) hafnium (TDMAH, Hf [N (CH 3) 2] 4) or Tetrakis (ethylmethylamide) hafnium).

[0230] In the case where an aluminum oxide film is formed with a deposition device using an ALD method, two kinds of gases are used, namely, H 2 O as an oxidizer and a source gas obtained by evaporating a liquid containing a solvent and an aluminum precursor (e.g. trimethylaluminum (TMA, Al (CH 3) 3)). Examples of another material include tris (dimethylamide) aluminum, triisobutyl aluminum, and aluminum tris (2,2,6,6-tetramethyl-3,5-heptanedionate).

[0231] In the case where a silicon oxide film is formed with a deposition means using an ALD method, hexachlorodisilane is adsorbed on a surface on which a film is formed, and radicals of an oxidizing gas (e.g., O 2 Or Nitrous oxide) are added to react with the adsorbate.

[0232] In the case where a tungsten film is formed with a deposition device using an ALD method, a WF 6 -Gas and a B 2 H 6 -Gas are introduced sequentially to form an initial tungsten film, and then become a WF 6 -Gas and an H 2 -Gas used to form a tungsten film. It should be noted that a SiH 4 -Gas instead of a B 2 H 6 -Gas can be used.

[0233] In the case where an oxide semiconductor film, such as. For example, an In-Ga-Zn-O film is formed with a deposition device using an ALD method, an In (CH 3) 3 -Gas and an O 3 -Gas used to form an In-O layer become a Ga (CH 3) 3 -Gas and an O 3 -Gas are used to form a Ga-O layer and then a Zn (CH 3) 2 -Gas and an O 3 Gas is used to form a Zn-O layer. It should be noted that the order of these layers is not limited to this example. A mixed compound layer such as B. an In-Ga-O layer, an In-Zn-O layer or a Ga-Zn-O layer can be formed by using these gases. It should be noted that although an H 2 O gas produced by nucleate boiling of water with an inert gas, such as. B. Ar, instead of an O 3 -Gas can be used, it is preferable to an O 3 - Use gas that does not contain H.

[0234] An embodiment of the present invention is not limited to the example described in this embodiment in which the transistor includes an oxide semiconductor film. In an embodiment of the present invention, the transistor does not necessarily include an oxide semiconductor film. For example, a channel region, the vicinity of the channel region, a source region or a drain region of the transistor using a material that contains silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs) or the like , be formed.

[0235] It should be noted that the structure and method described in this embodiment can be used in suitable combination with the structure and method described in any of the other embodiments. (Embodiment 2)

[0236] In this embodiment, a modification example of the transistor used in the embodiment 1 will be described. has been described and can be used in an embodiment of the present invention.

[0237] In the transistor 100C , which is in Fig. 4A and Fig. 4B, an area 108n_2, as in Fig. 45, between the first area 108i and the second area 108n provided by the conductive film 112 is made shorter in the channel length direction of the transistor than the insulating film 110 and a heat treatment is performed or an impurity element is added by a doping treatment or a plasma treatment. The conductivity of the area 108n_2 is higher than that of the first area 108i and lower than that of the second area 108n . The region 108n_2 can prevent the intensity of an electric field at an end portion of a drain of the transistor from being locally increased during operation of a semiconductor device or a display device.

[0238] It should be noted that the structure and method described in this embodiment can be used in suitable combination with the structure and method described in any of the other embodiments. (Embodiment 3)

[0239] In this embodiment, an oxide semiconductor that can be used in an embodiment of the present invention will be described. <Composition of an oxide semiconductor>

[0240] An oxide semiconductor preferably contains at least indium or zinc. In particular, indium and zinc are preferably contained. In addition, aluminum, gallium, yttrium, tin or the like is preferably contained. Further, one or more element (s) selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like can be included / become.

[0241] Here, the case is taken into account in which an oxide semiconductor is InMZnO, the indium, an element M and contains zinc. The element M is aluminum, gallium, yttrium, tin or the like. Alternatively, the element M Boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium or the like. It should be noted that two or more of the above items may be used in combination as item M in some cases. can be used. <structure>

[0242] An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor. Examples of a non-monocrystalline oxide semiconductor include a crystalline oxide semiconductor with alignment with respect to the c-axis (c-axis aligned crystalline oxide semiconductor, CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a- similar OS) and an amorphous oxide semiconductor.

[0243] The CAAC-OS has an orientation with respect to the c-axis, its nanocrystals are connected in the direction of the a-b plane, and the crystal structure has a distortion. It should be noted that a distortion denotes a section in which the direction of a lattice arrangement changes between an area with a uniform lattice arrangement and another area with a uniform lattice arrangement in an area in which the nanocrystals are connected.

[0244] The shape of the nanocrystal is basically a hexagon, but not always a regular hexagon, and in many cases it is an irregular hexagon. A pentagonal lattice arrangement, a heptagonal lattice arrangement and the like are included in the distortion in some cases. Note that even in the vicinity of the distortion, no clear crystal grain boundary can be observed in the CAAC-OS. That is, a lattice arrangement is distorted so that the formation of a crystal grain boundary is prevented. This is probably because the CAAC-OS can allow distortion due to a low density of arrangement of oxygen atoms in an a-b plane direction, change in an interatomic bond distance by replacing a metal element, and the like.

[0245] The CAAC-OS tends to have a layered crystal structure (also referred to as a multilayer structure) in which a layer containing indium and oxygen (hereinafter In layer) and a layer containing element M, zinc and oxygen (hereinafter (M, Zn) layer) are arranged one above the other. It should be noted that indium and the element M can be replaced by one another and, when the element M of the (M, Zn) layer is replaced by indium, the layer can also be referred to as the (In, M, Zn) layer . If the indium of the In layer is replaced by the element M, the layer can also be referred to as the (In, M) layer.

[0246] In the nc-OS, a microscopic area (for example, an area with a size greater than or equal to 1 nm and less than or equal to 10 nm, particularly an area with a size greater than or equal to 1 nm and smaller than or equal to 3 nm) a regular atomic arrangement. There is no regularity of crystal orientation between different nanocrystals in the nc-OS. Therefore, no orientation of the whole film is observed. Therefore, in some cases, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

[0247] The a-like OS has a structure intermediate that of the nc-OS and that of the amorphous oxide semiconductor. The a-like OS has a cavity or low density area. That is, the a-like OS has a low crystallinity compared to the nc-OS and the CAAC-OS.

[0248] An oxide semiconductor can have various structures showing various different properties. Two or more of the amorphous oxide semiconductor, the polycrystalline oxide semiconductor, the a-like OS, the nc-OS, and the CAAC-OS can be included in an oxide semiconductor of one embodiment of the present invention. <Atomic ratio>

[0249] Next, preferred ranges of the atomic ratio of indium to the element become M and zinc contained in an oxide semiconductor according to the present invention with reference to Fig. 8A to Fig. 8C. It should be noted that the proportion of oxygen atoms in Fig. 8A to Fig. 8C is not shown. The terms of the atomic ratio of indium to the element M and zinc contained in the oxide semiconductor are denoted by [In], [M] and [Zn], respectively.

[0250] In Fig. 8A to Fig. 8C, broken lines represent a line on which the atomic ratio [In]: [M]: [Zn] is (1 + α) :( 1-α): 1 (-1 ≤ α 1), a line which the atomic ratio [In]: [M]: [Zn] is (1 + α) :( 1-α): 2, a line on which the atomic ratio [In]: [M]: [Zn] is ( 1 + α) :( 1-α): 3, a line on which the atomic ratio [In]: [M]: [Zn] is (1 + α) :( 1-α): 4, and a line on which the atomic ratio [In]: [M]: [Zn] is (1 + α) :( 1-α): 5.

[0251] Dash-dot lines represent a line on which the atomic ratio [In]: [M]: [Zn] is 5: 1: β (β ≥ 0), a line on which the atomic ratio [In]: [M]: [Zn] is 2: 1: β, a line on which the atomic ratio [In]: [M]: [Zn] is 1: 1: β, a line on which the atomic ratio [In]: [M]: [ Zn] is 1: 2: β, a line on which the atomic ratio [In]: [M]: [Zn] is 1: 3: β, and a line on which the atomic ratio [In]: [ M]: [Zn] is 1: 4: β.

[0252] Furthermore, an oxide semiconductor with the atomic ratio of [In]: [M]: [Zn] = 0: 2: 1 or the vicinity thereof tends to be in Fig. 8A to Fig. 8C to have a spinel crystal structure.

[0253] A plurality of phases (e.g. two phases or three phases) exist in the oxide semiconductor in some cases. For example, when the atomic ratio [In]: [M]: [Zn] is close to 0: 2: 1, two phases of a spinel crystal structure and a slit crystal structure are likely to exist. In addition, when the atomic ratio [In]: [M]: [Zn] is close to 1: 0: 0, two phases of a bixbyite crystal structure and a split crystal structure are likely to exist. In the case where a plurality of phases exist in the oxide semiconductor, a grain boundary might be formed between different crystal structures.

[0254] An area A in Fig. 8A provides examples of the preferred ranges of the atomic ratio of indium to the element M and zinc contained in an oxide semiconductor.

[0255] In addition, the oxide semiconductor containing indium in a higher proportion can have high charge carrier mobility (electron mobility). Accordingly, an oxide semiconductor with a high indium content has a higher charge carrier mobility than an oxide semiconductor with a low indium content.

[0256] In contrast, as the indium content and the zinc content become lower in an oxide semiconductor, the carrier mobility becomes lower. Therefore, with an atomic ratio of [In]: [M]: [Zn] = 0: 1: 0 and the vicinity thereof (e.g., a region C in Fig. 8C), the insulating performance is improved.

[0257] Accordingly, an oxide semiconductor of one embodiment of the present invention preferably has an atomic ratio defined by the region A in Fig. 8A is shown. In the atomic ratio, a multilayer structure having high carrier mobility and few grain boundaries is easily obtained.

[0258] An oxide semiconductor with an atomic ratio in the region A, particularly in a region B in Fig. 8B, is excellent because the oxide semiconductor easily becomes a CAAC-OS and has high carrier mobility.

[0259] The CAAC-OS is an oxide semiconductor with high crystallinity. In contrast, in the CAAC-OS, a decrease in electron mobility due to the grain boundary is less likely to occur because a clear grain boundary cannot be observed. Ingress of impurities, formation of defects, or the like could lower the crystallinity of an oxide semiconductor. This means that the CAAC-OS has small amounts of impurities and defects (e.g. oxygen vacancies). Therefore, an oxide semiconductor containing a CAAC-OS is physically stable. Therefore, the oxide semiconductor containing CAAC-OS is heat-resistant and has high reliability.

[0260] It should be noted that the region B has an atomic ratio of [In]: [M]: [Zn] = 4: 2: 3 to 4: 2: 4.1 and the vicinity thereof. The neighborhood includes an atomic ratio of [In]: [M]: [Zn] = 5: 3: 4. It should be noted that the region B has an atomic ratio of [In]: [M]: [Zn] = 5: 1: 6 and the vicinity thereof and an atomic ratio of [In]: [M]: [Zn] = 5: 1: 7 and the neighborhood thereof.

[0261] It should be noted that the property of an oxide semiconductor is not uniquely determined by an atomic ratio. Even with the same atomic ratio, the property of an oxide semiconductor might differ depending on a formation condition. For example, in the case where the oxide semiconductor is deposited by a sputtering device, a film having an atomic ratio different from the atomic ratio of a target is formed. In particular, depending on the substrate temperature during deposition, [Zn] in the film could be smaller than [Zn] in the target. Therefore, the illustrated ranges each represent an atomic ratio at which an oxide semiconductor tends to have specific properties, and boundaries of the ranges Ab to C are not clear. [Transistor containing oxide semiconductor]

[0262] Next, the case where the above-described oxide semiconductor is used for a transistor will be described.

[0263] Note that when the oxide semiconductor is used for a transistor, carrier scattering or the like at a grain boundary can be reduced; therefore, the transistor can have high field effect mobility. In addition, the transistor can have high reliability.

[0264] An oxide semiconductor having a low carrier density is preferably used for a channel region of the transistor. In order to decrease the carrier density of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film is decreased, so that the density of the defect states can be decreased. In this specification and the like, a state having a low impurity concentration and a low density of the defect states is referred to as a highly pure intrinsic or a substantially highly pure intrinsic state. For example, an oxide semiconductor whose carrier density is lower than 8 × 10 11 / cm 3 , preferably lower than 1 × 10 11 / cm 3 , more preferably lower than 1 × 10 10 / cm 3 and higher than or equal to 1 × 10 -9 / cm 3 is used.

[0265] A high purity intrinsic or substantially high purity intrinsic oxide semiconductor film has a low density of defect states and thus a low density of trapped states in some cases.

[0266] A charge trapped by the trapping states in the oxide semiconductor takes a long time to be released, and it can behave like a fixed charge. Therefore, a transistor whose channel region is formed in an oxide semiconductor with a high density of trapping states has unstable electrical properties in some cases.

[0267] In order to maintain stable electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to decrease the impurity concentration in the oxide semiconductor, it is preferable to decrease the impurity concentration in a film adjacent to the oxide semiconductor. Examples of the impurities include hydrogen, nitrogen, an alkali metal, an alkaline earth metal, iron, nickel and silicon. <Impurities>

[0268] Here, the influence of impurities in the oxide semiconductor is described.

[0269] When silicon or carbon, which is one of the elements of group 14 which contains oxide semiconductors, defect states are formed. Therefore, the silicon or carbon concentration in the oxide semiconductor and around an interface with the oxide semiconductor (measured by secondary ion mass spectrometry (SIMS)) becomes less than or equal to 2 × 10 18 Atoms / cm 3 , and preferably less than or equal to 2 × 10 17 Atoms / cm 3 set.

[0270] When the oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states are formed and charge carriers are generated in some cases. Therefore, a transistor containing an alkali metal or alkaline earth metal-containing oxide semiconductor is likely to be normally on. Therefore, it is preferable to reduce the alkali metal or alkaline earth metal concentration in the oxide semiconductor. Specifically, the alkali metal or alkaline earth metal concentration in the oxide semiconductor measured by SIMS becomes less than or equal to 1 × 10 18 Atoms / cm 3 , and preferably less than or equal to 2 × 10 16 Atoms / cm 3 set.

[0271] When the oxide semiconductor contains nitrogen, the oxide semiconductor easily becomes n-type by generating electrons serving as carriers and increasing the carrier density. Therefore, a transistor whose semiconductor contains a nitrogen-containing oxide semiconductor is likely to be normally on. For this reason, nitrogen in the oxide semiconductor is preferably reduced as much as possible; the nitrogen concentration in the oxide semiconductor measured by SIMS can be, for example, lower than 5 × 10 19 Atoms / cm 3 , preferably less than or equal to 5 × 10 18 Atoms / cm 3 , more preferably less than or equal to 1 × 10 18 Atoms / cm 3 , and even more preferably less than or equal to 5 × 10 17 Atoms / cm 3 be.

[0272] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, and therefore it creates an oxygen vacancy in some cases. As a result of the penetration of hydrogen into the oxygen vacancy, an electron is generated in some cases, which serves as a charge carrier. Further, in some cases, bonding of a portion of hydrogen to oxygen bonded to a metal atom causes generation of an electron that serves as a charge carrier. Therefore, a transistor containing an oxide semiconductor containing hydrogen is likely to be normally on. Accordingly, hydrogen in the oxide semiconductor is preferably reduced as much as possible. In particular, the hydrogen concentration in the oxide semiconductor measured by SIMS becomes lower than 1 × 10 20 Atoms / cm 3 , preferably lower than 1 × 10 19 Atoms / cm 3 , more preferably lower than 5 x 10 18 Atoms / cm 3 , and even more preferably lower than 1 × 10 18 Atoms / cm 3 set.

[0273] If an oxide semiconductor having a sufficiently reduced impurity concentration is used for a channel formation region in a transistor, the transistor can have stable electrical properties. <Band diagram>

[0274] Next, the case where the oxide semiconductor has a two-layer structure or a three-layer structure will be described. A band diagram of a multilayer structure composed of an oxide semiconductor S1, an oxide semiconductor S2 and an oxide semiconductor S3 and of insulators that are in contact with the multilayer structure, a band diagram of a multilayer structure composed of the oxide semiconductors S2 and S3 and of insulators that are in contact with the multilayer structure, and a band diagram of a multilayer structure made up of the oxide semiconductors S1 and S2 and insulators in contact with the multilayer structure based on Fig. 9A to Fig. 9C.

[0275] Fig. 9A is an example of a band diagram of a multilayer structure in a thickness direction using an insulator I1 , the oxide semiconductor S1 , the oxide semiconductor S2 , the oxide semiconductor S3 and an insulator I2 includes. Fig. 9B is an example of a band diagram of a multilayer structure in a thickness direction including the insulator 11 , the oxide semiconductor S2 , the oxide semiconductor S3 and the isolator I2 includes. Fig. 9C is an example of a band diagram of a multilayer structure in a thickness direction including the insulator I1 , the oxide semiconductor S1 , the oxide semiconductor S2 and the isolator I2 includes. It should be noted that for easy understanding, the band diagrams each show the conduction band minimum (Ec) of the isolator I1 , the oxide semiconductor S1 , the oxide semiconductor S2 , the oxide semiconductor S3 and the isolator I2 demonstrate.

[0276] The conduction band minimum of each of the oxide semiconductors S1 and S3 is closer to the vacuum level than that of the oxide semiconductor S2 . Typically, a difference between the conduction band minimum of the oxide semiconductor is S2 and the conduction band minimum of each of the oxide semiconductors S1 and S3 preferably greater than or equal to 0.15 eV or greater than or equal to 0.5 eV and less than or equal to 2 eV or less than or equal to 1 eV. That is, the difference between the electron affinity of each of the oxide semiconductors is S1 and S3 and the electron affinity of the oxide semiconductor S2 is greater than or equal to 0.15 eV or greater than or equal to 0.5 eV and less than or equal to 2 eV or less than or equal to 1 eV.

[0277] As in Fig. 9A to Fig. 9C, the conduction band minimum of each of the oxide semiconductors S1 changes. to S3 gradually. In other words: the conduction band minimum changes continuously or is continuously connected. In order to obtain such a band diagram, the density of the defect states in a mixed layer formed at the interface between the oxide semiconductors is S1 and S2 or at the interface between the oxide semiconductors S2 and S3 preferably made low.

[0278] In particular, in the case where the oxide semiconductor S1 and S2 or the oxide semiconductors S2 and S3 containing an identical element (as a main component) in addition to oxygen, a mixed layer having a low density of defect states can be formed. For example, in the case where the oxide semiconductor S2 is an In-Ga-Zn oxide semiconductor, preferably an In-Ga-Zn oxide semiconductor, a Ga-Zn oxide semiconductor, gallium oxide or the like as each of the oxide semiconductors S1 and S3 used.

[0279] At this time, the oxide semiconductor S2 is used. as the main carrier route. Since the density of the defect states at the interface between the oxide semiconductors S1 and S2 and the interface between the oxide semiconductors S2 and S3 can be made low, the influence of the interfacial scattering on the carrier transfer is small, and a high forward current can be obtained.

[0280] When an electron is trapped in a trapped state, the trapped electron behaves like a fixed charge; therefore, the threshold voltage of the transistor is shifted in the positive direction. The oxide semiconductors S1 and S3 can change the trapping state of the oxide semiconductor S2 keep away. This structure can prevent the positive shift in the threshold voltage of the transistor.

[0281] A material whose conductivity is sufficiently lower than that of the oxide semiconductor S2 , for the oxide semiconductor S1 and S3 used. In this case, the oxide semiconductors S2 are used. , the interface between the oxide semiconductors S1 and S2 and the interface between the oxide semiconductors S2 and S3 mainly as a canal area. For example, an oxide semiconductor having a high insulating performance and the atomic ratio represented by the region C in Fig. 8C is shown as oxide semiconductor S1 and S3 be used. It should be noted that the in Fig. Area C shown in Fig. 8C represents the atomic ratio of [In]: [M]: [Zn] = 0: 1: 0, 1: 3: 2 and 1: 3: 4 and the neighborhood thereof.

[0282] Specifically, in the case where an oxide semiconductor having the atomic ratio represented by the area A becomes oxide semiconductor S2 is used, preferably as each of the oxide semiconductors S1 and S3 an oxide semiconductor having an atomic ratio in which [M] / [In] is greater than or equal to 1, preferably greater than or equal to 2, is used. In addition, it is advantageous that the oxide semiconductor S3 an oxide semiconductor having a sufficiently high insulating performance and an atomic ratio in which [M] / ([Zn] + [In]) is greater than or equal to 1 is used. <Structure in which the oxide semiconductor is used for a transistor>

[0283] Next, a structure in which the oxide semiconductor is used in a transistor will be described.

[0284] Note that when the oxide semiconductor is used for a transistor, carrier scattering or the like at a grain boundary can be reduced; therefore, the transistor can have high field effect mobility. In addition, the transistor can have high reliability.

[0285] An oxide semiconductor having a low carrier density is preferably used for a channel region of the transistor. For example, an oxide semiconductor whose carrier density is lower than 8 × 10 11 / cm 3 , preferably lower than 1 × 10 11 / cm 3 , more preferably lower than 1 × 10 10 / cm 3 and higher than or equal to 1 × 10 -9 / cm 3 is used.

[0286] A high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor has few charge carrier generation sources, and therefore it can have a low charge carrier density. A high purity intrinsic or substantially high purity intrinsic oxide semiconductor has, in some cases, a low density of the defect states and, accordingly, a low density of the trapped states.

[0287] A charge trapped by the trapping states in the oxide semiconductor takes a long time to be released, and it can behave like a fixed charge. Therefore, a transistor whose channel region is formed in an oxide semiconductor with a high density of trapping states has unstable electrical properties in some cases.

[0288] In order to maintain stable electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to decrease the impurity concentration in the oxide semiconductor, it is preferable to decrease the impurity concentration in a film adjacent to the oxide semiconductor. Examples of the impurities include hydrogen, nitrogen, an alkali metal, an alkaline earth metal, iron, nickel and silicon.

[0289] Here, the influence of impurities in the oxide semiconductor is described.

[0290] When silicon or carbon, which is one of the elements of group 14 in which oxide semiconductor is contained, defect states are formed. Therefore, the silicon or carbon concentration in the oxide semiconductor and around an interface with the oxide semiconductor (measured by secondary ion mass spectrometry (SIMS)) becomes less than or equal to 2 × 10 18 Atoms / cm 3 , and preferably less than or equal to 2 × 10 17 Atoms / cm 3 set.

[0291] When the oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states are formed and charge carriers are generated in some cases. Therefore, a transistor containing an alkali metal or alkaline earth metal-containing oxide semiconductor is likely to be normally on. Therefore, it is preferable to reduce the alkali metal or alkaline earth metal concentration in the oxide semiconductor. Specifically, the alkali metal or alkaline earth metal concentration in the oxide semiconductor measured by SIMS becomes less than or equal to 1 × 10 18 Atoms / cm 3 , and preferably less than or equal to 2 × 10 16 Atoms / cm 3 set.

[0292] When the oxide semiconductor contains nitrogen, the oxide semiconductor easily becomes n-type by generating electrons serving as carriers and increasing the carrier density. Therefore, a transistor whose semiconductor contains a nitrogen-containing oxide semiconductor is likely to be normally on. For this reason, nitrogen in the oxide semiconductor is preferably reduced as much as possible; the nitrogen concentration in the oxide semiconductor measured by SIMS may, for example, be lower than 5 × 10 19 Atoms / cm 3 , preferably less than or equal to 5 × 10 18 Atoms / cm 3 , more preferably less than or equal to 1 × 10 18 Atoms / cm 3 , and more preferably less than or equal to 5 × 10 17 Atoms / cm 3 be.

[0293] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, and therefore it creates an oxygen vacancy in some cases. As a result of the penetration of hydrogen into the oxygen vacancy, an electron is generated in some cases, which serves as a charge carrier. Further, in some cases, bonding of a portion of hydrogen to oxygen bonded to a metal atom causes generation of an electron that serves as a charge carrier. Therefore, a transistor containing an oxide semiconductor containing hydrogen is likely to be normally on. Accordingly, hydrogen in the oxide semiconductor is preferably reduced as much as possible. In particular, the hydrogen concentration in the oxide semiconductor measured by SIMS becomes lower than 1 × 10 20 Atoms / cm 3 , preferably lower than 1 × 10 19 Atoms / cm 3 , more preferably lower than 5 × 10 18 Atoms / cm 3 , and even more preferably lower than 1 × 10 18 Atoms / cm 3 set.

[0294] If an oxide semiconductor having a sufficiently reduced impurity concentration is used for a channel formation region in a transistor, the transistor can have stable electrical properties.

[0295] The energy gap of the oxide semiconductor film is preferably 2 eV or more, 2.5 eV or more, or 3 eV or more.

[0296] The thickness of the oxide semiconductor film is greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, more preferably greater than or equal to 3 nm and less than or equal to 60 nm.

[0297] When the oxide semiconductor film is an In-M-Zn oxide, an atomic ratio of metal elements in a sputtering target used for forming the In-M-Zn oxide becomes In: M: Zn = 1: 1: 0.5, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 1.5, In: M: Zn = 2: 1: 2,3, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4.1, In: M: Zn = 5: 1: 7 or the like is preferable.

[0298] It should be noted that the atomic ratios of the metal elements in the formed oxide semiconductor films each deviate from the above atomic ratio of the metal elements in the sputtering target in a range of approximately ± 40%. For example, if a sputtering target having an atomic ratio of In: Ga: Zn = 4: 2: 4.1 is used, the atomic ratio of In to Ga and Zn in the oxide semiconductor film can be approximately 4: 2: 3. In the case where a sputtering target whose atomic ratio of In to Ga and Zn is 5: 1: 7 is used, the atomic ratio of In to Ga and Zn in the formed oxide semiconductor film may be approximately 5: 1: 6. <Structure of an oxide semiconductor>

[0299] The following describes the composition of a cloud-aligned composite oxide semiconductor (CAC-OS) that can be used for a transistor disclosed in one embodiment of the present invention.

[0300] For example, the CAC-OS has a composition in which elements contained in an oxide semiconductor are unevenly distributed. Materials that contain non-uniformly distributed elements each have a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm or a similar size. Note that, in the following description of an oxide semiconductor, a state in which one or more metal element (s) is / are unevenly distributed and areas containing the metal element (s) are mixed is referred to as a mosaic pattern or a patch-like pattern. The area has a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm or a similar size.

[0301] It should be noted that an oxide semiconductor preferably contains at least indium. In particular, indium and zinc are preferably contained. Additionally, one or more of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium the like be included.

[0302] For example, with regard to the CAC-OS, an In-Ga-Zn oxide with the CAC composition (such an In-Ga-Zn oxide can in particular be referred to as CAC-IGZO) has a composition in which materials in indium oxide (InO X1, Where X1 is a real number greater than 0) or indium zinc oxide (In X2 Zn Y2 O Z2, Where X2, Y2 and Z2 are real numbers greater than 0) and in gallium oxide (GaO X3, Where X3 is a real number greater than 0) or gallium zinc oxide (Ga X4 Zn Y4 O Z4, Where X4, Y4 and Z4 are real numbers greater than 0) are divided and a mosaic pattern is formed. Then InO becomes X1 or In X2 Zn Y2 O Z2 that forms the mosaic pattern is evenly distributed throughout the film. This composition is also known as a cloud-like composition.

[0303] That is, the CAC-OS is a compound oxide semiconductor having a composition in which a region, the GaO X3 as the main component, and an area that In X2 Zn Y2 O Z2 or InO X1 contains as the main component, are mixed. Note that in this specification, for example, when the atomic ratio of In to an element is M in a first region is greater than the atomic ratio of In to the element M in a second area, the first area has a higher concentration of In than the second area.

[0304] Note that a compound containing In, Ga, Zn, and O is also known as IGZO. Typical examples of IGZO include a crystalline compound represented by InGaO 3 (ZnO) m1 (m1 is a natural number) and a crystalline compound represented by In (1+x0) Ga (1-x0) O 3 (ZnO) m0 is represented (-1 ≤ x0 ≤ 1; m0 is a given number).

[0305] The above crystalline compounds have a single crystalline structure, a polycrystalline structure or a CAAC structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals are aligned with respect to the c-axis and are connected to each other in the direction of the a-b plane without alignment.

[0306] On the other hand, the CAC-OS relates to the material composition of an oxide semiconductor. With a material composition of a CAC-OS including In, Ga, Zn, and O, regions with nanoparticles containing Ga as a main component are observed in a part of the CAC-OS, and regions with nanoparticles containing In as a main component become observed in part of it. These areas with nanoparticles are irregularly dispersed to form a mosaic pattern. Hence, the crystal structure is a secondary element for the CAC-OS.

[0307] It should be noted that the CAC-OS does not include a multilayer structure including two or more films having different atomic ratios. For example, a two-layer structure of a film containing In as a main component and a film containing Ga as a main component is not included.

[0308] A boundary between the area of ​​GaO X3 as the main component, and the area that In X2 Zn Y2 O Z2 or InO X1 as the main component is not clearly observed in some cases.

[0309] In the case where one or more of aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium like is / are contained in a CAC-OS instead of gallium, areas with nanoparticles containing the selected metal element (s) as the main component (s) are observed in a part of the CAC-OS, and areas with nanoparticles that contain Contained in as a main component are observed in a part thereof, and these nanoparticle regions are irregularly dispersed to form a mosaic pattern in the CAC-OS.

[0310] The CAC-OS can be formed, for example, by a sputtering method under conditions where a substrate is not intentionally heated. In the case where the CAC-OS is formed by a sputtering method, one or more gases selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas can be used as the deposition gas become. The percentage of the flow rate of the oxygen gas in the total flow rate of the deposition gas in the deposition is preferably as low as possible, and for example, the percentage of the flow rate of the oxygen gas is preferably higher than or equal to 0% and lower than 30%, more preferably higher than or equal to 0% and less than or equal to 10%.

[0311] The CAC-OS is characterized in that no clear peak is observed in a measurement using a θ / 2θ scan by an out-of-plane method, which is an X-ray diffraction (XRD) measurement method becomes. That is, the X-ray diffraction shows no alignment in a measurement area in the direction of the a-b plane and in the direction of the c-axis.

[0312] In an electron diffraction image of the CAC-OS obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanometer-sized electron beam), a ring-shaped area with high luminance and a plurality of luminous points are observed in the ring-shaped area. Thus, the electron diffraction pattern suggests that the crystal structure of the CAC-OS has a nanocrystalline (nanocrystal, nc-) structure with no orientation in a plan and cross-sectional direction.

[0313] For example, an energy dispersive X-ray spectroscopy (EDX) distribution pattern confirms that an In-Ga-Zn oxide having the CAC composition has a structure in which a region that is GaO X3 as the main component, and an area that In X2 Zn Y2 O Z2 or InO X1 contains, are unevenly distributed and mixed.

[0314] The CAC-OS has a structure different from that of an IGZO compound in which metal elements are evenly distributed, and it has properties different from those of the IGZO compound. That is, in the CAC-OS areas that GaO X3 or the like as a main component, and areas included in X2 Zn Y2 O Z2 or InO X1 contained as a main component, are separated to form a mosaic pattern.

[0315] The conductivity of an area that is In X2 Zn Y2 O Z2 or InO X1 as a main component is higher than that of a region containing GaO X3 or the like as a main component. In other words, when charge carriers flow through areas that are In X2 Zn Y2 O Z2 or InO X1 as the main component, conductivity of an oxide semiconductor is shown. Accordingly, when areas included in In X2 Zn Y2 O Z2 or InO X1 contained as the main component, distributed in an oxide semiconductor like a cloud, a high field effect mobility (µ) can be achieved.

[0316] In contrast, the insulating property of a region, the GaO X3 or the like as a main component, higher than that of a range included in In X2 Zn Y2 O Z2 or InO X1 contains as the main component. In other words, when areas that include GaO X3 or the like as a main component are dispersed in an oxide semiconductor, leakage current can be suppressed and an advantageous switching function can be obtained.

[0317] Thus, when a CAC-OS is used for a semiconductor element, the insulating property made of GaO X3 compliments. or the like, and the conductivity obtained from In X2 Zn Y2 O Z2 or InO X1 originates with each other, whereby a high forward current (I on) and a high field effect mobility (µ) can be obtained.

[0318] A semiconductor element including a CAC-OS has high reliability. Therefore, the CAC-OS is advantageously used in various semiconductor devices, typically a display.

[0319] At least a part of this embodiment can optionally be implemented in combination with any of the other embodiments described in this specification. (Embodiment 4)

[0320] An oxide conductor is suitably used for the conductive film 112 used in the transistor 100 of an embodiment of the present invention because the insulating film 110 Excess oxygen can be added and then the oxygen in the first area 108i of the oxide semiconductor film 108 can diffuse. In this case, it is possible to find defects in the insulating film 110 containing a silicon oxynitride film. In this embodiment, defects in the insulating film become 110 , wherein an oxide conductor for the conductive film 112 is used.

[0321] Defects in the silicon oxynitride film affect leakage current generated when an electric field is applied between films above and below the silicon oxynitride film. Therefore, if a metal-oxide-silicon (MOS) sample with a metal film over a silicon oxynitride film and a MOS sample with an oxide conductor over a silicon oxynitride film are fabricated and leakage current is measured in the silicon oxynitride films in the MOS samples, data via defects in the silicon oxynitride films.

[0322] For the evaluation of defects in the insulating film 110 , wherein an oxide conductor for the conductive film 112 is used, two samples, namely a first MOS sample 317 and a second MOS sample 318 , manufactured. For the first MOS sample, 317 a 10 nm thick silicon oxynitride film is formed over a silicon substrate to which impurities that impart p-type conductivity are added, and a metal film is formed over the silicon oxynitride film.

[0323] For the second MOS sample, 318 a 10 nm thick silicon oxynitride film is formed over a silicon substrate to which impurities that impart p-type conductivity are added, a conductive oxide film is formed over the silicon oxynitride film, and a metal film is formed over the conductive oxide film.

[0324] Each of the metal films is formed using 30 nm thick titanium nitride, 135 nm thick tungsten over it, and 200 nm thick aluminum over it. The conductive oxide film is formed by a sputtering method using a target made of an In-Ga-Zn oxide (In: Ga: Zn = 4: 2: 4.1 [atomic ratio]) in an atmosphere containing an oxygen gas (100%) contains.

[0325] In an area with a high electric field, Fowler-Nordheim (F-N) current is dominant in current flowing in the silicon oxynitride film. The F-N current is given by J FN shown in Formula 1. [Formula 1] J F. N = ( q 2 E. 2 m 8th π H Φ b m * ) ∗ exp { - [ 4th 2 m * ( q Φ b ) 3 / 2 3 G H E. ] }

[0326] By plotting In (JlE 2) And 1 / E obtained from Formula 1, a straight line can be obtained. In the case where there is a deep defect state, the F-N plot deviates partially from the straight line. An area deviating from the straight line called a ledge area is caused by an operation of capturing an electron of the F-N current into a deep defect state. In particular, a trapped electron forms a fixed charge and causes the I-V curve to shift in parallel, so that a ledge area is formed. The trapped charge density can be estimated from the amount of parallel displacement.

[0327] Fig. 10A is an energy band diagram of a metal region 310 , an oxide region 311 and a silicon region 312 with a MOS structure.

[0328] A film that corresponds to the oxide region 311 corresponds in each case to the first MOS sample 317 and the second MOS sample 318 the silicon oxynitride film. A film that matches the metal area 310 is 317 in the case of the first MOS sample. the metal film, and in the case of the second MOS sample, 318 the conductive oxide film and the overlying metal film.

[0329] When a voltage is applied between the films above and below the silicon oxynitride film, it occurs as in Fig. 10A shown an injection 315 of an electron in the metal region 310 into a trap 314 in the oxide region 311 on.

[0330] A trapped charge density (Q t (T)) and a centroid position 316 of a trapped charge (x) can be derived from Formula 2 for the case where a positive charge is captured by the trapped state, Formula 3 for the case where a negative charge is captured by the trapped state, and the amount of change in IV curve (ΔV g) Can be estimated before and after a charge injection. In the formula 2, t denotes ox the thickness of the oxide region 311 . [Formula 2] Δ V G ( + ) = Q t ( t ) ε 0 ε O X ( t OX - x ¯ ) [Formula 3] Δ V G ( - ) = Q t ( t ) ε O ε O X x ¯

[0331] Here the center of gravity position becomes 316 of the trapped charge in the oxide region 311 by the distance up to the interface to the silicon area 312 shown. It should be noted that the surface density of the total trapped charge in the oxide region 311 can be calculated from the charge injection time dependence of the trapped charge density.

[0332] Fig. 10B shows the surface density of the total trapped charge in the oxide region obtained in the above-described manner and Fig. 10C shows the center of gravity position of the trapped cargo. The results suggest that the second MOS sample 318 has a lower surface density of the total trapped charge in the silicon oxynitride film than the first MOS sample 317 . In addition, the focus position is 316 the trapped charge of the second MOS sample 318 farther from an electrode than that of the first MOS sample 317 .

[0333] In the F-N plot (see Fig. 11A) a ledge area becomes 321 , which in the measurement result of the first MOS sample 317 is considered in the measurement result of the second MOS sample 318 not considered. The vertical axis in Fig. 11A represents In (JlE 2) [A / MV 2 ], which corresponds to the leakage current per unit area. Fig. 10A to Fig. 10C and Fig. 11A and Fig. 11B suggest that the trapped charge density (the density of electrons trapped by deep defect states) in the silicon oxynitride film in the second MOS sample 318 is reduced because the conductive oxide film is formed over the silicon oxynitride film.

[0334] Fig. 11B illustrates structures of the first MOS sample 317 and the second MOS sample 318 schematically. Each of the samples contains silicon 319 , a silicon oxynitride film 326 and a metal film 325 . The second MOS sample 318 further includes a conductive oxide film 313 . For the first MOS sample 317 where the metal film 325 over the silicon oxynitride film 326 is formed, a gravity center position is 328 a captured charge 327 in the silicon oxynitride film 326 almost in the middle of the silicon oxynitride film 326 positioned, suggesting that defects are uniform in the silicon oxynitride film 326 could exist (see Fig. 11B). In contrast, in the case of using the oxide conductive film, 313 a center of gravity position 329 of the captured cargo 327 closer to the interface between the silicon 319 and the silicon oxynitride film 326 positioned and the trapped charge density is low. The above results suggest that the defect density in the silicon oxynitride film 326 in an area closer to the conductive oxide film 313 thanks to the formation of the conductive oxide film 313 is decreased.

[0335] As described above, the use of an oxide conductor for the conductive film 112 in the transistor 100 one embodiment of the present invention, the defect density in the insulating film 110 reduce. (Embodiment 5)

[0336] In this embodiment, the characteristics of the transistor 100 , wherein a silicon oxynitride film for the insulating film 110 is formed at a substrate temperature of 350 ° C.

[0337] The insulating film 110 serving as the gate insulating film of transistor 100 Serves an embodiment of the present invention, ideally, for example, has few defects, causes only minor damage to the oxide semiconductor film 108 and leads the oxide semiconductor film 108 excess oxygen too.

[0338] In the embodiment 1 For example, a silicon oxynitride film formed by a plasma-assisted chemical vapor deposition method is used for the insulating film 110 used as the gate insulating film of transistor 100 an embodiment of the present invention serves. As with the embodiment 1 described, excess oxygen is added to voids in a silicon oxynitride film formed at low temperatures, and a large amount of excess oxygen can be absorbed or supplied to the oxide semiconductor film.

[0339] A silicon oxynitride film formed at high temperatures can have a high film density; H. have few defects. Therefore, in order to increase the reliability, it is effective that the insulating film 110 a multilayer structure of a silicon oxynitride film formed at a substrate temperature of 350 ° C. and a silicon oxynitride film formed at a substrate temperature of 220 ° C. over the first region 108i of the oxide semiconductor film 108 having.

[0340] Taking into account the productivity of the insulating film 110 with a multilayer structure, the superposed films are ideally formed at the same temperature.

[0341] Fig. 12A shows the comparison result of wet etching rates of silicon oxynitride films. Both for a sample 351 as well as for a sample 352 a silicon oxynitride film was formed over glass. A substrate temperature during the formation was 351 in the case of the sample. 220 ° C, and a substrate temperature during formation was 352 in the case of the sample. 350 ° C.

[0342] Both for sample 351 as well as the sample 352 The silicon oxynitride film was formed by a plasma CVD method using a gas containing 20 sccm SiH 4 and 3000 sccm N 2 O contains. The deposition pressure was 200 Pa and the deposition power was 100 W. In the wet etching, HF (0.5%) was used as a solution, and the temperature was adjusted to room temperature.

[0343] As in Fig. As shown in Figure 12A, the sample has 352 a lower etching rate. This suggests that a silicon oxynitride film formed at a substrate temperature of 350 ° C may be denser than that formed at a substrate temperature of 220 ° C.

[0344] Fig. 12B shows the comparison result of silicon oxynitride films measured by FT-IR. Both for a sample 353 as well as for a sample 354 a silicon oxynitride film was formed over a silicon wafer. A substrate temperature during formation in the case of the sample 353 was 220 ° C, and a substrate temperature during formation in the case of the sample 354 was 350 ° C. A dotted line 357 at a wave number of 1050 cm -1 that is parallel to the vertical axis in Fig. Fig. 12B represents the wavenumber resulting from a Si-O bond.

[0345] Both for sample 353 as well as the sample 354 the silicon oxynitride film was obtained by a plasma CVD method using a gas containing 20 sccm SiH 4 and 3000 sccm N 2 O contains, trained. The deposition pressure was 200 Pa and the deposition power was 100 W.

[0346] As in Fig. As shown in Figure 12B, the sample has 354 the density of Si-O bonds, which is slightly higher than that of the sample 353 . This also suggests that a silicon oxynitride film formed at a substrate temperature of 350 ° C may be denser than that formed at a substrate temperature of 220 ° C.

[0347] Fig. 12C shows the comparison result of nitrogen oxide (NO x -) concentration in silicon oxynitride films measured by an ESR method. The vertical axis represents spin density. Both for a sample 355 as well as for a sample 356 a 10 nm thick oxide semiconductor film was formed over a glass, a 20 nm thick silicon oxynitride film was formed, and a 100 nm thick conductive oxide film was formed over it. It should be noted that the conductive oxide film was removed before the ESR measurement.

[0348] The silicon oxynitride film became in sample 355 at a substrate temperature of 220 ° C and for the sample 356 formed at a substrate temperature of 350 ° C. Both for sample 355 as well as the sample 356 the oxide semiconductor film was formed by a sputtering method using a target made of an In-Ga-Zn oxide (In: Ga: Zn = 4: 2: 4.1 [atomic ratio]) in an atmosphere containing an argon gas (90%) and a Containing oxygen gas (10%) was formed at a substrate temperature of 130 ° C. The silicon oxynitride films were each formed by a plasma CVD method using a gas containing 20 sccm SiH 4 and 3000 sccm N 2 O contains. The deposition pressure was 200 Pa and the deposition power was 100 W. The conductive oxide films were each formed by a sputtering method using a target made of an In-Ga-Zn oxide (In: Ga: Zn = 4: 2: 4.1 [atomic ratio]) )educated.

[0349] Fig. 12C shows the spin density [spins / cm 3 ] derived from nitrogen oxide (NO x) after the formation of the silicon oxynitride film and after the removal of the conductive oxide film. As in Fig. As shown in FIG. 12C, a silicon oxynitride film can be formed to have a lower nitrogen oxide (NO x -) concentration when formed at a substrate temperature of 350 ° C than when formed at a substrate temperature of 220 ° C.

[0350] The above results suggest that it is preferable that a silicon oxynitride film, which is formed at a substrate temperature of 350 ° C and has a high density, few defects and a low nitrogen oxide (NO x -) concentration, for the insulating film 110 is used. However, if a silicon oxynitride film formed at a substrate temperature of 350 ° C., for the insulating film, 110 is used, the resistance of the oxide semiconductor film 108 can be decreased, as in Fig. 43A shown.

[0351] To reduce the resistance of the oxide semiconductor film 108 To prevent this, the following procedures can be used. One method is oxygen plasma treatment 361 made using a plasma CVD apparatus after forming the insulating film 110 is carried out (see Fig. 13A). Another method is heat treatment performed after the insulating film 116 is carried out (see Fig. 13B). The above treatments can include the supply of excess oxygen 362 to the oxide semiconductor film 108 facilitate. In particular, the two treatments are preferably used.

[0352] The oxygen plasma treatment 361 using a plasma CVD apparatus after forming the insulating film 110 can be carried out by a method described in Example 1, for example. The heat treatment after the formation of the insulating film 116 can for example be carried out for one hour in a nitrogen atmosphere at 350 ° C.

[0353] Fig. 14A and Fig. 14B shows the results of experiments conducted to prove that the heat treatment performed after the insulating film 116 is effective for adding oxygen to the oxide semiconductor film. For each sample used in the experiments, a 100 nm thick oxide semiconductor film was formed over a glass substrate, a 100 nm thick silicon oxynitride film was formed thereover, a 100 nm thick conductive oxide film was formed thereover, and a 100 nm thick silicon nitride film was formed thereover .

[0354] The oxide semiconductor films were each formed by a sputtering method using a target made of an In-Ga-Zn oxide (In: Ga: Zn = 4: 2: 4.1 [atomic ratio]) in an atmosphere containing an argon gas (90%) and containing an oxygen gas (10%) was formed at a substrate temperature of 130 ° C.

[0355] The silicon oxynitride films were each formed to have a multilayer structure of two layers formed under different conditions by a plasma CVD method at a substrate temperature of 220 ° C. The first conditions were as follows: A gas containing 50 sccm SiH 4 was used. and 2000 sccm N 2 O, the deposition pressure was 20 Pa, and the deposition power was 100 W. A silicon oxynitride film formed under the first conditions had a thickness of 30 nm. This film contains a small amount of NO x . The second conditions were as follows: A gas containing 160 sccm SiH 4 was used. and 160 sccm N 2 O, the deposition pressure was 200 Pa, and the deposition power was 1500 W. A silicon oxynitride film formed under the second condition had a thickness of 70 nm.

[0356] The silicon oxynitride films were each formed to have a multilayer structure of two layers formed under different conditions using a target made of an In-Ga-Zn oxide (In: Ga: Zn = 4: 2: 4.1 [atomic ratio ]) were trained. The first conditions were as follows: a sputtering method was used, an atmosphere that was 18 was used. O gas (100%), and the substrate temperature was set to 170 ° C. A conductive oxide film formed under the first conditions had a thickness of 10 nm. The second conditions were as follows: a sputtering method was used, an atmosphere containing an argon gas (90%) and a 18 was used. O gas (10%), and the substrate temperature was set to 170 ° C. A conductive oxide film formed under the second condition had a thickness of 90 nm.

[0357] The silicon nitride film was formed under the following conditions: the substrate temperature was set to 220 ° C; a silane gas with a flow rate of 50 sccm, a nitrogen gas with a flow rate of 5000 sccm, and an ammonia gas with a flow rate of 100 sccm were introduced into a chamber; the pressure was 200 Pa; and an RF power of 1000 W was supplied between parallel plate electrodes provided in a plasma CVD device.

[0358] A sample 365 was completed without heat treatment, a sample 366 was completed by performing heat treatment at 250 ° C in a nitrogen atmosphere, and a sample 367 was completed by performing heat treatment at 350 ° C in a nitrogen atmosphere.

[0359] Fig. 14A and Fig. 14B show the results of 18 O concentration distribution in the sample 365 , the sample 366 and the sample 367 that were analyzed using SIMS. For each of the samples 365 , 366 and 367 became 18 ○ used only when the conductive oxide film was formed; therefore, if the 18 O concentration in other films is high at which 18 O probably around the 18 O diffused from the oxide conductive film. The SIMS analysis was carried out while digging from the substrate to the film surface side to obtain profiles.

[0360] In each of the Fig. 14A and Fig. 14B, the horizontal axis represents the depth from a sample surface and the vertical axis represents SIMS signals obtained by detecting 18 O in a conductive oxide film 368 , a silicon oxynitride film 369 and an oxide semiconductor film 370 were obtained. Fig. 14A shows the quantified measurement results of 18 O concentration in the silicon oxynitride film 369 . Fig. 14B shows the quantified measurement results of 18 O concentration in the oxide semiconductor film 370 .

[0361] As from the results in Fig. 14A and Fig. 14B, when heat treatment is performed after the formation of the silicon nitride film, the amount of oxygen that diffuses from the silicon oxynitride film into the oxide semiconductor film can be increased.

[0362] Fig. 14C shows the results of experiments conducted to find out in what step the heat treatment for effectively adding oxygen to the oxide semiconductor film should be performed.

[0363] In a sample used in the experiments, a 40 nm thick oxide semiconductor film was formed over a quartz substrate, a 150 nm thick silicon oxynitride film was formed thereover, a 100 nm thick conductive oxide film was formed thereover, and a 100 nm thick silicon nitride film was formed thereover . In Fig. 14C, the horizontal axis represents the formation steps and the vertical axis represents the resistance of the oxide semiconductor film. The formation steps will be described below.

[0364] First, the oxide semiconductor film was formed over the substrate (step A). The conditions for forming the oxide semiconductor film were the same as the conditions for forming the oxide semiconductor films in samples 365 to 367 . The resistance of the oxide semiconductor film was measured after step A.

[0365] Next, the silicon oxynitride film was formed over the oxide semiconductor film (step B). The silicon oxynitride film was formed by a plasma CVD method at a substrate temperature of 350 ° C. using a gas containing 20 sccm SiH 4 and 3000 sccm N 2 O contains, trained. The deposition pressure was 200 Pa and the deposition power was 100 W. The resistance of the oxide semiconductor film after the B step was measured.

[0366] Then, heat treatment was carried out at 350 ° C. in a nitrogen atmosphere (step C). The resistance of the oxide semiconductor film was measured after step C.

[0367] An oxygen plasma treatment was then carried out at a substrate temperature of 350 ° C. (step D). The oxygen plasma treatment was carried out for 250 seconds under the following conditions: Oxygen was introduced into a chamber at a flow rate of 3000 sccm, the pressure was adjusted to 40 Pa, and an RF current of 3000 W was applied between parallel plate electrodes in a plasma CVD facility provided. The resistance of the oxide semiconductor film after step D was measured.

[0368] Next, the conductive oxide film was formed (step E). The conditions for forming the conductive oxide film were the same as the conditions for forming the conductive oxide films in samples 365 to 367 . The resistance of the oxide semiconductor film after the step E was measured.

[0369] Then the silicon nitride film was formed (step F). The silicon nitride film formation conditions were the same as the silicon nitride film formation conditions in samples 365 to 367 . The resistance of the oxide semiconductor film was measured after Step F.

[0370] Then, heat treatment was carried out at 250 ° C. in a nitrogen atmosphere (step G1). The resistance of the oxide semiconductor film was measured after step G1. Furthermore, a heat treatment was carried out on another sample at 350 ° C. instead of at 250 ° C. in a nitrogen atmosphere (step G2). The resistance of the oxide semiconductor film was measured after step G2.

[0371] As from the resistances of the oxide semiconductor film, which were measured after the respective steps A to G1 or G2 and in Fig. 14C, the resistance of the oxide semiconductor film decreases in the step of forming silicon oxynitride and increases greatly when heat treatment is performed at 350 ° C. after the formation of the silicon nitride film. It should be noted that the resistances of the oxide semiconductor film after Step A and Step G2 are higher than 4.0 × 10 7 Ω, the upper measurement limit of a resistance meter.

[0372] The results suggest that the supply of excess oxygen is facilitated when heat treatment is carried out at 350 ° C. after the silicon nitride film is formed. The 18 O concentration, which was analyzed by SIMS and in Fig. 14A and Fig. 14B also suggests this facilitation of the supply of excess oxygen.

[0373] When oxygen plasma treatment was performed after the formation of the silicon oxynitride film and heat treatment was performed at 350 ° C. after the formation of the silicon nitride film, the reliability of the transistor was 100 , in which a silicon oxynitride film formed at 350 ° C for the insulating film 110 was used, equivalent to the reliability of transistor 100 , in which a silicon oxynitride film was formed at a substrate temperature of 350 ° C and then a silicon oxynitride film was formed at a substrate temperature of 220 ° C to provide the insulating film 110 to train. It should be noted that here the reliability was measured by the bias-temperature stress tests described in Example 1 below.

[0374] In other words, a silicon oxynitride film which is formed at a substrate temperature of 350 ° C. and has a high density and a low defect density can be used for the insulating film 110 can be used as long as a treatment for supplying sufficient excess oxygen to the oxide semiconductor film 108 is carried out. In this case, productivity can be improved.

[0375] The structures described in this embodiment can be appropriately combined with any of the structures described in the other embodiments. (Embodiment 6)

[0376] In this embodiment, examples of a display device including the transistor described in the above embodiments will be explained below with reference to Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19 and Fig. 20 described.

[0377] Fig. Fig. 15 is a plan view of an example of a display device. A display device 700 in Fig. 15 includes a pixel portion 702 over a first substrate 701 is arranged, a source driver circuit section 704 and a gate drive circuit section 706 that is above the first substrate 701 are arranged, a sealant 712 which is arranged to be the pixel portion 702 , the source driver circuit section 704 and the gate drive circuit section 706 surrounds, and a second substrate 705 , which is arranged to be the first substrate 701 is facing. The first substrate 701 and the second substrate 705 are with the sealant 712 sealed. That is, the pixel portion 702 , the source driver circuit section 704 and the gate drive circuit section 706 are from the first substrate 701 , the sealant 712 and the second substrate 705 enclosed. Although in Fig. 15, not shown, is a display element between the first substrate 701 and the second substrate 705 provided.

[0378] In the case of the display device 700 is a flexible printed circuit (FPC) terminal section (FPC terminal section) 708 that is electrically connected to the pixel section 702 , the source driver circuit section 704 and the gate drive circuit section 706 is provided in a region different from the region overlying the first substrate 701 and from the sealant 712 is enclosed. There is also an FPC 716 with the FPC connection section 708 connected, and various signals and the like are added to the pixel portion 702 , the source driver circuit section 704 and the gate drive circuit section 706 from the FPC 716 fed. Furthermore, a signal line is 710 with the pixel portion 702 , the source driver circuit section 704 , the gate drive circuit section 706 and the FPC connector section 708 connected. Via the signal line 710 various signals and the like are assigned to the pixel portion 702 , the source driver circuit section 704 , the gate driver circuit section 706 and the FPC connector section 708 from the FPC 716 fed.

[0379] A plurality of gate driver circuit sections 706 can in the display device 700 be provided. The structure of the display device 700 is not limited to the example shown here in which the source driver circuit section 704 and the gate drive circuit section 706 as well as the pixel portion 702 over the first substrate 701 are trained. For example, only the gate driver circuit section 706 over the first substrate 701 can be formed, or only the source driver circuit section 704 over the first substrate 701 be formed. In this case, a substrate over which a source driver circuit, a gate driver circuit, or the like is formed (e.g., a driver circuit board formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be formed on the first substrate 701 be formed. Note that there is no particular limitation on the method of connecting the separately provided driver circuit board, and a chip-on-glass (COG) method, a wire bonding method, or the like can be used .

[0380] The pixel portion 702 , the source driver circuit section 704 and the gate drive circuit section 706 that are shown in the display device 700 contain a variety of transistors.

[0381] The display device 700 can contain different elements. As examples of the elements, an electroluminescent (EL) element (e.g., an EL element containing organic and inorganic materials, an organic EL element, an inorganic EL element, or an LED), a light-emitting one Transistor element (a transistor that emits light depending on current), an electron emitter, a liquid crystal element, an electronic ink display, an electrophoretic element, an electrowetting element, a plasma display panel (PDP), a microelectromechanical system (micro electro mechanical systems, MEMS) display (e.g. a grating light valve (GLV) or light grid valve, a digital micromirror device (DMD, digital micromirror device), a digital micro shutter or digital micro shutter (DMS) element or an element for a screen with interferometic modulator (interferometic modulator display, IMOD) and a piezoelectric ceramic display can be specified.

[0382] An example of a display device including an EL element is an EL display. Examples of a display device including an electron emitter include a field emission display (FED) and a surface-conduction electron-emitter display (SED). An example of a display device including a liquid crystal element is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, or a projection liquid crystal display). An example of a display device that includes an electronic ink display or electrophoretic element is electronic paper. In a transflective liquid crystal display or a reflective liquid crystal display, some or all of the pixel electrodes can serve as reflective electrodes. For example, some or all of the pixel electrodes may contain aluminum, silver, or the like. In this case, a memory circuit such as B. an SRAM can be arranged under the reflective electrodes, which leads to lower power consumption.

[0383] As the display system of the display device 700 For example, a progressive system, an interlace system, or the like can be used. Further, color elements controlled in color display in pixels are not limited to three colors: R, G and B (R, G and B correspond to red, green and blue, respectively). For example, four pixels can be used, namely an R pixel, a G pixel, a B pixel and a W (white) pixel. Alternatively, a color element can consist of two colors of R, G and B as in the PenTile arrangement. The two colors may differ depending on the color elements. Alternatively, one or more colors of yellow, cyan, magenta and the like can be added to R, G and B. It should be noted that the size of a display area may differ between dots of the color elements. An embodiment of the disclosed invention is not limited to a color display device; the disclosed invention can also be applied to a monochrome display device.

[0384] A layer of color (also called a color filter) can be used to obtain a full color display device using white light (W) for backlighting (e.g. an organic EL element, an inorganic EL element, an LED or a fluorescent lamp )is used. For example, a red (R) color layer, green (G) color layer, blue (B) color layer and yellow (Y) color layer can be combined appropriately. By using the color layer, high color reproducibility can be obtained as compared with the case with no color layer. By providing an area with a color layer and an area without a color layer, white light in the area without a color layer can be used directly for display. By partially providing the area without a color layer, a decrease in luminance of a bright image due to the color layer can be suppressed, and power consumption can be reduced by 20% to 30% in some cases. In the case where a full color display is made using a self-luminous element such as An organic EL element or an inorganic EL element, elements can emit light in their respective colors, R, G, B, Y and W. By using a self-luminous element, the power consumption can be further reduced as compared with the case with the paint layer.

[0385] As the coloring method, one of the following systems can be used: the above-described color filter system in which a part of white light is converted into red light, green light and blue light by color filters; a three-color system using red light, green light and blue light; and a color conversion system or quantum dot system in which a part of blue light is converted into red light or green light.

[0386] In this embodiment, a structure including a liquid crystal element as a display element and a structure including an EL element as a display element will be explained with reference to Fig. 16, Fig. 17 and Fig. 18 described. Fig. 16 and Fig. 17 are each a cross-sectional view taken along a chain line Q-R in Fig. 15 and 15 illustrate the structure including a liquid crystal element as a display element. Fig. 18 is a cross-sectional view taken along chain line Q-R in Fig. Fig. 15 shows the structure including an EL element as a display element.

[0387] Sections corresponding to the Fig. 16, the Fig. 17 and the Fig. 18 are common will be described first, and then different sections will be described. <Sections Common to Display Devices>

[0388] The display device 700 in Fig. 16, Fig. 17 and Fig. 24 includes a connecting line section 711 , the pixel portion 702 , the source driver circuit section 704 , the FPC connection section 708 and the sealant 712 . The connecting line section 711 contains the signal line 710 . The pixel portion 702 includes a transistor 750 and a capacitor 790 . The source driver circuit section 704 includes a transistor 752 .

[0389] The transistor 750 and the transistor 752 each have a structure similar to that of the one in Fig. 3A and Fig. 3B illustrated transistor 100B is similar. It should be noted that transistor 750 and the transistor 752 each may include the structure of any of the other transistors described in the above embodiments.

[0390] The transistor used in this embodiment includes an oxide semiconductor film which is highly pure and in which formation of oxygen vacancies is suppressed. The transistor can have a small reverse current. Accordingly, an electrical signal, such as. An image signal can be held for a long time, and a long writing interval can be set in a pass state. Accordingly, the frequency of updating can be reduced, which suppresses power consumption.

[0391] In addition, the transistor used in this embodiment can have a relatively high field effect mobility and is therefore suitable for high speed operation. For example, in a liquid crystal display device including such a transistor which can operate at a high speed, a switching transistor in a pixel portion and a driving transistor in a driving circuit portion can be formed over a substrate. That is, no additional semiconductor device formed using a silicon wafer or the like is required as a drive circuit; consequently, the number of components of the semiconductor device can be reduced. In addition, by using the transistor which can operate at high speed in the pixel portion, a high quality image can be provided.

[0392] The capacitor 790 includes a lower electrode and an upper electrode. The lower electrode is formed by a step of processing a conductive film which becomes a conductive film to be the first gate electrode of the transistor 750 serves. The upper electrode is formed by a step of processing a conductive film which becomes a conductive film to serve as the source and drain electrode or second gate electrode of the transistor 750 serves. Between the lower electrode and the upper electrode is an insulating film which is formed by a step of forming an insulating film that becomes an insulating film, which is the first gate insulating film of the transistor 750 and insulating films formed by a step of forming insulating films to become insulating films to be used as an insulating protective film over the transistor 750 serve, be trained, provided. That is, the capacitor 790 has a multilayer structure in which an insulating film serving as a dielectric film is sandwiched between the pair of electrodes.

[0393] In Fig. 16, Fig. 17 and Fig. 18 is a planarization insulating film 770 above the transistor 750 , the transistor 752 and the capacitor 790 educated.

[0394] Although Fig. 16, Fig. 17 and Fig. 18 each illustrate an example in which the transistor 750 located in the pixel section 702 is included, and the transistor 752 included in the source driver circuit section 704 have the same structure, an embodiment of the present invention is not limited thereto. For example, the pixel portion can be 702 and the source driver circuit section 704 contain different transistors. In particular, a structure in which a top gate transistor in the pixel portion 702 is used and a bottom gate transistor in the source driver circuit section 704 is used, or a structure in which a bottom gate transistor is used in the pixel portion 702 is used and a top gate transistor in the source driver circuit section 704 is used. It should be noted that the term “source driver circuit section 704” can be replaced by the term “gate driver circuit section”.

[0395] The signal line 710 is formed by the same process as the conductive films that serve as the source electrodes and drain electrodes of the transistors 750 and 752 serve. In the case where the signal line 710 is formed using a material containing copper, for example, a signal delay or the like due to line resistance is reduced, which enables display on a large screen.

[0396] The FPC connector section 708 includes a connection electrode 760 , an anisotropic conductive film 780 and the FPC 716 . It should be noted that the connection electrode 760 is formed by the same process as the conductive films serving as source electrodes and drain electrodes of the transistors 750 and 752 serve. The connection electrode 760 is about the anisotropic conductive film 780 electrically connected to a connector which is in the FPC 716 is included.

[0397] For example, glass substrates can be used as the first substrate 701 and second substrate 705 be used. As the first substrate 701 and second substrate 705 flexible substrates can also be used. An example of the flexible substrate is a plastic substrate.

[0398] A structure 778 is between the first substrate 701 and the second substrate 705 provided. The structure 778 is a columnar spacer obtained by selectively etching an insulating film, and is provided to reduce the distance between the first substrate 701 and the second substrate 705 (Cell gap) to control. Alternatively, a spherical spacer can also be used as a structure 778 be used.

[0399] An opaque film 738 serving as a black matrix, a color film 736 , which serves as a color filter, and an insulating film 734 in contact with the opaque film 738 and the color film 736 are on the side of the second substrate 705 provided. <Structural example of a display device including a liquid crystal element>

[0400] The display device 700 in Fig. 16 includes a liquid crystal element 775 . The liquid crystal element 775 includes a conductive film 772 , a conductive film 774 and a liquid crystal layer 776 . The conductive film 774 is on the side of the second substrate 705 provided and serves as a counter electrode. The display device 700 in Fig. 16 can display an image by transmitting or not transmitting to light by the alignment state in the liquid crystal layer 776 that is changed depending on a voltage that is applied between the conductive film 772 and the conductive film 774 is applied, is controlled.

[0401] The conductive film 772 is electrically connected to the conductive film serving as the source electrode or drain electrode of the transistor 750 serves. The conductive film 772 is over the planarization insulating film 770 and serves as a pixel electrode, i. H. as the electrode of the display element.

[0402] A conductive film that transmits visible light or a conductive film that reflects visible light can be used as the conductive film 772 be used. For example, a material containing an element selected from indium (In), zinc (Zn) and tin (Sn) can be used for the conductive film that transmits visible light. For example, a material containing aluminum or silver can be used for the conductive film that reflects visible light.

[0403] In the case where a conductive film that reflects visible light is used as the conductive film 772 is used, the display device is 700 a reflective liquid crystal display device. In the case where a conductive film that transmits visible light is used as the conductive film 772 is used, the display device is 700 a transmissive liquid crystal display device.

[0404] The operating method of the liquid crystal element can be changed by changing the structure over the conductive film 772 will be changed; an example for this case is in Fig. 17 shown. The one in Fig. Display device 700 shown in FIG. Fig. 13 is an example in which a horizontal electric field mode (e.g., an FFS mode) is used as the operation mode of the liquid crystal element. With the in Fig. 17 becomes an insulating film 773 over the conductive film 772 is provided, and the conductive film 774 becomes 773 over the insulating film. provided. In such a structure, the conductive film 774 serves. as a common electrode, and an electric field created between the conductive film 772 and the conductive film 774 through the insulating film 773 is generated, the alignment state of the liquid crystal layer 776 Taxes.

[0405] Although in Fig. 16 and Fig. 17 not shown, the conductive film 772 or / and the conductive film 774 on one side in contact with the liquid crystal layer 776 be provided with an alignment film. Although in Fig. 16 and Fig. 17 not shown, an optical element (an optical substrate) or the like, such as. B. a polarizing element, a retardation element or an anti-reflective element can be provided. For example, circular polarization can be obtained using a polarizing substrate and a retardation substrate. In addition, backlighting, side lighting or the like can be used as the light source.

[0406] In the case where a liquid crystal element is used as a display element, a thermotropic liquid crystal, a low molecular liquid crystal, a high molecular liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an anti-ferroelectric liquid crystal or the like can be used. These liquid crystal materials have a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase or the like depending on the conditions.

[0407] In the case where a horizontal electric field mode is used, a liquid crystal having a blue phase, for which an alignment film is not necessary, can be used. The blue phase is one of the liquid crystal phases that is generated just before a cholesteric phase changes to an isotropic phase when the temperature of a cholesteric liquid crystal increases. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which a chiral material of several weight% or more is mixed is used for the liquid crystal layer in order to improve the temperature range. The liquid crystal composition containing a liquid crystal having a blue phase and a chiral material has a short response time and optical isotropy, which eliminates the need for the alignment process. An alignment film is not necessarily required to be provided, and therefore rubbing treatment is not required; consequently, damage due to electrostatic discharge caused by the rubbing treatment can be prevented, and defects and damage of a liquid crystal display device in the manufacturing process can be reduced. In addition, the liquid crystal material having a blue phase has only a slight dependence on the viewing angle.

[0408] In the case where a liquid crystal element is used as a display element, a twisted nematic (TN) mode, an in-plane switching (IPS) mode, a fringe field switching (FFS) mode, an axially symmetric aligned micro-cell (ASM) mode, an optically compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode anti-ferroelectric liquid crystal (AFLC) mode or the like can be used.

[0409] Furthermore, a normally black liquid crystal display device such as e.g. B. a transmissive liquid crystal display device in a vertical alignment (VA) mode can be used. There are a few examples of a vertical alignment mode; for example, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, an ASV mode or the like can be used. <Display device including a light-emitting element>

[0410] The one in Fig. Display device 700 shown in FIG. includes a light-emitting element 782 . The light-emitting element 782 includes a conductive film 772 , an EL layer 786 and a conductive film 788 . The one in Fig. Display device 700 shown in FIG. can display an image by light emission from the EL layer 786 of the light-emitting element 782 is used. It should be noted that the EL layer 786 an organic compound or an inorganic compound, such as. B. contains a quantum dot.

[0411] Examples of materials that can be used for an organic compound include a fluorescent material and a phosphorescent material. Examples of materials that can be used for a quantum dot include a gelatinous quantum dot material, an alloyed quantum dot material, a core-shell quantum dot material, and a core quantum dot material. A material that contains elements belonging to groups 12 and 16 belong to elements belonging to the groups 13 and 15 or contains elements belonging to the groups 14 and 16 can be used. Alternatively, a quantum dot material can be used which comprises an element such as e.g. B. Cadmium (Cd), Selenium (Se), Zinc (Zn), Sulfur (S), Phosphorus (P), Indium (In), Tellurium (Te), Lead (Pb), Gallium (Ga), Arsenic (As ) or aluminum (Al).

[0412] The above-described organic compound and the inorganic compound can be deposited by a method such as. B. an evaporation process (including a vacuum evaporation process), a droplet ejection process (also known as an inkjet process), a coating process or a gravure printing process. A low molecular weight material, a medium molecular weight material (including an oligomer and a dendrimer) or a high molecular weight material can be used in the EL layer 786 be included.

[0413] Here, a method of forming the EL layer becomes 786 by a droplet ejection method using Fig. 21A to Fig. 21D. Fig. 21A to Fig. 21D are cross-sectional views showing the method of forming the EL layer 786 represent.

[0414] First, the conductive film becomes 772 over the insulating planarization film 770 and an insulating film 730 is formed around part of the conductive film 772 to be covered (see Fig. 21A).

[0415] Then a droplet becomes 784 from a droplet ejector 783 to an exposed portion of the conductive film 772 , which is an opening of the insulating film 730 is ejected, so that a layer 785 containing a composition is formed. The droplet 784 is a composition that contains a solvent and adheres to the conductive film 772 staples (see Fig. 21B).

[0416] It should be noted that the step of ejecting the droplet 784 can be performed under reduced pressure.

[0417] Next, the solvent is removed from the composition containing layer 785 removed, and the obtained layer is solidified to form the EL layer 786 trained (see Fig. 21C).

[0418] The solvent can be removed by drying or heating.

[0419] Next, the conductive film becomes 788 over the EL layer 786 educated; accordingly, the light-emitting element becomes 782 trained (see Fig. 21D).

[0420] When the EL layer 786 as described above is formed by a droplet ejection method, the composition can be selectively ejected; consequently, the loss of materials can be reduced. Furthermore, a lithography process or the like for molding is not necessary, and therefore the process can be simplified and a reduction in cost can be achieved.

[0421] The droplet ejecting method described above is a general term for a means comprising a nozzle provided with a composition ejecting orifice or a means for ejecting droplets such as a spray nozzle. B. comprises a head with a nozzle or a plurality of nozzles.

[0422] Next, a droplet ejecting device used for the droplet ejecting method will be explained with reference to Fig. 22 described. Fig. Fig. 22 is a conceptual diagram showing a droplet ejector 1400 represents.

[0423] The droplet ejector 1400 includes a droplet ejector 1403 . In addition, the droplet ejecting means is 1403 with a head 1405 and a head 1412 Mistake.

[0424] The heads 1405 and 1412 are with a control means 1407 connected, and this control means 1407 is made by a computer 1410 controlled; this way a preprogrammed pattern can be drawn.

[0425] The drawing can, for example, based on a marking 1411 that is above a substrate 1402 is trained. Alternatively, the reference point can be based on an outer edge of the substrate 1402 to be determined. Here the marking becomes 1411 by an imaging agent 1404 and detected by an image processing means 1409 converted into a digital signal. Then the digital signal is 1410 through the computer. perceived, and then a control signal is generated and sent to the control means 1407 transfer.

[0426] An image sensor or the like using a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) can be used as the imaging means 1404 be used. It should be noted that information about a pattern that is over the substrate 1402 is to be trained in a storage medium 1408 are stored and that a control signal based on the information is sent to the control means 1407 is transmitted so that the heads 1405 and 1412 of the droplet ejector 1403 can be controlled separately from each other. The heads 1405 and 1412 are supplied with a material that is from material supply sources 1413 or 1414 is ejected through pipes.

[0427] In the head 1405 are a space indicated by a dashed line 1406 and is filled with a liquid material, and a nozzle is provided which is a discharge outlet. Although not shown, an internal structure of the head is 1412 that of the head 1405 similar. When the nozzle sizes of the heads 1405 and 1412 different from each other, different materials with different widths can be ejected at the same time. Each head can emit and draw a wide variety of light-emitting materials. In the case of drawing over a large area, the same drawing material can be ejected from a plurality of nozzles at the same time to improve throughput. If a large substrate is used, the heads can 1405 and 1412 the substrate in directions indicated by arrows X, Y and Z in Fig. 22, freely scan, and an area in which a pattern is drawn can be freely specified. Therefore, a plurality of the same pattern can be drawn several times over a substrate.

[0428] Furthermore, the step of discharging the composition can be carried out under reduced pressure. A substrate can be heated as the composition is ejected. After the composition has been ejected, either drying and / or baking is performed. Both drying and baking are heat treatments; however, they are different in purpose, temperature and length of time. The steps of drying and baking are carried out under normal pressure or under reduced pressure by laser light irradiation, rapid thermal annealing, heating using a heating oven, or the like. It should be noted that there is no particular limitation on the timing of heat treatment and the number of heat treatments. The appropriate temperature in carrying out the drying step and the baking step depends on the materials of the substrate and the properties of the composition.

[0429] In the manner described above, the EL layer can be 786 be formed with the droplet ejector.

[0430] 700 is used to explain the display device. that is in Fig. 18 is shown, returned.

[0431] With the in Fig. Display device 700 shown in FIG. the insulating film is 730 over the insulating planarization film 770 and the conductive film 772 provided. The insulating film 730 covers part of the conductive film 772 . It should be noted that the light-emitting element 782 has a top emission structure. Therefore, the conductive film has 788 has a light transmission property and transmits light emitted from the EL layer 786 is emitted. Although the top emission structure is described by way of example in this embodiment, the structure is not limited thereto. For example, a bottom emission structure in which light is directed to the side of the conductive film 772 can also be used. is emitted, or a dual-emission structure can be used in which light is emitted both to the side of the conductive film 772 as well as to the conductive film side 788 is emitted.

[0432] The color film 736 is arranged to be in contact with the light-emitting element 782 overlaps, and the opaque film 738 is in the connecting line section 711 and in the source driver circuit section 704 Arranged so as to be with the insulating film 730 overlaps. The color film 736 and the opaque film 738 are with the insulating film 734 covered. A space between the light-emitting element 782 and the insulating film 734 is covered with a sealing film 732 filled. The structure of the display device 700 is not based on the example in Fig. 18, in which the color film 736 is provided. For example, a structure without the color film 736 in the case where the EL layer 786 is formed by a separate color scheme, are used. <Structural example of a display device provided with an input / output device>

[0433] An input / output device can be found in Fig. 17 and Fig. Display device 700 shown in FIG. to be provided. A touch screen or the like can be given as an example of the input / output device.

[0434] Fig. 19 shows a structure in which the information specified in Fig. Display device 700 shown in FIG. a touch screen 791 includes. Fig. 20 illustrates a structure in which the information specified in Fig. Display device 700 shown in FIG. the touch screen 791 includes.

[0435] Fig. 19 is a cross-sectional view of the structure in which the touch screen 791 in the in Fig. 17 shown display device 700 is provided, and Fig. 20 is a cross-sectional view of the structure in which the touch screen 791 in the in Fig. Display device 700 shown in FIG. is provided.

[0436] Below is the first in Fig. 19 and Fig. 20 shown touchscreen 791 described.

[0437] The one in Fig. 19 and Fig. 20 shown touchscreen 791 is a so-called in-cell touchscreen that is installed between the substrate 705 and the color film 736 is provided. The touch screen 791 is on the side of the substrate 705 formed before the color film 736 is trained.

[0438] It should be noted that the touch screen 791 the opaque film 738 , an insulating film 792 , an electrode 793 , an electrode 794 , an insulating film 795 , an electrode 796 and an insulating film 797 includes. Changes in the mutual capacitance between the electrodes 793 and 794 can be detected when, for example, an object such as B. a finger or a pen approaches.

[0439] A section where the electrode 793 and the electrode 794 tick is in the upper section of the in Fig. 19 and Fig. 20 illustrated transistor 750 shown. The electrode 796 is electrical with the two electrodes 793 between which the electrode 794 is located via openings made in the insulating film 795 are provided, connected. Note that a structure in Fig. 19 and Fig. 20 is shown by way of example, in which a region in which the electrode 796 is provided in the pixel section 702 is provided; however, an embodiment of the present invention is not limited thereto. For example, the area in which the electrode 796 is provided in the source driver circuit section 704 to be provided.

[0440] The electrode 793 and the electrode 794 are provided in an area coincident with the opaque film 738 overlaps. As in Fig. 19, the electrode 793 overlaps. preferably not with the light-emitting element 775 . As in Fig. 20, the electrode 793 overlaps. preferably not with the liquid crystal element 782 . In other words: the electrode 793 has an opening in an area that communicates with the light-emitting element 782 and the liquid crystal element 775 overlaps. That is, the electrode 793 has a network shape. With such a structure, the electrode blocks 793 no light emitted from the light-emitting element 782 is emitted, or alternatively the electrode 793 blocks. no light emitting the liquid crystal element 775 happens. Therefore, since the luminance is hardly lowered even if the touch screen 791 is provided, a display device with good visibility and low power consumption can be obtained. It should be noted that the electrode 794 may have a structure similar to that of the electrode 793 is similar.

[0441] Since the electrode 793 and the electrode 794 not with the light-emitting element 782 may overlap, a metal material having a low transmittance with respect to visible light for the electrode 793 and the electrode 794 be used. Furthermore, since the electrode 793 and the electrode 794 not with the liquid crystal element 775 overlap, a metal material with a low transmittance in terms of visible light for the electrode 793 and the electrode 794 be used.

[0442] Therefore, the resistance of the electrodes can be 793 and 794 can be reduced as compared with the case where an oxide material whose visible light transmittance is high is used, whereby the sensitivity of the sensor of the touch screen can be increased.

[0443] For example, a conductive nanowire for the electrodes 793 , 794 and 796 be used. The nanowire can have an average diameter greater than or equal to 1 nm and less than or equal to 100 nm, preferably greater than or equal to 5 nm and less than or equal to 50 nm, more preferably greater than or equal to 5 nm and less than or equal to 25 nm. As a nanowire, a carbon nanotube or a metal nanowire, such as. B. an Ag nanowire, a Cu nanowire or an Al nanowire can be used. For example, in the case where one Ag nanowire is used for one or all of electrodes 793 , 794 and 796 is used, the visible light transmittance can be greater than or equal to 89%, and the sheet resistance can be greater than or equal to 40 Ω / sq and less than or equal to 100 Ω / sq.

[0444] Although the structure of the in-cell touchscreen is in Fig. 19 and Fig. 20, an embodiment of the present invention is not limited thereto. For example, a message above the display device 700 trained touchscreen, a so-called on-cell touchscreen, or one on the display device 700 attached touchscreen, a so-called out-cell touchscreen, can be used.

[0445] In this way, the display device of an embodiment of the present invention can be combined with different types of touch screens.

[0446] It should be noted that the structures described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments. (Embodiment 7)

[0447] In this embodiment, a display device including a semiconductor device of an embodiment of the present invention will be explained with reference to Fig. 23A to Fig. 23C. <Circuit configuration of a display device>

[0448] One in Fig. The display device shown in FIG. 23A includes an area including pixels of display elements (hereinafter referred to as pixel portion 502), A circuit portion which is outside of the pixel portion 502 and includes a circuit for driving the pixels (hereinafter the circuit section is referred to as driver circuit section 504), circuits having a function of protecting elements (hereinafter the circuits are referred to as protection circuits 506) and a terminal section 507 . It should be noted that the protection circuits 506 not necessarily provided.

[0449] Preferably, part or all of the driver circuit section is 504 formed over a substrate over which the pixel portion 502 is trained. Therefore, the number of components and the number of terminals can be reduced. When part or all of the driver circuit section 504 is not formed over the substrate over which the pixel portion 502 is formed, the part or the whole of the driver circuit section 504 by COG or tape automated bonding (TAB).

[0450] The pixel portion 502 includes a plurality of circuits for driving display elements arranged in X (X is a natural number of 2 or more) rows and Y (Y is a natural number of 2 or more) columns (hereinafter the circuits are referred to as pixel circuits 501 designated). The driver circuit section 504 includes driver circuits such as B. a circuit for supplying a signal (scanning signal) to select a pixel (hereinafter the circuit is referred to as a gate driver 504a), And a circuit for supplying a signal (data signal) to a display element in a pixel (hereinafter the circuit is referred to as the source driver 504b).

[0451] The gate driver 504a includes a shift register or the like. The gate driver 504a receives a signal for driving the shift register via the connection section 507 and emits a signal. For example, the gate driver receives 504a a start pulse signal, a clock signal, or the like and outputs a pulse signal. The gate driver 504a has a function of controlling the potentials of lines to which scanning signals are supplied (hereinafter referred to as scanning lines GL_1 to GL_X). It should be noted that a variety of gate drivers 504a may be provided to scan lines GL_1 to GL_X to be controlled separately. Alternatively, the gate driver has 504a a function for supplying an initialization signal. Without being limited to this, another signal from the gate driver 504a are fed.

[0452] The source driver 504b includes a shift register or the like. The source driver 504b receives, in addition to a signal for controlling the shift register, a signal from which a data signal is generated (image signal) via the connection section 507 . The source driver 504b has a function of generating a data signal to be input to the pixel circuit 501 is written from the image signal. The source driver 504b additionally has a function of controlling the output of a data signal in response to a pulse signal generated by inputting a start pulse, a clock signal or the like. The source driver also has 504b has a function of controlling the potentials of lines to which data signals are supplied (hereinafter referred to as data lines DL_1 to DL_Y). Alternatively, the source driver has 504b a function for supplying an initialization signal. Without being limited to this, another signal from the source driver can be 504b are fed.

[0453] The source driver 504b includes a variety of analog switches, for example. By turning on the plurality of analog switches one by one, the source driver 504b Output temporally divided signals as data signals. The source driver 504b may include a shift register or the like.

[0454] A pulse signal and a data signal are transmitted through one of the plurality of scan lines GL , to which scanning signals are fed, or via one of the large number of data lines DL , to which data signals are supplied, into each of the plurality of pixel circuits 501 entered. The writing and holding of the data signal in each of the plurality of pixel circuits 501 are controlled by the gate driver 504a controlled. For example, 501 in the m -th row and the n-th column (m is a natural number of X or less, and n is a natural number of Y or less) a pulse signal from the gate driver 504a via the scan line GL_m is input and a data signal is input from the source driver 504b via the data line DL_n according to the potential of the scan line GL_m entered.

[0455] The protective circuit 506 in Fig. For example, 23A is associated with scan line GL between the gate driver 504a and the pixel circuit 501 connected. The protective circuit 506 is alternatively with the data line DL between the source driver 504b and the pixel circuit 501 connected. The protective circuit 506 can alternatively also with a line between the gate driver 504a and the connector section 507 be connected. The protective circuit 506 can alternatively with a line between the source driver 504b and the connector section 507 be connected. It should be noted that the terminal portion 507 denotes a portion having terminals for inputting power, control signals and image signals to the display device from external circuits.

[0456] The protective circuit 506 connects a line that is connected to the protective circuit electrically to another line when a potential lying outside a certain range is supplied to the line that is connected to the protective circuit.

[0457] As in Fig. 23A, the protection circuits 506 that is for the pixel section 502 and the driver circuit section 504 are provided to improve the resistance of the display device to an overcurrent generated by electrostatic discharge (ESD) or the like. It should be noted that the configuration of the protection circuits 506 is not limited to; for example, the protection circuit 506 with the gate driver 504a or the source driver 504b be connected. The protective circuit 506 can alternatively with the connection section 507 be connected.

[0458] An embodiment of the present invention is not limited to the example in Fig. 23A in which the driver circuit section 504 the gate driver 504a and the source driver 504b includes. For example, only the gate driver 504a and a separately prepared substrate over which a source drive circuit is formed (e.g., a drive circuit board formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.

[0459] Each of the plurality of pixel circuits 501 in Fig. 23A can, for example, contain the information in Fig. 23B have the configuration shown.

[0460] The pixel circuit 501 in Fig. 23B includes a liquid crystal element 570 , a transistor 550 and a capacitor 560 . As a transistor 550 For example, the transistor described in the above embodiment can be used.

[0461] The potential of one of a pair of electrodes of the liquid crystal element 570 according to the specifications of the pixel circuit 501 as required. set. The alignment state of the liquid crystal element 570 depends on the data written in it. A common potential may be of one of the pair of electrodes of the liquid crystal element 570 that are supplied in each of the plurality of pixel circuits 501 is included. The potential that the one of the pair of electrodes of the liquid crystal element 570 in the pixel circuit 501 differentiate between lines.

[0462] Examples of a method of driving the display device using the liquid crystal element 570 includes a TN mode, an STN mode, a VA mode, an axially symmetric aligned micro-cell (ASM) mode, an optically compensated birefringence (OCB) Mode, a ferroelectric liquid crystal (FLC) mode, an anti-ferroelectric liquid crystal (AFLC) mode, an MVA mode, a Patterned Vertical Alignment (PVA) mode, an IPS Mode, an FFS mode and a Transverse Bend Alignment (TBA) mode. Further examples of the method for driving the display device include an electrically controlled birefringence (electically controlled birefringence, ECB) mode, a polymer dispersed liquid crystal (PDLC) mode, a polymer network liquid crystal (polymer network liquid crystal , PNLC) mode and a guest-host mode. Various liquid crystal elements and methods of operation can be used without being limited thereto.

[0463] With the pixel circuit 501 in the m-th row and the n-th column is either a source electrode or a drain electrode of the transistor 550 electrically with the data line DL_n connected, and the other of the source electrode and the drain electrode of the transistor 550 is electrical with the other of the pair of electrodes of the liquid crystal element 570 connected. A gate electrode of the transistor 550 is electrical with the scan line GL_m connected. The transistor 550 is configured to be turned on or off to control whether a data signal is written.

[0464] One of a pair of electrodes of the capacitor 560 is electrically connected to a line through which a potential is supplied (hereinafter referred to as potential supply line VL), and the other of the pair of electrodes of the capacitor 560 is electrical with the other of the pair of electrodes of the liquid crystal element 570 connected. The potential of the potential supply line VL according to the specifications of the pixel circuit 501 set. The capacitor 560 serves as a storage capacitor for storing the written data.

[0465] For example, in the display device using the pixel circuits, 501 in Fig. 23B includes the gate driver 504a in Fig. 23A shows the pixel circuits 501 line by line to set the transistors 550 turn on and data signals are written.

[0466] When the transistor 550 is turned off, the pixel circuit becomes 501 in which the data has been written is placed in a hold state. This process is carried out one line at a time; thus an image can be displayed.

[0467] Alternatively, each of the plurality of pixel circuits 501 in Fig. 23A, for example, the one in Fig. 23C have the configuration shown.

[0468] The pixel circuit 501 in Fig. 23C includes transistors 552 and 554 , a capacitor 562 and a light emitting element 572 . The transistor described in the above embodiment can be used as transistor 552 and / or transistor 554 be used.

[0469] Either a source electrode or a drain electrode of transistor 552 is electrically connected to a line through which a data signal is supplied (hereinafter referred to as data line DL_n). A gate electrode of the transistor 552 is electrically connected to a line through which a gate signal is supplied (hereinafter referred to as scan line GL_m).

[0470] The transistor 552 is configured to be turned on or off to control whether a data signal is written.

[0471] One of a pair of electrodes of the capacitor 562 is electrically connected to a line through which a potential is supplied (hereinafter referred to as potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552 connected.

[0472] The capacitor 562 serves as a storage capacitor for storing the written data.

[0473] Either a source electrode or a drain electrode of transistor 554 is electrically connected to the potential supply line VL_a connected. A gate electrode of the transistor 554 is electrical with the other of the source electrode and the drain electrode of the transistor 552 connected.

[0474] Either an anode or a cathode of the light-emitting element 572 is electrical with a potential supply line VL_b connected, and the other of the anode and the cathode of the light-emitting element 572 is electrical with the other of the source electrode and the drain electrode of the transistor 554 connected.

[0475] As a light-emitting element 572 For example, an organic electroluminescent element (also referred to as an organic EL element) can be used. It should be noted that the light-emitting element 572 is not limited to this, and an inorganic EL element containing an inorganic material can be used.

[0476] A high power supply potential V DD becomes one of the potential supply lines VL_a and the potential supply line VL_b is supplied, and a low power supply potential Vss becomes the other of the potential supply line VL_a and the potential supply line VL_b fed.

[0477] In the display device using the pixel circuit 501 in Fig. 23C, the pixel circuits become 501 through the gate driver 504a in Fig. 23A is selected one after the other row by row, whereby the transistors 552 switched on and data signals written.

[0478] When the transistors 552 are turned off, the pixel circuit becomes 501 in which the data has been written is placed in a hold state. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 flows, controlled according to the potential of the written data signal. The light-emitting element 572 emits light with a luminance according to the amount of current flowing. This process is carried out one line at a time; thus an image can be displayed.

[0479] It should be noted that the structures described in this embodiment can be combined with any of the structures described in the other embodiments as necessary. (Embodiment 8)

[0480] In this embodiment, configuration examples of the circuits to which the transistors described in the above embodiments can be applied will be explained with reference to Fig. 24A to Fig. 24C, Fig. 25A to Fig. 25C, Fig. 26A and Fig. 26B and Fig. 27A and Fig. 27B.

[0481] It should be noted that, in the following description, in this embodiment, the transistor which has been described in the above embodiment and includes an oxide semiconductor is referred to as an OS transistor. <Configuration example of an inverter circuit>

[0482] Fig. 24A is a circuit diagram of an inverter that can be used for a shift register, buffer, or the like included in the drive circuit. An inverter 800 outputs a signal the logic of which is reversed from the logic of a signal sent to an input terminal IN is supplied to an output terminal OUT out. The inverter 800 contains a variety of OS transistors. A signal S BG can switch electrical properties of the OS transistors.

[0483] Fig. 24B shows a circuit diagram of the inverter 800 The inverter 800 includes an OS transistor 810 and an OS transistor 820 . The inverter 800 can be formed using only n-channel transistors; therefore the inverter 800 can be formed at a lower cost than an inverter formed using a complementary metal oxide semiconductor (i.e., a complementary metal oxide semiconductor (CMOS) inverter).

[0484] It should be noted that the inverter 800 that includes the OS transistors can be provided over a CMOS circuit that includes Si transistors. Since the inverter 800 can be provided such that it overlaps with the CMOS circuit, no additional area becomes for the inverter 800 needed; therefore, an increase in the circuit area can be suppressed.

[0485] The OS transistors 810 and 820 each include a first gate serving as a front gate, a second gate serving as a back gate, a first terminal serving as a source or drain, and a second terminal serving as the other terminal of the source and drain.

[0486] The first gate of the OS transistor 810 is connected to its second port. The second gate of the OS transistor 810 is connected to a line that carries the signal S BG feeds, connected. The first connection of the OS transistor 810 is connected to a line that supplies a voltage VDD. The second connection of the OS transistor 810 is with the output connection OUT connected.

[0487] The first gate of the OS transistor 820 is with the input connection IN connected. The second gate of the OS transistor 820 is with the input connection IN connected. The first connection of the OS transistor 820 is with the output connection OUT connected. The second connection of the OS transistor 820 is connected to a line that supplies a voltage VSS.

[0488] Fig. 24C is a timing chart showing the operation of inverter 800 represents. The timing diagram in Fig. 24C illustrates changes in a signal waveform of the input terminal IN , a signal waveform of the output terminal OUT , a signal waveform of the signal S BG and the threshold voltage of the OS transistor 810 represent.

[0489] The signal S BG can be the second gate of the OS transistor 810 are fed to the threshold voltage of the OS transistor 810 to control.

[0490] The signal S BG includes a voltage V SG_A to shift the threshold voltage in negative direction and a voltage V BG_B to shift the threshold voltage in positive direction. The threshold voltage of the OS transistor 810 can in negative direction up to a threshold voltage V TH_A shifted when the voltage \ / BG_A is applied to the second gate. The threshold voltage of the OS transistor 810 can be used in a positive direction up to a threshold voltage V TH_B shifted when the voltage V BG_B is applied to the second gate.

[0491] To visualize the description above, Fig. shows. 25A a I d - V g Curve, which is one of the electrical properties of a transistor.

[0492] When a high voltage, such as B. the voltage \ / BG_A , is applied to the second gate, the electrical properties of the OS transistor 810 moved to with one in Fig. 25A by a dashed line 840 match the curve shown. When a low voltage such as B. the voltage V BG_B , is applied to the second gate, the electrical characteristics of the OS transistor 810 moved to one in Fig. 25A by a solid line 841 match the curve shown. As in Fig. 25A, enables the switching of the signal S BG between the voltage V BG_A and the voltage \ / BG_B that the threshold voltage of the OS transistor 810 is shifted in positive direction or negative direction.

[0493] The shift of the threshold voltage in the positive direction up to the threshold voltage V TH_B can reduce the likelihood of current in the OS transistor 810 flows. Fig. 25B visualizes this state.

[0494] As in Fig. 25B, current I B that is in the OS transistor 810 flows, be very low. Therefore, when a signal sent to the input terminal IN is supplied, is at a high level and the OS transistor 820 is ON, the voltage of the output terminal OUT reduce suddenly.

[0495] There, as in Fig. 25B, a state in which current is less likely to be present in the OS transistor 810 flows can be obtained, a signal waveform 831 of the output terminal in the timing diagram in Fig. 24C can be made steep. The breakdown current between the line that supplies the voltage VDD and the line that supplies the voltage VSS can be low, resulting in low power consumption operation.

[0496] The shift of the threshold voltage in the negative direction up to the threshold voltage V TH_A can ensure that the current in the OS transistor 810 flows easily. Fig. 25C visualizes this state. As in Fig. 25C, a current I A that flows at this point in time is at least higher than the current I B be. Therefore, when a signal sent to the input terminal IN is supplied, is at a low level and the OS transistor 820 is OFF, the voltage of the output terminal OUT increase suddenly. There, as in Fig. 25C, a state in which current is likely to be in the OS transistor 810 flows can be obtained, a signal waveform 832 of the output terminal in the timing diagram in Fig. 24C can be made steep.

[0497] It should be noted that the threshold voltage of the OS transistor 810 preferably by the signal S BG is controlled before the state of the OS transistor 820 is switched, d. H. before time T1 or time T2. For example, preferably, as in Fig. 24C, the threshold voltage of the OS transistor 810 from the threshold voltage V TH_A to the threshold voltage \ / TH_B is switched before time T1 at which the level of the signal supplied to the input terminal IN is supplied, is switched to a high level. Furthermore, as in Fig. 24C, the threshold voltage of the OS transistor 810 from the threshold voltage V TH_B to the threshold voltage \ / TH_A is switched before time T2 at which the level of the signal supplied to the input terminal IN is supplied, is switched to a low level.

[0498] Although the timing diagram in Fig. 24C illustrates the structure in which the level of the signal S BG according to the input port IN applied signal is switched, a different structure can be used, in which, for example, a voltage for controlling the threshold voltage through the second gate of the OS transistor 810 is kept in a floating state. Fig. 26A illustrates an example of such a circuit configuration.

[0499] The circuit configuration in Fig. 26A is the one in Fig. 24B the same except that an OS transistor 850 is added. A first connection of the OS transistor 850 is to the second gate of the OS transistor 810 connected. A second connection of the OS transistor 850 is with a wire that carries the voltage V BG_B (or the voltage \ / BG_A ) is connected. A first gate of the OS transistor 850 is with a wire that has a signal S F feeds, connected. A second gate of the OS transistor 850 is with the line that carries the voltage V BG_B (or the voltage \ / BG_A ) is connected.

[0500] How the circuit configuration works in Fig. 26A is illustrated in Fig. using a timing diagram. 26B.

[0501] The voltage for controlling the threshold voltage of the OS transistor 810 becomes the second gate of the OS transistor 810 before time T3 at which the level of the signal applied to input terminal IN is supplied, is switched to a high level. The signal S F is set to a high level, and the OS transistor 850 is switched on so that the voltage V BG_B to control the threshold voltage to a node N BG is fed.

[0502] The OS transistor 850 is turned off after the voltage of the node N BG to V BG_B has become. Since the reverse current of the OS transistor 850 is very low, the voltage can be V BG_B from the node N BG is maintained while the OS transistor 850 remains off. Therefore, the number of times the voltage V BG_B the second gate of the OS transistor 850 is supplied, decreased; consequently, the power consumption for rewriting the voltage can be V BG_B be reduced.

[0503] Although Fig. 24B and Fig. 26A each illustrate the case where the voltage is applied to the second gate of the OS transistor 810 is supplied by external control, for example, a different structure can be used in which the voltage is used to control the threshold voltage based on the signal sent to the input terminal IN and the second gate of the OS transistor 810 is fed. Fig. 27A illustrates an example of such a circuit configuration.

[0504] The circuit configuration in Fig. 27A is the one in Fig. 24B, except that a CMOS inverter 860 between the input terminal IN and the second gate of the OS transistor 810 is provided. An input terminal of the CMOS inverter 860 is with the input connection IN connected. An output terminal of the CMOS inverter 860 is connected to the second gate of the OS transistor 810 connected.

[0505] How the circuit configuration works in Fig. 27A is illustrated in Fig. using a timing diagram. 27B. The timing diagram in Fig. 27B illustrates changes in a signal waveform of the input terminal IN , a signal waveform of the output terminal OUT , an output waveform IN_B of the CMOS inverter 860 and a threshold voltage of the OS transistor 810 represent.

[0506] The output waveform IN_B that corresponds to a signal whose logic is different from the logic of the input terminal IN input signal is reversed, it may be a signal showing the threshold voltage of the OS transistor 810 controls. Therefore, as with Fig. 25A to Fig. 25C, the threshold voltage of the OS transistor 810 being controlled. For example, this is the input connection IN applied signal at a high level, and the OS transistor 820 becomes Fig. at time T4. 27B switched on. The output waveform is IN_B at a low level. As a result, the possibility that the current in the OS transistor 810 flows; therefore, the voltage of the output terminal can be OUT be reduced suddenly.

[0507] In addition, there is the signal that is sent to the input terminal IN is supplied, at a low level, and the OS transistor 820 becomes Fig. at time T5. 27B switched off. The output waveform is IN_B at a high level. As a result, the current can easily flow in the OS transistor 810 flow; therefore, an increase in the voltage of the output terminal OUT be made abruptly.

[0508] As described above, in the configuration of the inverter including the OS transistor, in this embodiment, the voltage of the back gate is set according to the logic of the signal inputted to the input terminal IN is supplied, switched. With such a configuration, the threshold voltage of the OS transistor can be controlled. The control of the threshold voltage of the OS transistor by the signal sent to the input terminal IN is supplied, a sudden change in the voltage of the output terminal OUT cause. In addition, the breakdown current between the lines that feed power supply voltages can be reduced. Therefore, the power consumption can be reduced.

[0509] It should be noted that the structures described in this embodiment can be combined with one of the structures described in the other embodiments as necessary. (Embodiment 9)

[0510] In this embodiment, examples of a semiconductor device in which transistors including an oxide semiconductor (OS transistor) described in the above embodiment are used in a variety of circuits will be explained with reference to Fig. 28A to Fig. 28E, Fig. 29A and Fig. 29B, Fig. 30A and Fig. 30B and Fig. 31A to Fig. 31C. <Configuration example of a circuit of a semiconductor device>

[0511] Fig. 28A is a block diagram of a semiconductor device 900 . The semiconductor device 900 includes a power supply circuit 901 , a circuit 902 , a voltage generating circuit 903 , a circuit 904 , a voltage generating circuit 905 and a circuit 906 .

[0512] The power supply circuit 901 is a circuit that generates a voltage V ORG that is used as a reference. The voltage V ORG is not necessarily just one voltage, and it can be a variety of voltages. The voltage V ORG can be based on a voltage V 0 generated from the outside of the semiconductor device 900 is fed. The semiconductor device 900 the voltage can be V ORG generate based on a power supply voltage that is supplied from the outside. Therefore, the semiconductor device 900 work without a large number of external power supply voltages.

[0513] The circuits 902 , 904 and 906 work with different power supply voltages. For example, the power supply voltage of the circuit is 902 a voltage based on the voltage V ORG and the voltage Vss (V ORG> V SS) is applied. For example, the power supply voltage of the circuit is 904 a voltage calculated on the basis of a voltage V POG and the voltage V SS (V POG> V ORG) Is created. For example, the power supply voltages of the circuit are 906 Stresses based on the stress V ORG , the voltage Vss and a voltage V NEG (V ORG> V SS> V NEG) Is created. When the voltage Vss is equal to a ground potential (GND), the types of voltages used in the power supply circuit 901 are generated, are reduced.

[0514] The voltage generating circuit 903 is a circuit that generates voltage V POG generated. The voltage generating circuit 903 the voltage can be V POG based on the voltage V ORG generated by the power supply circuit 901 is fed. Therefore, the semiconductor device 900 who have the circuit 904 includes, operate on the basis of a power supply voltage that is supplied from the outside.

[0515] The voltage generating circuit 905 is a circuit that generates voltage V NEG generated. The voltage generating circuit 905 the voltage can be V NEG based on the voltage V ORG generated by the power supply circuit 901 is fed. Therefore, the semiconductor device 900 that have the circuit 906 includes, operate on the basis of a power supply voltage that is supplied from the outside.

[0516] Fig. 28B shows an example of the circuit 904 at voltage V POG works, and Fig. 28C illustrates an example of a waveform of a signal for driving the circuit 904 represent.

[0517] Fig. 28B represents a transistor 911 A signal sent to a gate of transistor 911 is supplied, for example, based on the voltage V POG and the voltage Vss. The signal becomes at the time when the transistor 911 is switched on based on the voltage V POG and is generated at the time when the transistor 911 is turned off based on the voltage Vss. As in Fig. 28C, the voltage is V POG higher than the voltage V ORG . Therefore, a conduction state between a source (S) and a drain (D) of the transistor 911 will certainly be preserved. As a result, the frequency of circuit malfunctions can be 904 be reduced.

[0518] Fig. 28D shows an example of the circuit 906 that at voltage V NEG working, and Fig. 28E illustrates an example of a waveform of a signal for driving the circuit 906 represent.

[0519] Fig. 28D represents a transistor 912 with a back gate. A signal that is sent to a gate of transistor 912 is supplied, for example, based on the voltage V ORG and the voltage Vss. The signal becomes at the time when the transistor 912 is switched on, based on the voltage V ORG and is generated at the time when the transistor 912 is turned off based on the voltage Vss. A signal sent to the back gate of transistor 912 is supplied, based on the voltage V NEG generated. Like in Fig. As shown in Figure 28E, the voltage is V NEG lower than the voltage Vss (GND). Therefore, the threshold voltage of the transistor 912 be controlled so that it shifts in the positive direction. Therefore, the transistor 912 can be turned off with certainty, and the current flowing between a source (S) and a drain (D) can be reduced. As a result, the frequency of circuit malfunctions can be 906 can be reduced and their power consumption can be reduced.

[0520] The voltage V NEG can be the back gate of transistor 912 can be fed directly. Alternatively, a signal sent to the gate of transistor 912 is supplied, based on the voltage V ORG and the voltage V NEG and the generated signal can be sent to the back gate of transistor 912 are fed.

[0521] Fig. 29A and Fig. 29B represent a modification example of Fig. 28D and Fig. 28E.

[0522] In one in Fig. 29A is a transistor 922 , whose conductive state is controlled by a control circuit 921 can be controlled between the voltage generating circuit 905 and the circuit 906 provided. The transistor 922 is an n-channel OS transistor. The control signal S BG that is generated by the control circuit 921 is output is a signal for controlling the conduction state of the transistor 922 . Transistors 912A and 912B that are in the circuit 906 are the same OS transistors as transistor 922 .

[0523] A timing diagram in Fig. 29B shows changes in the potential of the control signal S BG and the potential of a node N BG . The potential of the node N BG represents the states of potentials of back gates of the transistors 912A and 912B When the control signal S BG is high, transistor 922 switched on, and the voltage of node N BG becomes the voltage V NEG . Then, when the control signal S BG is at a low level, node N BG placed in an electrically floating state. Since the transistor 922 is an OS transistor, its reverse current is small. Accordingly, even if the node N BG is in an electrically floating state, the applied voltage V NEG being held.

[0524] Fig. 30A illustrates an example of a circuit configuration used for the voltage generating circuit 903 described above. is usable. The one in Fig. Voltage generating circuit 903 shown in FIG. 30A. is a five-stage charge pump, the diodes D1 to D5 , Capacitors C1 to C5 and an inverter INV includes. A clock signal CLK becomes the capacitors C1 to C5 directly or via the inverter INV fed. When a power supply voltage of the inverter INV is a voltage based on the voltage V ORG and the voltage Vss is applied, the voltage V POG in response to the application of the clock signal CLK can be obtained by setting the voltage V ORG to a voltage which is five times a potential difference between the voltage V ORG and the voltage \ / ss is increased. It should be noted that a forward voltage of the diodes D1 to D5 is at 0 V. A required voltage V POG can be obtained when the number of stages of the charge pump is changed.

[0525] Fig. 30B illustrates an example of a circuit configuration common to the voltage generating circuit 905 described above. is usable. The one in Fig. Voltage generating circuit 905 shown in FIG. 30B. is a four-stage charge pump that uses the diodes D1 to D5 , the capacitors C1 to C5 and the inverter INV includes. The clock signal CLK becomes the capacitors C1 to C5 directly or via the inverter INV fed. When a power supply voltage of the inverter INV is a voltage based on the voltage V ORG and the voltage Vss is applied, the voltage V NEG in response to the application of the clock signal CLK can be obtained by taking the earth voltage, i.e. H. the voltage Vss, to a voltage which is four times the potential difference between the voltage V ORG and the voltage \ / ss is reduced. It should be noted that a forward voltage of the diodes D1 to D5 is at 0 V. A required voltage V NEG can be obtained when the number of stages of the charge pump is changed.

[0526] The circuit configuration of the voltage generating circuit 903 does not affect the configuration of the in Fig. 30A is limited. Modification examples for the voltage generating circuit 903 are in Fig. 31A to Fig. 31C shown. It should be noted that other modification examples for the voltage generating circuit 903 can be obtained by adding voltages that are supplied to lines, or an arrangement of elements at in Fig. 31A to Fig. Voltage generating circuits 903A shown in Figure 31C. to 903C be changed.

[0527] The one in Fig. Voltage generating circuit 903A shown in Fig. 31A. includes transistors M1 to M10 , Capacitors C11 to C14 and an inverter INV1 . The clock signal CLK becomes the gates of the transistors M1 to M10 directly or via the inverter INV1 fed. In response to the application of the clock signal CLK the voltage can be V POG can be obtained by setting the voltage V ORG to a voltage which is four times the potential difference between the voltage V ORG and the voltage \ / ss is increased. A required voltage V POG can be obtained when the number of stages is changed. At the voltage generating circuit 903A in Fig. 31A can be the reverse current of the transistors M1 to M10 each be low when the transistors M1 to M10 OS transistors are, and draining a charge that is in the capacitors C11 to C14 can be suppressed. Accordingly, the increase in voltage V ORG to the voltage V POG be carried out efficiently.

[0528] The one in Fig. Voltage generating circuit 903B shown in FIG. 31B. includes transistors M11 to M14 , Capacitors C15 and C16 and an inverter INV2 . The clock signal CLK becomes the gates of the transistors M11 to M14 directly or via the inverter INV2 fed. In response to the application of the clock signal CLK the voltage can be V POG can be obtained by setting the voltage V ORG to a voltage which is twice the potential difference between the voltage V ORG and the voltage Vss is increased. At the voltage generating circuit 903B in Fig. 31B can be the reverse current of the transistors M11 to M14 each be low when the transistors M11 to M14 OS transistors are, and draining a charge that is in the capacitors C15 and C16 can be suppressed. Accordingly, the increase in voltage V ORG to the voltage V POG be carried out efficiently.

[0529] The voltage generating circuit 903C in Fig. 31C includes an inductor Ind1 , a transistor M15 , a diode D6 and a capacitor C17 . The conductive state of transistor M15 is activated by a control signal EN controlled. Thanks to the control signal EN the voltage can be V POG that by increasing the voltage V ORG will be obtained. Since the voltage generating circuit 903C in Fig. 31C the voltage by means of the inductor Ind1 increased, the voltage can be increased efficiently.

[0530] As described above, in one of the structures of this embodiment, a voltage required for circuits included in a semiconductor device can be generated internally. Therefore, in the semiconductor device, the types of power supply voltages that are supplied from the outside can be reduced.

[0531] It should be noted that the structures and the like described in this embodiment are combined with any of the structures described in the other embodiments as necessary. (Embodiment 10)

[0532] In this embodiment, a display module and electronic equipment each including a semiconductor device of an embodiment of the present invention will be explained with reference to Fig. 32, Fig. 33A to Fig. 33E, Fig. 34A to Fig. 34G and Fig. 35A and Fig. 35B. <Display module>

[0533] For one in Fig. 32 shown display module 7000 are a touch screen 7004 that works with an FPC 7003 connected, a display field 7006 that works with an FPC 7005 connected, a backlight 7007 , a frame 7009 , a printed circuit board 7010 and a battery 7011 between a top cover 7001 and a lower cover 7002 provided.

[0534] For example, the semiconductor device of one embodiment of the present invention can be used for the display panel 7006 be used.

[0535] The shapes and sizes of the top cover 7001 and the bottom cover 7002 can as required according to the sizes of the touch screen 7004 and the display field 7006 be changed.

[0536] The touch screen 7004 can be a resistive touchscreen or a capacitive touchscreen and deal with the display field 7006 overlap. Alternatively, a counter substrate (sealing substrate) of the display panel 7006 have a touchscreen function. Alternatively, a photo sensor can be installed in each pixel of the display field 7006 be provided to form an optical touch screen.

[0537] The backlight 7007 includes a light source 7008 . An embodiment of the present invention is not limited to the structure in Fig. 32, in which the light source 7008 above the backlight 7007 provided is limited. For example, a structure can be used in which the light source 7008 at an end portion of the backlight 7007 is provided and a light diffusion disk is also provided. It should be noted that in the case where a self-luminous light-emitting element such as An organic EL element is used, or in the case where a reflective screen or the like is used, the backlight 7007 does not have to be provided.

[0538] The frame 7009 protects the display field 7006 and serves as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 7010 be generated. The frame 7009 can also serve as a radiating plate.

[0539] The printed circuit board 7010 includes a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As the power source for supplying power to the power supply circuit, an external utility power source or the separately provided battery 7011 be used. The battery 7011 can be omitted in the case where an AC power source is used.

[0540] The display module 7000 can also be combined with an element such as B. a polarizing plate, a retardation plate or a prism sheet. <Electronic device 1>

[0541] Next put Fig. 33A to Fig. 33E are examples of electronic devices.

[0542] Fig. 33A is an external view of a camera 8000 at which a viewfinder 8100 is appropriate.

[0543] The camera 8000 includes a housing 8001 , a display section 8002 , an operating button 8003 , a release button 8004 and the same. There is also a detachable lens 8006 on the camera 8000 appropriate.

[0544] Although the lens 8006 of the camera 8000 here from the housing 8001 can be removed for replacement, the lens 8006 in the case 8001 be included.

[0545] Pictures can be taken with the camera 8000 by pressing the release button 8004 be included. In addition, images can be viewed by touching the display section 8002 that serves as a touch screen.

[0546] The housing 8001 of the camera 8000 includes a holder with an electrode so that the viewfinder 8100 , a strobe or the like with the housing 8001 can be connected.

[0547] The viewfinder 8100 includes a housing 8101 , a display section 8102 , a button 8103 and the same.

[0548] The housing 8101 Includes a bracket that snaps onto the bracket of the camera 8000 so that the viewfinder 8100 with the camera 8000 can be connected. The holder includes an electrode, and an image or the like taken from the camera 8000 is received through the electrode can be displayed on the display section 8102 are displayed.

[0549] The button 8103 serves as a power button. The on / off state of the display section 8102 can be done with the button 8103 be switched on and off.

[0550] A display device of an embodiment of the present invention can be used for the display section 8002 the camera 8000 and the display section 8102 of the viewfinder 8100 be used.

[0551] Although the camera 8000 and the viewfinder 8100 in Fig. 33A are separate and detachable electronic devices, the housing 8001 the camera 8000 include a viewfinder with a display device.

[0552] Fig. 33B is an external view of a head-worn display 8200 .

[0553] The display 8200 that can be worn on the head. includes a holding portion 8201 , a lens 8202 , a main body 8203 , a display section 8204 , a cable 8205 and the same. The holding section 8201 includes a battery 8206 .

[0554] The main body 8203 gets power from the battery 8206 via the cable 8205 fed. The main body 8203 includes a wireless receiver or the like to receive video data such as B. image data to be received and then displayed on the display section 8204 to display. The movement of a user's eyeball or eyelid is detected by a camera in the main body 8203 and then coordinates of the points the user is looking at are calculated using the captured data to use the user's eye as an input means.

[0555] The holding section 8201 may include a plurality of electrodes such that they are in contact with the user. The main body 8203 may be configured to sense current flowing through the electrodes with the movement of the user's eyeball to detect the direction of their eyes. The main body 8203 may be configured to sense current flowing through the electrodes to monitor the user's heart rate. The holding section 8201 can sensors such as B. a temperature sensor, a pressure sensor or an acceleration sensor, so that biological information of the user on the display section 8204 can be displayed. The main body 8203 may be configured to detect the movement of the user's head or the like to display an image displayed on the display section 8204 is displayed to move in synchronization with the movement of the user's head or the like.

[0556] The display device of one embodiment of the present invention can be displayed in the display section 8204 be used.

[0557] Fig. 33C to Fig. 33E are exterior views of a head-worn display 8300 . The display 8300 that can be worn on the head. includes a housing 8301 , a display section 8302 , a fastening tape 8304 and a pair of lenses 8305 .

[0558] A user can view a display on the display section 8302 through the lenses 8305 see. It is preferable that the display section 8302 is curved. When the display section 8302 is curved, a user can have a high realistic impression of images. Although the structure exemplified in this embodiment includes a display section 8302 is included, the number of the display section is 8302 not limited to one. For example, two display sections 8302 can be provided, in which case a display section is provided for a corresponding eye of the user, so that a three-dimensional display using the parallax or the like is enabled.

[0559] The display device of one embodiment of the present invention can be displayed in the display section 8302 be used. The display device including the semiconductor device of one embodiment of the present invention has very high resolution; therefore, even if an image is taken using the lenses 8305 is enlarged, as in Fig. 33E, the user pixels are not true, and therefore a more realistic image can be displayed. <Electronic device 2>

[0560] Next put Fig. 34A to Fig. 34G provides examples of electronic devices different from those in Fig. 33A to Fig. 33E are shown.

[0561] The one in Fig. 34A to Fig. Electronic devices shown in Figure 34G include a housing 9000 , a display section 9001 , a speaker 9003 , an operation button 9005 (including a power switch or an operating switch), a connection terminal 9006 , a sensor 9007 (a sensor with a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric Energy, radiation, flow rate, humidity, gradient, vibration, odor or infrared ray), a microphone 9008 and the same.

[0562] The one in Fig. 34A to Fig. The electronic devices shown in Fig. 34G have various functions, such as: A function of displaying various information (e.g., a still image, a moving image and a text image) on the display section, a touch screen function, a function of displaying a calendar, date, time and the like, a function of Controlling processing with various kinds of software (programs), a wireless communication function, a function of connecting to various computer networks by means of a wireless communication function, a function of transmitting and receiving various data by means of a wireless communication function and a function of reading out a program or data, which is / are stored in a storage medium, and displaying them on the display section. It should be noted that functions of the electronic devices in Fig. 34A to Fig. 34G are not limited to this, and the electronic devices may have various functions. Although in Fig. 34A to Fig. 34G, the electronic devices may each have a plurality of display sections. Further, the electronic devices may each be provided with a camera and the like to perform a function of capturing a still picture, a function of capturing a moving image, a function of storing the captured image in a storage medium (an external storage medium or a storage medium stored in built into the camera) to have a function of displaying the captured image on the display section or the like.

[0563] The following are the electronic devices in Fig. 34A to Fig. 34G described in detail.

[0564] Fig. 34A is a perspective view showing a television set 9100 represents. The television set 9100 can display section 9001 that has a large screen size such as 50 inches or more or 100 inches or more.

[0565] Fig. 34B is a perspective view of a portable information terminal 9101 . The portable information terminal 9101 serves as one or more of a telephone set, a notebook, and an information retrieval system, for example. In particular, the portable information terminal can be used as a smartphone. It should be noted that the portable information terminal 9101 the speaker 9003 , the connection terminal 9006 , the sensor 9007 or the like. The portable information terminal 9101 can display characters and image information on its variety of surfaces. For example, three operating buttons 9050 (also referred to as operating icons or simply as icons) on a surface of the display section 9001 are displayed. Information can also be found at 9051 represented by dashed rectangles on another surface of the display section 9001 are displayed. Examples of the information 9051 Include an indication of the receipt of an email, social networking service (SNS) notification or call, the subject and sender of an email or SNS notification, the date the Shows the time, the remaining battery capacity and the reception strength of an antenna. Alternatively, the control buttons 9050 or the like at the positions of the information 9051 are displayed.

[0566] Fig. 34C is a perspective view of a portable information terminal 9102 . The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display section 9001 on. This is where information 9052 , Information 9053 and information 9054 displayed on different surfaces. For example, a user of the portable information terminal can use 9102 the display (here the information 9053) on the portable information terminal 9102 that is carried in a breast pocket of his garment. Specifically, the telephone number, name or the like of the caller of an incoming call is displayed at a position from above the portable information terminal 9102 can be seen from. The user can watch the display without using the portable information terminal 9102 out of the pocket and decide whether to take the call.

[0567] Fig. 34D is a perspective view of a portable information terminal 9200 in the form of a wrist watch. The portable information terminal 9200 can do various applications, such as B. cell phone calls, e-mailing, reading and editing texts, playing music, Internet communication and computer games. The display surface of the display section 9001 is curved, and display can be performed on the curved display surface. The portable information terminal 9200 can use short-range communication according to a communication standard. For example, by mutual communication between the portable information terminal 9200 and a headset that is suitable for wireless communication, a hands-free telephone conversation can be achieved. The portable information terminal 9200 also includes the connection terminal 9006 and can carry out direct data communication with another information terminal via a connector. Charging through the connection port 9006 is also possible. It should be noted that charging without the connection terminal 9006 can be done by wireless power supply.

[0568] Fig. 34E, Fig. 34F and Fig. 34G are perspective views of a collapsible portable information terminal 9201 , which is opened, which is set from the opened state to the folded state or from the folded state to the open state or which is collapsed. The portable information terminal 9201 is very portable when it is folded. When the portable information terminal 9201 is open, a seamless large display area is very searchable. The display section 9001 of the portable information terminal 9201 is made up of three housings 9000 worn by joints 9055 are connected to each other. The shape of the portable information terminal 9201 can be reversibly changed from the open state to the collapsed state by turning the hinges 9055 between the two adjacent housings 9000 is collapsed. For example, the portable information terminal can 9201 be bent with a radius of curvature greater than or equal to 1 mm and less than or equal to 150 mm.

[0569] Next, in Fig. 35A and Fig. 35B shows an example of an electronic device that differs from the ones in Fig. 33A to Fig. 33E and Fig. 34A to Fig. 34G differs from the electronic devices shown. Fig. 35A and Fig. 35B are perspective views of a display device including a plurality of display panels. The plurality of display fields are in the perspective view in Fig. 35A wound and in the perspective view in Fig. 35B settled.

[0570] A display device 9500 that is in Fig. 35A and Fig. 35B includes a plurality of display panels 9501 , one axis 9511 and a bracket 9512 . The variety of display fields 9501 each includes a display area 9502 and a translucent area 9503 .

[0571] Each of the plurality of display fields 9501 is flexible. Two adjacent display fields 9501 are provided so that they partially overlap each other. For example, the transparent areas 9503 of the two adjacent display fields 9501 overlap each other. A display device having a large screen can be provided with the plurality of display panels 9501 can be obtained. The display device is very versatile because the display fields 9501 can be wrapped depending on their intended use.

[0572] Although the display areas 9502 of the adjacent display fields 9501 in Fig. 35A and Fig. 35B are separated from each other, the display areas 9502 of the adjacent display fields 9501 without being limited to this structure, for example, overlap each other without a gap so that a continuous display area 9502 is obtained.

[0573] Electronic devices described in this embodiment are characterized by including a display section for displaying certain kinds of information. It should be noted that the semiconductor device of one embodiment of the present invention can also be used for an electronic device that does not have a display section.

[0574] It should be noted that the structures described in this embodiment can be combined with any of the structures described in the other embodiments as necessary. (Embodiment 11) <Semiconductor Circuit>

[0575] The transistors disclosed in this specification and the like can be used in various semiconductor circuits, e.g. B. logic circuits such. B. an OR circuit, an AND circuit, a NAND circuit and a NOR circuit, an inverter circuit, a buffer circuit, a shift register circuit, a flip-flop circuit, an encoder circuit, a decoder Formwork, an amplifier circuit, an analog switching circuit, an integrating circuit, a differentiating circuit, a storage element and the like can be used.

[0576] Examples of a semiconductor circuit including the transistor disclosed in this specification and the like are shown in circuit diagrams in Fig. 46A to Fig. 46C. In the circuit diagrams, “OS” is written next to the circuit symbol of a transistor that contains an oxide semiconductor to clearly show that the transistor contains an oxide semiconductor.

[0577] The one in Fig. 46A has a configuration of an inverter circuit in which the p-channel transistor 281 and the n-channel transistor 282 are connected in series and in which the gates of the transistor are connected to one another.

[0578] The one in Fig. 46B has a configuration of an analog switching circuit in which the p-channel transistor 281 and the n-channel transistor 282 are connected in parallel with each other.

[0579] The one in Fig. 46C has a configuration of a NAND circuit using a transistor 281a , a transistor 281b , a transistor 282a and a transistor 282b includes. A potential output from the NAND circuit changes in Dependence on the combination of potentials in an input connection IN_A and an input terminal IN_B can be entered. <Storage device>

[0580] The one in Fig. 47A has a configuration of a memory device in which a source or a drain of a transistor 289 with a gate of a transistor 1281 and one electrode of a capacitor 257 connected is. The one in Fig. 47B has a configuration of a memory device in which the source or drain of the transistor 289 with one electrode of the capacitor 257 connected is.

[0581] In each of the circuits in Fig. 47A and Fig. 47B, charges drawn from the other terminal of the source and drain of transistor 289 be injected at a node 256 get saved. The transistor 289 is a transistor containing an oxide semiconductor that allows charges to be deposited on node 256 can be stored for a long time.

[0582] Although the transistor 1281 in Fig. 47A is a p-channel transistor, transistor 1281 be an n-channel transistor. For example, the transistor 281 or the transistor 282 as transistor 1281 be used. An OS transistor can also be used as a transistor 1281 be used.

[0583] The semiconductor devices (memory devices) listed in Fig. 47A and Fig. 47B are described in detail herein.

[0584] The one in Fig. The semiconductor device shown in 47A includes the transistor 1281 using a first semiconductor, transistor 289 using a second semiconductor and the capacitor 257 .

[0585] The transistor 289 is one of the OS transistors disclosed in the above embodiment. Since the reverse current of transistor 289 is low, stored data can be held at a predetermined node of the semiconductor device for a long period of time. In other words, the power consumption of the storage device can be reduced because a refresh operation is unnecessary or the frequency of the refresh operations can be very low.

[0586] In Fig. 47A is a line 251 electrically with a connection of the source and drain of the transistor 1281 connected, and a line 252 is electrical to the other terminal of the source and drain of transistor 1281 connected. One line 253 is electrical with a terminal of the source and drain of the transistor 289 connected. One line 254 is electrical to a gate of transistor 289 connected. The gate of transistor 1281 , the other terminal of the source and drain of transistor 289 and the one electrode of the capacitor 257 are electrical with the node 256 connected. One line 255 is electrical with the other electrode of the capacitor 257 connected.

[0587] The storage device in Fig. 47A has a feature that the charges assigned to node 256 supplied, can be held, and therefore enables writing, holding and reading of data as follows. [Write and hold]

[0588] The writing and holding of data are described. First, the potential of the line 254 set to a potential at which the transistor 289 is switched on. As a result, the potential of the line becomes 253 the node 256 fed. That is, the node 256 a predetermined charge is supplied (writing). One of two types of charges that provide different levels of potential (hereinafter referred to as “low level charge” and “high level charge”) is applied here. After that, the potential of the line becomes 254 is set to a potential at which the transistor 289 is turned off. Thus, the charge at node 256 held.

[0589] It should be noted that the high-level charge is a charge given to node 256 supplies a higher potential than the low level charge. In the case where the transistor 1281 is a p-channel transistor, the high-level charge and the low-level charge are each a charge that supplies a potential higher than the threshold voltage of the transistor 1281 . In the case where the transistor 1281 is an n-channel transistor, both the high-level charge and the low-level charge are a charge that supplies a potential lower than the threshold voltage of the transistor 1281 . In other words, the high-level charge and the low-level charge are each a charge that supplies a potential at which the transistor 1281 is turned off.

[0590] Since the reverse current of transistor 289 is very low, the charge on node 256 held for a long time. [Reading process]

[0591] Reading of data will be described next. A reading potential V R becomes the line 255 while a predetermined potential (constant potential) different from the potential of the line 252 differentiates, the line 251 is supplied, whereby data that is sent to the node 256 can be read.

[0592] The reading potential V R is set to {(V th - V H) + (V th + V L)} / 2, where V H is the potential supplied in the case of the high charge, and V L is the potential applied in the case of the low charge. It should be noted that the potential of the line 255 in a period during which data is not read, to a potential which in the case where the transistor 1281 is a p-channel transistor, is higher than V H , and is set to a potential which, in the case where the transistor 1281 is an n-channel transistor, is lower than V L .

[0593] For example, in the case where the transistor 1281 is a p-channel transistor, V R at -2 V if V th of transistor 1281 is -2 V, V H is at 1 V and V L is at -1 V. When the potential applied to node 256 is written at V H and V R on the line 255 is applied, V becomes R + V H , d. H. -1 V, on the gate of transistor 1281 created. Because -1 V is higher than V th , the transistor becomes 1281 not switched on. Therefore, the potential of the line becomes 252 not changed. When the potential applied to node 256 is written at V L and V R on the line 255 is applied, V becomes R + V L , d. H. -3 V, on the gate of transistor 1281 created. Because -3 V is lower than V th , the transistor becomes 1281 switched on. Therefore, the potential of the line becomes 252 changed.

[0594] In the case where the transistor 1281 is an n-channel transistor, V R at -2 V if V th of transistor 1281 is -2 V, V H is 1 V and V L is at -1 V. When the potential applied to node 256 is written at V H and V R on the line 255 is applied, V R + V H , d. H. 3 V, to the gate of transistor 1281 created. Because 3 V higher than V th the transistor becomes 1281 switched on. Therefore, the potential of the line becomes 252 changed. When the potential applied to node 256 is written, at V L and V R on the line 255 is applied, V R + V L , d. H. 1 V, to the gate of transistor 1281 created. Because 1 V is lower than V th , the transistor becomes 1281 not switched on. Therefore, the potential of the line becomes 252 not changed.

[0595] By the potential of the line 252 is determined, data stored at the node 256 are held.

[0596] The semiconductor device in Fig. 47B is different from the semiconductor device in Fig. 47A in that transistor 1281 is not provided. In this case, too, data can be entered in a manner similar to the semiconductor device in Fig. 47A can be written and held.

[0597] It becomes reading of data in the semiconductor device in Fig. 47B. If the line 254 a potential at which the transistor 289 is switched on, the line 253 , which is in a floating state, and the capacitor 257 connected to each other, and the charge is between the line 253 and the capacitor 257 redistributed. As a result, the potential of the line becomes 253 changed. The amount of change in the potential of the line 253 varies depending on the potential of the node 256 (or the charge accumulated on node 256).

[0598] The potential of the line 253 after the charge has been redistributed, for example (C B × V B0 + C × V) / (C B + C), where V is the potential of the node 256 represents, C is the capacitance of the capacitor 257 represents C B the capacitance component of the line 253 represents and V B0 the potential of the line 253 before the charge is redistributed. It can thus be determined that, assuming that the memory cell is in one of the two states in which the potential of the node 256 at V 1 and V 0 (V 1> V 0) Is the potential of the line 253 in the case where the potential V 1 (= (C B × V B0 + C × V 1) / (C B + C)) is higher than the potential of the line 253 in the case where the potential V 0 (= (C B × V B0 + C × V 0) / (C B + C)).

[0599] Then, by changing the potential of the line 253 is compared with a predetermined potential, data is read.

[0600] With a transistor using an oxide semiconductor and having a very low reverse current, the memory device described above can hold stored data for a long time. In other words, the power consumption of the semiconductor device can be reduced because a refresh operation becomes unnecessary or the frequency of the refresh operations can be very low. Further, stored data can be held for a long time even when no power is supplied (it should be noted that a potential is preferably fixed).

[0601] The memory device does not need a high voltage to write data, and deterioration of elements is less likely to occur. In contrast to a conventional non-volatile memory, it is not necessary, for example, to inject electrons into a floating gate and to extract them from it; therefore, there arises a problem such as B. a deterioration of an isolator does not occur. That is, the memory device of one embodiment of the present invention has no limitation on the number of times data can be overwritten, which is a problem in a conventional nonvolatile memory, and its reliability is greatly improved. Furthermore, data is written according to the on / off state of the transistor, whereby high-speed operation can be achieved. <CPU>

[0602] Next, an example of a CPU including any of the above-described transistors will be described. Fig. 48 is a block diagram illustrating a structural example of a CPU that includes any of the above-described transistors as a component.

[0603] The one in Fig. 48 includes 1190 over a substrate. an arithmetic logic unit (ALU) 1191 , an ALU control 1192 , an instruction decoder 1193 , an interrupt controller 1194 , a timing controller 1195 , a register 1196 , a register control 1197 , a bus interface (Bus I / F) 1198 , a rewritable ROM 1199 and a ROM interface (ROM I / F) 1189 . A semiconductor substrate, an SOI substrate, a glass substrate, or the like is used as the substrate 1190 used. The ROM 1199 and the ROM interface 1189 can be provided via a separate chip. As need not be mentioned separately, the CPU is in Fig. 48 is just an example in which the structure is simplified, and an actual CPU may have a variety of configurations depending on the application. The CPU can have the following configuration, for example: a structure with the CPU, as in Fig. 48 or an arithmetic circuit are regarded as the core; a plurality of the cores are included; and the cores work in parallel. The number of bits that the CPU can process in an internal arithmetic circuit or in a data bus can, for example, be 8 , 16 , 32 or 64 be.

[0604] A command that is sent to the CPU via the bus interface 1198 is entered, the command decoder 1193 entered and decoded in it, and then in the ALU control 1192 , the interrupt controller 1194 , the register control 1197 and the timing 1195 entered.

[0605] The ALU control 1192 , the interrupt control 1194 , the register control 1197 and the timing 1195 perform various controls according to the decoded command. In particular, the ALU control generates 1192 Signals to control the operation of the ALU 1191 . While the CPU is executing a program, the interrupt controller processes 1194 an interrupt request from an external input / output device or a peripheral circuit based on its priority or a mask state. The register control 1197 generates an address of the register 1196 and reads / writes data from / to register 1196 according to the state of the CPU.

[0606] The time control 1195 generates signals to control the operation time of the ALU 1191 , the ALU control 1192 , of the command decoder 1193 , the interrupt controller 1194 and the register control 1197 . The time control 1195 includes, for example, an internal clock generator for generating an internal clock signal on the basis of a reference clock signal and supplies the internal clock signal to the above-mentioned circuits.

[0607] With the in Fig. 48 is a memory cell in the register 1196 provided. For the memory cell of the register 1196 Any of the transistors described above, the memory device described above, or the like can be used.

[0608] With the in Fig. 48 selects register control 1197 executes an operation in which data according to a command of ALU 1191 in the register 1196 being held. That is, the register control 1197 selects whether data from a flip-flop or a capacitor is held in the memory cell stored in the register 1196 is included. If the data storage is selected by the flip-flop, a storage element in the register 1196 a power supply voltage is supplied. When data retention by the capacitor is selected, the data in the capacitor is overwritten and the supply of a power supply voltage to the memory cell in the register 1196 to be interrupted.

[0609] Fig. 49 is an example of a circuit diagram of a memory element to be used as register 1196 can be used. A storage element 1730 includes a circuit 1701 , in which the stored data are volatile when the power supply is interrupted, a circuit 1702 , in which the stored data is non-volatile even if the power supply is interrupted, a switch 1703 , a switch 1704 , a logical element 1706 , a capacitor 1707 and a circuit 1720 that has a selection function. The circuit 1702 includes a capacitor 1708 , a transistor 1709 and a transistor 1710 . It should be noted that the memory element 1730 if necessary, another element, such as. B. a diode, a resistor or an inductor.

[0610] Here, the memory device described above can be used as a circuit 1702 be used. When the supply of a power supply voltage to the memory element 1730 is interrupted, a ground potential (0 V) or a potential at which the transistor 1709 in the circuit 1702 is turned off, continues into a gate of transistor 1709 entered. For example, the gate of transistor 1709 over a load, such as B. a resistor, grounded.

[0611] Here, an example is described in which the switch 1703 around a transistor 1713 with one conductivity type (e.g. an n-channel transistor) and with the switch 1704 around a transistor 1714 with a conductivity type that is the opposite of one conductivity type (e.g. a p-channel transistor). A first connection of the switch 1703 corresponds to a connection of the source and drain of the transistor 1713 , a second connection of the switch 1703 corresponds to the other connection of source and drain of transistor 1713 , and conducting or not conducting between the first terminal and the second terminal of the switch 1703 (i.e., the on / off state of the transistor 1713) is selected by a control signal RD inputted into a gate of the transistor 1713 is entered. A first connection of the switch 1704 corresponds to a connection of the source and drain of the transistor 1714 , a second connection of the switch 1704 corresponds to the other connection of source and drain of transistor 1714 , and conducting or not conducting between the first terminal and the second terminal of the switch 1704 (i.e., the on / off state of the transistor 1714) is selected by the control signal RD inputted into a gate of the transistor 1714 is entered.

[0612] A connection of the source and drain of transistor 1709 is electrical with one of a pair of electrodes of the capacitor 1708 and a gate of transistor 1710 connected. The connection section is referred to here as node M2. A connection of the source and drain of transistor 1710 is electrically connected to a line capable of supplying a low power supply potential (e.g., a GND line), and the other terminal is electrically connected to the first terminal of the switch 1703 (one terminal of the source and drain of the transistor 1713). The second connection of the switch 1703 (the other connection of the source and drain of the transistor 1713) is electrical with the first connection of the switch 1704 (one terminal of the source and drain of the transistor 1714). The second connection of the switch 1704 (the other terminal of the source and drain of the transistor 1714) is electrically connected to a line which can supply a power supply potential VDD. The second connection of the switch 1703 (the other connection of the source and drain of the transistor 1713), the first connection of the switch 1704 (the one terminal of the source and drain of the transistor 1714), one input terminal of the logic element 1706 and one of a pair of electrodes of the capacitor 1707 are electrically connected to each other. The connection section is shown here as node M1 designated. The other electrode of the pair of electrodes of the capacitor 1707 can be supplied with a constant potential. For example, the other electrode of the pair of electrodes of the capacitor 1707 be supplied with a low power supply potential (e.g. GND) or a high power supply potential (e.g. VDD). The other electrode of the pair of electrodes of the capacitor 1707 is electrically connected to the line which can supply a low power supply potential (e.g. a GND line). The other electrode of the pair of electrodes of the capacitor 1708 can be supplied with a constant potential. For example, the other electrode of the pair of electrodes of the capacitor 1708 be supplied with a low power supply potential (e.g. GND) or a high power supply potential (e.g. VDD). The other electrode of the pair of electrodes of the capacitor 1708 is electrically connected to the line which can supply a low power supply potential (e.g. a GND line).

[0613] The capacitor 1707 and the capacitor 1708 need not necessarily be provided as long as the parasitic capacitance of the transistor, the line or the like is actively used.

[0614] A control signal WE is fed into the gate electrode of transistor 1709 entered. Both with the switch 1703 as well as the switch 1704 a conductive state or a non-conductive state between the first terminal and the second terminal is selected by the control signal RD, which is different from the control signal WE. When the first connection and the second connection of one of the switches are in the conductive state, the first connection and the second connection of the other switch are in the non-conductive state.

[0615] A signal that corresponds to the circuit 1701 corresponding to the data held is transferred to the other terminal of the source and drain of transistor 1709 entered. Fig. 49 shows an example in which a signal derived from the circuit 1701 is output to the other terminal of the source and drain of transistor 1709 is entered. The logical value of a signal that comes from the second connection of the switch 1703 (the other terminal of the source and drain of the transistor 1713) is output by the logic element 1706 inverted, and the inverted signal is output via the circuit 1720 into the circuit 1701 entered.

[0616] In the example in Fig. 49 becomes a signal that comes from the second terminal of switch 1703 (the other connection of the source and drain of the transistor 1713) is output via the logic element 1706 and the circuit 1720 into the circuit 1701 entered; however, an embodiment of the present invention is not limited thereto. The signal from the second connection of the switch 1703 (the other terminal of the source and drain of transistor 1713) can be output to the circuit 1701 can be entered without its logical value being inverted. For example, in the case where the circuit 1701 includes a node at which a signal obtained by inversion of the logical va...

Claims

[1] Semiconductor device comprising a transistor, wherein the transistor comprises: an oxide semiconductor film over a substrate; a gate insulating layer over the oxide semiconductor film; and a gate electrode above the gate insulating layer, wherein the gate insulating layer comprises a silicon oxynitride film, and where, when the gate insulating layer is analyzed by thermal desorption spectroscopy, the highest peak of a quantity of emitted gas with a mass-to-charge ratio M / z of 32 is observed at a substrate temperature higher than or equal to 150 °C and lower than or equal to 350 °C. [2] Semiconductor device according to claim 1, wherein the emitted gas with a mass-to-charge ratio M / z of 32 corresponds to one oxygen molecule. [3] Semiconductor device according to claim 1, wherein the thermal desorption spectroscopy is carried out in a substrate temperature range of higher than or equal to 80 °C and lower than or equal to 500 °C. [4] Semiconductor device according to claim 1, wherein the oxide semiconductor film comprises In, M and Zn, wherein M is Al, Ga, Y or Sn. [5] Semiconductor device according to claim 1, wherein the oxide semiconductor film comprises a crystal portion, and where the crystal part has an orientation with respect to the c-axis. [6] Display device comprising the semiconductor device according to claim 1. [7] Display module, which includes: the display device according to claim 6; and a touch sensor. [8] Electronic device comprising: the display device according to claim 6; and a control button and / or a battery. [9] Manufacturing process of a semiconductor device comprising the following steps: Formation of an oxide semiconductor film over a substrate; Forming a gate insulating layer comprising at least one silicon oxynitride film over the oxide semiconductor film; Formation of a gate electrode above the gate insulating layer; Performing an oxygen plasma treatment on the gate insulating layer; and Performing a heat treatment at a temperature higher than or equal to 150 °C and lower than or equal to 450 °C after the formation of the gate electrode, causing oxygen in the gate insulating layer to diffuse into the oxide semiconductor film and reducing the conductivity of the oxide semiconductor film. [10] Manufacturing method of a semiconductor device according to claim 9, wherein the silicon oxynitride film is formed by a plasma CVD process at a substrate temperature of less than or equal to 350 °C. [11] Manufacturing method of a semiconductor device according to claim 9, wherein the oxygen plasma treatment is carried out at a substrate temperature of less than or equal to 350 °C. [12] Manufacturing process of a semiconductor device comprising the following steps: Formation of an oxide semiconductor film over a substrate; Forming a gate insulating layer comprising at least one silicon oxynitride film over the oxide semiconductor film; Deposition of a layer comprising an oxide semiconductor onto the gate insulating layer in an atmosphere comprising oxygen by a sputtering process, thereby adding oxygen to the gate insulating layer; Forming a gate electrode by etching the layer comprising the oxide semiconductor; and Performing a heat treatment at a temperature higher than or equal to 150 °C and lower than or equal to 450 °C, causing oxygen in the gate insulating layer to diffuse into the oxide semiconductor film and reducing the conductivity of the oxide semiconductor film. [13] Manufacturing method of a semiconductor device according to claim 12, wherein the silicon oxynitride film is formed by a plasma CVD process at a substrate temperature of less than or equal to 350 °C.