An electrical connecting bridge and a precursor thereto, a packing substrate assembly and an electronic device packaging comprising an electrical connecting bridge, a computing system and a system comprising this, as well as a method for producing a via and a method for producing an electrical connecting bridge comprising this and an electrical connecting bridge produced therether.

Abstract

Electrical connecting bridge (230), comprising: a shaped bridge substrate (231) comprising a molding compound material; a plurality of conductor layers (232a-d) within the bridge substrate (231), each conductor layer having a plurality of fine and closely spaced (FLS) conductor tracks (234a-f), and a via (235a-d) extending through the bridge substrate (231) and electrically connecting at least one of the FLS conductor tracks (234a-f) in one of the conductor path layers (232a-d) with at least one of the FLS conductor tracks (234a-f) in another of the conductor path layers (232a-d), wherein the coefficient of thermal expansion of the material of the conduction path layers (232a-d) is 7 to 50 ppm per degree Celsius.

Description

Technical area

[0001] Embodiments described herein relate generally to electronic device packages and, more particularly, to interconnect bridges of package substrates. background

[0002] High-bandwidth interconnects in a single package are increasingly important for high-performance computing. The embedded multi-die interconnect bridge (EMIB) from Intel ®pioneered and developed represents a breakthrough that addresses this need and facilitates a cheaper and simpler 2.5D packaging approach for very high-density connections between heterogeneous dies of a single package. Instead of an expensive silicon interposer with through-silicon vias (TSVs), a typical EMIB comprises a small silicon bridge chip embedded in the package substrate, enabling high-density connections between dies only where needed, such as with fine line and spaced (FLS) traces. Standard flip-chip assembly is used for robust power delivery and to connect high-speed signals directly from a die to a package substrate. The EMIB eliminates the need for TSVs and specialized interposer silicon, which increase complexity and cost.

[0003] US 2014 / 0 174 807 A1 discloses an organic interconnect bridge. The interconnect bridge comprises a plurality of layers. The layers include various routing layers embedded in a dielectric layer. A metal layer forms a bottom surface of the interconnect bridge. The metal layer is attached to a substrate by means of an adhesive layer.

[0004] US 2013 / 0 168 854 A1 discloses a semiconductor package comprising a first active die and a second active die. The two dies are connected by a bridge. The bridge comprises a plurality of conductive traces embedded in a dielectric material.

[0005] EP 1 780 790 A2 discloses a method for producing a via. The via is formed on a conductive element using spacers. The spacers are surrounded by a molding material. Furthermore, the spacers are removed by an etching process, allowing the via to be produced.

[0006] US 2003 / 0 186 536 A1 discloses a method for forming a via for an integrated circuit. The via is formed using a pillar. The pillar serves as sacrificial material for contacting two leads. The pillar is then removed by an etching process. Short description of the drawings

[0007] The features and advantages of the invention will become apparent from the detailed description below when taken in conjunction with the accompanying drawings, which together illustrate, by way of example, various embodiments. Fig. 1 illustrates a schematic cross-section of an electronic device package according to an example; Fig. 2 illustrates a schematic cross-section of an electronic interconnect bridge according to an example; Fig. 3 illustrates dimensions of traces, vias, and via pad dimensions according to an example; Fig. 4A illustrates patterning conductive elements of an interconnect bridge using dry film photoresist (DFR) lamination according to one example of a method for fabricating an electrical interconnect bridge; Fig. 4B illustrates the construction of conductive elements of a connecting bridge according to an example of a method for manufacturing an electrical connecting bridge; Fig.4C illustrates the removal of the DFR lamination according to an example method for manufacturing an electrical interconnect bridge; Fig. 4D illustrates the formation of a spacer on a conductive element according to an example method for manufacturing an electrical interconnect bridge; Fig. 4E illustrates depositing a material at least partially around the lateral sides of a spacer according to an example method of fabricating an electrical interconnect bridge; Fig. 4F illustrates the removal of a spacer to form an opening in the material connecting to the conductive element according to an example method of making an electrical interconnect bridge; Fig.4G illustrates depositing conductive material in the opening to form a via according to an example method for fabricating an electrical interconnect bridge; Fig. 4H illustrates patterning conductive elements on a conductive layer of an interconnect bridge using a dry film photoresist (DFR) lamination according to one example of a method for fabricating an electrical interconnect bridge; Fig. 4I illustrates the construction of conductive elements on a conductive layer of an interconnect bridge according to an example method of manufacturing an electrical interconnect bridge; Fig. 4J illustrates the removal of the DFR lamination according to an example method for manufacturing an electrical interconnect bridge; Fig.4K illustrates the removal of excess conductive material from a conductive layer according to an example method for fabricating an electrical interconnect bridge; Fig. 5 illustrates molded material around a spacer according to an example method of manufacturing an electrical interconnect bridge; Fig. 6 illustrates an electrical interconnect bridge having multiple conductive layers of conductive elements connected by vias, arranged on a carrier according to an example of a method for manufacturing an electrical interconnect bridge; Fig. 7 illustrates the removal of the carrier to form an electrical connection bridge according to an example of a method for manufacturing an electrical connection bridge; Fig.8A illustrates a plurality of electrical connecting bridges arranged on a carrier according to an example of a method for manufacturing an electrical connecting bridge; Fig. 8B illustrates encapsulation material disposed over a plurality of electrical interconnect bridges according to an example method of fabricating an electrical interconnect bridge; Fig. 8C illustrates the singulation and removal of a plurality of electrical connecting bridges with encapsulation material from a carrier according to an example of a method for producing an electrical connecting bridge; and Fig. Figure 9 is a schematic illustration of an example computing system.

[0008] Reference will now be made to the illustrated embodiments, and specific language will be used herein to describe them. It should be understood, however, that no limitation of the scope or specific embodiments of the invention is intended thereby. Description of the embodiments

[0009] Before embodiments of the invention are disclosed and described, it is to be understood that no limitation to the specific structures, process steps, or materials disclosed herein is intended, but equivalents thereof are also included as would be recognized by one of ordinary skill in the art. It is also to be understood that the terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting. The same reference numerals in the various drawings represent the same element. Numbers provided in flowcharts and processes are provided for clarity in illustrating steps and operations and do not necessarily indicate a particular order or sequence.Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

[0010] As used in this written description, the singular forms "a" and "the" expressly support plural references unless the context clearly indicates otherwise. Thus, for example, reference to "a layer" includes a plurality of such layers.

[0011] In this application, "comprises," "comprising," "including," "having," and the like may have the meanings ascribed to them under U.S. patent law, and may mean "comprise," "having," and the like, and are generally construed as open-ended terms. The terms "consisting of" or "consists of" are closed-ended terms and include only the components, structures, or the like specifically listed in connection with such terms, as contemplated by U.S. patent law. "Consisting essentially of" or "consisting essentially of" have the meanings generally ascribed to them under U.S. patent law.In particular, such expressions are generally closed expressions, except for the permissibility of including additional details, materials, components, steps, or elements that do not materially affect the basic and novel characteristics or function of the article(s) used in connection with it. For example, conductive trace elements present in a composition but not affecting the essence or characteristics of the composition would be permissible if they were present according to the phrase "consisting essentially of," even if they are not necessarily explicitly mentioned in a list of items following such terminology.When using an open expression in the written description such as "comprising" or "having", it is understood that the expression "consisting essentially of" and the expression "consisting of" are also directly supported as if they were expressly mentioned, and vice versa.

[0012] The terms "first," "second," "third," and the like, when used in the specification and claims, are intended to distinguish between similar elements and not necessarily to describe a particular sequential or chronological order. It is understood that the terms so used are interchangeable under appropriate circumstances, so that, for example, the embodiments described herein are capable of operating in sequences other than those illustrated or otherwise described herein.Likewise, if a method is described herein as comprising a series of steps, the order presented herein is not necessarily the only order in which such steps may be performed, and certain of the recited steps may be omitted and / or certain other steps not described herein may be added to the method.

[0013] The terms "left," "right," "front," "rear," "top," "bottom," "above," "below," and the like in the specification and claims, where used, are used for descriptive purposes and not necessarily to describe permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances, so that, for example, the embodiments described herein are capable of operation in orientations other than those illustrated or otherwise described herein. The term "connected," as used herein, is defined as directly or indirectly connected in an electrical or non-electrical manner. Objects described herein as being "adjacent" to one another may be in physical contact with one another, in close proximity to one another, or in the same general region or area, as appropriate for the context in which the phrase is used.Occurrences of the phrase "in one embodiment" or "in one aspect" herein do not necessarily refer to the same embodiment or aspect.

[0014] As used herein, the term "substantially" refers to the complete or almost complete extent or degree of an action, feature, characteristic, condition, structure, thing, or result. For example, an object that is "substantially" enclosed would mean that the object is either completely enclosed or almost completely enclosed. The exact permissible degree of departure from absolute completeness may, in some cases, depend on the specific context. However, generally speaking, almost completeness will be such that it has the same overall result as if absolute and total completeness had been achieved.The use of "essentially" is equally applicable when used with a negative connotation to denote the complete or almost complete lack of an action, characteristic, property, condition, structure, thing, or result. For example, a composition that is "essentially" free of particles would either be completely lacking in particles or almost completely lacking in particles, so that the effect would be the same as if it were completely lacking in particles. In other words, a composition that is "essentially free of" an ingredient or element may nevertheless actually contain such a thing, as long as there is no measurable effect from it.

[0015] As used herein, the term "approximately" is used to provide flexibility to an endpoint of a numerical range by implying that a specified value may be "slightly above" or "slightly below" the endpoint.

[0016] As used herein, a plurality of items, structural elements, compositional elements, and / or materials may be presented in a common listing for convenience. However, such listings should be construed as if each item of the listing is individually identified as a separate and distinct item. Thus, no individual item of such a listing should be construed as a de facto equivalent of any other item of the same listing solely based on their presentation in a common group without indication to the contrary.

[0017] Concentrations, amounts, sizes, and other numerical data may be expressed or presented herein in a range format. It is understood that such a range format is used only for convenience and brevity and thus is to be flexibly interpreted to include not only the numerical values ​​expressly stated as range limits, but also all individual numerical values ​​and subranges that lie within that range, as if each numerical value and subrange were expressly stated. By way of illustration, a numerical range of "about 1 to about 5" is to be interpreted to include not only the expressly stated values ​​from about 1 to about 5, but also to include individual values ​​and subranges within the stated range. Thus, included within this numerical range are individual values ​​such as 2, 3, and 4, and subranges such as 1-3, 2-4, and 3-5, etc., as well as 1, 2, 3, 4, and 5 individually.

[0018] This same principle applies to ranges where only a numerical value is specified as a minimum or maximum. Furthermore, such an interpretation is intended to apply regardless of the width of the range or the properties described.

[0019] A reference in this specification to "an example" means that a particular feature, structure, function, or characteristic described in connection with the example is present in at least one embodiment. Thus, references to "an example" in various places in the specification may not necessarily all refer to the same embodiment.

[0020] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in this description, such as layout examples, spacing, mesh examples, etc. However, one skilled in the art will recognize that many variations are possible without one or more of the specific details, or with different methods, components, layouts, dimensions, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail, but are still considered within the scope of the disclosure. Exemplary embodiments

[0021] An initial overview of embodiments of the technology is provided below, and specific embodiments of the technology are then described in more detail. This initial summary is intended to enable readers to more quickly understand the technology, but is not intended to identify primary or essential features of the technology, nor is it intended to limit the scope of the claimed subject matter.

[0022] Although a typical EMIB offers significant advantages and cost benefits over other solutions available for die interconnects, such as a silicon interposer or high-density substrate surface layers, a typical EMIB has some disadvantages. For example, a typical EMIB bridge is constructed of silicon and is manufactured using a costly manufacturing process. Also, the silicon material has a low coefficient of thermal expansion (CTE) compared to the dielectric material structure of packaging substrates into which the silicon is embedded. As a result, a typical EMIB suffers from thermomechanical problems such as stresses, warpage, etc. due to the different thermal expansions of the materials involved.

[0023] Accordingly, electrical interconnect bridges are disclosed that are formed from inexpensive material that can be constructed using inexpensive techniques, while providing FLS conductive traces on multiple conductive layers. In one aspect, thermomechanical problems may be mitigated to some extent by the electrical interconnect bridges of the present disclosure. In one example, an electrical interconnect bridge according to the present disclosure may include a bridge substrate formed from a molding compound material. The electrical interconnect bridge may also include a plurality of conductive layers within the bridge substrate, each conductive layer including a plurality of FLS conductive traces.Additionally, the electrical interconnect bridge may comprise a via extending through the substrate and electrically connecting at least one of the FLS conductive traces in one of the conductive layers to at least one of the FLS conductive traces in another of the conductive layers.

[0024] With reference to Fig.1 schematically illustrates an exemplary electronic device package 100 in cross-section. The package 100 may include a packaging substrate 110 and a plurality of electronic components 120, 121 mounted on or otherwise connected to the packaging substrate 110. The package 100 may also include an electrical interconnect bridge 130 embedded in the packaging substrate 110, for example, to interconnect the first electronic component 120 and the second electronic component 121 for carrying electrical signals between the electronic components 120, 121. The bridge 130 may generally be referred to as an example of an embedded multi-chip interconnect bridge (EMIB) architecture or assembly. The bridge 130 embedded in the packaging substrate 110 may be a packaging substrate assembly of the electronic device 101.

[0025] The electronic components 120, 121 may be any electronic device or component that may be included in an electronic device package, such as a semiconductor device (e.g., a die, a chip, or a processor). In one embodiment, each of the electronic components 120, 121 may represent a discrete chip. The electronic components 120, 121 may, in some embodiments, be, include, or be a part of a processor, memory, or an application-specific integrated circuit (ASIC). The electronic components 120, 121 may be attached to the packaging substrate 110 according to a variety of suitable configurations, including a flip-chip configuration as shown, or other configurations such as wire bonding and the like.In the flip-chip configuration, the active side of each of the electronic components 120, 121 is attached to a surface of the packaging substrate 110 using interconnect structures 122, such as bumps or pillars. The interconnect structures 122 may be configured to carry electrical signals between the electronic components 120, 121 and the packaging substrate 110. In some embodiments, the interconnect structures 122 may be configured to carry electrical signals, such as, for example, I / O signals and / or power or ground signals related to the operation of the electronic components 120, 121.

[0026] The packaging substrate 110 may include electrical routing features configured to carry electrical signals to or from the electronic components 120, 121. The electrical routing features may be internal and / or external to the bridge 130. For example, in some embodiments, the packaging substrate 110 may include electrical routing features, such as contact pads or traces, configured to receive the interconnect structures 122 and carry electrical signals to or from the electronic components 120, 121. Package-level connections (not shown), such as solder bumps, may be connected to a surface of the packaging substrate 110 to further carry the electrical signals to other electrical devices (e.g., motherboard or other chipset).In some embodiments, the packaging substrate 110 is an epoxy-based laminate substrate with a core and / or buildup layers. The packaging substrate 110 may comprise other suitable types of substrates in other embodiments.

[0027] The bridge 130 may be a dense interconnect structure that provides a routing path for electrical signals. The bridge 130 may include a bridge substrate 131 with electrical routing features formed thereon to provide a chip-to-chip connection between the electronic components 120, 121. The bridge 130 may, in some embodiments, be embedded within a cavity of the packaging substrate 110. The bridge 130 may be consistent with embodiments described herein in connection with other figures. In some embodiments, a portion of the electronic components 120, 121 may overlie the embedded bridge 130, as illustrated.

[0028] The bridge 130 may include electrically conductive contact pads at least partially on or within a top surface of the bridge. The electrically conductive contact pads may comprise a conductive metal, such as copper, gold, silver, aluminum, zinc, nickel, brass, bronze, iron, etc. A dielectric layer may be formed over the bridge 130 and the packaging substrate 110. Conductive vias and solder connections may extend through the dielectric layer. In one aspect, such a dielectric layer may accommodate dimensional variations in the placement of the embedded bridge 130 and electrically isolate connection areas. The dielectric layer may comprise oxide or other materials, such as insulating materials.

[0029] The packaging substrate 110 may be formed from any suitable semiconductor material (e.g., among other substrates, silicon, gallium, indium, germanium, or variations or combinations thereof), one or more insulating layers such as glass-reinforced epoxy such as FR-4, polytetrafluoroethylene (Teflon), cotton paper-reinforced epoxy (CEM-3), phenolic glass (G3), paper phenolic (FR-1 or FR-2), polyester glass (CEM-5), ABF (Ajinomoto Build-up Film), any other dielectric material such as glass, or any combination as may be used in printed circuit boards (PCBs).

[0030] Even if two electronic components 120, 121, which are electrically connected by a single bridge 130, in Fig.1, other embodiments may include any suitable number of electronic components and bridges interconnected in other possible configurations, including three-dimensional configurations. For example, another electronic component mounted on the packaging substrate 110 relative to the components 120, 121 of Fig. 1 extending into and out of the side, may be connected to one or both of the electronic components 120, 121 by means of another bridge.

[0031] Fig. Figure 2 illustrates an electrical connection bridge 230 according to an example of the present disclosure. The bridge 230 may be incorporated into a packaging substrate as described above with reference to Fig.1. The bridge 230 may include a bridge substrate 231 and a plurality of conductive layers 232a-d. The bridge substrate 231 may comprise any suitable material and may be fabricated by any suitable process. As discussed in more detail below, the bridge substrate of one or more of the conductive layers 232a-d may comprise a molding compound material. Fig.2, the bridge substrate of multiple conductive layers comprises the same material (e.g., molding compound), which therefore has the same coefficient of thermal expansion (CTE). In one aspect, all conductive layers of the bridge substrate may comprise the same material and the same CTE. The CTE of the material of conductive layers 232a-d may be from about 7 to about 50 ppm per degree Celsius. In some embodiments, the CTE of the material of conductive layers 232a-d may be from about 7 to about 25 ppm per degree Celsius. The material of the conductive layers may therefore have a CTE higher than that of silicon (about 3 ppm per degree Celsius), which may mitigate the thermomechanical issues to some extent.The bridge substrate 231 may optionally also include an encapsulant material 233 disposed at least partially around each of the conductive layers 232a-d such that the encapsulant material is proximate a portion of a package substrate in which the bridge is disposed, as shown in FIG. Fig. 1. Any suitable encapsulation material may be used and disposed around the bridge substrate in any suitable manner, such as molding an overmold material around the bridge substrate. The encapsulation material may have any CTE.

[0032] Each conductive layer 232a-d may include conductive traces 234a-f to electrically connect electronic components. The bridge 230 is set at 90 degrees with respect to the orientation of the Fig. 1 shown bridge so that the conductor tracks are in Fig.2 extend into and out of the side. One or more vias 235a-d may extend through the bridge substrate 231 and electrically connect one or more of the conductive traces in one conductive layer to one or more conductive traces in another conductive layer. Even if Fig. 2 shows vias electrically connecting traces in four conductive layers, it can be seen that the bridge substrate 231 can have any suitable number of conductive layers with any number of conductive traces, and that any suitable number of vias can be used to electrically connect traces in different conductive layers. Furthermore, the vias can have any shape or configuration, such as a circular and / or non-circular (e.g., rectangular) cross-section.

[0033] Fig.Figure 3 is an example of a top view of contact pads, conductive traces, and vias according to various embodiments. In particular, Fig. 3 illustrates a top view of a conductive layer of a bridge as disclosed herein. The bridge may include a plurality of conductive traces, such as conductive traces 334a-c. In some embodiments, conductive traces 334a-c may be made of copper, while in other embodiments, the conductive traces may be made of another electrically and / or thermally conductive material.

[0034] In some embodiments, some of the conductive traces, such as conductive traces 334a and 334c, may be connected to a contact pad, such as the via contact pad 336a and 336c, respectively. The contact pads 336a, 336c may be constructed from the same or similar materials as the conductive traces 334a-c. For example, the contact pads 336a, 336c may be constructed from copper. In other embodiments, the contact pads 336a, 336c may be constructed from a different material than the conductive traces 334a-c, for example, from a different electrically and / or thermally conductive material.

[0035] As in Fig.3, the contact pads 336a, 336c may have a larger footprint than the conductive traces 334a-c, as discussed below. As discussed herein, "footprint" may generally refer to the lateral size of the element. Likewise, it can be seen that not all conductive traces may be directly connected to a contact pad. For example, it is possible that the conductive trace 334b ​​may not be connected to a contact pad. In some embodiments, the contact pads 336a, 336c may be connected to one or more conductive vias such as the vias 335a and 335c. As shown in Fig.3, the vias 335a, 335c may have a smaller footprint than the contact pads 336a, 336c. That is, the vias 335a, 335c may have a smaller diameter than the contact pads 336a, 336c. The smaller diameter of the via may serve to provide a small manufacturing error tolerance so that if the via is not placed directly in the center of the contact pad, the via may not extend beyond the perimeter of the contact pad. It should be understood that although the traces 334a-c are depicted as generally linear and the contact pads 336a, 336c and the vias 335a, 335c are depicted as generally circular, the traces, contact pads, and / or vias may have a different shape.

[0036] In one aspect, the conductive traces 334a-c may comprise fine and closely spaced (FLS) conductive traces characterized by certain dimensional attributes. Fig. Figure 3 illustrates a variety of dimensions or measurements referred to herein. For example, the distance between the center of contact pads 336a and 336c is a value that is Fig. 2 as an “X”. Likewise, the conductive traces 334a-c may have a width that is Fig. 3 as “Y”. The distance between two elements such as between the contact pads 336a, 336c and the conductive track 334b ​​is a value which is Fig.3 as "Z". The dimension Z is generally referred to herein as trace pitch, which may indicate the space between two elements, such as the space between two traces (e.g., traces 334a and 334b) or the space between a trace and a via pad (e.g., between via pad 336a and trace 334b), as applicable to a particular embodiment or configuration. Reference is made herein to a plurality of traces, such as in the context of a routing layer. Such a plurality of traces includes traces and via pads connected to the traces and arranged in the same routing layer.Thus, a reference to a trace pitch in a plurality of traces includes a reference to the space between two traces and / or the space between a trace and a via pad.

[0037] In general, the values ​​for X, Y, and Z can be specified on the order of micrometers. The values ​​for Y and Z, respectively, can be specified on the order of approximately 10 µm or less. Such FLS traces with a width of approximately 10 µm or less and / or with a spacing of approximately 10 µm or less from each other are referred to herein as 10 / 10 L / S. Smaller values ​​for Y and / or Z may allow the value of X to be reduced. If these smaller values ​​for X, Y, and / or Z can be achieved, significant advantages can be provided. For example, as bridge performance requirements increase, it may be advantageous to provide more I / O ports. A smaller FLS value may allow more traces and / or contact pads to be placed in a bridge routing layer, thereby enabling a higher number of I / O ports without increasing cost or Z height.

[0038] Fig.4A-8C illustrate aspects of an exemplary method for manufacturing an electrical interconnect bridge as disclosed herein. Fig.4A illustrates a process for patterning conductive elements (e.g., traces) of an interconnect bridge using dry film photoresist (DFR) lamination. In this process, a dry film laminate 440 is applied to a conductive (e.g., copper) layer 441 supported by a carrier plate 442. The conductive layer 441 may be included in the carrier plate 442 in the form of a foil, or a seed layer of conductive material may be provided as needed, such as when the foil is insufficient. The film is exposed and developed to provide a pattern of the conductive elements. The pattern may be configured to provide any conductive element configuration or dimension. For example, the pattern may be configured to provide conductive elements with dimensions and pitch characteristics of FLS traces.Using the structure, conductive elements 434a-c can be built up on the conductive layer 441, such as by electrolytic copper plating on the layer, as shown in . Fig. 4B. Once the conductive elements 434a-c are formed, the DFR laminate can be removed or stripped, as shown in Fig. 4C.

[0039] The carrier plate 442 may be referred to as a "peelable core." This carrier plate 442 may have various configurations in different embodiments. In some embodiments, the carrier plate may have two copper layers separated by a weak layer that may allow separation of a fabricated, unsingulated, formed bridge substrate from the carrier. In this case, a copper etching process may be used at the end of the process described below to remove the sacrificial copper layer, i.e., the copper layer that remains adhered to the fabricated, unsingulated, formed bridge substrate after separation of the substrate from the carrier. However, other embodiments may have two dielectric layers, or a dielectric layer and a copper layer, to allow peeling.In embodiments where the sacrificial material after peeling is a dielectric material, a removal process such as wet blasting or other removal process may be used to remove this dielectric material instead of the copper etching process described above. Other types of carriers, such as a releasable tape and a metal carrier, may also be used. In such a case, a metal seed layer, such as copper, may be deposited before proceeding to the subsequent processing steps. Accordingly, a thermal stripping and subsequent tape residue cleaning step may be performed prior to the copper etching, as described in the case of the peelable core.

[0040] Fig. 4D-4G illustrate aspects of a method for forming a via for electrically connecting conductive elements of a bridge as disclosed herein. Fig.4D illustrates the formation of a spacer 450 on a suitable conductive element, such as conductive element 434b, which may be configured as a via pad. As further explained below, spacer 450 is a temporary structure that provides a space or opening for the formation of a via between conductive elements of different conductive layers. A via formed in such a spacer opening has dimensional characteristics and a geometry similar to that of spacer 450. Thus, spacer 450 may have a shape that is circular or non-circular in cross-section (e.g., rectangular), depending on the desired configuration of the via to be formed. Spacer 450 may also have dimensional attributes that reflect the desired dimensional attributes of a via to be formed.

[0041] When manufacturing contact pads and vias, the alignment tolerances between the contact pad and the via may require the contact pads to be sized larger than the process alignment tolerances to ensure that the entire via lands on the contact pad. As a result, the size of the contact pads can be limiting in terms of the number of traces that can be laid out on a given layer. Consequently, improving the alignment capability of the contact pad and via manufacturing process can increase the number of traces in a conductive layer.Typically, the spacer 450 is formed by a technique or process that enables the spacer to have dimensional characteristics and positioning consistent with the FLS traces, such that a via formed in the spacer opening has acceptable alignment with a pad of the trace. The spacer 450 may be formed by any technique or process. In one aspect, the spacer 450 may be formed by curtain coating, spin-coating, printing, dispensing, etc., to deposit material onto the conductive element 434b. For example, in some embodiments, a high-precision inkjet printer may be used to precisely place the spacer 450 in the desired location using device plane alignment, thereby resulting in a tighter tolerance between the via and pad.This tighter tolerance may enable a smaller value of X as described herein. As a result, the underlying pad size may be significantly reduced to enable FLS connections. In other embodiments, the spacer 450 may be curtain coated, exposed, and developed, resulting in a tight tolerance between the via and pad and enabling FLS connection. In some cases, a shape of the spacer 450 may be defined once material is deposited on the conductive element 434b. In such cases, the shape of the spacer 450 may be defined by exposing / defining the shape or structure, dry etching the shape or structure, and / or any other technique or process for defining a shape or structure in a pre-existing or previously deposited spacer material.

[0042] Because the spacer 450 is temporary and subsequently removed as described below, to facilitate the formation of a via, the spacer may be made or constructed from any material that can facilitate the removal of the spacer. For example, the spacer 450 may be made from a sacrificial material that maintains sufficient dimensional stability to facilitate the formation of a via as described herein and also facilitates the removal of the spacer, if desired. In one aspect, the sacrificial material may be thermally decomposable, although any suitable type of sacrificial material may be utilized, such as liquid-soluble materials. Examples of suitable sacrificial materials include, but are not limited to, polynorbornene- and / or polycarbonate-based polymers that decompose when exposed to a relatively high temperature.In some embodiments, such a temperature may be at or above 180 degrees Celsius. In other embodiments, the temperature may be at or above 200 degrees Celsius. In some embodiments, an additional cleaning step may be necessary to remove remnants of the sacrificial element 450 from the via 452.

[0043] In one aspect, Fig. 4D also illustrates an electrical interconnect precursor comprising a conductive trace (e.g., conductive element 434b) with a via pad and a spacer 450 formed from a sacrificial material disposed on the via pad. The illustrated electrical interconnect precursor also includes a support plate 442 supporting the conductive trace.

[0044] In Fig.4E, a material 460 is disposed at least partially around the lateral sides of the spacer 450. The material 460 may form a portion of a bridge substrate conductive layer and therefore may comprise any suitable material for a bridge substrate. The material 460 may be applied around the spacer 450 by any dispensing technique and may be in any suitable shape (e.g., a viscous form, solid particles, a sheet, etc.). The material 460 is then formed around the spacer 450 by any molding technique (e.g., a compression molding process and / or a transfer molding process), and therefore the material 460 may comprise any suitable molding material, such as an epoxy molding compound.

[0045] Compression molding of the material 460 around the spacer 450 may be advantageous, as shown in Fig.5. In this case, the spacer 450, which may be made of a relatively elastic or flexible material (e.g., a polymer), may be axially compression-pressed 461 to some extent and formed flush with the material 460. A mold release material 462 may be used to facilitate the release of the mold material 460 and / or the spacer 450 from a mold component. In addition to the axial compressive forces 461, lateral forces 463 acting from the mold material 460 on the spacer 450 may hold the spacer 450 in place (e.g., little to no movement) during the compression-forming process. Thus, an exposed upper portion of the spacer 450 may become flush with the top surface of the mold material 460 as a result of the compression-forming process, eliminating the need for additional processing (e.g.,Grinding is eliminated to achieve such a relationship, thereby reducing costs and improving yield. Furthermore, since grinding of the molding compound may not be required, the surface of the molding compound may not be inherently damaged, enabling significantly higher reliability and the ability to pattern finer lines and pitches.

[0046] In one aspect, Fig. 4E also illustrates a precursor to an electrical interconnect bridge, in this case further including material 460 (e.g., a molding compound) that is at least partially disposed around the lateral sides of spacer 450. Spacer 450 may be made of a sacrificial material that may facilitate removal of the spacer, leaving an opening in material 460 connecting to a via pad, as discussed below.

[0047] For example, Fig.4F shows the spacer that has been removed to form an opening 452 in the material 460 connecting to the conductive element 434b. The spacer may be removed by any technique or process. As stated above, the spacer may be made of a sacrificial material that may facilitate removal of the spacer through exposure to heat and / or liquid. Therefore, in one aspect, the spacer may be removed by heating the spacer to a temperature sufficient to decompose the sacrificial material (e.g., into a gas) while not adversely affecting the surrounding materials or structures (e.g., melting the material 460). Because the spacer is held in place when the material 460 is disposed around the spacer (e.g.,by compression molding), a narrow profile is created for a via through the opening 452 formed by the removal of the spacer in the material 460, which can facilitate the formation of a via with minimal misalignment to the underlying contact pad.

[0048] With an opening formed in the material 460 by the removal of the spacer, a conductive material (e.g., copper) can be disposed in the opening 452 to form a via 435 as shown in Fig.4G. A conductive material may be disposed in the opening 452 by any suitable technique or process, such as forming a seed layer of the conductive material and / or coating the conductive material. Conductive material may also be disposed on the material 460 to form a thin conductive layer 441' (e.g., a seed layer for forming additional conductive elements).

[0049] Conductive elements (e.g., conductive traces) for the next conductive layer may be formed in any suitable manner, as previously described with reference to Fig. 4A-4C. For example, Fig.4H illustrates a process for patterning conductive elements (e.g., traces) of a connecting bridge using a DFR laminate, in which a dry film laminate 440 is applied to the conductive layer 441' formed on the material 460. The film is exposed and developed to provide a pattern of the conductive elements of the next conductive layer. The pattern may be configured to provide any conductive element configuration or dimension. For example, the pattern may be configured to provide conductive elements with dimensions and spacing characteristics of FLS traces. Using the pattern, conductive elements 434a'-c' may be built up on the conductive layer 441' and the via 435, such as by electrolytic copper plating on the layer, as shown in Fig.4I. In this process, the opening in the material 460 may also be filled with conductive material, further forming the via 435. Once the conductive elements 434a'-c' are formed, the DFR laminate may be stripped, as shown in Fig. 4J. Exposed portions 443a-d of conductive material extending from and between the conductive elements 434a'-c' may be removed or stripped, as shown in Fig. 4K to ensure that there is no unwanted electrical connection between the conductive elements.

[0050] At this point, the Fig. 4D-4G may be repeated to form another via extending to another routing layer, and the process described in Fig.The process described in 4H-4K can be repeated to form conductive elements of the next conductive layer. These processes can be repeated to form any number of vias and conductive layers. Since multiple DFR stripping techniques may not be necessary for each layer, the overall cost and manufacturing complexity of the package can be reduced.

[0051] If no further conductive layers are desired, material (e.g. molding compound) can be applied around the exposed conductive elements (e.g. the Fig. 4K) to cover the conductive elements and form the final bridge substrate conductive layer. The result of this process may be a bridge with multiple conductive layers of FLS conductive traces connected by vias, as shown in Fig.6. The desired CTE for molding materials can be achieved by modifying the molding compound formulations, such as by reducing the filler content and / or modifying the fillers. For example, the table below shows some molding compound formulations that can be used as a bridge substrate. Varying the CTE by the filler content Type molding compound filler CTE (ppm / °C) Granular Epoxyphenol Silicon dioxide 7-24 Fluid Epoxy anhydride Silicon dioxide 7-24 Fluid Epoxidamine Silicon dioxide 7-24 Granular Epoxyphenol Silicon dioxide 7-50 Granular Epoxyphenol aluminum oxide 7-50 Granular Epoxyphenol Organic 7-50

[0052] As in Fig.7, the conductive layer 441 and the substrate or carrier 442 may be removed by any suitable technique or process, such as peeling and / or etching, resulting in a completed bridge 430. In one embodiment noted above, the carrier 442 may include a peelable core that may be peeled at the peelable interface of the peelable core to remove the carrier 442, followed by a copper etch to remove the conductive layer 441. Surface finishing of the contact pads may then be performed, followed by the application of solder bumps (not shown) to complete the bridge. If desired, multiple bridges may be fabricated simultaneously using the processes disclosed herein. If necessary, multiple simultaneously formed bridges may be singulated to form individual bridges.Any suitable technique, including mechanical and chemical techniques, may be used to separate (e.g., split or separate) bridges from one another, such as cutting (e.g., laser), sawing, shearing, milling, broaching, etching, etc.

[0053] In some cases, it may be desirable to have an encapsulation material disposed around at least a portion of the bridge 430, such as portions of the routing layers. Fig. 8A-8C illustrate a process for accomplishing this. For example, Fig. 8A a plurality of bridges 430a-c, which correspond to the bridge 430 of Fig.7 and are arranged on a carrier 470 (e.g., by "pick and place"). The carrier 470 may be of any configuration and made of any type of material (e.g., stainless steel). A release material 471 (e.g., a thermal release tape) may be arranged on the carrier 470 to facilitate the detachment and separation of the finished bridges from the carrier. As shown in Fig. 8B, encapsulation material 433 may be applied over the bridges 430a-c, such as by overmolding. The finished bridges 430a'-c', each with an encapsulation material 433a'-c', may each be singulated and removed from the carrier, as shown in Fig. 8C. The present disclosure therefore provides a bridge that can be manufactured using low-cost substrate packaging formation (e.g., molding) instead of the typical expensive wafer fabrication process.

[0054] Finished bridges can be placed (e.g., "picked and placed") at desired locations on the packaging substrate to provide electrical connections between electronic components. Once placed in or combined with a packaging substrate, typical processing can be performed to prepare the packaging substrate for connection to electronic components.

[0055] Fig.9 illustrates an example computing system 502. The computing system 502 may include an electronic device package 500 disclosed herein connected to a motherboard 580. In one aspect, the computing system 502 may also include a processor 581, a memory device 582, a radio 583, a heat sink 584, a connector 585, a slot, or any other device or component operatively connectable to the motherboard 580. The computing system 502 may include any type of computing system, such as a desktop computer, a laptop computer, a tablet computer, a smartphone, a server, etc. Other embodiments need not include all of the Fig. 9 and may have alternative features specified in Fig. 9 are not specified. Examples

[0056] The following examples are further embodiments.

[0057] In one example, an electrical interconnect bridge is provided comprising a bridge substrate formed from a molding material, a plurality of conductive layers within the bridge substrate, each conductive layer having a plurality of FLS conductive traces, and a via extending through the substrate and connecting at least one of the FLS conductive traces in one of the conductive layers to at least one of the FLS conductive traces in another of the conductive layers.

[0058] In one example of an electrical interconnect bridge, the molding compound material of the bridge substrate of a first conductive layer of the plurality of conductive layers comprises a first molding compound material and the molding compound material of the bridge substrate of a second conductive layer of the plurality of conductive layers comprises a second molding compound material.

[0059] In one example of an electrical interconnect bridge, the bridge substrate of the plurality of conductive layers comprises the same molding material.

[0060] In one example of an electrical interconnect bridge, the molding material comprises epoxy phenol, epoxy anhydride, epoxy amine, or a combination thereof.

[0061] In an example of an electrical interconnect bridge, the first and second plurality of FLS traces have a maximum width of approximately 10 µm.

[0062] In an example of an electrical interconnect bridge, the first plurality of FLS conductor tracks are spaced apart by at most approximately 10 µm.

[0063] In an example of an electrical interconnect bridge, the second plurality of FLS conductor tracks are spaced apart from each other by at most approximately 10 µm.

[0064] In an example of an electrical connecting bridge, the via has a non-circular cross-section.

[0065] In one example of an electrical interconnect bridge, the bridge substrate further comprises an encapsulation material at least partially disposed around each of the plurality of conductive layers.

[0066] In an example of an electrical interconnect bridge, a CTE of the molding material is from approximately 7 to approximately 25 ppm per degree Celsius.

[0067] In one example, an electrical interconnect precursor is provided that includes a conductive trace having a via pad and a spacer formed from a sacrificial material deposited on the via pad.

[0068] In an example of a precursor to an electrical connecting bridge, the conductor track has a maximum width of approximately 10 µm.

[0069] In one example of a precursor to an electrical connecting bridge, the conductive track comprises a plurality of conductive tracks spaced apart by at most approximately 10 µm.

[0070] In one example of a precursor to an electrical interconnect bridge, the sacrificial material is thermally decomposable.

[0071] In one example of an electrical interconnect bridge precursor, the sacrificial material comprises polynorbornene, polycarbonate, or a combination thereof.

[0072] In an example of a precursor to an electrical interconnect bridge, the spacer has a non-circular cross-section.

[0073] In one example of an electrical interconnect bridge precursor, the electrical interconnect bridge precursor comprises a molding material disposed at least partially around the lateral sides of the spacer, wherein the sacrificial material facilitates removal of the spacer such that an opening remains in the molding material in communication with the via pad.

[0074] In one example of an electrical interconnect precursor, the electrical interconnect precursor includes a carrier that supports the conductive trace.

[0075] In one example, a packaging substrate assembly of an electronic device is provided, comprising a packaging substrate, and an electrical interconnect bridge embedded in the packaging substrate and configured to transmit electrical signals between a first electronic component and a second electronic component connected to the packaging substrate, wherein the electrical interconnect bridge comprises a bridge substrate formed from a molding material, wherein a first conductive layer within the bridge substrate comprises a first plurality of FLS conductive traces, a second conductive layer disposed proximate the first conductive layer within the bridge substrate,a second plurality of FLS conductor tracks and a via extending through the bridge substrate and electrically connecting at least one of the first plurality of FLS conductor tracks to at least one of the second plurality of FLS conductor tracks.,

[0076] In one example of a packaging substrate assembly of an electronic device, the molding material of the bridge substrate of the first conductive layer comprises a first molding material and the molding material of the bridge substrate of the second conductive layer comprises a second molding material.

[0077] In one example of a packaging substrate assembly of an electronic device, the bridge substrate of the first and second conductive layers comprises the same molding material.

[0078] In one example of an electronic device package substrate assembly, the molding compound material comprises epoxy phenol, epoxy anhydride, epoxy amine, or a combination thereof.

[0079] In one example of a package substrate assembly of an electronic device, the first and second plurality of FLS traces have a maximum width of approximately 10 µm.

[0080] In an example of a package substrate assembly of an electronic device, the first plurality of FLS traces are spaced apart from each other by at most about 10 µm.

[0081] In an example of a package substrate assembly of an electronic device, the second plurality of FLS traces are spaced apart from each other by at most about 10 µm.

[0082] In one example of a package substrate assembly of an electronic device, the via has a non-circular cross-section.

[0083] In one example of a packaging substrate assembly of an electronic device, the bridge substrate further comprises an encapsulant material disposed at least partially around the first and second conductive layers such that the encapsulant material is proximate a portion of the packaging substrate.

[0084] In an example of a package substrate assembly of an electronic device, a CTE of the molding material is from about 7 to about 25 ppm per degree Celsius.

[0085] In one example, an electronic device package is provided comprising a first electronic component, a second electronic component, a packaging substrate, and an electrical interconnect bridge embedded in the packaging substrate for carrying electrical signals between the first electronic component and the second electronic component connected to the packaging substrate, wherein the electrical interconnect bridge comprises a bridge substrate formed from a molding material, wherein a first conductive layer within the bridge substrate comprises a first plurality of FLS conductive traces, a second conductive layer disposed proximate the first conductive layer within the bridge substrate,a second plurality of FLS conductor tracks and a via extending through the bridge substrate and electrically connecting at least one of the first plurality of FLS conductor tracks to at least one of the second plurality of FLS conductor tracks.,

[0086] In one example of an electronic device package, the molding material of the bridge substrate of the first conductive layer comprises a first molding material and the molding material of the bridge substrate of the second conductive layer comprises a second molding material.

[0087] In one example of an electronic device package, the bridge substrate of the first and second conductive layers comprises the same molding material.

[0088] In one example of an electronic device package, the molding material comprises epoxy phenol, epoxy anhydride, epoxy amine, or a combination thereof.

[0089] In one example of an electronic device package, the first and second plurality of FLS traces have a maximum width of approximately 10 µm.

[0090] In one example of an electronic device package, the first plurality of FLS traces are spaced apart by at most about 10 µm.

[0091] In an example of an electronic device package, the second plurality of FLS traces are spaced apart by at most about 10 µm.

[0092] In an example of an electronic device package, the via has a non-circular cross-section.

[0093] In one example of an electronic device package, the bridge substrate further comprises an encapsulant material disposed at least partially around the first and second conductive layers such that the encapsulant material is proximate a portion of the package substrate.

[0094] In an example of an electronic device package, a CTE of the molding material is from about 7 to about 25 ppm per degree Celsius.

[0095] In one example, a computing system is provided comprising a first motherboard and an electronic device package operatively connected to the motherboard, the electronic device package comprising a first electronic component, a second electronic component, a packaging substrate, and an electrical interconnect bridge embedded in the packaging substrate for carrying electrical signals between the first electronic component and the second electronic component connected to the packaging substrate, the electrical interconnect bridge comprising a bridge substrate formed from a molding material, a first conductive layer within the bridge substrate comprising a first plurality of FLS conductive traces, a second conductive layer disposed proximate the first conductive layer within the bridge substrate,a second plurality of FLS conductor tracks and a via extending through the bridge substrate and connecting at least one of the first plurality of FLS conductor tracks to at least one of the second plurality of FLS conductor tracks.,

[0096] In an example of a computing system, the computing system includes a desktop computer, a laptop, a tablet, a smartphone, a server, or a combination thereof.

[0097] In one example of a computing system, the computing system further includes a processor, a memory device, a heat sink, a radio, a slot, a connector, or a combination thereof operatively connected to the motherboard.

[0098] In one example, a method is provided for forming a via to electrically connect conductive elements, comprising forming a spacer on a conductive element, molding a molding material at least partially around the lateral sides of the spacer, removing the spacer to form an opening in the molding material in connection with the conductive element, and disposing a conductive material in the opening to form a via.

[0099] In one example of a method of forming a via to electrically connect conductive elements, forming a spacer includes disposing a sacrificial material on the conductive element.

[0100] In one example of a method for forming a via to electrically connect conductive elements, the conductive element comprises a via contact pad.

[0101] In one example of a method for forming a via to electrically connect conductive elements, disposing a sacrificial material on the conductive element comprises curtain coating, spin coating, printing, dispensing, or a combination thereof.

[0102] In one example of a method for forming a via to electrically connect conductive elements, the method includes defining a shape of the spacer.

[0103] In an example of a method for forming a via to electrically connect conductive elements, defining a shape includes photodefining the shape, dry etching the shape, or a combination thereof.

[0104] In one example of a method for manufacturing a via, the shape of the spacer has a non-circular cross-section.

[0105] In one example of a method for forming a via to electrically connect conductive elements, forming a molding material around the spacer includes compression molding such that the spacer is flush with the molding material.

[0106] In one example of a method of forming a via to electrically connect conductive elements, the spacer is formed from a sacrificial material, and wherein removing the spacer comprises heating the spacer sufficiently to decompose the sacrificial material.

[0107] In one example of a method for forming a via to electrically connect conductive elements, the sacrificial material comprises polynorbornene, polycarbonate, or a combination thereof.

[0108] In one example of a method of forming a via to electrically connect conductive elements, disposing a conductive material in the opening includes forming a seed layer of the conductive material, coating with the conductive material, or a combination thereof.

[0109] In one example of a method of forming a via to electrically connect conductive elements, the conductive element comprises at least one of a conductive trace and a via pad.

[0110] In one example of a method for producing a via to electrically connect conductive elements, the conductor track has a maximum width of approximately 10 µm.

[0111] In one example of a method for producing a via to electrically connect conductive elements, the conductive track comprises a plurality of conductive tracks spaced apart from each other by at most approximately 10 µm.

[0112] In one example of a method of forming a via to electrically connect conductive elements, the method includes disposing a conductive material on the via to form a second conductive element.

[0113] In one example of a method for forming a via to electrically connect conductive elements, the method includes forming a second spacer on the second conductive element, molding a molding material at least partially around the lateral sides of the second spacer, removing the second spacer to form a second opening in the molding material in connection with the second conductive element, and disposing a conductive material in the second opening to form a second via.

[0114] In one example of a method for forming a via to electrically connect conductive elements, the second conductive element comprises a conductive trace.

[0115] In one example of a method for producing a via to electrically connect conductive elements, the conductor track has a maximum width of approximately 10 µm.

[0116] In one example of a method for producing a via to electrically connect conductive elements, the conductive track comprises a plurality of conductive tracks spaced apart from each other by at most approximately 10 µm.

[0117] In one example, a method of fabricating an electrical interconnect bridge is provided, comprising forming a first conductive element, forming a via as described herein on the first conductive element, and forming a second conductive element on the via.

[0118] In one example, an electrical interconnect bridge is provided which is manufactured by the above method.

[0119] Circuitry used in electronic components or devices (e.g., a die) of an electronic device package may include hardware, firmware, program code, executable code, computer instructions, and / or software. Electronic components and devices may include a non-transitory computer-readable storage medium, which may be a computer-readable medium that does not include a signal. In the case of executing program code on programmable computers, the computing devices recited herein may include a processor, a processor-readable storage medium (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.The volatile and non-volatile memories and / or storage elements may be RAM, EPROM, a flash drive, a solid-state drive, or other medium for storing electronic data. Nodes and wireless devices may also include a transceiver module, a counter module, a processing module, and / or a clock or timer module. One or more programs implementing or utilizing techniques described herein may utilize an application programming interface (API), reusable control elements, and the like. Such programs may be implemented in a high-level procedural or object-oriented programming language to communicate with a computer system. However, the program(s) may be implemented in assembly or machine language, if desired. In any event, the language may be a compiled or interpreted language and may be combined with hardware implementations.

[0120] While the foregoing examples are illustrative of specific embodiments in one or more particular applications, it will be apparent to those skilled in the art that numerous modifications in form, usage, and implementation details may be made without departing from the principles and concepts expressed herein.

Claims

[1] Electrical connecting bridge (230), comprising: a molded bridge substrate (231) comprising a molding material; a plurality of conductive layers (232a-d) within the bridge substrate (231), each conductive layer having a plurality of fine and closely spaced (FLS) conductive traces (234a-f), and a via (235a-d) extending through the bridge substrate (231) and electrically connecting at least one of the FLS conductive traces (234a-f) in one of the conductive layers (232a-d) to at least one of the FLS conductive traces (234a-f) in another of the conductive layers (232a-d), wherein the thermal expansion coefficient of the material of the conductive layers (232a-d) is 7 to 50 ppm per degree Celsius. [2] The electrical interconnect bridge (230) of claim 1, wherein a first conductive layer of the plurality of conductive layers (232a-d) comprises a first molding material and a second conductive layer of the plurality of conductive layers (232a-d) comprises a second molding material. [3] The electrical interconnect bridge (230) of claim 1, wherein the plurality of conductive layers (232a-d) each comprise the same molding material. [4] The electrical interconnect bridge (230) of claim 1, wherein the molding compound material comprises epoxy phenol, epoxy anhydride, epoxy amine, or a combination thereof. [5] The electrical interconnect bridge (230) of claim 1, wherein the first and second plurality of FLS conductive traces (234a-f) have a maximum width of approximately 10 µm. [6] The electrical interconnect bridge (230) of claim 1, wherein the first plurality of FLS conductive traces (234a-f) are spaced apart from each other by at most approximately 10 µm. [7] The electrical interconnect bridge (230) of claim 6, wherein the second plurality of FLS conductive traces (234a-f) are spaced apart from each other by at most approximately 10 µm. [8] Electrical connecting bridge (230) according to claim 1, wherein the via (235a-d) has a non-circular cross-section. [9] The electrical interconnect bridge (230) of claim 1, wherein the bridge substrate (231) further comprises an encapsulation material disposed at least partially around each of the plurality of conductive layers (232a-d). [10] The electrical interconnect bridge (230) of claim 1, wherein a CTE of the molding compound material is from about 7 to about 25 ppm per degree Celsius. [11] Precursor to an electrical connecting bridge, comprising: a conductor track with a via contact island; and a spacer formed from a sacrificial material deposited on the via pad. [12] An electrical connecting bridge precursor according to claim 11, wherein the conductive path has a maximum width of approximately 10 µm. [13] An electrical interconnect precursor according to claim 11, wherein the conductive path comprises a plurality of conductive paths (234a-f) spaced apart from each other by at most approximately 10 µm. [14] An electrical interconnect bridge precursor according to claim 11, wherein the sacrificial material is thermally decomposable. [15] The precursor of an electrical interconnect bridge according to claim 11, wherein the sacrificial material comprises polynorbornene, polycarbonate or a combination thereof. [16] An electrical interconnect bridge precursor according to claim 11, wherein the spacer has a non-circular cross-section. [17] The precursor of an electrical interconnect bridge according to claim 11, further comprising a molding material disposed at least partially around the lateral sides of the spacer, wherein the sacrificial material facilitates removal of the spacer to leave an opening in the molding material in communication with the via pad. [18] An electrical interconnect precursor according to claim 11, further comprising a carrier supporting the conductive trace. [19] A packaging substrate assembly of an electronic device, comprising: a packaging substrate (110); and an electrical connection bridge (230) embedded in the packaging substrate and configured to carry electrical signals between a first electronic component (120) and a second electronic component (121) connected to the packaging substrate (110), the electrical connection bridge (230) comprising: a molded bridge substrate (231) comprising a molding material, a first conductive layer within the bridge substrate (231) having a first plurality of fine and spaced (FLS) conductive traces (234a-f), a second routing layer disposed near the first routing layer within the bridge substrate (231) and having a second plurality of FLS conductive lines (234a-f), and a via (235a-d) extending through the bridge substrate (231) and electrically connecting at least one of the first plurality of FLS conductive traces (234a-f) to at least one of the second plurality of FLS conductive traces (234a-f), wherein a back side of the bridge substrate (231) is directly contacted with the packaging substrate (110). [20] The electronic device packaging substrate assembly of claim 19, wherein the first conductive layer comprises a first molding material and the second conductive layer comprises a second molding material. [21] The electronic device packaging substrate assembly of claim 19, wherein the first and second conductive layers comprise the same molding material. [22] The electronic device packaging substrate assembly of claim 19, wherein the molding compound material comprises epoxy phenol, epoxy anhydride, epoxy amine, or a combination thereof. [23] The electronic device packaging substrate assembly of claim 19, wherein the first and second pluralities of FLS conductive lines (234a-f) have a maximum width of approximately 10 µm. [24] The electronic device packaging substrate assembly of claim 19, wherein the first plurality of FLS traces (234a-f) are spaced apart from each other by at most about 10 µm. [25] The electronic device packaging substrate assembly of claim 24, wherein the second plurality of FLS traces (234a-f) are spaced apart from each other by at most about 10 µm. [26] The electronic device package substrate assembly of claim 19, wherein the via (235a-d) has a non-circular cross-section. [27] The packaging substrate assembly of an electronic device according to claim 19, wherein the bridge substrate (231) further comprises an encapsulant material disposed at least partially around the first and second conductive layers such that the encapsulant material is proximate a portion of the packaging substrate. [28] The electronic device package substrate assembly of claim 19, wherein a CTE of the molding compound material is from about 7 to about 25 ppm per degree Celsius. [29] Electronic device package comprising: a first electronic component; a second electronic component; a packing substrate; and an electrical connection bridge (230) embedded in the packaging substrate for carrying electrical signals between the first electronic component and the second electronic component, the electrical connection bridge (230) comprising: a molded bridge substrate (231) comprising a molding material, a first conductive layer within the bridge substrate (231) having a first plurality of fine and closely spaced (FLS) conductive traces (234a-f), a second routing layer disposed near the first routing layer within the bridge substrate (231) and having a second plurality of FLS conductive lines (234a-f), and a via (235a-d) extending through the bridge substrate (231) and electrically connecting at least one of the first plurality of FLS conductive traces (234a-f) to at least one of the second plurality of FLS conductive traces (234a-f), wherein the bridge substrate (231) is directly contacted with the packaging substrate (110). [30] The electronic device package of claim 29, wherein the first conductive layer comprises a first molding material and the second conductive layer comprises a second molding material. [31] The electronic device package of claim 29, wherein the first and second conductive layers comprise the same molding material. [32] The electronic device package of claim 29, wherein the molding material comprises epoxy phenol, epoxy anhydride, epoxy amine, or a combination thereof. [33] The electronic device package of claim 29, wherein the first and second pluralities of FLS traces (234a-f) have a maximum width of approximately 10 µm. [34] The electronic device package of claim 29, wherein the first plurality of FLS traces (234a-f) are spaced apart from each other by at most about 10 µm. [35] The electronic device package of claim 34, wherein the second plurality of FLS traces (234a-f) are spaced apart by at most about 10 µm. [36] The electronic device package of claim 29, wherein the via (235a-d) has a non-circular cross-section. [37] The electronic device package of claim 29, wherein the bridge substrate (231) further comprises an encapsulant material disposed at least partially around the first and second conductive layers such that the encapsulant material is proximate a portion of the package substrate. [38] The electronic device package of claim 29, wherein a CTE of the molding material is from about 7 to about 25 ppm per degree Celsius. [39] Computing system comprising: a motherboard; and an electronic device package according to any one of claims 29-38, operatively connected to the motherboard. [40] The system of claim 39, wherein the computing system comprises a desktop computer, a laptop, a tablet, a smartphone, a server, or a combination thereof. [41] The system of claim 39, further comprising a processor, a memory device, a heat sink, a radio, a slot, a connector, or a combination thereof operatively connected to the motherboard. [42] A method of forming a via for electrically connecting conductive elements, comprising: Forming a spacer on a conductive element; Forming a molding material at least partially around the lateral sides of the spacer; Removing the spacer to form an opening in the mold material in communication with the conductive element; and Arranging a conductive material in the opening to form a via, wherein the spacer is formed from a sacrificial material, and wherein removing the spacer comprises heating the spacer sufficiently to decompose the sacrificial material. [43] The method of claim 42, wherein forming a spacer comprises disposing a sacrificial material on the conductive element. [44] The method of claim 43, wherein the conductive element comprises a via pad. [45] The method of claim 43, wherein disposing a sacrificial material on the conductive element comprises curtain coating, spin coating, printing, dispensing, or a combination thereof. [46] The method of claim 42, further comprising defining a shape of the spacer. [47] The method of claim 46, wherein defining a shape of the spacer comprises photodefining the shape, dry etching the shape, or a combination thereof. [48] ​​The method of claim 46, wherein the shape of the spacer has a non-circular cross-section. [49] The method of claim 42, wherein forming a molding material around the spacer comprises compression molding such that the spacer is flush with the molding material. [50] A method according to any one of claims 42-49, wherein the sacrificial material comprises polynorbornene, polycarbonate or a combination thereof. [51] The method of claim 42, wherein disposing a conductive material in the opening comprises forming a seed layer of the conductive material, coating with the conductive material, or a combination thereof. [52] The method of claim 42, wherein the conductive element comprises at least one of a conductive trace and a via pad. [53] The method of claim 52, wherein the conductor track has a maximum width of approximately 10 µm. [54] The method of claim 52, wherein the conductive path comprises a plurality of conductive paths spaced apart from each other by at most about 10 µm. [55] The method of claim 42, further comprising disposing a conductive material on the via to form a second conductive element. [56] The method of claim 55, further comprising: forming a second spacer on the second conductive element; Forming a molding material at least partially around the lateral sides of the second spacer; Removing the second spacer to form a second opening in the molding material in communication with the second conductive element; and Disposing a conductive material in the second opening to form a second via. [57] The method of claim 55, wherein the second conductive element comprises a conductive trace. [58] The method of claim 57, wherein the conductor track has a maximum width of approximately 10 µm. [59] The method of claim 57, wherein the conductive path comprises a plurality of conductive paths spaced apart from each other by at most about 10 µm. [60] A method for producing an electrical connecting bridge, comprising: forming a first conductive element; Forming a via according to any one of claims 42-59 on the first conductive element; and Forming a second conductive element on the via. [61] An electrical connecting bridge produced by the method of claim 60.

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