Ethernet auto-negotiation with parallel detection for 10G-DAC or other non-automatically negotiated modes

Abstract

Method (100) performed by an Ethernet device (500) comprising a transmitter (516, 517) and a receiver (518, 519), comprising the following steps: Sending (102) autonegotiation (AN) base pages via the sender (516, 517) to an Ethernet link peer (552) to offer that the Ethernet device (500) has the capability to support at least one IEEE (“Institute of Electrical and Electronics Engineers”) 802.3 Ethernet specification that supports an AN; Detect (104) at the receiver (518, 519) using a first detection mode, a valid signal sent by the Ethernet link peer (552) that does not support autonegotiation (AN); and Detect (104) at the receiver (518, 519) using a second detection mode, of AN pages sent by the Ethernet link peer (552) using an Ethernet IEEE-802.3 link specification that supports an AN, wherein the first detection mode includes: Detect (108) whether a signal received at the receiver (518, 519) is a valid signal sent by an Ethernet link peer (552) that does not support AN; in response to the detection (108) that the signal received at the receiver (518, 519) is a valid signal sent by an Ethernet link peer (552) that does not support AN, starting (110) an autonegotiation wait timer; and Detect (112) whether both a single_link_ready state and an autoneg_wait_timer_done state are true, and the Ethernet connection, which does not support AN, is a 10 Gigabit-per-second direct link cable (10G-DAC) connection, further comprising: in response to the detection (112) that both the single link_ready state and the autoneg_wait_timer_done state are true, Disable (114) the AN transmission and switch the transmitter (516, 517) to a 10G-DAC mode.

Description

GENERAL STATE OF THE ART

[0001] As computing has shifted from local resources, such as office or laptop computers, to remotely distributed resources, such as cloud hosting services, data transfer speeds over networks have become increasingly important. Fast network connections are therefore crucial for data centers and high-performance computing (HPC). One of the main network technologies in data centers and HPC environments is high-speed Ethernet.

[0002] The original Ethernet standard was defined in 1983 by the Institute of Electrical and Electronics Engineers (IEEE) 802.3. Since then, most Ethernet standards have been developed and specified under a committee based on IEEE 802.3. The IEEE 802.3 Ethernet standard defines several data rates that can be used when connecting two systems. For backplane and copper cabling media, there is an Autonegotiation (AN) protocol, defined in Clause 73 of the standard (803.2-2012, Section Five), which allows the selection of a port type and other features, such as forward error correction (FEC), based on the capabilities offered by both sides. Network management can be used to program which capabilities are offered for a port and thus control the data rate selected by the AN.For some rates, the AN process includes a link training period, which makes it possible to improve the received signal quality and to work with more demanding media (e.g. longer cables).

[0003] In contrast, the implementation of Ethernet operation over copper cables at 10 gigabits per second (GB / s) outside of IEEE 802.3 was defined in the Small Form Factor (SFF) 8418 committee and referred to as the "Small Form Factor Pluggable" SFP+ direct connection or 10GSFP+Cu, also called 10G direct connection cable or 10G DAC. The form factor and electrical interface for 10G DAC are defined by a multi-source agreement, are widely used in modern data centers, and are expected to continue to see significant use in the future. Unlike the 802.3 standard, 10G DAC does not support autonegotiation or FEC, nor does it support link training.

[0004] US 2002 / 0 046 267 A1 shows physical layer interface circuits with common autonegotiation.

[0005] US 7 720 135 B2 discloses a method and apparatus for negotiating a data transmission mode via a Direct Data Interconnect (DDI) interface.

[0006] WO2016 / 089355 A1 shows a system for autonegotiation via an extended backplane, comprising an enclosure and a switch outside the enclosure.

[0007] The problem stated is solved according to the invention by the features of claim 1. Further embodiments of the invention are described in the dependent claims and the respective subclaims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The foregoing aspects and many of the associated advantages of the present invention will be more readily recognized when they become more readily understood with reference to the following detailed description, when viewed in conjunction with the accompanying drawings, in which the same reference numerals throughout the various views refer to the same parts, unless otherwise indicated. They show: Fig. 1. A flowchart illustrating the processes and logic for an implemented parallel detection of 10G-DAC signals and 10GBASE-KR (and / or other IEEE 802.3 Ethernet standards which support the AN) signals according to an embodiment; Fig.2 a table showing the bits of the Technology Ability Field, which includes an extension of Table 73-4 in Clause 73 to further support the IEEE 802.3 Ethernet standards 25GBASE-KR-S or 25GBASE-CR-S and 25GBASE-KR or 25GBASE-CR; Fig. 3 a diagram showing a connection codeword base page in accordance with Fig. 73-6 from IEEE-802.3-2012 Clause 73; Fig. 4a and Fig. 4b respective sections of an AN arbitration state diagram configured to support parallel detection of IEEE 802.3 Ethernet signals, supporting AN and Ethernet signals in accordance with Ethernet standards that do not support AN, including 10G-DAC, according to one embodiment; and Fig.5 A schematic diagram illustrating an architecture for a network node that uses a network chip configured to implement the prevention of false packet acceptance in accordance with the embodiments disclosed herein. DETAILED DESCRIPTION

[0009] This document describes embodiments of methods and devices for Ethernet autonegotiation with parallel detection for 10G DACs or other non-automatically negotiated modes. Numerous specific details are presented in the following description to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will recognize that the invention can be implemented without one or more of these specific details or using other methods, components, materials, etc. In other cases, well-known structures, materials, or processes are not shown or described in detail so as not to obscure aspects of the invention.

[0010] References to “a single embodiment” or “an embodiment” throughout this description mean that a particular feature, structure, or distinguishing characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Therefore, appearances of the expressions “in a single embodiment” or “in an embodiment” at various points throughout this description do not necessarily all refer to the same embodiment. Furthermore, the particular features, structures, or distinguishing characteristics may be combined arbitrarily in one or more embodiments.

[0011] For the sake of clarity, components in the figures can also be referenced here by their names in the figures instead of by a specific reference symbol. Furthermore, reference symbols that refer to a specific component type (as opposed to a specific component) can be indicated by a reference symbol followed by "(type)", which means "typical". It is understood that the configuration of these components is typical for similar components that may exist but are not shown in the drawings for the sake of simplicity and clarity, or for otherwise similar components that are not designated with separate reference symbols. However, "(type)" should not be interpreted as meaning that the component, element, etc., is typically used for its disclosed function, implementation, purpose, etc.

[0012] Ethernet has defined separate connector types for data rates of 40 GB / s and 100 GB / s for backplane and copper cabling media (for 40G, 40GBASE-KR4, as defined in clause 84 for backplanes, and 40GBASE-CR4, as defined in clause 85 for copper cabling; for 100G, 100GBASE-KR4, as defined in clause 93 for backplanes, and 100GBASE-CR4, as defined in clause 92 for copper cabling). For these transmission rates, capabilities are offered separately by the Ethernet Operator (AN) for each medium. The 802.3by working group also defines new connector types for data rates of 25 GB / s (25GBASE-KR, as defined in clause 111 for backplanes, 25GBASE-CR, as defined in clause 110 for copper cabling). For a transmission rate of 25G, backplanes and copper cables are offered as a single capability.In addition, Ethernet has connection types for backplanes with lower data transmission rates, 10 GB / s (10GBASE-KR) and 1 GB / s (1000BASE-KX), which can also be offered by the AN, but there is no special connection type for copper cables for these transmission rates.

[0013] In backplane systems, autonegotiation can be used to reduce a connection to a lower data rate when needed for various reasons, such as power saving or poor signal or media quality (assuming the partner supports the lower rate). Thus, a port supporting 40GBASE-KR4 can be downgraded to run 10GBASE-KR (using only one of the four lanes), or a port supporting a 25GBASE-KR connection can be downgraded to run 10GBASE-KR or 1000BASE-KX (using lower signal rates). Using autonegotiation provides an interoperable way to downgrade a port and restore the connection to the partner.Currently, however, the 10G-DAC mode cannot be selected for downscaling because it does not include AN, and the capability cannot be offered.

[0014] The 10GBASE-KR port, defined for backplanes, can also operate over copper cabling, providing access, link training, and optional FEC over that medium, and also extending the selection of a down / up mode. However, the problem is that a port using 10GBASE-KR over copper cabling cannot work with a port configured as a 10G DAC. Due to the large installed base of 10G DAC, this can delay the adoption of 10GBASE-KR over copper cabling, thus preventing users from benefiting from the additional capabilities offered by this feature. The current workaround is to program both ends of the link to use 10G DAC instead of Ethernet access. This requires controlling both ends of the link, which is more complex and sometimes impractical.

[0015] The existing AN protocol requires a device to send a specific signal (AN page) from its transmitter while simultaneously searching for a partner sending a similar signal at its receiver. The transmission of AN pages continues until an AN-enabled partner is detected.

[0016] The AN also defines a "parallel detection" mode to interoperate with legacy devices that do not support AN (and therefore do not transmit AN pages) but have a specified signal transmission rate of 1.25 GB / s or 3.125 GB / s (1000BASE-KX or 10GBASE-KX4, respectively). A device performing parallel detection transmits AN pages but, in addition to searching for AN pages, also looks for a valid 1000BASE-KX or 10GBASE-KX4 signal. If either of these signals is detected, the device stops transmitting AN pages and switches directly to the detected mode. The partner (a legacy device that does not use AN) identifies the new mode, which matches its own mode, and a connection is established.

[0017] The embodiments described herein disclose a similar method for "parallel detection" to detect 10G-DAC signaling and thus enable connection and interaction with 10G-DAC devices. The method supports the use of 10GBASE-KR with AN for copper cabling instead of the 10G-DAC mode, thereby enabling link training, optional FEC, and automatic rate adjustments on copper cabling. Furthermore, the embodiments allow for a smooth upgrade of existing networks that may include 10G-DAC connections that cannot be configured as 10GBASE-KR.

[0018] Fig.Figure 1 shows a flowchart 100 that depicts the processes and logic for the implemented parallel detection of 10G-DAC signals and 10GBASE-KR (and / or other IEEE 802.3 Ethernet standards that support the AN) signals according to one embodiment. The process begins in a block 102 where a port sends AN base pages offering 10GBASE-KR. It can also offer other copper cable options (such as, without limitation, 25GBASE-CR, 25GBASE-KR, and 40GBASE-KR).

[0019] Offering is done by setting Technology Ability Field bits, as shown in Table 200. Fig. 2 (which is an extended version of Table 73-4 in Clause 73) and Fig. 3 (which is a copy of Fig. 73-6 in clause 73) is shown. The basic connection codeword (basic page) sent in a DME page transmits the information in Fig.3. Encoding shown. The autonegotiation function supports additional pages using the "Next Page" function. The encoding for the one or more link codewords used in the exchange of next pages is defined in 802.3-2012 clause 73.7.7. In a DME page, D0 is the first transmitted bit. D[4:0] contains the "Selector" field. D[9:5] contains the "Echoed Nonce" field. D[12:10] contains capability bits to offer capabilities unrelated to the PHY. C[1:0] is used to offer a pause capability. The remaining capability bit, C[2], is reserved. D[15:13] contains the RF, Ack, and NP bits. These bits function as specified in 28.2.1.2. D[20:16] contains the "Transmitted Nonce" field. D[45:21] contains the "Technology Ability Field". D[47:46] contains the FEC capability (see clause 73.6.5).

[0020] The Technology Ability Field (A[24:0]) is a 25-bit field containing information specifying the supported technologies for the selector field value when used with backplane Ethernet autonegotiation. These bits are assigned to individual technologies, allowing for multiple options for a single selector field value. The current encoding for the Technology Ability Field for the IEEE 802.3 selector with backplane Ethernet autonegotiation is described in Table 73-4.

[0021] As in Fig. As shown in Figure 2, two additional bits were defined for the "Technology Ability Field". Setting bit A9 allows support for either 25GBASE-KR-S or 25GBASE-CR-S, whereas setting bit A10 allows support for either 25GBASE-KR or 25GBASE-CR.

[0022] Back to Fig.1. The device searches in block 104 at the receiver for AN pages and / or a valid signal of a certain supported Ethernet mode that does not support AN; this is shown in the first section of the AN arbitration state diagram 400 in Fig. 4a is marked with “link_control_[PD]←SCAN_FOR_CARRIER” 402, where “PD” means “Parallel Detection”. It is intended that all modes supported for parallel detection would be enabled (SCAN_FOR_CARRIER). In various embodiments of the parallel detection modes described herein, processing of received signals searching for AN sides or valid signals can be performed concurrently, or can be performed by rapidly switching detection modes, as indicated by the dashed double arrow labeled “Switch” in Fig. 1 shown.

[0023] One embodiment extends the PD modes that are shown in the arbitration state diagram in Fig. 73-11 of Clause 73 are defined to include a 10G DAC detection mode; for the purposes of Clause 73, this would conceptually constitute a new definition of "PD" as set forth below in TABLE 1: TABLE 1 PD Represents all of the following elements that are present: 1000BASE-KD PMD; 10GBASE-KX4 (or 10GBASE-CX4) PMD; and 10G-DAC PMD

[0024] As in Fig. Figure 1 shows the processes for detecting a 10G-DAC and an 802.3 connection peer, respectively, in the left and right sections of flowchart 100, under block 104. As further indicated, these processes are executed in parallel, either simultaneously or by rapidly switching between the detection modes.

[0025] The operations in block 106 and decision block 108 regarding 10G-DAC detection are executed in a loop, searching for a valid signal that includes a 10G-DAC. As shown in section 400 of the arbitration state diagram in Fig.As shown in Figure 4a, the detection of a valid 10G-DAC signal leads to a state `link_state[10G_DAC]=OK`, which also coincides with a YES result for decision block 108. In response, the arbitration state diagram 400 moves to Fig. 4a continues with LINK STATUS CHECK 404, which includes Start autoneg_wait_timer 404, which is also shown in a block 110 in the flowchart 100.

[0026] In decision block 112, it is determined whether both the state `single_link_ready` and `autoneg_wait_time_done` are true, indicating that a valid signal is present during the waiting time defined for the autonegotiation wait time meter. If the answer to decision block 112 is YES, the logic proceeds to block 114, in which transmission from the AN side is deactivated and the transmitter is switched to 10G DAC mode.

[0027] If the answer to either decision block 108 or decision block 112 is NO, the logic loops back to block 106. If the mode detection operations are performed concurrently, the 10G-DAC detection process is repeated continuously. If parallel detection is performed by switching between detection modes, the 10G-DAC detection process can either be repeated back to block 106, or the logic can switch to performing an 802.3AN detection.

[0028] During 802.3 AN detection, the receiver searches for AN pages sent by an IEEE 802.3 link peer supporting 10GBASE-KR or by other high-speed 802.3 Ethernet links implemented over copper cabling that support AN. The process includes operations in blocks 116 and 118, where 802.3 link AN operations are performed in accordance with Arbitration State Diagram 400. In decision block 120, a determination is made as to whether an IEEE 802.3 Ethernet link peer supporting AN is found. If the answer is yes, the logic proceeds to block 122, where an IEEE 802.3 Ethernet link is initialized by completing AN operations, performing link training, and configuring optional FEC support. If simultaneous detection is also performed, the 10G-DAC detection mode will be deactivated.If the answer to decision block 120 is NO, the logic returns in a loop to block 116, after which it either repeats the 802.3-AN detection operations or switches to the 10G-DAC detection operations, depending on whether the parallel detection mode is performed concurrently or alternately.

[0029] It should be noted that the criteria for determining whether a valid 10G-DAC signal has been found depend on the implementation. For example, a receiver might use a frequency lock indicator, a PCS / scrambler lock indicator, a signal quality or eye-opening measurement, or a combination thereof. The receiver may need to be configured differently to detect AN-sides, KX, KX4, and 10G-DAC modes. This can be achieved by having the receiver periodically switch between these modes until a valid signal is detected. Variations of this method are possible and depend on the specific implementation.

[0030] Similar to those previously described for 10G-DAC, other modes can also be added. For example, a device can also be capable of detecting 2.5G Ethernet and 5G Ethernet (currently defined in 802.3cb) in parallel, detect other connection types that do not use autonegotiation, or detect any other signaling method.

[0031] Fig.Figure 5 shows an architecture 500 for a computer node that uses a multimodal network chip 502 configured to implement aspects of the embodiments disclosed herein. The computer node is exemplary of various host platforms in which a multimodal network chip or NIC may be installed. The network chip 502 comprises multimodal PHY circuits 504, including an 802.3 PHY block 506, a 10G DAC PHY block 508, an autonegotiation module 510, mode control logic 512, multiplexing circuits 514, a transmit (Tx) port 516 comprising transmit circuits 517, and a receive (Rx) port 518 comprising receive circuits 519. The transmit and receive circuits can support a single track (x1) or four tracks (x4), which can be reconfigured to function as a single track when connected to a link partner that only supports a single-track Ethernet connection.

[0032] The 802.3 PHY block 506 is an example of a PHY circuit block configured to support one of the high-speed 802.3 Ethernet technologies described here, including 10GBASE-KR4, 25GBASE-KR4, and 40GBASE-KR4. The 802.3 PHY block 506 includes a Physical Coding Sublayer (PCS) module 520, an FEC module 522 which includes an FEC decoder 523, a Physical Media Interface (PMA) module 524, and a Physical Media Dependent (PMD) module 526. The 10G-DAC PHY block 508 is configured to implement the 10G-DAC physical interface circuitry and logic according to SFF-8418. In one embodiment, the 10G-DAC-PHY block 508 is implemented as an application-specific integrated circuit that includes serialization and deserialization circuitry (ASIC / SerDes) as described in SFF-8418. As further illustrated, a PHY block that does not support autonegotiation (i.e.,a non-AN PHY block), instead of the 10G DAC PHY block 508, together with suitable circuitry to implement the associated non-AN Ethernet connection (not shown).

[0033] The network chip 502 further comprises a DMA (Direct Memory Access) interface 528, a PCIe (Peripheral Component Interconnect Express) interface 530, a MAC module 532, and an RS module 534. The computer node 500 also comprises a system-on-a-chip (SoC) 536, which includes a central processing unit (CPU) 538 having one or more processor cores coupled to a memory interface 540 and a PCIe interface 542 via an interconnect 544. The memory interface 540 is further shown coupled to the memory 546.In a typical configuration, the network chip 502, the SoC 536 and the memory 546 are mounted on a circuit board 548, which includes circuitry for communicative coupling of these components, or are otherwise coupled to it in an operational manner, as shown by individual lines connecting the DMA 528 to the memory 546 and the PCIe interface 530 to the PCIe interface 542 at a PCIe connector 550.

[0034] In one embodiment, the MAC module 532 and the RS module 534 are each configured to implement aspects of the MAC layer operations and the matching layer operations as defined for one or more high-speed 802.3 Ethernet links, including 10GBASE-KR4, 25GBASE-KR4, and 40GBASE-KR4. The MAC module 532 is also configured to support MAC layer operations for a 10G DAC link and is configured to switch between one or more 802.3 Ethernet links and the 10G DAC link.

[0035] During connection initialization, the autonegotiation module 510 is implemented for the autonegotiation of the connection speed and capabilities for an 802.3 Ethernet connection. As previously described, the AN format consists of a base page, which is the first set of formatted information exchanged with the connection partner, as represented by a connection partner 522 comprising a receiver port 544 and a transmitter port 556. As shown, the computer node 500 and the connection partner 552 are communicatively connected via an Ethernet link 558, implemented using a copper cable.

[0036] The mode control logic 512 is configured to implement the operations and logic described in the flowchart 100 above. Fig.Figure 1 illustrates this. This includes controlling the multiplex circuits 514, which are used to selectively couple the transmit and receive circuits 517 and 519 with the 802.3 PHY block 506 or the 10G DAC PHY block 508. In one embodiment, the multiplex circuits 514 are configured to couple signals received by the receive circuits 517 to each of the 802.3 PHY block 506 and the 10G DAC PHY block 508 simultaneously.

[0037] In addition to implementing the in Fig.The five circuit components and modules shown in the diagram, which are integrated into a network chip such as a network interface controller (NIC) chip, can be implemented as discrete components mounted on a printed circuit board or similar, or otherwise within a multi-component package. For example, the 802.3 PHY block 506 and the 10G DAC PHY block 508 could be implemented using separate chips. In addition to being implemented in a computer node, a network chip 502, or a chip or multi-component module with similar functionality, can also be implemented in a network switch that includes multiple ports.

[0038] Further aspects of the subject matter described herein are set out in the following numbered paragraphs: [to be added if the claims are approved]

[0039] Furthermore, the embodiments described herein can be implemented not only in a semiconductor chip but also in machine-readable media. For example, the previously described designs can be stored on and / or embedded in machine-readable media linked to a design tool used for designing semiconductor devices. Examples include a netlist formatted in the VHSIC Hardware Description Language (VHDL), Verilog, or SPICE. Some examples of netlists include: a behavior-level netlist, a register-transfer-level (RTL) netlist, a gate-level netlist, and a transistor-level netlist. Machine-readable media also include media containing design information, such as a GDS-II file.Furthermore, netlist files or other machine-readable media can be used to design semiconductor chips in a simulation environment to perform the procedures of the teachings described above.

[0040] Although some embodiments have been described with reference to specific implementations, other implementations are possible according to some embodiments. Furthermore, the arrangement and / or sequence of elements or other features shown in the drawings and / or described herein need not be arranged in the specific manner shown and described. Many other arrangements are possible according to some embodiments.

[0041] In any system shown in a figure, the elements may sometimes have the same reference symbol or a different reference symbol to suggest that the depicted elements could be different and / or similar. However, an element may be flexible enough to have different implementations and to interact with some or all of the systems shown or described here. The various elements shown in the figures may be the same or different. Which of these is designated as the first element and which as the second element is arbitrary.

[0042] The terms "coupled" and "connected," as well as their derivatives, may be used in the description and claims. It is understood that these terms are not synonymous. Rather, in certain embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" can mean that two or more elements are in direct physical or electrical contact. However, "coupled" can also mean that two or more elements are not in direct contact with each other, but nevertheless work together or interact.

[0043] An embodiment is an implementation or example of the inventions. A reference in the description to "an embodiment," "a single embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or distinguishing characteristic described in connection with the embodiments is included in at least some, but not necessarily all, embodiments of the inventions. The various appearances of "an embodiment," "a single embodiment," or "some embodiments" do not necessarily all refer to the same embodiments.

[0044] Not all components, features, structures, distinguishing marks, etc., described and illustrated herein need be included in one or more specific embodiments. For example, if the description states that a component, feature, structure, or distinguishing mark "may" or "could" be included, that specific component, feature, structure, or distinguishing mark need not necessarily be included. If the description or claim refers to "one" element, this does not mean that only a single instance of the element is present. If the description or claims refer to "an additional" element, this does not preclude the existence of more than one instance of the additional element.

[0045] An algorithm is understood here, and generally, as a coherent sequence of steps or operations that lead to a desired result. This includes physical manipulations of physical quantities. Usually, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, or otherwise manipulated. It has sometimes proven practical, mainly for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It is understood, however, that all these and similar terms must be associated with the appropriate physical quantities and are merely practical labels applied to those quantities.

[0046] As previously discussed, various aspects of the embodiments can be enabled by appropriate software and / or firmware components and applications, such as software and / or firmware executed by an embedded processor or the like. Thus, the embodiments of the present invention can be used as, or to support, software programs, software modules, firmware, and / or distributed software that are executed on some form of processor, processing core, or embedded logic of a virtual machine running on a processor or core, or otherwise implemented or configured on or in a computer-readable or machine-readable, non-temporary storage medium.A computer-readable or machine-readable non-temporary storage medium comprises any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a computer-readable or machine-readable non-temporary storage medium includes any mechanism that provides (i.e., stores and / or transmits) information in a form accessible to a computer or calculating machine (e.g., a computing device, an electronic system, etc.), such as writable / non-writable media (e.g., ROM, RAM, magnetic disk storage media, optical storage media, flash storage devices, etc.). The content can be directly executable (as an "object" or in "executable" form), source code, or differential code ("delta" or "patch" code).A computer-readable or machine-readable non-temporary storage medium may also include a storage device or database from which content can be downloaded. The computer-readable or machine-readable non-temporary storage medium may also include a device or product on which content is stored at the time of sale or delivery. Thus, the delivery of a device with stored content or the offering of content for download via a communication medium is to be understood as the provision of a manufactured item that includes a computer-readable or machine-readable non-temporary storage medium with the content described herein.

[0047] Various components described herein, previously referred to as processes, servers, or tools, can serve as a means of executing the described functions. The operations and functions performed by these components can be implemented by software running on a processing element, via embedded hardware or the like, or by any combination of hardware and software. These components can be implemented as software modules, hardware modules, specialized hardware (e.g., application-specific hardware, ASICs, DSPs, etc.), embedded controllers, hard-wired circuits, hardware logic, and so on. Software content (e.g., data, instructions, configuration information, etc.) can be provided via a manufacturing item that includes a computer-readable or machine-readable, non-temporary storage medium providing content that represents instructions for execution.The content may cause a computer to perform various functions / operations described here.

[0048] As used here, a list of items joined by the phrase "at least one of" can mean any combination of the listed items. For example, the phrase "at least one of A, B or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C.

[0049] The above description of embodiments of the invention, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the exact forms disclosed. Although specific embodiments and examples of the invention are described here for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as will be apparent to those skilled in the art.

[0050] These modifications can be made to the invention in light of the detailed description above. The terms used in the following claims are not intended to limit the invention to the specific embodiments disclosed in the description and drawings. Rather, the scope of the invention as a whole is to be determined by the following claims, which are to be interpreted in accordance with the usual principles of claim interpretation.

Claims

[1] Method (100) performed by an Ethernet device (500) comprising a transmitter (516, 517) and a receiver (518, 519), comprising the following steps: Sending (102) autonegotiation (AN) base pages via the sender (516, 517) to an Ethernet link peer (552) to offer that the Ethernet device (500) has the capability to support at least one IEEE (“Institute of Electrical and Electronics Engineers”) 802.3 Ethernet specification that supports an AN; Detect (104) at the receiver (518, 519) using a first detection mode, a valid signal sent by the Ethernet link peer (552) that does not support autonegotiation (AN); and Detect (104) at the receiver (518, 519) using a second detection mode, of AN pages sent by the Ethernet link peer (552) using an Ethernet IEEE-802.3 link specification that supports an AN, wherein the first detection mode includes: Detect (108) whether a signal received at the receiver (518, 519) is a valid signal sent by an Ethernet link peer (552) that does not support AN; in response to the detection (108) that the signal received at the receiver (518, 519) is a valid signal sent by an Ethernet link peer (552) that does not support AN, starting (110) an autonegotiation wait timer; and Detect (112) whether both a single_link_ready state and an autoneg_wait_timer_done state are true, and the Ethernet connection, which does not support AN, is a 10 Gigabit-per-second direct link cable (10G-DAC) connection, further comprising: in response to the detection (112) that both the single link_ready state and the autoneg_wait_timer_done state are true, Disable (114) the AN transmission and switch the transmitter (516, 517) to a 10G-DAC mode. [2] Method (100) according to claim 1, wherein the detection (106, 116) of the valid signal and the AN sides is performed in parallel by switching between the first and second detection modes. [3] Method (100) according to claim 1, wherein the detection (106, 116) of the valid signal and the AN sides is performed in parallel by simultaneously processing signals received at the receiver (518, 519) that are sent by an Ethernet link peer (552) that does not support AN and an IEEE 802.3 Ethernet link peer (552) that does support AN. [4] Method (100) according to any of the preceding claims, wherein the Ethernet connection which does not support AN is a 10 gigabits per second direct link cable (10G-DAC) connection. [5] Method (100) according to any one of the preceding claims, wherein the Ethernet connection supporting an AN is one of a 10GBASE-KR connection, a 25GBASE-KR connection and a 40GBASE-KR connection. [6] Method (100) according to claim 1, further comprising: in response to at least one of Detect (108) that the signal received at the receiver (518, 519) is not a valid signal sent by an Ethernet link peer (552) that does not support AN; and Detect (112) that at least one of the states single_link_ready and autoneg_wait_timer_done is not true, Switching from the first detection mode to the second detection mode. [7] Method (100) according to any one of the preceding claims, wherein the second detection mode comprises: Detect (116), via the AN sides sent by an Ethernet link peer (552), that the Ethernet link peer (552) supports one or more IEEE 802.3 Ethernet specifications supported by the Ethernet device (500); and Completing (118) the autonegotiation and link training with the Ethernet link peer (552) to initialize link operations with the Ethernet link peer (552) using one or more IEEE 802.3 Ethernet link specifications supported by the Ethernet link peer (552) and the Ethernet device (500). [8] Method (100) according to claim 6, further comprising disabling the first detection mode. [9] Ethernet device (500), comprising: a receiver (518, 519) configured to receive Ethernet signals in accordance with at least one IEEE (“Institute of Electrical and Electronics Engineers”) 802.3 Ethernet specification that supports autonegotiation (AN), and Ethernet signals in accordance with at least one Ethernet specification that does not support AN, a transmitter (516, 517) configured to transmit Ethernet signals in accordance with at least one IEEE 802.3 Ethernet specification that supports AN, and Ethernet signals in accordance with at least one Ethernet specification that does not support AN; a first block (506) of physical layer (PHY) circuits configured to perform PHY processing of Ethernet signals in accordance with at least one IEEE 802.3 Ethernet specification that supports an AN; a second block (508) of PHY circuits configured to perform PHY processing of Ethernet signals in accordance with at least one Ethernet specification that does not support AN; and an autonegotiation module comprising circuitry and logic configured to perform AN operations in accordance with at least one IEEE 802.3 Ethernet specification that supports AN, the Ethernet device (500) is further configured to Sending (102) of AN base pages via the transmitter (516, 517) to offer that the Ethernet device (500) has the capability to support at least one IEEE 802.3 Ethernet specification that supports an AN; Detect (104) at the receiver (518, 519) using a first detection mode, a valid signal sent by an Ethernet link peer that does not support autonegotiation (AN); and Detect (104) at the receiver (518, 519) using a second detection mode, of AN pages sent by an IEEE 802.3 Ethernet link peer using IEEE 802.3 Ethernet link technology that supports an AN, the first detection mode includes the following: Detect (108) whether a signal received at the receiver (518, 519) is a valid signal sent by an Ethernet link peer (552) that does not support AN; in response to the detection (108) that the signal received at the receiver (518, 519) is a valid signal sent by an Ethernet link peer (552) that does not support AN, starting (110) an autonegotiation wait timer; and Detect (112) whether both a single link_ready state and an autoneg_wait_timer_done state are true., and wherein the Ethernet link peer (552) which does not support AN is a 10 Gigabit per second direct link cable (10G-DAC) Ethernet link peer (552), and wherein the first detection mode further includes the following: in response to the detection (112) that both the single link_ready state and the autoneg_wait_timer_done state are true, Disable (114) the transmission of the AN base pages and switch the transmitter (518, 519) to a 10G-DAC mode. [10] Ethernet device (500) according to claim 9, wherein the first and second detection modes are performed in parallel by switching between the first and second detection modes. [11] Ethernet device (500) according to claim 9, wherein the first and second detection modes are performed in parallel by processing received Ethernet signals simultaneously using the first (506) and second (508) blocks of PHY circuits. [12] Ethernet device (500) according to any one of claims 9 to 11, wherein the Ethernet link peer (552) which does not support AN is a 10 Gigabit per second direct link cable (10G-DAC) Ethernet link peer (552). [13] Ethernet device (500) according to any one of claims 9 to 12, wherein the Ethernet link peer (552) supporting an IEEE 802.3 Ethernet specification which supports an AN is one of a 10GBASE-KR, a 25GBASE-KR and a 40GBASE-KR Ethernet link peer. [14] Ethernet device (500) according to any one of claims 9-13, wherein the first detection mode further comprises: in response to at least one of Detect that the signal received at the receiver (518, 519) is not a valid signal sent by an Ethernet connection peer that does not support AN; and Detect that at least one of the states single link_ready and autoneg_wait_timer_done is not true, Switching from the first detection mode to the second detection mode. [15] Ethernet device (500) according to any one of claims 9 to 14, wherein the second detection mode comprises: Detect (116), via the AN sides sent by an IEEE 802.3 Ethernet connection peer (552), that the Ethernet connection peer (552) supports one or more 802.3 Ethernet connection types supported by the Ethernet device (500); and Completing (118) the autonegotiation and connection training with the IEEE 802.3 Ethernet connection peer (552) to initialize connection operations with the IEEE 802.3 Ethernet connection peer (552) using one of the one or more 802.3 Ethernet connection types supported by the IEEE 802.3 Ethernet connection peer (552) and the Ethernet device (500). [16] Multimodal Ethernet network interface controller (NIC) (500), comprising: a receiver (518, 519) configured to receive 10 gigabits per second (10G) Ethernet signals; a transmitter (516, 517) configured to send 10G Ethernet signals; a first physical layer (PHY) circuit block (506) that is selectively coupled to the receiver and transmitter (516, 517) and is configured to process IEEE (“Institute of Electrical and Electronics Engineers”) 802.3 10GBASE-KR Ethernet signals; a second PHY circuit block (508) that is selectively coupled to the receiver and transmitters and configured to process 10G Direct Link Cable (DAC) Ethernet signals, wherein the multimodal Ethernet NIC (500) is further configured, when coupled to an Ethernet port to which an Ethernet Linking Peer (552) is communicatively coupled via a copper cable, to detect whether the Ethernet Linking Peer (552) is transmitting 10G-DAC Ethernet signals or 10GBASE-KR Ethernet signals, Sending (102) autonegotiation (AN) base pages via the transmitter (516, 517) to offer that the multimodal Ethernet NIC (500) has the capability to support 10GBASE-KR Ethernet signals that support an AN; Detect (104) at the receiver (518, 519) using a first detection mode, a valid signal sent by an Ethernet link peer (552) transmitting 10G-DAC Ethernet signals; and Detect, at the receiver (518, 519) using a second detection mode (104), of AN pages sent from a 10GBASE-KR Ethernet link peer (552), wherein the first detection mode includes: In response to the detection (112) that the Ethernet signal received at the receiver (518, 519) is a valid signal sent by a 10G-DAC Ethernet link peer (552), an autonegotiation wait timer is started; and Detect (112) whether both a single link_ready state and an autoneg_wait_timer_done state are true, and in response to the detection (112) that both the single link_ready state and the autoneg_wait_timer_done state are true, Disable (114) the transmission of the AN base pages and switch the transmitter to a 10G-DAC mode. [17] Multimodal Ethernet NIC (500) according to claim 16, wherein the first and second detection modes are executed in parallel by switching between the first and second detection modes. [18] Multimodal Ethernet NIC (500) according to one of claims 16 to 17, wherein the second detection mode comprises: Detect (116), via the AN sides sent by a 10GBASE-KR Ethernet connection peer (552), that the Ethernet connection peer (552) supports one or more 802.3 Ethernet connection types supported by the multimodal Ethernet NIC (500); and Complete (118) the autonegotiation and connection training with the 10GBASE-KR Ethernet connection peer to initialize connection operations with the 10GBASE-KR Ethernet connection peer (552) using 10GBASE-KR Ethernet signaling.

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