Memory cell structure

Abstract

Memory cell structure, exhibiting: a synaptic memory cell with a plurality of cell components, each of the plurality of cell components containing at least one unit cell; a plurality of write lines configured to write a synaptic state to the synaptic memory cell, each of the plurality of write lines configured to write a first set of a predetermined number of states to a corresponding cell component of the plurality of cell components by writing a second set of the predetermined number of states to all of the at least one unit cell contained in the corresponding cell component, the first set depending on the second set and a number of the at least one unit cell contained in the corresponding cell component; and a read line configured to read the synaptic state from the synaptic memory cell, wherein the read line is further configured to read the first set of the predetermined number of states from all of the plurality of cell components simultaneously.

Description

TECHNICAL AREA

[0001] The present invention relates to a memory cell structure. BACKGROUND

[0002] Recently, various techniques regarding memory cell structure have become known. The hardware implementation of a neuromorphic system includes synaptic memory, a neuronal operating block, and an axon connection network.

[0003] A system with offline learning is known for the synaptic memory. The synaptic memory data is not updated in this mode, as the memory write operation is only activated in offline learning mode.

[0004] On the other hand, a system with online learning is also known. The performance of the synaptic memory determines the performance of the system. Synaptic memory cells are divided into two types: analog synaptic cell types and digital synaptic cell types.

[0005] Both types have their disadvantages. Synaptic cells are controlled much more conveniently and precisely when these disadvantages are overcome.

[0006] Therefore, there is a need in the field of technology to solve the problem mentioned above.

[0007] S. Truong et al., “New Memristor-Based Crossbar Array Architecture with 50-% Area Reduction and 48-% Power Saving for Matrix-Vector Multiplication of Analog Neuromorphic Computing”, Journal of Semiconductor Technology and Science, Vol. 14, 2014, No. 3, pp. 356-363, proposes a memristor-based crossbar array architecture for matrix-vector multiplication in analog neuromorphic computations.

[0008] US 2014 / 0310220 A1 reveals electronic synapses for reinforcement learning.

[0009] DE 10 2008 045 963 A1 describes multi-level storage devices and methods for operating them. SUMMARY

[0010] From a first perspective, the present invention provides a memory cell structure comprising: a synaptic memory cell with a plurality of cell components, each of the plurality of cell components comprising at least one unit cell; a plurality of write lines configured to write a synaptic state into the synaptic memory cell, each of the plurality of write lines configured to write a first set of a predetermined number of states into a corresponding cell component of the plurality of cell components by writing a second set of the predetermined number of states into all of the at least one unit cell contained in the corresponding cell component, the first set depending on the second set and the number of at least one unit cell contained in the corresponding cell component;and includes a read line configured to read the synaptic state from the synaptic memory cell, the read line further being configured to read the first set of the predetermined number of states simultaneously from all of the plurality of cell components.

[0011] From another perspective, the present invention provides a memory cell system comprising: a synaptic memory cell with a plurality of cell components, each of the plurality of cell components comprising at least one unit cell; a plurality of write drivers configured to write a synaptic state to the synaptic memory cell, each of the plurality of write drivers being configured to write a first set of a predetermined number of states to a corresponding cell component of the plurality of cell components by writing a second set of the predetermined number of states to all of the at least one unit cell contained in the corresponding cell component, the first set being dependent on the second set and on the number of the at least one unit cell contained in the corresponding cell component;and includes a read driver configured to read the synaptic state from the synaptic memory cell, the read driver further being configured to read the first set of the predetermined number of states simultaneously from all of the plurality of cell components.

[0012] From another perspective, the present invention provides a method for producing a memory cell structure, comprising: creating a plurality of unit cells; assembling a plurality of cell components, wherein each of the plurality of cell components contains at least one unit cell from the plurality of unit cells; assembling a synaptic memory cell containing the plurality of cell components;Arranging a plurality of write lines configured to write a synaptic state to the synaptic memory cell, each of the plurality of write lines being configured to write a first set of a predetermined number of states to a corresponding cell component of the plurality of cell components by writing a second set of the predetermined number of states to all of the at least one unit cell contained in the corresponding cell component, the first set being dependent on the second set and a number of the at least one unit cell contained in the corresponding cell component; and arranging a read line configured to read the synaptic state from the synaptic memory cell, the read line further being configured to read the first set of the predetermined number of states simultaneously from all of the plurality of cell components.

[0013] According to one embodiment of the present invention, a memory cell structure is provided. The memory cell structure includes a synaptic memory cell containing a plurality of cell components. Each of the plurality of cell components contains at least one unit cell. The memory cell structure further includes a plurality of write lines arranged for writing a synaptic state into the synaptic memory cell. Each of the plurality of write lines is configured to write one state from a first set of a predetermined number of states into a corresponding cell component of the plurality of cell components by writing one state from a second set of a predetermined number of states into each of the at least one unit cell contained in the corresponding cell component.The first set depends on the second set and a number of at least one unit cell contained in the corresponding cell component. The memory cell structure further includes a read line arranged for reading the synaptic state from the synaptic memory cell. The read line is configured to read one of the predetermined number of states from the first set simultaneously from all of the cell components.

[0014] According to a further embodiment of the present invention, a memory cell system is provided. The memory cell system comprises a synaptic memory cell containing a plurality of cell components. Each of the plurality of cell components contains at least one unit cell. The memory cell system further comprises a plurality of write drivers configured to write a synaptic state to the synaptic memory cell. Each of the plurality of write drivers is operated such that it writes one state from a first set of a predetermined number of states into a corresponding cell component of the plurality of cell components by writing one state from a second set of a predetermined number of states into each of the at least one unit cell contained in the corresponding cell component.The first set depends on the second set and a number of at least one unit cell contained in the corresponding cell component. The memory cell system further includes a read driver configured to read the synaptic state from the synaptic memory cell. The read driver is configured to read one of the predetermined number of states from the first set simultaneously from all of the multiple cell components.

[0015] According to yet another embodiment of the present invention, a method for producing a memory cell structure is provided. The method includes creating a plurality of unit cells. The method includes assembling a plurality of cell components, each of which contains at least one unit cell of the plurality of unit cells. The method includes assembling a synaptic memory cell containing the plurality of cell components. The method further includes arranging a plurality of write lines for writing a synaptic state into the synaptic memory cell.Each of the plurality of write lines is configured to write one state from a first set of a predetermined number of states into a corresponding cell component of the plurality of cell components by writing one state from a second set of a predetermined number of states into each of the at least one unit cell contained in the corresponding cell component. The first set depends on the second set and the number of at least one unit cell contained in the corresponding cell component. The method further includes an arrangement of a read line for reading the synaptic state from the synaptic memory cell. The read line is configured to read one state from the first set of the predetermined number of states simultaneously from each of the plurality of cell components. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention will now be described by way of example only, with reference to preferred embodiments as shown in the following figures: Fig. Figure 1 shows a synaptic memory with a crossbar array structure in accordance with the prior art and in which a preferred embodiment of the present invention can be implemented; Fig. 2A shows cell components of a synaptic memory cell according to an exemplary embodiment; Fig. 2B shows cell components of a synaptic memory cell according to an exemplary embodiment; Fig. 2C shows cell components of a synaptic memory cell according to an exemplary embodiment; Fig. 2D shows cell components of a synaptic memory cell according to an exemplary embodiment; Fig. Figure 3 shows a synaptic memory cell system according to an exemplary embodiment; Fig. Figure 4 shows timing diagrams showing the times of signal outputs from write drivers, signal outputs from a read driver, and state transitions of the synaptic memory cell according to an embodiment of the present invention; Fig. Figure 5 shows a synaptic storage system and data flows in the synaptic storage system according to an exemplary embodiment; and Fig. Figure 6 shows a block / flow diagram illustrating a method for manufacturing a synaptic memory cell system according to an exemplary embodiment. DETAILED DESCRIPTION

[0017] Exemplary embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0018] It should be noted that the present invention is not limited to the exemplary embodiments listed below and can be implemented with various modifications within the scope of protection of the present invention. Furthermore, the drawings used here serve for illustrative purposes and do not necessarily show actual dimensions.

[0019] The hardware implementation of a neuromorphic system can include synaptic memory as well as neuronal bodies and axon connection networks. Fig. Figure 1 shows a synaptic memory of 100 with a crossbar array structure. As in Fig. As shown in Figure 1, the synaptic memory can contain 100 synaptic memory cells 10, which are arranged / placed at all intersection points of all axons 20 and all dendrites 30. Each of the synaptic memory cells 10 can store a synaptic weight value as an example of a synaptic state, which indicates a weighting of a synaptic connection between a corresponding axon 20 and a corresponding dendrite 30.

[0020] A synaptic memory cell 10 is categorized into two types, namely an analog synaptic memory cell (e.g. an analog cell) and a digital synaptic memory cell (e.g. a digital cell).

[0021] The analog cell can express a continuous synaptic weight value. However, controlling the synaptic weight value with a specific accuracy is difficult. Furthermore, it requires complex peripheral circuitry to control the synaptic weight value with such precision. Additionally, fluctuations in the power of synaptic memory cell 10 directly affect the performance of the neuromorphic system.

[0022] The digital cell can be further subdivided into a single-level cell (SLC) and a multi-level cell (MLC).

[0023] SLC uses a single threshold to distinguish between two states (e.g., a heavy state and a light state). SLC can only represent one state, with or without a connection between the pre-synaptic and post-synaptic terminals. Therefore, SLC usually requires additional memory to represent more than two synaptic weight values. Consequently, access to multiple memory locations is necessary.

[0024] The MLC uses multiple thresholds. Assuming the number of thresholds is n (> 1), the MLC can express (n + 1) synaptic weight values. For example, if n is seven, eight synaptic weight values ​​can be stored in an MLC. The MLC can express a more accurate synaptic weight value than the SLC. However, controlling the synaptic weight value, as well as the analog cell mentioned above, is difficult. Furthermore, the MLC requires high-resolution acquisition circuitry and complex encoding / decoding circuitry to read and write the synaptic weight value.

[0025] Synaptic memory cell 10 is more conveniently and accurately controlled when these disadvantages are overcome.

[0026] Synaptic memory cell 10, with a simple structure described below, is more accurate than the MLC. This synaptic memory cell 10 requires neither high-resolution acquisition circuitry nor complex encoding / decoding circuitry.

[0027] Referring to the Fig. Figures 2A to 2D are cell components of a synaptic memory cell 10 according to an exemplary embodiment. In this exemplary embodiment, the synaptic memory cell 10 is assumed to be a resistive memory cell containing a plurality of unit resistors. Each of the plurality of unit resistors is assumed to have a weight value W. Einheit exhibits a conductivity value (e.g., the reciprocal of a resistance value R). Einheit). In an exemplary embodiment, it is assumed that each of the plurality of unit resistors is implemented with the SLC described above. That is, it is assumed that the weight value W Einheit It has two states, namely a heavy state and a light state. For example, the weight value W Einheit to be one (1) if he is in a severe condition, and zero (0) if he is in a light condition.

[0028] In one embodiment, cell components can be created, each consisting of 2 i-1 Unit resistances exist, where i ranges from 1 to n. If i is not 1, the 2 i-1 Unit resistors can be connected in parallel. This allows the resistance from the two i-1 Unit resistances existing cell components have a weight value that is divided by 2 i-1 - times W Einheit is expressed (or a resistance value that is represented by a 2 i-1 -tel (1 / 2 i-1) by R Einheit (expressed). That means that the result from the 2 i-1 Unit resistances existing cell component a weight value of “0” or “2” i-1 “ can have.

[0029] For example, it shows Fig. 2A a cell component 11, which is a cell component for i = 1. The cell component 11 can contain a unit resistance 111. Thus, the cell component 11 can have a weight value that is given by W Einheit is expressed. This means that cell component 11 can have a weight value of "0" or "1". The weight values ​​"0" and "1" serve as an example of a first set of a predetermined number of states. For the single-cell component for i = 1, the weight values ​​"0" and "1" also serve as an example of a second set of a predetermined number of states. Furthermore, it shows Fig. 2A an upper node (TN) and a lower node (BN) of cell component 11.

[0030] Fig. Figure 2B shows a cell component 12, which is a cell component for i = 2. The cell component 12 can contain unit resistors 121 and 122 connected in parallel. Thus, the cell component 12 can have a weight value that is given by twice W. Einheit is expressed (or a resistance value that is divided by half (1 / 2) of R Einheit (expressed). This means that cell component 12 can have a weight value of "0" or "2". The weight values ​​"0" and "2" serve as an example of a first set of a predetermined number of states. Furthermore, it shows Fig. 2B a TN formed by connecting upper nodes of unit resistors 121 and 122, and a BN formed by connecting lower nodes of unit resistors 121 and 122.

[0031] Fig. Figure 2C shows a cell component 13, which is a cell component for i = 3. The cell component 13 can contain unit resistors 131 to 134 connected in parallel. Thus, the cell component 13 can have a weight value that is determined by four times W. Einheit is expressed (or a resistance value that is one quarter (1 / 4) of R Einheit (expressed). This means that cell component 13 can have a weight value of "0" or "4". The weight values ​​"0" and "4" serve as an example of a first set of a predetermined number of states. Furthermore, it shows Fig. 2C a TN formed by connecting upper nodes of unit resistors 131 to 134, and a BN formed by connecting lower nodes of unit resistors 131 to 134.

[0032] Similarly, cell components can be formed for i = 4 to i = n - 1. Now, referring to Fig. 2D shows Fig. 2D a cell component 1N, which is a cell component for i = n. The cell component 1N can be 2 n-1 The cell component contains unit resistors connected in parallel. Therefore, the cell component 1N can have a weight value that is divided by 2. n-1 - times W Einheit is expressed (or a resistance value that is represented by a 2 n-1 -tel (1 / 2 n-1 ) by R Einheit (expressed). This means that the cell component 1N has a weight value of "0" or "2". n-1 “ can have. The weight values ​​“0” and “2” n-1 “ serve as an example of a first set of a predetermined number of states. Furthermore, it shows Fig. 2D a TN, which is created by connecting the upper nodes of the 2 n-1 Unit resistances are formed, and a BN is formed by connecting lower nodes of the 2 n-1Unit resistances are formed. By combining these cell components for i = 1 to i = 3, the synaptic weight values ​​"0" to "7" can be expressed, for example. This means that the synaptic weight values ​​for n-digit binary numbers can be expressed using these cell components for i = 1 to i = n.

[0033] In Fig. Figure 3 shows a synaptic memory cell system according to an exemplary embodiment.

[0034] Fig. Figure 3 first shows a structure of the synaptic memory cell 10 using cell components 11 to 16, each representing cell components for i = 1 to i = 6. It is assumed that cell component 11 is implemented with a unit resistance of 1 (= 2°), as shown in the Fig. 2A and Fig. 3 shown. It is assumed that cell component 12 with 2 (= 2 1 ) unit resistors are implemented, as in the Fig. 2B and Fig. 3 shown. It is assumed that cell component 13 with 4 (= 2 2 ) unit resistors are implemented, as in the Fig. 2C and Fig. 3 shown. It is assumed that cell component 14 with 8 (= 2 3 ) unit resistors are implemented, as in the Fig. 2D (i = 4) and 3 are shown. It is assumed that cell component 15 with 16 (= 2 4 ) unit resistors are implemented, as in the Fig. 2D (i = 5) and 3 are shown. It is assumed that the cell component 16 with 32 (= 2 5 ) unit resistors are implemented, as in the Fig. 2D (i = 6) and 3 are shown. In Fig. 3. It is therefore assumed that a synaptic cell with 63 (= 2 6-1 ) is implemented with unit resistors.

[0035] Fig. Figure 3 further shows a write driver array 40, a read driver 50, a current sensor 60, a neuron body 70, a weight evaluator 80 and a weight encoder 90 as structural elements that work for the synaptic memory cell 10.

[0036] The write driver array 40 can be configured to write a synapse weight value to synapse memory cell 10 in response to a learning operation input or a recognition operation input. Specifically, the write driver array 40 can contain write drivers 41 to 46 for cell components 11 to 16. The TN of each cell component 11 to 16 can be connected via a write line to an output node of a corresponding write driver of the write drivers 41 to 46 in the write driver array 40. Thus, the write drivers 41 to 46 can write a weight value "0" or "1" via a corresponding write line to each of the one or more unit resistors that form a corresponding cell component 11 to 16. Furthermore, the BNs of the cell components 11 to 16 can be connected together with common DC nodes of the write drivers 41 to 46.

[0037] The read driver 50 can be configured to read a synapse weight value from synapse memory cell 10 in response to a recognition operation input. The terminal nodes of cell components 11 to 16 can be connected together with an output node of the read driver 50. Thus, the read driver 50 can simultaneously apply power to all of the cell components 11 to 16.

[0038] The current sensor 60 can also be configured to read a synapse weight value from the synapse memory cell 10. The BNs of cell components 11 to 16 can be connected to the current sensor 60 via a read line. A common DC node of the read driver 50 can also be connected to the current sensor 60. Thus, the current sensor 60 can detect the total current of all cell components 11 to 16 via a single read line.

[0039] Neuron body 70 can perform neuronal operations. In particular, neuron body 70 can obtain the synaptic weight value based on the total current detected by current sensor 60. Neuron body 70 can then output the synaptic weight value as a recognition operation output to another synaptic storage system and to weight evaluator 80. A cell component can allow a high current to pass through if a large number of unit resistances of the cell component have a weight value of "1". Conversely, a cell component can allow a low current to pass through if a large number of unit resistances of the cell component have a weight value of "0". Accordingly, the total current detected by current sensor 60 can represent the synaptic weight value stored in synaptic storage cell 10.

[0040] The weight evaluator 80 can evaluate the current synaptic weight value from the neuron output signal of the neuron body 70 and determine the next synaptic weight value. In particular, the weight evaluator 80 can compare the neuron output signal received from the neuron body 70 with a desired output signal provided as a learning operation input and calculate the next synaptic weight value with which the current synaptic weight value stored in the synaptic memory cell 10 is to be updated.

[0041] The weight encoder 90 can encode the next synapse weight value calculated by the weight evaluator 80. Specifically, the weight encoder 90 can encode the next synapse weight value into binary-coded values, each of which is to be provided to a corresponding write driver 41 to 46, and control the write drivers 41 to 46 such that each of them can write a corresponding binary-coded value into a corresponding cell component 11 to 16.

[0042] In Fig. Figure 4 shows timing diagrams 450, 550, and 150. Timing diagram 450 shows the times of signal outputs from any one of the write drivers 41 to 46 during writing to synaptic memory cell 10. Timing diagram 550 shows the times of signal outputs from the read driver 50 during reading from synaptic memory cell 10. Furthermore, timing diagram 150 shows the times of state transitions of synaptic memory cell 10.

[0043] To write a synapse weight value to synapse memory cell 10, each of the write drivers 41 to 46 can be driven to a higher or lower value than a set or reset threshold.

[0044] Initially, it is assumed that all cell components 11 to 16 are preset to a light state, resulting in a weight value of "0". This is achieved by activating all write drivers 41 to 46 so that they can control cell components 11 to 16 in a reset direction (for example, lower than a reset threshold). In timing diagram 450, this operation is performed in a "Reset1" state of timing diagram 150.

[0045] Next, it is assumed that only selected cell components 11 to 16 are set to a heavy state, resulting in a weight value of "1," by activating selected write drivers 41 to 46 so that they can control the selected cell components in a set direction (for example, higher than a set threshold). In time diagram 450, this operation is performed in a "Set1" state of time diagram 150.

[0046] Next, the selected cell components can be set to a light state, resulting in a weight value of "0," by enabling the selected write drivers to control the selected cell components in a reset direction (for example, lower than a reset threshold). In time graph 450, this operation is performed in a "Reset2" state of time graph 150.

[0047] To read a synapse weight value from synapse memory cell 10, the read driver 50 can be activated. In timing diagram 550, this operation is performed in the states "Read1" and "Read2" of timing diagram 150. At any given time, the total current output by all cell components 11 to 16, which is proportional to the synapse weight, can be detected by the current sensor 60.

[0048] Note that the level of a signal output by read driver 50 can be lower than the set threshold, so that the synaptic weight value stored in synaptic memory cell 10 is not destroyed (e.g., overwritten) by the signal output by read driver 50. In the analog cell or the MLC structure, precise control of the unit resistors is essential. However, with this structure, such precise control of the unit resistors can be avoided. This is because, as with the SLC, all unit resistors are controlled in only two states, and unlike the MLC, neither a verification read nor an additional write is required.

[0049] To avoid driver conflicts, write (reset / set) and read times can be mutually exclusive. This means that the write driver array 40 and the read driver 50 can be controlled so that they are not activated simultaneously. For example, the write driver array 40 can be kept in a high-impedance (Hi-Z) state while the read driver 50 accesses synaptic memory cell 10, and vice versa.

[0050] With reference to Fig. Figure 5 shows an example of a neurosynaptic nucleus system, which is the synaptic storage cell system of Fig. 3 contains. The data flows in this system follow the one in Fig. 5 exemplary embodiment shown. In Fig. 5. It is assumed that the synaptic memory 100 is used to implement this system with online learning.

[0051] As in Fig. As shown in Figure 5, the neurosynaptic core system can contain the synaptic memory 100, write driver arrays 400, read drivers 500, current sensors 600, neuron bodies 700, weight evaluators 800 and weight encoders 900.

[0052] The synaptic memory 100 can contain a plurality of synaptic memory cells 10, as they are in Fig. 1 are shown.

[0053] The write driver arrays 400 can contain a plurality of write driver arrays, one of which is designated as the write driver array 40 in Fig. Figure 3 shows that each of the plurality of write driver arrays can be connected to the individual synaptic memory cell 10 with the common structure shown in Figure 3. Fig. 3 is shown.

[0054] The read drivers 500 can contain multiple read drivers, one of which is designated as read driver 50. Fig. Figure 3 shows that each of the plurality of read drivers can be connected to the individual synaptic memory cell 10 with the common structure shown in Figure 3. Fig. 3 is shown.

[0055] The 600 current sensors can contain multiple current sensors, one of which is designated as the 60 current sensor. Fig. Figure 3 shows that each of the current sensors can be connected to the individual synaptic memory cells 10 with the common structure shown in Figure 3. Fig. 3 is shown.

[0056] Neuron bodies 700 can contain a plurality of neuron bodies, one of which is designated as neuron body 70 in Fig. Figure 3 shows that each of the neuron bodies can be connected to the individual current sensor 60, which is connected to the individual memory cells 10 via the common structure shown in Figure 3. Fig. 3 are shown.

[0057] The Weight Evaluator 800 can contain multiple Weight Evaluators, one of which is designated as Weight Evaluator 80 in Fig. 3 is shown. Each of the weight evaluators can be connected to the individual weight encoder 90, which is connected via the individual write driver array 40 to the individual synaptic memory cell 10 with the common structure shown in Fig. 3 is shown.

[0058] The Weight Encoder 900 can contain multiple weight encoders, one of which is designated as Weight Encoder 90. Fig. Figure 3 shows that each of the weight encoders can be connected to the individual write driver array 40, which is connected to the individual synaptic memory cell 10 with the common structure shown in Figure 3. Fig. 3 is shown.

[0059] Fig. Figure 5 further shows a data flow in a learning mode, indicated by hatched arrows, and a data flow in a recognition mode, indicated by outlined arrows.

[0060] In the learning mode, as in Fig. As shown in Figure 5, one of the write driver arrays 400 applies a voltage to a corresponding synaptic memory cell 10 in the synaptic memory 100 in response to a recognition operation input. If, in this case, one of the write driver arrays 400 applies a voltage whose level is between the reset threshold and the set threshold of Fig. If 4 is present, it does not overwrite any synapse weight value stored in synapse memory cell 10.

[0061] Then, one of the current sensors 600 can detect the total current from a corresponding dendrite 30 connected to the synaptic memory cell 10. One of the neuron bodies 700 can calculate a neuron membrane potential value based on the total current detected by one of the current sensors 600 and provide a neuron output to one of the weight evaluaters 800. One of the weight evaluaters 800 can compare the neuron output received from one of the neuron bodies 700 with a learning operation input and calculate the next synaptic weight value, which is used to update the contents of the synaptic memory cell 10 based on the result of the comparison. One of the weight encoders 900 can encode the next synaptic weight value into binary code and control one of the write driver arrays 400 to write the binary code to the synaptic memory cell 10.One of the write driver arrays 400 can control the binary-coded values ​​as synapse weight value into the synapse memory cell 10.

[0062] In the detection operating mode, as described in Fig. Figure 5 shows that the read drivers 500, in response to a recognition operation input, apply a current to the axons 20, which are connected to the synaptic memory cells 10 in the synaptic memory 100.

[0063] The current sensors 600 can then detect the total current from the dendrites 30 connected to the synaptic memory cells 10. The neuron bodies 700 can calculate the neuronal membrane potential based on the total current detected by the current sensors 600 and provide the neuronal output to another synaptic memory system as recognition operation output.

[0064] In Fig. Figure 6 shows a block / flow diagram illustrating a manufacturing process of the synaptic memory cell system according to an embodiment that includes write and read drivers.

[0065] As in Fig.As shown in Figure 6, a plurality of unit resistors of the minimum size can be created to write and read one of two weight values ​​(Step 101). For example, the two weight values ​​can be a weight value "1", corresponding to a heavy state, and a weight value "0", corresponding to a light state. The plurality of unit resistors can be connected in parallel to assemble the plurality of cell components (Step 102). Next, different types of cell components 11 to 16 can be created, each containing a binary weighted number of unit resistors (Step 103). The different types of cell components 11 to 16 can be combined to assemble the synaptic memory cell 10 (Step 104).

[0066] Simultaneously, write drivers 41 to 46 can be created for the separate but simultaneous parallel writing of weight values ​​to cell components 11 to 16 in synaptic memory cell 10 (step 105). This means that write drivers 41 to 46 can be created for digital writing. This step can further include the arrangement of write lines used for such digital writing. Read driver 50 can be created for the simultaneous reading of a synaptic weight value from cell components 11 to 16 in synaptic memory cell 10 (step 106). This means that read driver 50 can be created for analog reading. This step can further include the arrangement of a read line used for such analog reading.

[0067] Next, an alternative exemplary embodiment is described.

[0068] In an alternative exemplary embodiment, the synapse memory cell 10 is assumed to be a capacitive memory cell containing a plurality of unit capacitors. The resistive memory cell in the exemplary embodiment can be replaced by the capacitive memory cell, since a synapse weight value can be expressed in the same way by both a conductance value of the resistive memory cell and a capacitance value of the capacitive memory cell. The capacitance value of the capacitive memory cell can be doubled if the unit capacitors are connected in parallel and halved if the unit capacitors are connected in series, just as with the conductance value of the resistive memory cell. It should be noted that in the alternative exemplary embodiment, the current sensor 60 (e.g., the current sensors 600) can also be replaced by a capacitance sensor (e.g.,Capacitance sensors) and the like can be replaced. Furthermore, the capacitance value of the capacitive memory cell can be generalized to a state of the unit cells, just as the conductivity value of the resistive memory cell can be generalized.

[0069] Another alternative exemplary embodiment is described below.

[0070] In the second alternative exemplary embodiment, it is assumed that the weight value W Einheit It has three states: a heavy state, a medium state, and a light state. For example, the weight value W Einheit Two if he has a severe condition, one if he has a moderate condition, and zero if he has a mild condition.

[0071] In the second alternative exemplary embodiment, cell components can be created, each consisting of 3 i-1Unit resistances exist, where i ranges from 1 to n. If i is not 1, the 3 i-1 Unit resistors can be connected in parallel. This allows the combination of the 3 i-1 Unit resistances existing cell components have a weight value that is divided by 3 i-1 - times W Einheit is expressed (or a resistance value that is represented by a 3 i-1 -tel (1 / 3 i-1 ) by R Einheit (expressed). This means that the cell component, which consists of the 3 i-1 Unit resistances consist of a weight value of "0", "3" i-1 “ or “2 × 3 i-1 “ can have.

[0072] For example, a cell component for i = 1 can have a weight value of "0", "1", or "2". The weight values ​​"0", "1", and "2" serve as an example of a first set of a predetermined number of states. For the single-cell component for i = 1, the weight values ​​"0", "1", and "2" also serve as an example of a second set of a predetermined number of states. A cell component for i = 2 can have a weight value of "0", "3", or "6". The weight values ​​"0", "3", and "6" serve as an example of a first set of a predetermined number of states. A cell component for i = 3 can have a weight value of "0", "9", or "18". The weight values ​​"0", "9", and "18" serve as an example of a first set of a predetermined number of states. By combining these cell components for i = 1 to i = 3, the synaptic weight values ​​"0" to "26", for example, can be expressed.This means that with these cell components, the synapse weight values ​​for n-digit ternary numbers can be expressed for i = 1 to i = n.

Claims

[1] Memory cell structure, having: a synaptic memory cell with a plurality of cell components, each of the plurality of cell components containing at least one unit cell; a plurality of write lines configured to write a synaptic state to the synaptic memory cell, each of the plurality of write lines configured to write a first set of a predetermined number of states to a corresponding cell component of the plurality of cell components by writing a second set of the predetermined number of states to all of the at least one unit cell contained in the corresponding cell component, the first set depending on the second set and a number of the at least one unit cell contained in the corresponding cell component; and a read line configured to read the synaptic state from the synaptic memory cell, wherein the read line is further configured to read the first set of the predetermined number of states from all of the plurality of cell components simultaneously. [2] Memory cell structure according to claim 1, wherein each of the at least one unit cell is a resistor and the predetermined number of states are states with respect to the conductivity of the resistor. [3] Memory cell structure according to claim 1, wherein each of the at least one unit cell is a capacitor and the predetermined number of states are states with respect to the capacitance of the capacitor. [4] Memory cell structure according to one of the preceding claims, wherein: a predetermined number of the predetermined number of states is two, where the i-th cell component is the plurality of cell components 2 i-1contains unit cells, where i is a natural number; and each of the predetermined number of states in the first set 2 i-1 -times a corresponding number of the predetermined number of states in the second set. [5] Memory cell structure according to any one of the preceding claims, wherein: a predetermined number of the predetermined number of states is three; the i-th cell component of the plurality of cell components 3 i-1 contains unit cells, where i is a natural number; and each of the predetermined number of states in the first set 3 i-1 -times a corresponding number of the predetermined number of states in the second set. [6] Memory cell system comprising: a synaptic memory cell with a plurality of cell components, each of the plurality of cell components containing at least one unit cell; a plurality of write drivers configured to write a synaptic state to the synaptic memory cell, each of the plurality of write drivers being configured to write a first set of a predetermined number of states to a corresponding cell component of the plurality of cell components by writing a second set of the predetermined number of states to all of the at least one unit cell contained in the corresponding cell component, the first set being dependent on the second set and a number of the at least one unit cell contained in the corresponding cell component; and a read driver configured to read the synaptic state from the synaptic memory cell, wherein the read driver is further configured to read the first set of the predetermined number of states simultaneously from all of the plurality of cell components. [7] Memory cell system according to claim 6, wherein each of the at least one unit cell is a resistor and the predetermined number of states are states with respect to the conductivity of the resistor. [8] Memory cell system according to claim 6, wherein each of the at least one unit cell is a capacitor and the predetermined number of states are states with respect to the capacitance of the capacitor. [9] Memory cell system according to any one of claims 6 to 8, wherein: a predetermined number of the predetermined number of states is two; the i-th cell component of the plurality of cell components 2 i-1 contains unit cells, where i is a natural number; and each of the predetermined number of states in the first set 2 i-1 -times a corresponding number of the predetermined number of states in the second set. [10] Memory cell system according to any one of claims 6 to 9, wherein: a predetermined number of the predetermined number of states is three; the i-th cell component of the plurality of cell components 3 i-1 contains unit cells, where i is a natural number; and each of the predetermined number of states in the first set 3 i-1 -times a corresponding number of the predetermined number of states in the second set. [11] Method for producing a memory cell structure, comprising the method: Creating a plurality of unit cells; Assembling a plurality of cell components, wherein each of the plurality of cell components contains at least one unit cell of the plurality of unit cells; Assembling a synaptic memory cell containing the majority of cell components; Arranging a plurality of write lines configured to write a synaptic state into the synaptic memory cell, each of the plurality of write lines being configured to write a first set of a predetermined number of states into a corresponding cell component of the plurality of cell components by writing a second set of the predetermined number of states into all of the at least one unit cell contained in the corresponding cell component, the first set being dependent on the second set and a number of the at least one unit cell contained in the corresponding cell component; and Arranging a read line configured to read the synaptic state from the synaptic memory cell, wherein the read line is further configured to read the first set of the predetermined number of states simultaneously from all of the plurality of cell components.

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