ELECTRONIC CONTROL UNIT, ON-BOARD SYSTEM AND POWER SUPPLY UNIT

Abstract

Electronic control unit (201), comprising a plurality of logic circuits (215, 216, 217, 218, 219, 220) and a power supply unit (210) for powering the plurality of logic circuits, wherein the power supply unit (210) includes a plurality of circuits (22), each generating and outputting current on the basis of a switching signal (C), which supplies the plurality of logic circuits (215, 216, 217, 218, 219, 220), a transition management unit (5, 25) that controls the multitude of circuits (22), and a clock generation unit (26) that generates a multitude of clock signals, the transition management unit (5, 25) includes a control signal generation unit (53) which generates intermediate control signals (C') based on the clock signals generated by the clock generation unit (26), and a plurality of delay units (54) which are provided according to the plurality of circuits (22) to delay the respective intermediate control signal (C') on the basis of a command signal and to output the delayed intermediate control signal (C1, C2, C3) as a switching signal, and the plurality of clock signals generated by the clock generation unit (26) shall include at least one clock signal having a different frequency, characterized by the fact that the transition management unit (5, 25) includes a transition determination unit (56) that generates the command signal based on preset control information, and The transition determination unit (56) calculates a total value of the change amounts of the input currents of the plurality of circuits (22) on the basis of the command signal and compares the calculated total value with a preset current change threshold in order to control a delay amount in the delay unit such that the compared total value is less than the current change threshold.

Description

Technical field

[0001] The present invention relates to an electronic control unit, an on-board system and a power supply unit, and in particular to a technique that is effective for controlling a power supply that provides power to a plurality of logic circuits. State of the art

[0002] Automated driving systems must recognize vehicles, pedestrians, white lines and the like based on signals input from sensors such as cameras and radars in order to transmit the recognized information to the driver or to control braking and steering, which requires advanced recognition algorithms and the simultaneous processing of a variety of algorithms.

[0003] To meet these requirements, studies are currently underway to improve the performance of an electronic control unit that uses a semiconductor component such as a system-on-a-chip (SoC). An SoC comprises various logic circuits, such as a central processing unit (CPU), integrated onto a single chip.

[0004] The logic circuits integrated into the SoC each have characteristic requirements regarding voltage, load current, disturbance, sequences, and transient response. Voltage requirements, in particular, vary. To enable this multi-channel capability, the power supply circuitry is often designed to include several parallel circuits that meet the requirements of the respective logic circuits.

[0005] The power supply circuit, configured from various circuits, generates interference caused by its switching operations. Since the power supply circuit in the electronic control unit is connected to the vehicle's battery for power, this interference can be transmitted to other vehicle-mounted devices connected to the same battery, leading to malfunctions and failures.

[0006] One known technique for reducing such conducted interference is to place a large-capacitance capacitor in the input stage of the power supply circuit. Alternatively, it is common to incorporate an interference suppression component such as a noise suppression circuit or filter.

[0007] Another technique for reducing interference is known in which the spectrum of switching interference is spread to lower the interference level (see, for example, JP 2016-054581A). The technique disclosed in JP 2016-054581A includes a frequency-changing device that repeatedly outputs a frequency-changing pattern with a multitude of frequency values ​​to perform switching control in a power supply circuit with one output that has a multitude of parallel circuits.

[0008] Then the switching elements are switched on and off at a switching frequency based on the frequency change pattern output by the frequency changer, and when the spectrum of the switching disturbance of each switching element overlaps, the switching frequency parameter of each element is changed.

[0009] Document US 2014 / 0253066A1 discloses a switching converter according to the preamble of claim 1 with multiple parallel paths, wherein a phase delay between the outputs is provided. Further prior art is disclosed in documents US 2012 / 0049821A1 and US 2017 / 0005567A1. Summary of the invention: Technical problem

[0010] In a multi-channel power supply circuit with a large number of parallel-connected circuits, if the switching control for each circuit is performed at the same constant switching frequency, a large conducted disturbance can occur due to this same switching frequency. Therefore, the multi-channel power supply circuit acts as a source of interference, which can lead to the malfunction or failure of other electronic devices.

[0011] The problem is that adding a large-capacity capacitor, an interference suppression circuit, or an interference suppression filter increases costs and the mounting area.

[0012] When the above JP 2016-054581A is applied to a multi-channel power supply circuit, it is also necessary to continuously change the frequency of an oscillator that outputs a switching control signal to change the switching frequency parameter of each switching element. Therefore, the frequency range is necessarily limited, and it is to be expected that a sufficient noise reduction effect cannot be achieved in an electronic control unit for an automatic driving system that requires a large number of power supply channels.

[0013] As described above, each output of the multi-channel power supply circuit is designed according to the requirements of the connected logic circuits. Since the switching frequency is a parameter that strongly influences the requirements for power efficiency and response time, the frequency range is further limited.

[0014] One object of the present invention is to provide a technique that makes it possible to reduce conducted disturbances in the input current at low cost in a power supply circuit with a multitude of channels.

[0015] These and other tasks and novel features of the present invention will become apparent from the following detailed description in conjunction with the accompanying drawings. Solution to the problem

[0016] The invention proposes to solve the aforementioned problem by means of an electronic control unit with the features of claim 1, an on-board system equipped with such a control unit, and a power supply unit with the features of claim 10. A representative example of the inventions disclosed in the present application is briefly set forth below.

[0017] This means that a representative electronic control unit comprises a multitude of logic circuits and a power supply unit that provides power to these logic circuits. The power supply unit includes a multitude of circuits, a transition management unit, and a clock generation unit.

[0018] The circuits each generate and supply current based on a switching signal, which powers the numerous logic circuits. The transition management unit controls the numerous circuits. The clock generation unit generates a multitude of clock signals.

[0019] The transition management unit comprises a control signal generation unit and a variety of delay units. The control signal generation unit generates an intermediate control signal from the clock signal output by the clock generation unit. The delay units are configured according to the variety of circuits to delay the intermediate control signal based on a command signal and output the delayed intermediate control signal as a switching signal.

[0020] Furthermore, the multitude of clock signals generated by the clock generation unit includes at least one clock signal that has a different frequency.

[0021] This means that the transition management unit has a transition determination unit that generates a command signal based on preset control information. Based on this command signal, the transition determination unit calculates a total value of the change magnitudes of the input currents of the multitude of circuits and compares this calculated total value with a preset current change threshold to control a delay amount in the delay unit such that the compared total value is less than or equal to the current change threshold. Advantageous effects of the invention

[0022] The effect achieved by a representative embodiment of the invention disclosed herein is as follows.

[0023] It is possible to provide a highly reliable electronic control unit at low cost. Brief description of the drawings [ Fig. 1] Fig. Figure 1 is a block diagram that represents a configuration example of an on-board system according to a first embodiment. [ Fig. 2] Fig. Figure 2 is a block diagram showing a configuration example of an autonomous driving control unit in the on-board system of Fig. 1 shows. [ Fig. 3] Fig. Figure 3 is an explanatory schematic representation showing a configuration example of a power supply circuit in the autonomous driving control unit of Fig. 2 shows. [ Fig. 4] Fig. Figure 4 is an explanatory schematic diagram showing an example of a circuit in the circuit of Fig. 3 shows. [ Fig. 5] Fig. Figure 5 is an explanatory schematic representation showing another example of a circuit in the circuit of Fig. 4 shows. [ Fig. 6] Fig. Figure 6 is a block diagram showing an example of a transition management unit in the power supply circuit of Fig. 3 shows. [ Fig. 7] Fig. 7 is a flowchart that shows an example of the transition determination processing carried out by the transition management unit of Fig. 6 is executed. [ Fig. 8] Fig. Figure 8 is an explanatory schematic representation that shows an example of a data configuration in a power supply circuit management database. Fig. 3 shows. [ Fig. 9] Fig. Figure 9 is a schematic representation showing an example of each signal waveform in the power supply circuit that was tested by the inventors. [ Fig. 10] Fig. 10 is a schematic representation that shows an example of each signal waveform in the power supply circuit of the in Fig. The transition management unit shown in section 6 is shown. [ Fig. 11] Fig. Figure 11 is an explanatory schematic representation showing a configuration example of a transition management unit 5 according to a second embodiment. [ Fig. 12] Fig. Figure 12 is a block diagram showing a configuration example of a power supply circuit according to a third embodiment. [ Fig. 13] Fig. Figure 13 is an explanatory schematic representation showing a configuration example of a transition management unit in the power supply circuit of Fig. 12 shows. Description of embodiments

[0024] In the drawings describing the embodiments, identical elements are consistently designated by the same reference numerals, and their description is not repeated.

[0025] The following section describes various embodiments in detail. (First embodiment)<Konfigurationsbeispiel des Bordsystems>

[0026] Fig. Figure 1 is a block diagram that represents a configuration example of an on-board system 10 according to a first embodiment.

[0027] The on-board system 10 is a system that, for example, controls the autonomous driving of a vehicle. As in Fig. As shown in Figure 1, the on-board system 10 includes a camera 101, a radar 102, a vehicle position sensor 103, an "automatic driving" button 104, a wireless communication unit 105, an auxiliary control unit 106, a brake control unit 107, an engine control unit 108, a power steering control unit 109 and an autonomous driving control unit 201.

[0028] Camera 101, radar 102, and vehicle position sensor 103 are sensors for detecting the external environment, which detect the vehicle's surroundings. Camera 101 and radar 102 are sensors for detecting the external environment in order to determine the distance to an object.

[0029] The vehicle position sensor 103 is a sensor that detects the vehicle's position using a global positioning system (GPS) or similar technology. The "automatic driving" button 104 is a button for starting automatic driving control or changing the automatic driving mode. The wireless communication unit 105 is a communication device that connects to a wireless network (not shown) to update an on-board system, for example, via an over-the-air (OTA) procedure.

[0030] The autonomous driving control unit 201 is an electronic control unit and an autonomous driving control unit for controlling the vehicle's automatic driving. The auxiliary control unit 106 is an auxiliary control unit for controlling the driving of the automatically driving vehicle. The brake control unit 107 is a control unit that performs the vehicle's brake control, that is, the control of the braking force.

[0031] The engine control unit 108 is a control unit that controls the motor which generates the vehicle's driving power. The power steering control unit 109 is a control unit that controls the vehicle's power steering.

[0032] The camera 101, the radar 102, the vehicle position sensor 103, the "autonomous driving" button 104, and the wireless communication unit 105 are each connected to the autonomous driving control unit 201. The autonomous driving control unit 201 receives update information from the wireless communication unit 105, including sensor information from the camera 101, the radar 102, and the vehicle position sensor 103, control signals for autonomous driving from the "autonomous driving" button 104, and processing information for controlling autonomous driving.

[0033] The autonomous driving control unit 201, the auxiliary control unit 106, the brake control unit 107, the engine control unit 108 and the power steering control unit 109 are, for example, communicatively connected to each other via a Controller Area Network (CAN).

[0034] When a request to start automatic driving is received from the “automatic driving” button 104, the autonomous driving control unit 201 calculates a route for the vehicle based on information about the external environment received from the camera 101, the radar 102, the vehicle position sensor 103 and the like.

[0035] Furthermore, the autonomous driving control unit 201 issues commands to the brake control unit 107, the engine control unit 108 and the power steering control unit 109 to control a brake, a drive force and the like, in order to move the vehicle along the above route.

[0036] The brake control unit 107, the engine control unit 108 and the power steering control unit 109 receive control commands for autonomous driving control from the autonomous driving control unit 201 and output actuation signals to control objects such as actuators.

[0037] That is, the autonomous driving control unit 201 is a main control unit that issues control commands, and the brake control unit 107, the engine control unit 108 and the power steering control unit 109 are auxiliary control units that control control objects according to the control commands issued by the autonomous driving control unit 201.

[0038] The auxiliary control unit 106 is an auxiliary control device that performs automatic driving control in place of the autonomous driving control unit 201 when the autonomous driving control unit 201 is in an abnormal state. <Autonome Fahrsteuereinheit>

[0039] Fig. Figure 2 is a block diagram showing a configuration example of the autonomous driving control unit 201 in the on-board system 10 of Fig. 1 shows.

[0040] The autonomous driving control unit 201 comprises a power supply circuit 210 and a variety of SoCs (System-on-Chip) 211, as shown in Fig. Figure 2 shows the power supply circuit 210, which is a power supply device that provides power to the multitude of SoCs 211. In other words, power is supplied to the multitude of SoCs 211.

[0041] Each SoC 211 comprises a CPU 212, a GPU 213, and an FPGA 214. The CPU 212 includes a core logic 215, which is a core logic circuit, and an I / O circuit 216, which is a logic circuit.

[0042] Accordingly, the GPU 213 comprises a core logic 217, which is a core logic circuit, and an I / O circuit 218, and the FPGA 214 comprises a core logic 219, which is a core logic circuit, and an I / O circuit 220. These core logics 215, 217 and 219, as well as the I / O circuits 216, 218 and 220, are composed of logic circuits.

[0043] For the sake of simplicity, details such as memory, communication devices, and the like are not described here. These core logics 215, 217, and 219 perform calculations for the respective detection, prediction, and control algorithms during automated driving.

[0044] The I / O circuits 216, 218, and 220 perform the information exchange between the respective core logics 215, 217, and 219, and the like. Since the processing load of the core logics 215, 217, and 219 and the communication frequency of the I / O circuits 216, 218, and 220 differ, the power supply requirements also vary.

[0045] The multi-channel power supply circuit 210 converts the current from the battery 300 according to the respective current requirements of the core logics 215, 217 and 219 as well as the I / O circuits 216, 218 and 220 and supplies them with power.

[0046] Although in Fig. As described in section 2, where a battery 300 and a power supply circuit 210 are used, both can have a redundant configuration in the event of a malfunction. In particular, the power can be supplied individually to a multitude of redundant SoCs via separate power supply circuits and separate batteries.

[0047] Furthermore, the number of SoCs mentioned above and the configuration of their logic circuitry are merely examples. These depend on the computing power of the autonomous driving control unit 201. For example, the higher the level of automated driving covered by the autonomous driving control unit 201, the greater the number of SoCs and the more complex the configuration of their logic circuitry, i.e., the core logic. <Konfigurationsbeispiel der Stromversorgungsschaltung>

[0048] Fig. Figure 3 is an explanatory schematic representation showing a configuration example of the power supply circuit 210 in the autonomous driving control unit 201 of Fig. 2 shows.

[0049] Power supply circuit 210 supplies loads 21-1 to 21-N with power from battery 300. Here, loads 21-1 to 21-N correspond to core logics 215, 217 and 219 and I / O circuits 216, 218 and 220 of Fig. 2. In the following, loads 21-1 to 21-N will simply be referred to as load 21 when they are referred to collectively.

[0050] The power supply circuit 210 comprises integrated circuits 22-1 to 22-N, inductors 23-1 to 23-N, capacitors 24-1 to 24-N, a transition management unit 25, a clock generation unit 26 and a management database 27.

[0051] In the following, circuits 22-1 to 22-N will simply be referred to as circuit 22 when they are collectively designated, and inductors 23-1 to 23-N will simply be referred to as inductor 23 when they are collectively designated. Furthermore, capacitors 24-1 to 24-N will simply be referred to as capacitor 24 when they are collectively designated.

[0052] Here, a step-down circuit is described as an example, in which circuit 22 uses a control method with pulse width modulation (PWM).

[0053] The clock generation unit 26 generates a clock signal. This clock signal is the basis of a control signal for switching a switch in the circuit 22 on and off. The frequency of the clock signal is called the switching frequency, and properties of the circuit 22, such as power efficiency and response behavior, depend on the switching frequency.

[0054] Since the values ​​required for these properties, as described above, are different for each load 21, the clock generation unit 26 generates different frequencies. Using these clock signals and the observed output voltages Vout1, Vout2, ..., VoutN for each load 21 as a reference, the transition management unit 25 generates control signals C1, C2, ..., CN based on the control information stored in the management database 27. These control signals C1, C2, ..., CN are switching signals.

[0055] Here, the output voltages Vout1, Vout2, ..., VoutN to the loads are simply referred to as output voltage Vout when they are collectively named. Furthermore, the control signals C1, C2, ..., CN sent to the circuits are simply referred to as control signal C when they are collectively named.

[0056] The control signal C can be a 1-bit signal of 1 ("High") or 0 ("Low") and is used to switch the respective switch on or off. Details of the transition management unit 25 and the management database 27 are described below.

[0057] Circuit 22 increases and decreases the induced current flowing through coil 23 by switching an internal switch on and off according to the control signal C above. Since the output voltage generated by the output current flowing through load 21 exhibits a large ripple due to the change in the induced current, it is smoothed by a capacitor 24 and brought to a voltage close to DC.

[0058] Here, the input currents Iin1 to IinN are input currents to the circuits 22-1 to 22-N, and the input currents Iin1 to IinN are simply referred to as input current Iin when they are referred to together.

[0059] The input current Iin and the input current IinS, which is the input current of the power supply circuit 210, are related to each other as follows. IinS=∑K=1NIinK

[0060] The conducted disturbance contained in the input current Iin of circuit 22 is therefore added in the same way, and it also follows from this equation that the sum thereof is transmitted to other electronic devices connected to battery 300. <Konfigurationsbeispiel des Schaltkreises>

[0061] Fig. Figure 4 is an explanatory diagram showing an example of a circuit in circuit 22 of Fig. 3 shows. Fig. Figure 5 is an explanatory diagram showing another example of the circuit in circuit 22 of Fig. 4 shows.

[0062] Fig. 4 and Fig. Figure 5 represents an example of a step-down circuit. The step-down circuit uses a switch to divide the DC input voltage into two phases and then smooths the divided voltage using an inductor and a capacitor (not shown) to obtain a desired DC output voltage.

[0063] The in Fig. Circuit 22, shown in Figure 4, is a synchronous step-down circuit and has switches 41 and 43. These switches 41 and 43 are each switched on and off by control signals C1H and C1L. The control signals C1H and C1L are, for example, supplied by the transition management unit 25 in Fig. 3 output. Ideally, the ON and OFF states of switches 41 and 43 are inversely proportional to each other.

[0064] The in Fig. Circuit 22 shown in Figure 5 represents an example of an asynchronous buck circuit and features a switch 41 and a diode 42. The difference to the one in Figure 5 is that... Fig. The difference in the synchronous circuit shown in section 4 lies in the fact that the switch connected to ground as the reference potential has been replaced by a diode 42; however, the basic operating principle remains the same. In circuit 22, the switch 41 is switched on and off by a control signal C1. The control signal C1 is, for example, supplied by the transition management unit 25. Fig. 3 issued.

[0065] The following describes the configuration of circuit 22, assuming it is an asynchronous buck circuit. Fig. 5. When using the synchronous step-down circuit, which is in Fig. As shown in Figure 4, a control signal must be added, since, as described above, two control signals C1H and C1L are required. The control signal to be added can be generated by inverting the original control signal, taking the dead time into account. <Konfigurationsbeispiel der Übergangsmanagementeinheit>

[0066] Fig. Figure 6 is a block diagram showing an example of the transition management unit 25 in the power supply circuit 210 of Fig. 3 shows.

[0067] For the sake of simplicity, a transition management unit 25 for three power supply channels is described here.

[0068] As in Fig. As shown in Figure 6, the transition management unit comprises 25 level conversion units 51-1 to 51-3, output fault detection units 52-1 to 52-3, control signal generation units 53-1 to 53-3, delay units 54-1 to 54-3, a reference voltage generation unit 55 and a transition determination unit 56.

[0069] In the following, the level shifting units 51-1 to 51-3 are referred to collectively as level shifting unit 51, and the output error detection units 52-1 to 52-3 are referred to collectively as output error detection unit 52. Furthermore, the control signal generation units 53-1 to 53-3 are referred to collectively as control signal generation unit 53, and the delay units 54-1 to 54-3 are referred to collectively as delay unit 54.

[0070] Furthermore, an output voltage correction unit is configured from a level conversion unit 51, an output error detection unit 52, a control signal generation unit 53 and a reference voltage generation unit 55.

[0071] The level shift unit 51 converts the output voltage Vout to the load so that the output voltage Vout is compatible with a reference voltage Vref. The level shift unit 51 outputs the converted voltage to the output fault detection unit 52. The reference voltage generation unit 55 generates the reference voltage Vref.

[0072] The output fault detection unit 52 outputs a difference between the voltage output by the level shift unit 51 and the reference voltage Vref generated by the reference voltage generation unit 55. The control signal generation unit 53 generates an intermediate control signal C' from the triangular wave input by the clock generation unit 26 and the difference output by the output fault detection unit 52. The intermediate control signal C' is a PWM signal. C1', C2', and C3' are intermediate control signals output by the control signal generation units 53-1, 53-2, and 53-3, respectively.

[0073] The intermediate control signal C' can be a 1-bit signal of 1 (high) or 0 (low) and is used to switch the switch on and off, respectively. Here, the time periods Tp1, Tp2, and Tp3 of the triangle waves, which are input by the clock generation unit 26 into the control signal generation units 53-1, 53-2, and 53-3, are set, for example, to times T, 2T, and 4T, respectively.

[0074] If the switching frequency, which is the inverse of the switching frequency, is increased, the switching loss increases and the power supply efficiency decreases, but the responsiveness to load fluctuations increases; conversely, if the switching frequency decreases, the opposite is true. In the description above, the power supply channel with Tp1 = T can be used for a CPU with a relatively low current draw but a relatively high operating frequency and large load fluctuations.

[0075] The power supply channel with Tp3 = 4T can be used for an FPGA (free programmable gate array) with relatively high current consumption, but relatively low operating frequency and low load fluctuations. The power supply channel with Tp2 = 2T can be used for a GPU (graphics processing unit), which is positioned in between.

[0076] Using a clock signal output by the clock generation unit 26, that is, with the cycle Ts = T / 10 as the trigger, the transition determination unit 56 samples the intermediate control signal C'. This clock signal is a measurement clock signal.

[0077] Then, from each sampled signal, a required delay amount for each power supply channel is derived by arithmetic processing, and a command signal is sent to the delay unit 54.

[0078] Details regarding the transition determination by the transition determination unit 56 are described below.

[0079] Here, an example is described in which, as a result of the arithmetic processing of the transition determination unit 56, the delay amounts of the command signals to the delay units 54-1, 54-2 and 54-3 are Td1 = 0, Td2 = 3Ts and Td3 = 5Ts, respectively.

[0080] The delay unit 54 receives the command signal with the delay amount issued by the transition determination unit 56 and delays the intermediate control signal C' accordingly. As a result, the delay units 54-1, 54-2 and 54-3 output the control signals C1 (= C1'), C2 (= C2' + 3Ts) and C3 (= C3' + 5Ts). <Transitional determination processing>

[0081] Fig. 7 is a flowchart that shows an example of the transition determination processing carried out by the transition management unit 25 of Fig. 6 is carried out.

[0082] The transition detection processing reduces the current ripple of the input current linS of the power supply circuit 210. An example is described here in which the transition management unit 25 detects an instantaneous value of the conducted disturbance. As in Fig. For the sake of simplicity, section 5 also describes a transition management unit 25 for three power supply channels.

[0083] When the transition determination processing starts, the transition management unit 25 first resets an internal counter value t of the transition management unit 25 to 0 and reads the control information of the set operating mode from the management database 27 (step S101). Details of this management database 27 are described below.

[0084] The processing then waits until a clock signal output by the clock generation unit 26 is received (step S102). When the clock signal is received, the counter value t is incremented, and C1'(t), C2'(t) and C3'(t) are obtained by sampling the intermediate control signals C1', C2' and C3' of each power supply channel according to the clock signal (step S103).

[0085] Then, based on these sampled values, currents lin1(t), lin2(t) and lin3(t), which are sampled values ​​of the input currents of circuits 22-1, 22-2 and 22-3, an input current IinS(t) of the power supply circuit and a change rate per unit of time ΔIin1(t), ΔIin2(t), ΔIin3(t) and ΔIinS(t) are calculated according to equations 2 to 5 below (step S104).

[0086] Here, ImN is a current coefficient, which is tax information read from the administrative database 27. IinN(t)=ImNCN'(t) IinS(t)=∑K=1NIinK(t) ΔIinN(t)=IinN(t)−IinN(t−1)Ts ΔIinS(t)=IinS(t)−IinS(t−1)TS

[0087] It is determined whether the absolute value of the change amount ΔIinS(t) per time period of the input current of the power supply circuit 210 is greater than a current change threshold value ΔIth, which is control information read from the management database 27 (step S105).

[0088] If the absolute value is below the threshold, processing proceeds to step S109, which is described below, and if the absolute value is above the threshold, processing is carried out in step S106 such that |ΔIinS(t)| is less than ΔIth.

[0089] That is, according to the priority information, which is a control information read from the administrative database 27, the ΔIinN(t) of the power supply channel with the highest priority is subtracted from ΔIinS(t).

[0090] Then ΔIinS(t) is replaced by the result of the subtraction, and the subtraction is repeated in the same way until the following equation is satisfied (step S106). In this example, the subtraction is performed according to priority order, but the subtraction can also be performed in order of the power supply channel with the larger |ΔIinN(t)|. |ΔIinS(t)|<ΔIth

[0091] Before the subtraction is performed with respect to all power supply channels, it is determined whether the above equation 6 is satisfied (step S107), and if the equation is not satisfied, a warning is issued to a host system, such as a control unit that manages the power supply (step S110). The processing then ends.

[0092] Otherwise, if the equation is satisfied, a command signal is sent to the delay unit 54 to delay the power supply channel on which the subtraction was performed by a delay amount TdN, which is control information read from the management database 27 (step S108).

[0093] Finally, during this series of processing steps, it is checked whether a command to switch the operating mode is received from the host system (step S109). If a switch command is present, the current processing is aborted, and if no switch command is present, the processing returns to step S102 to continue.

[0094] Although an example has been described here where an instantaneous value of the conducted disturbance is detected, a similar approach is also applicable where a time-averaged value is detected. For example, ΔIinN(t) and ΔIinS(t) can be replaced by a time-averaged value up to a counter value t, where the number of samples is constant. <Konfigurationsbeispiel der Verwaltungsdatenbank>

[0095] Fig. Figure 8 is an explanatory schematic representation that shows an example of a data configuration in the management database 27 of the power supply circuit 210 of Fig. 3 shows.

[0096] In the administrative database 27, each operating mode 72 is assigned tax information 73-1 to 73-6, which are parameters for the transition determination processing in these modes. Here, tax information 73-1 to 73-6 is simply referred to as tax information 73 when referred to collectively. The administrative database 27 is referenced by the transition management unit 25.

[0097] Here, operating mode 72 represents an application example for automatic driving and includes a mode A, which is a city driving mode, a mode B, which is a highway driving mode, a mode C, which is a parking mode, and a mode D, for example, when an anomaly of the control unit is detected.

[0098] In control information 73, which corresponds to these operating modes 72, control information 73-1 contains information about the detection mode of the line-borne fault. In this case, control information 73-1 is set so that in normal operation, i.e., in modes A to C, instantaneous value acquisition and average value acquisition are performed, while in the mode in case of an anomaly of the control unit, i.e., in emergency mode D, only instantaneous value acquisition is performed.

[0099] Control information 73-2, for example, stores information such as the time interval Ts for sampling the intermediate control information C'. Depending on the operating mode, the time interval can be set shorter to perform detection with higher accuracy, or it can be set longer to perform arithmetic processing with less delay.

[0100] If the time interval is variable, it can be controlled by sending a command signal to the clock generation unit 26 to generate a clock corresponding to the time interval. Alternatively, the clock generation unit 26 can generate a short-period timing control signal in advance, and the transition determination unit 56 can selectively use the timing control signals in a suitable manner.

[0101] Control information 73-3 stores information about the current change threshold ΔIth. For instantaneous value detection and average value detection, the current change threshold can be set separately as ΔIthpk and ΔIthav, respectively. These numerical values ​​are set, for example, by referencing the standard values ​​of the conducted disturbance.

[0102] The control information 73-4 stores information about the current coefficients Im1 to ImN for calculating the input current of each circuit 22. The current coefficients Im1 to ImN are set on the basis of the maximum current flowing through a load connected to each circuit 22, which is derived in advance, for example, by simulation or actual measurement.

[0103] Control information 73-5 stores information about the delay amounts Td1 to TdN for each power supply channel. The transition management unit 25 determines the delay amount by the delay unit 54 according to this information.

[0104] Control information 73-6 stores information about the priority of each power supply channel for transition management. The higher the priority, the greater the delay priority. In other words, the priority of the power supply channel that powers the core logic, which performs highly reliable operations, is set low.

[0105] As described above, the transition determination processing can be modified according to the operating mode. For example, the management database 27 can be updated and added to operating modes and control information for automated driving from a server in the cloud via an over-the-air (OTA) procedure over a wireless network.

[0106] When a directive is set on the server to add to a database, update data for the wireless communication unit 105 of the on-board system 10 is first sent. Fig. 1. The wireless communication unit 105 transmits the received update data to the transition management unit 25 of the autonomous driving control unit 201. This completes the processing for changing or supplementing operating modes and control information for automated driving.

[0107] This makes it possible to flexibly readjust the transition determination processing of the computational load required for the automatic driving operating mode, such as power and delay. Even if a new operating mode for automatic driving is added, transition management information used in the added operating mode can be subsequently added to the power supply circuit 210 without affecting the operating mode currently in use.

[0108] For example, the current change threshold ΔIth of the control information 73-3 of the vehicle environment or the arithmetic processing of the SoC 211 can be used. Fig. 2. Specifically, in Mode A, which is a city driving mode, the current change threshold ΔIth is adjusted according to the traffic congestion level on the road, depending on whether a traffic jam is present. This applies accordingly to Mode B, which is a highway driving mode. This makes it possible to generate a more precise control signal C, which enables a more accurate reduction of the conducted disturbance of the input current. <wirkungen>

[0109] The following describes the effects with reference to Fig. 9 and Fig. 10 described.

[0110] Fig. Figure 9 is a schematic representation showing an example of each signal waveform in the power supply circuit tested by the inventors.

[0111] Fig. Figure 9 shows an example of a transition management unit, whose Fig. Figure 7 shows that the transition determination processing has no function for controlling the delay and represents, from top to bottom, the signal timing control of each waveform of the control signals C1 to C3 output by the transition management unit, the input currents lin1 to lin3 to the circuits, and the input current linS of the power supply circuit. The horizontal axis represents the reference to Fig. 7 represents the described clock signal.

[0112] In this case, as in Fig. 6 described, the time periods Tp1, Tp2 and Tp3 of the control signals are T, 2T and 4T respectively, and the cycle Ts of the clock signal from the clock generation unit 26 is T / 10.

[0113] Due to the control signals C1 to C3, the input current to the circuits exhibits a behavior like lin1 to lin3, and linS is the waveform of the input current to the power supply circuit, which is the sum of these.

[0114] Here, the control signals C1, C2, and C3 increase at a point in Fig. 9 shown point A1 (t = 2 to 3) simultaneously switches from low to high, causing linS at point A3 to have a ΔIinS(3) that is greater than the current change threshold ΔIth set with respect to the standard value for conducted disturbance.

[0115] Furthermore, it can be seen that the control signal C1 and the control signal C2 are connected at a point A2 in Fig. 9 increase simultaneously. It follows that the conducted disturbance generated at point A4 is smaller than the disturbance generated at point A3, therefore reducing the conducted disturbance at point A3 has the highest priority.

[0116] Fig. Figure 10 is a schematic representation showing an example of each signal waveform in the power supply circuit 210 of the in Fig. Transition management unit 25 is shown in section 6.

[0117] Accordingly, it Fig. Figure 10, from top to bottom, represents the signal timing control of each waveform of the control signals C1 to C3 output by the transition management unit 25, the input currents lin1 to lin3 to the circuits 22, and the input current linS of the power supply circuit 210. The horizontal axis represents the reference to Fig. 7 represents the described clock signal.

[0118] In this case, the control signals C2 and C3 are replaced by the ones in Fig. 6 and Fig. 7 described transition determination processing in comparison to Fig. 9 each by 3Ts and 5Ts such that ΔIinS(3) does not exceed the current change threshold ΔIth.

[0119] This results in ΔIinS(3) at point A3 in Fig. 9 significantly reduced to below ΔIth, as in point B3 in Fig. 10 is shown. In contrast, ΔIinS at point B4 in Fig. 10 greater than at point B3, but lies below ΔIth.

[0120] Since, in the example of the present embodiment, the switching frequency of the third circuit is chosen to be an integer multiple of the switching frequency of the other two circuits, it is sufficient to perform the delay control only once, and there is hardly any need to perform a delay control thereafter. Although the switching frequencies of the three circuits all differ from each other here, a comparable effect can be achieved if only one of them is different.

[0121] In this way it is possible to effectively reduce conducted interference even in an automatic driving control unit that has a large number of power supply channels, by controlling the delay amount of the control signal on the basis of the total value of the change amounts of the input currents of the large number of circuits 22.

[0122] This enables the provision of a highly reliable electronic control unit, that is, an autonomous driving control unit 201. Furthermore, since no high-capacity input capacitor and the like are required, miniaturization and cost reduction can be achieved for the autonomous driving control unit 201. (Second embodiment)

[0123] In the first embodiment, the transition management unit 25 dynamically controls the delay of the control signal to reduce the conducted disturbance, but in the second embodiment a technique for carrying out static control is described. <Konfigurationsbeispiel der Übergangsmanagementeinheit>

[0124] Fig. Figure 11 is an explanatory schematic representation showing a configuration example of a transition management unit 25 according to the second embodiment.

[0125] The following describes the transition management unit 25, which differs significantly from that in the first embodiment, in particular with reference to Fig. 11 described. For the sake of simplicity, a transition management unit 25 is described here, which performs transition determination processing for three power supply channels.

[0126] As in Fig. As shown in Figure 11, the transition management unit comprises 25 level-shifting units 51-1 to 51-3, output fault detection units 52-1 to 52-3, control signal generation units 53-1 to 53-3, delay units 54-1 to 54-3, and a reference voltage generation unit 55. The transition management unit 25 of Fig. 11 differs from the transition management unit 25 from Fig. 6 according to the first embodiment in that no transition determination unit 56 is provided.

[0127] In the following, the level shifting units 51-1 to 51-3 are simply referred to as level shifting unit 51 when referred to collectively, and the output fault detection units 52-1 to 52-3 are simply referred to as output fault detection unit 52 when referred to collectively.

[0128] Furthermore, the control signal generation units 53-1 to 53-3 are simply referred to as control signal generation unit 53 when referred to collectively, and the delay units 54-1 to 54-3 are simply referred to as delay unit 54 when referred to collectively.

[0129] The level shift unit 51 converts the output voltage Vout to the load so that the output voltage Vout is compatible with a reference voltage Vref, and outputs the converted voltage to the output error detection unit 52 in the next stage. The output error detection unit 52 outputs a difference between the input voltage from the level shift unit 51 and the reference voltage Vref. The reference voltage generation unit 55 generates the reference voltage Vref.

[0130] The control signal generation unit 53 generates intermediate control signals C1', C2' and C3', which are PWM signals, from the triangle wave input by the clock generation unit 26 and the difference output by the output error detection unit 52.

[0131] Here are the time periods Tp1, Tp2 and Tp3 of the triangle waves, which are input from the clock generation unit 26 into the control signal generation units 53-1, 53-2 and 53-3, for example times T, 2T and 4T respectively.

[0132] The delay unit 54 outputs control signals C1, C2, and C3, which are obtained by delaying the intermediate control signals C1', C2', and C3' by predetermined delay amounts Td1, Td2, and Td3. The delay amounts of the delay unit 54 are preset.

[0133] These delay amounts are derived and set, for example when the switching frequencies are specified as above, by measuring or simulating in advance the delay amount of each circuit that ensures the conducted disturbance does not exceed the tolerance value.

[0134] Since the delay amount of the delay unit 54 is fixed, the power supply circuit 210 does not require a management database 27. Therefore, in this case, the power supply circuit 210 has a configuration that is obtained by retrieving the management database 27 from the one in Fig. The configuration of the first embodiment shown in point 3 is omitted.

[0135] This also results in a current waveform similar to that of Fig. 10 according to the first embodiment. This makes it possible to reduce conducted interference. In this example, the switching frequencies of the three circuits all differ from one another, but even if only one switching frequency is set differently from the others, the advantageous conducted interference suppression effect can be achieved.

[0136] Since the administrative database 27 and the transition determination unit 56 are eliminated as described above, it is possible to reduce the costs of the autonomous driving control unit 201. (Third embodiment)

[0137] In the first embodiment, the input current Iin of the circuit 22 is estimated using the intermediate control signal C, but in the third embodiment, a technique for directly measuring the input current Iin is described in order to control the conducted disturbance with high accuracy. <Konfigurationsbeispiel der Stromversorgungsschaltung>

[0138] In the following, a power supply circuit and a transition management unit, which differ from the first embodiment, are described in particular with reference to Fig. 12 and Fig. 13 described.

[0139] Fig. Figure 12 is a block diagram showing a configuration example of a power supply circuit 210 according to the third embodiment.

[0140] The power supply circuit 210 of Fig. 12 differs from the power supply circuit 210 in Fig. 3. This includes the provision of additional current sensors 28-1 to 28-N, which are current measuring units. The current sensors 28-1 to 28-N are simply referred to as current sensor 28 when they are referred to collectively.

[0141] The current sensors 28-1 to 28-N are each provided at input sections of the circuits 22-1 to 22-N and measure the input currents Iin1 to IinN.

[0142] The measurement results obtained by these current sensors 28 are sent to the transition management unit 25 and used in the transition determination processing described below. The current sensors 28 can use a current detection circuit comprising a current transformer, a Hall effect sensor, a giant magnetoresistance (GMR) element, or the like. For more accurate current measurement, an additional current sensor can be provided to measure the input current IinS of the power supply circuit 210. <Konfigurationsbeispiel der Übergangsmanagementeinheit>

[0143] Fig. Figure 13 is an explanatory schematic representation showing a configuration example of the transition management unit 25 in the power supply circuit 210 of Fig. 12 shows.

[0144] For the sake of simplicity, a transition management unit 25 is described here, which performs transition determination processing for three power supply channels.

[0145] The transition management unit 25 comprises level conversion units 51-1 to 51-3, output fault detection units 52-1 to 52-3, control signal generation units 53-1 to 53-3, delay units 54-1 to 54-3, a reference voltage generation unit 55 and a transition determination unit 56.

[0146] The level conversion unit 51 converts the output voltage Vout to the load so that the output voltage Vout is compatible with a reference voltage Vref generated by the reference voltage generation unit 55, and outputs the converted voltage to the output error detection unit 52 in the next stage.

[0147] The output fault detection unit 52 outputs a difference between the voltage output by the level shift unit 51 and the reference voltage Vref. The control signal generation unit 53 generates the intermediate control signals C1', C2' and C3', which are PWM signals, from the triangle wave input by the clock generation unit 26 and the difference output by the output fault detection unit 52.

[0148] Here are the time periods Tp1, Tp2 and Tp3 of the triangle waves, which are input from the clock generation unit 26 into the control signal generation units 53-1, 53-2 and 53-3, for example times T, 2T and 4T respectively.

[0149] Using a timing signal (cycle Ts = T / 10) output as a trigger by the clock generation unit 26, the transition determination unit 56 samples the input current Iin measured by the current sensor 28.

[0150] Then, by arithmetic processing, a required delay amount for each power supply channel is derived from these samples, and a command signal is sent to the delay unit 54. Here, the result of the arithmetic processing by the transition determination unit 56 is that command signals with delay amounts Td1 = 0, Td2 = 3Ts and Td3 = 5Ts are sent to the delay units 54-1, 54-2 and 54-3, respectively.

[0151] The delay unit 54 receives the command issued by the transition determination unit 56 with the specified delay amount and delays the intermediate control signal C' accordingly. As a result, the delay units 54-1, 54-2, and 54-3 output the control signals C1 (= C1'), C2 (= C2' + 3Ts), and C3 (= C3' + 5Ts).

[0152] Accordingly, the input current of the circuits 22 is measured by current sensors 28, and the delay amount of the control signal is preset on the basis of the total value of the change amounts so that it is possible to control the conducted disturbance of the input current with increased accuracy even in a control unit with a large number of power supply channels, that is, in the autonomous driving control unit 201.

[0153] This enables the provision of a highly reliable autonomous driving control unit 201. Since a large-capacity input capacitor or the like can be omitted, it is also possible to reduce the cost of the autonomous driving control unit 201 and achieve miniaturization.

[0154] Each of the configurations, functions, processing units, processing means, and the like described above can be implemented by hardware, for example, by implementing part or all of them using an integrated circuit. Each of the configurations, functions, and the like described above can also be implemented by software, by interpreting and executing a program that implements each function using a processor. Information such as a program, a table, a file, and the like, which implements each function, can be stored in a storage device such as memory, a hard disk drive, or a solid-state drive (SSD), or in a storage medium such as an IC card, an SD card, or a DVD.

[0155] Furthermore, control and data lines deemed necessary for the description were shown, but not necessarily all control and data lines required for a product were depicted. In practice, almost all components can be considered interconnected. List of reference symbols 10 On-board system 21 Last 22 Circuit 23 coil 24 Capacitor 25 Transition Management Unit 26 Clock generation unit 27 Administrative database 28 Current sensor 41 switches 42 Diode 43 switches 51 Level conversion unit 52 Output fault detection unit 53 Control signal generation unit 54 Delay unit 55 Reference voltage generation unit 56 Transitional determination unit 101 Camera 102 Radar 103 Vehicle position sensor 104 Button “automatic driving” 105 wireless communication unit 106 Auxiliary control unit 107 Brake control unit 108 Engine control unit 109 Power steering control unit 201 Autonomous driving control unit 210 Power supply circuit 215 Core Logic 216 I / O circuit 217 Core Logic 218 I / O circuit 219 Core Logic 220 I / O circuit 300 battery< / wirkungen>

Claims

Electronic control unit (201), comprising a plurality of logic circuits (215, 216, 217, 218, 219, 220) and a power supply unit (210) for powering the plurality of logic circuits, wherein the power supply unit (210) comprises a plurality of circuits (22) which each generate and output current based on a switching signal (C) with which the plurality of logic circuits (215, 216, 217, 218, 219, 220) is supplied, a transition management unit (5, 25) which controls the plurality of circuits (22), and a clock generation unit (26) which generates a plurality of clock signals, wherein the transition management unit (5, 25) comprises a control signal generation unit (53) which generates intermediate control signals (C') based on the clock signals generated by the clock generation unit (26), and a plurality of delay units (54) which are provided according to the plurality of circuits (22),to delay the respective intermediate control signal (C') based on a command signal and to output the delayed intermediate control signal (C1, C2, C3) as a switching signal, and the plurality of clock signals generated by the clock generation unit (26) includes at least one clock signal having a different frequency, characterized in that the transition management unit (5, 25) has a transition determination unit (56) that generates the command signal based on preset control information, and the transition determination unit (56) calculates a total value of the change amounts of the input currents of the plurality of circuits (22) based on the command signal and compares the calculated total value with a preset current change threshold in order to control a delay amount in the delay unit such that the compared total value is less than the current change threshold. Electronic control unit according to claim 1, wherein the transition determination unit (56) calculates the total value of the change amounts of the input currents of the plurality of circuits (22) from the intermediate control signals (C') generated by the control signal generation unit (53). Electronic control unit according to claim 1, wherein the power supply unit (210) has a current measuring unit (28-1, 28-N) which measures an input current which is fed into the plurality of circuits (22), and the transition determination unit (56) calculates the total value of the change magnitudes of the input currents from the measurement results of the currents measured by the current measuring unit (28-1, 28-N). Electronic control unit according to claim 1, wherein the transition determination unit (56) determines whether the input currents rise or fall synchronously with a measurement clock signal and calculates the total value of the change amounts of the input currents from the determination result. Electronic control unit according to claim 1, wherein the current change threshold compared by the transition determination unit (56) is a different value for each operating mode of the control unit. Electronic control unit according to claim 1, wherein the power supply unit (210) has a management database (27) which stores control information, the management database (27) stores at least one of a current coefficient used in the calculation of the input current, a respective delay amount for each of the circuits or a priority of the circuits (22) to be delayed, and the current coefficient, the delay amount or the priority stored in the management database (27) are set for each operating mode of the electronic control unit. Electronic control unit according to claim 1, wherein the transition management unit (5, 25) has an output voltage correction unit which detects an error in each output voltage generated by the plurality of circuits (22) and corrects the intermediate control signal (C') on the basis of the detection result in order to reduce the error in the output voltage. On-board system with an autonomous driving control unit that controls the autonomous driving of a vehicle, wherein the autonomous driving control unit is an electronic control unit according to one of the preceding claims. On-board system according to claim 8, wherein the current change threshold compared by the transition determination unit (56) is a different value for each operating mode of the autonomous driving control unit. Power supply device comprising: a plurality of circuits (22) that generate and output current based on a switching signal (C), which supplies the plurality of logic circuits; a transition management unit (5, 25) that controls the plurality of circuits; and a clock generation unit (26) that generates a plurality of clock signals, wherein the transition management unit (5, 25) comprises a control signal generation unit that generates an intermediate control signal based on the clock signals generated by the clock generation unit (26), and a plurality of delay units, each provided corresponding to the plurality of circuits, to delay the intermediate control signal based on a command signal and to output the delayed intermediate control signal as a switching signal, and the plurality of clock signals generated by the clock generation unit (26) comprise at least one clock signal having a different frequency.characterized in that the transition management unit (5, 25) has a transition determination unit (56) which generates the command signal based on preset control information, and the transition determination unit (56) calculates a total value of the change amounts of the input currents of the plurality of circuits based on the command signal and compares the calculated total value with a preset current change threshold in order to control a delay amount in the delay unit such that the compared total value is less than the current change threshold.

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