Semiconductor device

Abstract

Semiconductor device (100), comprising: a semiconductor substrate (10); a transistor section (70) and a diode section (80) arranged on the semiconductor substrate (10), wherein the transistor section (70) includes a gate trench section (40) arranged extending in a direction of extension which differs in plan view from the direction of arrangement; several terminal pads arranged above a top surface (21) of the semiconductor substrate (10) and arranged in an arrangement direction between a region in which the transistor section (70) or the diode section (80) is arranged and a first end face on the top surface (21) of the semiconductor substrate (10); and a gate runner section that transmits a gate voltage to the transistor section (70), wherein: The Gate Runner section contains: a first gate runner (50) which, in plan view, is arranged extending between the first end face of the semiconductor substrate (10) and at least one of the terminal surfaces; and a second gate runner (51) which, in plan view, is arranged between at least two of the several terminal surfaces and the transistor section (70), the transistor section (70) is also arranged in at least one of those intermediate terminal area regions (130) which are inserted between two terminal areas in plan view, the gate trench section (40), which is arranged in at least one intermediate connection area (130), is connected to the first gate runner (50), and the gate trench section (40), which is arranged so that it faces the second gate runner (51) in the direction of extension, is connected to the second gate runner (51).

Description

BACKGROUND 1. TECHNICAL AREA

[0001] The present invention relates to a semiconductor device. 2. STATE OF THE ART

[0002] A semiconductor device has been proposed to date in which a transistor device, such as an insulated-gate bipolar transistor (IGBT), and a diode device, such as a freewheeling diode (FWD), are arranged on the same semiconductor substrate (see, for example, patent document 1). Several terminal pads are arranged on the semiconductor substrate, which are connected to the transistor device, the diode device, or the like. The prior art documents include the following documents. Patent document 1: JP 2017 - 147 435 A Patent document 2: JP 2017 - 069 412 A Patent document 3: JP 2017 - 069 412 A Patent document 4: US 2015 / 0 325 558 A1 Patent document 5: WO 2018 / 030 440 A1 TECHNICAL TASK

[0003] Several connection pads are arranged along any one side of a semiconductor substrate. In a semiconductor device, an intermediate connection pad area is preferably used efficiently.

[0004] To solve the problem described above, a semiconductor device according to claim 1 is provided according to a first aspect of the present invention. A semiconductor device according to claim 2 is provided according to a second aspect of the present invention. A semiconductor device according to claim 3 is provided according to a third aspect of the present invention. Further aspects of the invention are the subject of the dependent claims, the drawings, and the description of exemplary embodiments.

[0005] The second gate runner can be arranged on at least two sides of at least one of the connection surfaces.

[0006] The distance between each contact surface and the second gate runner can be 200 µm or less in the top view.

[0007] The diode section can contain a cathode region of a first conductivity type, which is exposed on one underside of the semiconductor substrate. The cathode region cannot be located in the inter-terminal area.

[0008] The transistor section may include a first-type conductivity emitter region exposed on the top surface of the semiconductor substrate and in contact with the gate-trough section. The semiconductor device may include an emitter electrode positioned above the top surface of the semiconductor substrate and connected to the emitter region. The diode section may include blind-trough sections extending in the direction of extension and connected to the emitter electrode. At least one of the blind-trough sections, positioned facing the inter-terminal areas in the direction of extension, may be arranged to extend to a corresponding inter-terminal area.

[0009] The transistor section can include a first-type conductivity emitter region exposed on the top side of the semiconductor substrate and in contact with the gate-trough section. The semiconductor device can include an emitter electrode arranged above the top side of the semiconductor substrate and connected to the emitter region. The diode section can include a first-type conductivity cathode region exposed on a bottom side of the semiconductor substrate. The diode section can include a blind-trough section extending in the direction of extension and connected to the emitter electrode. The cathode region and the blind-trough section can be located in at least one of the inter-terminal areas.

[0010] The transistor section may contain an emitter region of the first conductivity type, exposed on the top side of the semiconductor substrate and in contact with the gate-trough section. At least the gate-trough section nearest to either of the two terminals in the inter-terminal area may not have the emitter region in contact with the gate-trough section in the inter-terminal area.

[0011] The transistor section can include a type-first conductivity emitter region exposed on the top surface of the semiconductor substrate and in contact with the gate-trough section. The semiconductor device can include an emitter electrode positioned above the top surface of the semiconductor substrate and connected to the emitter region. The semiconductor device can include a dielectric interlayer film positioned between the semiconductor substrate and the emitter electrode. A contact hole connecting the emitter electrode to the semiconductor substrate can be located in the dielectric interlayer film between the gate-trough section nearest one of the two terminal faces in the inter-terminal area and the terminal face.

[0012] A blind trench section connected to the emitter electrode can be arranged between the gate trench section, which is the nearest to one of the two terminal faces in the intermediate terminal face area, and the terminal face.

[0013] Each of the multiple connection surfaces can be arranged in such a position that the connection surface is at least partially facing the diode section in the direction of extension.

[0014] The summary section does not necessarily describe all necessary features of the embodiments of the present invention. The present invention may also be a subcombination of the features described above. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a drawing illustrating the structure of a top surface of a semiconductor device 100 according to an embodiment of the present invention. Fig. Figure 2 is an enlarged view of an area surrounding a region A in Fig. 1. Fig. 3 is a drawing that shows an example of one along BB in Fig. 2. Cross-section taken is illustrated. Fig. Figure 4 is an enlarged view of an area surrounding a region B in Fig. 1. Fig. Figure 5 is an enlarged view of an area surrounding a region C in Fig. 1. Fig. Figure 6 is a drawing illustrating an example arrangement of an emitter electrode 52 in a top view. Fig. Figure 7 is a drawing illustrating an example arrangement of a cathode region 82. Fig. Figure 8 is an enlarged view of an area surrounding a region D in Fig. 7. Fig. Figure 9 is a drawing illustrating another arrangement example of the cathode region 82. Fig. Figure 10 is an enlarged view of an area surrounding a region E in Fig. 9. Fig. Figure 11 illustrates another example of area B in Fig. 1. Fig. Figure 12 is a drawing illustrating an arrangement example of the gate trench sections 40 in an active main section 120 and an intermediate connection area 130. Fig. Figure 13 is a drawing illustrating another arrangement example of the gate trench sections 40 in the active main section 120 and the intermediate connection area 130. Fig. Figure 14 is a drawing illustrating another arrangement example of the gate trench sections 40 in the active main section 120 and the intermediate connection area 130. DESCRIPTION OF EXAMPLE FORMS OF EXECUTION

[0015] The present invention is described below with regard to embodiments.

[0016] In this description, one side oriented in a direction parallel to a depth direction of a semiconductor substrate is referred to as a "top" side, while the other side is referred to as a "bottom" side. A surface of two principal surfaces of a substrate, layer, layer, or other component is referred to as a top surface, while the other surface is referred to as a bottom surface. The "top" and "bottom" directions are not limited to the direction of gravity or a mounting direction at the time of mounting a semiconductor device onto the substrate or the like.

[0017] According to the present description, technical objects can in some cases be described using orthogonal coordinate axes of an X-axis, a Y-axis, and a Z-axis. According to the present description, a plane parallel to a top surface of the semiconductor substrate is defined as an XY plane, while the depth direction perpendicular to the top surface of the semiconductor substrate is defined as the Z-axis.

[0018] Examples are illustrated according to the respective embodiments in which a first conductivity type is defined as an N-type and a second conductivity type is defined as a P-type, but the first conductivity type may also be defined as the P-type and the second conductivity type may also be defined as the N-type. In this case, the conductivity types of a substrate, layer, region, and the like, according to the corresponding embodiments, each have opposite polarities. Additionally, in a case where a P+ type (or an N+ type) is described in the present description, it means that the doping concentration is higher than that of the P-type (or the N-type), while in a case where a P- type (or an N- type) is described, it means that the doping concentration is lower than that of the P-type (or the N-type).

[0019] The doping concentration in this description refers to the concentration of impurities that have been transformed into donors or acceptors. In some cases, the difference between the concentrations of donors and acceptors may be defined as the doping concentration. Additionally, in some cases, a peak value of a doping concentration distribution within a doping region may be defined as the doping concentration within that region.

[0020] Fig. Figure 1 is a drawing illustrating the structure of a top surface of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 comprises a semiconductor substrate 10. The semiconductor substrate 10 can be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate, such as gallium nitride or the like. The semiconductor substrate 10 in this example is a silicon substrate.

[0021] In this description, an end section of an outer circumference of the semiconductor substrate 10 is defined as an outer circumference end 140 in a top view. The top view refers to a case in which the observation is made from a side of the top surface of the semiconductor substrate 10 parallel to the Z-axis. Additionally, any of the end faces at the outer circumference end 140 of the semiconductor substrate 10 is defined as a first end face 142 in the top view. A direction parallel to the first end face 142 in the top view is defined as an X-axis direction, while a direction perpendicular to the first end face 142 is defined as a Y-axis direction.

[0022] The semiconductor device 100 comprises an active main section 120 and an edge termination section 90. The active main section 120 corresponds to a region within an active area where a current flows in the depth direction within the semiconductor substrate 10 from the top of the semiconductor substrate 10 to the bottom or from the bottom to the top, except for an intermediate termination area 130, which is described. The active area is, for example, a region in which, in a case where a transistor device contained in the semiconductor device 100 is controlled to be in an on-state, or in a case where the transistor device is switched from the on-state to an off-state, a main current flows between the top and bottom of the semiconductor substrate 10.The active main section 120 can also refer to an area excluding the connection surfaces and the intermediate connection surface area 130 in an area surrounded by a first gate-runner 50, which is described below.

[0023] A transistor section 70 and a diode section 80 are arranged in the active main section 120. In the present description, both the transistor section 70 and the diode section 80 may in some cases be referred to as a device section or a device area. In this example, the transistor sections 70 and the diode sections 80 are arranged alternately in the active main section 120 in the direction of the X-axis.

[0024] Several connection pads are located above the top surface of the semiconductor substrate 10 (in the example according to Fig. 1. A scanning pad 114, an emitter pad 115, a gate pad 116, a cathode pad 117, and an anode pad 118 are arranged. The scanning pad 114 is connected to a current sensing device 119. The current sensing device 119 has the same structure as the transistor section 70 and, in plan view, also has a smaller area (corresponding to the area of ​​the channel) than the transistor section 70. If a current flowing through the current sensing device 119 is detected, a current flowing through the entire semiconductor device 100 can be estimated. The emitter pad 115 is connected to an emitter electrode arranged above the top surface of the semiconductor substrate 10. The gate pad 116 is connected to a gate electrode of the transistor section 70.In this example, the gate terminal 116 is connected to a gate runner section, which is described below. The cathode terminal 117 and the anode terminal 118 are connected to a temperature sensing section 110, which is described below. It is stated that the number and type of terminals arranged in the semiconductor substrate 10 do not depend on the one shown in the figure. Fig. The illustrated example is limited.

[0025] Each of the contact surfaces is made of a metallic material, such as aluminum. The multiple contact surfaces are arranged in a predetermined orientation between the active main section 120 and the first end face 142 on the top surface of the semiconductor substrate 10. In this example, the multiple contact surfaces are arranged such that they are inserted along the Y-axis between the device area and the first end face 142.

[0026] The arrangement direction of the multiple connection surfaces can be a straight line connecting the centers of two connection surfaces (in this example, the scanning connection surface 114 and the anode connection surface 118), which are arranged in plan view at both ends in a direction parallel to the first end face 142, beneath the multiple connection surfaces. The arrangement direction can be parallel to the first end face 142. The arrangement direction can also have an inclination of up to 30 degrees with respect to the first end face 142. The inclination can be up to 20 degrees and can also be up to 10 degrees. The arrangement direction in this example is parallel to the first end face 142.

[0027] The area enclosed in the plan view by two connection surfaces is defined as the intermediate connection surface area 130. In this example, the intermediate connection surface area 130 is an overlapping area in which two connection surface areas extend towards the mutual connection surfaces in a direction parallel to the X-axis. In this example, an area between the overlapping area and the first gate runner 50, which is arranged along the first end face 142, is also included in the intermediate connection surface area 130.

[0028] In the semiconductor device 100, the device area is also arranged in at least one of the inter-terminal areas 130. In this example, the transistor section 70 is arranged in at least one of the inter-terminal areas 130. In accordance with the structure mentioned above, the area of ​​the device area can be increased by the effective use of the inter-terminal areas 130.

[0029] The semiconductor device 100 contains the gate runner section, which transmits a gate voltage to the transistor section 70. In this example, the semiconductor device 100 includes a first gate runner 50, a second gate runner 51, and a third gate runner 48 as the gate runner sections. In this example, each of the gate runners is arranged above the top surface of the semiconductor substrate 10 and insulated from the top surface of the semiconductor substrate 10 by a dielectric interlayer film.

[0030] The first gate runner 50 is arranged in a top view between the first end face 142 of the semiconductor substrate 10 and at least one of the terminal pads. In this example, the first gate runner 50 is arranged parallel to the first end face 142, which runs between each of the scanning terminal pad 114, the emitter terminal pad 115, the gate terminal pad 116, the cathode terminal pad 117, and the anode terminal pad 118 and the first end face 142. The first gate runner 50 is connected to the gate terminal pad 116.

[0031] Additionally, the first gate runner 50 is arranged such that it surrounds the active main section 120 between the other end face of the semiconductor substrate 10 and the active main section 120. In other words, the first gate runner 50 in this example is arranged circularly along each end face of the semiconductor substrate 10. The gate runner 50 can be a metallic wiring, such as aluminum, or it can also be a semiconductor wiring, such as polysilicon, into which impurities are doped. The first gate runner 50 can have a structure in which the metallic wiring and the semiconductor wiring are arranged to overlap with an intervening dielectric film. A contact hole connecting the metallic wiring to the semiconductor wiring is located in the dielectric film. The first gate runner 50 in this example is a metallic wiring.

[0032] The material of the second gate runner 51 and the third gate runner 48 can be similar to the material described for the first gate runner 50. In this example, the second gate runner 51 is a metallic wiring, while the third gate runner 48 is a semiconductor wiring.

[0033] The second gate runner 51 is arranged in the top view between at least one of the terminal pads and the transistor section 70. The at least one of the terminal pads is a terminal pad other than the emitter terminal pad 115. In this example, the second gate runner 51 is arranged with respect to all terminal pads except the emitter terminal pad 115. The second gate runner 51 is arranged such that it is inserted through the terminal pad and the active main section 120 (i.e., the transistor section 70 and the diode section 80) in the direction of the Y-axis. In any of the terminal pads, the second gate runner 51 can be arranged along two or more sides of the terminal pad.

[0034] In a terminal surface (in this example the anode terminal surface 118) which is arranged at one end in the direction of the X-axis, the second gate runner 51 is arranged along two intersecting sides, and the first gate runner 50 is also arranged along the other two sides.

[0035] Additionally, the current sensing device 119 is located in the intermediate terminal area 130 between a terminal (in this example, the sensing terminal 114) located at the other end in the direction of the X-axis and the emitter terminal 115. The transistor section 70 and the diode section 80 cannot be located in the intermediate terminal area 130 where the current sensing device 119 is located. In one example, a pot region of the P+ type, which is described below, can be located in the region where the current sensing device 119 is not located in the intermediate terminal area 130.

[0036] Each connection surface in this example contains two pairs of parallel sides in the top view. In the example according to Fig. 1 Each terminal area contains two sides parallel to the X-axis and two sides parallel to the Y-axis. The gate runner section cannot be located on a side facing the current sensing device 119 beneath the sides of the terminal area. In the sensing terminal area 114 in this example, the second gate runner 51 is located along a side facing the active main section 120. The gate runner section is not located on the side facing the current sensing device 119, with the first gate runner 50 located along the other two sides. The second gate runner 51, located along the sensing terminal area 114, can be connected via the third gate runner 48 to the second gate runner 51 located along the other terminal area.

[0037] More specifically, the two second gate runners 51, which are arranged in the two connection areas (in this example, the scanning connection area 114 and the gate connection area 116), which are arranged so that they align with the emitter connection area 115 in the direction of the X-axis, can be connected to each other via the third gate runner 48. The third gate runner 48 is arranged between the active main section 120 and the emitter connection area 115 and the intermediate connection area 130 in the direction of the Y-axis.

[0038] Additionally, the second gate runner 51 is arranged along three sides, excluding the side facing the first end face 142, in the connection surfaces (in this example, the gate connection surface 116 and the cathode connection surface 117), which are arranged in the direction of the X-axis at positions except for the two ends, with the first gate runner 50 being arranged along the side facing the first end face 142. The gate runner sections arranged around each connection surface are interconnected to form a circular enclosure around the connection surface.

[0039] The transistor section 70 contains a gate trench section extending in a direction (in this example, the direction of the Y-axis) that differs in plan view from the orientation of the arrangement. A structure of the gate trench section is described below. The gate trench section located in the inter-terminal area 130 is directly or indirectly connected to the first gate runner 50, which is arranged along the first end face 142. In other words, the gate trench section located in the inter-terminal area 130 extends in the direction of the Y-axis to a position where the gate trench section can be directly or indirectly connected to the first gate runner 50, which is arranged along the first end face 142 of the semiconductor substrate 10.

[0040] Additionally, the gate trench section of the active main section 120, which is arranged such that it faces the second gate runner 51 in the direction of extension (direction of the Y-axis), is directly or indirectly connected to the second gate runner 51. In other words, the gate trench section, which is arranged such that it faces the second gate runner 51 in the direction of the Y-axis, and which extends in the direction of the X-axis between the connection surface and the active main section 120, is directly or indirectly connected to the second gate runner 51.

[0041] In accordance with the configuration mentioned above, the gate trench section of the transistor section located in the active main section 120 and the intermediate terminal area 130 can be connected to the gate runner section. It is stated that if the first gate runner 50 and the second gate runner 51 are configured as the metallic connections, the variation in the timing of the gate voltages being transmitted to the corresponding gate trench sections and the variation in the damping values ​​of the gate voltages can be reduced.

[0042] Additionally, among the gate trench sections arranged in the active main section 120, the gate trench section located at a position facing the third gate runner 48 in the direction of the Y-axis can be connected to the third gate runner 48. Additionally, the gate trench section located at a position facing the first gate runner 50, which is arranged along the end face opposite the first end face 142, can be directly or indirectly connected to the first gate runner 50.

[0043] Transistor section 70 contains a transistor, such as an IGBT. Diode section 80 and transistor sections 70 are arranged alternately on the top side of semiconductor substrate 10 in the direction of the X-axis. An N+-type cathode region is located in each of the diode sections 80 in a region in contact with the underside of semiconductor substrate 10. The area is defined by a solid line in Fig. The diode section 80 shown is a region in which the cathode region is located on the underside of the semiconductor substrate 10. In the semiconductor device 100 in this example, the regions, with the exception of the cathode region, below the areas in contact with the underside of the semiconductor substrate are collector regions of the P+ type.

[0044] Diode section 80 is a region where the cathode region protrudes in one direction of the Z-axis. Transistor section 70 is a region where the collector region is formed on the underside of the semiconductor substrate 10, with a unit structure containing an N+-type emitter region being periodically formed on the top side of the semiconductor substrate 10. A region obtained by extending the area where the cathode region protrudes in the Z-axis direction into the active region in the Y-axis direction can also be defined as diode section 80. A region other than diode section 80 can also be defined as transistor section 70. A boundary between diode section 80 and transistor section 70 in the X-axis direction is a boundary between the cathode region and the collector region.

[0045] The transistor section 70 can be arranged at both ends of the active main section 120 in the direction of the Y-axis. The active main section 120 can be divided by the third gate runner 48 in the direction of the Y-axis. In the respective divided regions of the active main section 120, the transistor sections 70 and the diode sections 80 are arranged alternately in the direction of the X-axis. In the example according to Fig. The active main section 120 is divided into three parts by two parts of the third gate runner 48, which extends in the direction of the X-axis. Additionally, the third gate runner 48, which is made of a semiconductor, can also be arranged along the first gate runner 50 and the second gate runner 51, which are made of a metal.

[0046] The edge termination section 90 is located between the first gate runner 50 and the outer circumferential end 140 of the semiconductor substrate 10 on the top side of the semiconductor substrate 10. The edge termination section 90 can be arranged in a circular pattern to surround the first gate runner 50 on the top side of the semiconductor substrate 10. In this example, the edge termination section 90 is arranged along the outer circumferential end 140 of the semiconductor substrate 10. The edge termination section 90 reduces the concentration of the electric field on the top side of the semiconductor substrate 10. The edge termination section 90 may include, for example, a guard ring structure, a field plate, a RESURF, or a combination thereof.

[0047] The semiconductor device 100 in this example includes the temperature sensing section 110 and the temperature sensing wires 112-1 and 112-2. The temperature sensing section 110 is arranged above the active main section 120. The temperature sensing section 110 can be located in the center of the active main section 120 in the top view of the semiconductor substrate 10. Alternatively, the temperature sensing section 110 can be located above the transistor section 70 in the top view of the semiconductor substrate 10. The temperature sensing section 110 senses the temperature of the active main section 120. The temperature sensing section 110 can be a pn-type temperature diode made of monocrystalline or polycrystalline silicon.

[0048] The temperature sensing wiring 112 is arranged above the active main section 120. The temperature sensing wiring 112 can be semiconductor wiring. The temperature sensing wiring 112 is connected to the temperature sensing section 110. The temperature sensing wiring 112 extends to a region between the active main section 120 and the outer circumferential end 140 on the top surface of the semiconductor substrate 10 and is connected to the cathode terminal 117 and the anode terminal 118. It is stated that the semiconductor device 100 may not include the temperature sensing section 110 and the temperature sensing wiring 112. Furthermore, the semiconductor device 100 may not include the current sensing device 119.

[0049] Fig. Figure 2 is an enlarged view of an area surrounding a region A in Fig. 1. Region A comprises transistor section 70, diode section 80, first gate runner 50, and edge termination section 90. In this example, the third gate runner 48 is arranged along the first gate runner 50. The third gate runner 48 can be positioned between the first gate runner 50 and the semiconductor substrate 10. The first gate runner 50, the third gate runner 48, and the semiconductor substrate 10 are isolated from each other by the dielectric interlayer films. The semiconductor device 100 in this example includes a guard ring 92, a gate trench section 40, a blind trench section 30, a pot region 11 of the P+ type, an emitter region 12 of the N+ type, a base region 14 of the P- type and a contact region 15 of the P+ type, which are arranged within the semiconductor substrate 10 and are exposed on the top side of the semiconductor substrate 10.In the present description, the gate trench section 40 or the blind trench section 30 may in some cases simply be referred to as a trench section. Additionally, in this example, the semiconductor device 100 includes an emitter electrode 52 and the first gate runner 50, which are arranged above the top surface of the semiconductor substrate 10. The emitter electrode 52 and the first gate runner 50 are arranged to be separated from each other.

[0050] The edge termination structure section 90 is located on the outer side of the first gate runner 50 (the positive side along the Y-axis). As described above, the edge termination structure section 90 can contain one or more guard rings 92. The guard ring 92 is a P-type region formed within the semiconductor substrate 10. The guard ring 92 is arranged in a circular shape, such that it surrounds the first gate runner 50 on its outer side.

[0051] The dielectric interlayer film is formed between the emitter electrode 52 and the first gate runner 50 and the top surface of the semiconductor substrate 10, but this is in Fig. 2 omitted. In this example, a contact hole 56, a contact hole 49 and a contact hole 54 are formed by the dielectric interlayer film.

[0052] The emitter electrode 52 is in contact with the emitter zone 12, the contact area 15, and the base zone 14 on the top surface of the semiconductor substrate 10 via the contact hole 54. Additionally, the emitter electrode 52 is connected via the contact hole 56 to a conductive blank section within the blank trench section 30. A connecting section 25, made of a conductive material such as polysilicon with impurities doped into it, can be arranged between the emitter electrode 52 and the conductive blank section. A dielectric film, such as an oxide film, is formed between the connecting section 25 and the top surface of the semiconductor substrate 10.

[0053] The first gate runner 50 is connected to the third gate runner 48 via the contact hole 49, which is located in the dielectric interlayer film. The third gate runner 48 is connected to a conductive gate section within the gate trench section 40. The third gate runner 48 is not connected to the conductive blind section within the blind trench section 30. In this example, the gate trench section 40 extends along the Y-axis to a position such that it overlaps with the third gate runner 48, while the blind trench section 30 extends along the Y-axis to a region where it does not overlap with the third gate runner 48.

[0054] The third gate runner 48, arranged along the first gate runner 50, extends in the Y-axis direction from a position where it overlaps the first gate runner 50 to a position where it does not. The third gate runner 48 is connected to the gate trench section 40 at a position where it does not overlap the first gate runner 50. It is stated that the semiconductor device 100 may not include the third gate runner 48 arranged along the first gate runner 50. In this case, the gate trench section 40 may be directly connected to the first gate runner 50.

[0055] In the present description, a state in which the gate trench section 40 is directly connected to the first gate runner 50 (or the second gate runner 51) refers to a state in which the gate trench section 40 is arranged such that it extends to a position where the gate trench section overlaps with the first gate runner 50 (or the second gate runner 51), and the gate trench section 40 is connected to the first gate runner 50 (or the second gate runner 51) via the contact hole.A state in which the gate trench section 40 is indirectly connected to the first gate runner 50 (or the second gate runner 51) refers to a state in which the third gate runner 48, which overlaps with the first gate runner 50 (or the second gate runner 51), is arranged extending in the direction of the Y-axis to a position where the third gate runner does not overlap with the first gate runner 50 (or the second gate runner 51), and the gate trench section 40 is connected to the first gate runner 50 (or the second gate runner 51) via the third gate runner 48. It is stated that in a case where the gate trench section 40 is indirectly connected to the first gate runner 50, the gate trench section 40 and the third gate runner 48 are connected to each other in the vicinity of the first gate runner 50.A distance along the Y-axis between a connection point of gate trench section 40 and the third gate runner 48 and the first gate runner 50 can be 10 times the width of the first gate runner 50 or shorter, or it can also be 5 times the width of the first gate runner 50 or shorter. Similarly, if gate trench section 40 is indirectly connected to the second gate runner 51, gate trench section 40 and the third gate runner 48 are connected in the vicinity of the second gate runner 51. A distance in the direction of the Y-axis between the connection point of the gate trench section 40 and the third gate runner 48 and the second gate runner 51 can be 10 times as long as the width of the second gate runner 51 or shorter in the direction of the Y-axis, or it can also be 5 times as long as the width of the second gate runner 51 or shorter.In the present description, the direct and the indirect connection may in some cases be referred to collectively as the connection.

[0056] In this example, the emitter electrode 52 and the first gate runner 50 are formed from a material containing a metal. At least one section of a region of each electrode is formed, for example, from aluminum or an aluminum-silicon alloy. Each electrode may contain a barrier metal formed from titanium, a titanium compound, or the like, arranged beneath a region formed from aluminum or the like, and may also contain a plug formed from tungsten or the like within the contact hole.

[0057] One or more gate trench sections 40 and one or more blind trench sections 30 are arranged at a predetermined interval along a predetermined orientation (in this example, the direction of the X-axis) on the top surface of the semiconductor substrate 10. In the transistor section 70 in this example, the one or more gate trench sections 40 and the one or more blind trench sections 30 are arranged alternately along the orientation.

[0058] The gate trench section 40 in this example can comprise two linear sections 39 extending linearly along the direction of extension (in this example, the direction of the Y-axis) perpendicular to the arrangement direction, and an edge section 41 connecting the two linear sections 39. At least one section of the edge section 41 is preferably configured to be curved on the top surface of the semiconductor substrate 10. In the two linear sections 39 of the gate trench section 40, the concentration of the electric field at the end sections of the linear sections 39 can be attenuated because the end sections, each of which is an end of a linear shape along the direction of extension, are connected by the edge section 41.

[0059] At least one of the blind trench sections 30 is arranged between the respective linear sections 39 of the gate trench section 40. These blind trench sections 30 can contain a linear section 29 and a boundary section 31 similar to the gate trench section 40. In another example, the blind trench section 30 can contain the linear section 29 and not the boundary section 31. In the example in Fig. In the illustrated example 3, the two linear sections 29 of the blind trench section 30 are arranged in the transistor section 70 between the two linear sections 39 of the gate trench section 40.

[0060] In the diode section 80, the multiple blind trench sections 30 are arranged on the top surface of the semiconductor substrate 10 along the direction of the X-axis. One shape of the blind trench section 30 in the diode section 80 in the XY plane can be similar to that of the blind trench section 30 arranged in the transistor section 70.

[0061] The edge section 31 and the linear section 29 of the blind-trough section 30 have similar shapes to those of the edge section 41 and the linear section 39 of the gate-trough section 40. The blind-trough section 30 arranged in the diode section 80 and the linearly shaped blind-trough section 30 arranged in the transistor section 70 can have the same length in the direction of the Y-axis.

[0062] The emitter electrode 52 is formed above the gate trench section 40, the blind trench section 30, the pot area 11, the emitter zone 12, the base zone 14, and the contact area 15. The pot area 11 and one of the ends of the contact hole 54 in the extension direction, which is located closer to the position of the first gate runner 50, are arranged apart in the XY plane. The diffusion depth of the pot area 11 can be greater than both the depth of the gate trench section 40 and the depth of the blind trench section 30. The portions of the areas of the gate trench section 40 and the blind trench section 30 in the vicinity of the first gate runner 50 are formed in the pot area 11. A bottom of the edge section 41 of the gate trench section 40 in the direction of the Z-axis and a bottom of the edge section 31 of the blind trench section 30 in the direction of the Z-axis can be covered with the pot area 11.

[0063] One or more mesa sections 60, inserted through the respective trench sections, are arranged in each of the transistor section 70 and the diode section 80. The mesa section 60 refers to an area above the bottom of the trench section, where the trench section is deepest, in the region of the semiconductor substrate 10 inserted through the trench sections.

[0064] Base zone 14 is formed in mesa section 60, which is inset by the respective trench sections. Base zone 14 exhibits a second conductivity type, which has a doping concentration lower than that of pot area 11 (P--type).

[0065] The contact area 15 of the second conductivity type, which has a higher doping concentration than the base zone 14, is formed on the top side of the base zone 14 of the mesa section 60. In this example, the contact area 15 is of the P+ type. The well area 11 on the top side of the semiconductor substrate 10 can be configured such that it is located in one direction of the first gate runner 50 away from the contact area 15 that is furthest away along the Y-axis. The base zone 14 is exposed between the well area 11 and the contact area 15 on the top side of the semiconductor substrate 10.

[0066] In transistor section 70, the first conductivity type emitter zone 12, with a higher doping concentration than a drift region formed within the semiconductor substrate 10, is selectively located on the top surface of the mesa section 60-1. The emitter zone 12 in this example is of the N+ type. A section of the base zone 14, adjacent to the emitter zone 12 in the depth direction (direction of the -Z-axis) of the semiconductor substrate 10 and in contact with the gate-trough section 40, acts as a channel section. When an ON voltage is applied to the gate-trough section 40, a channel forms in the Z-axis direction in a section of the base zone 14 adjacent to the gate-trough section 40, located between the emitter zone 12 and the drift region. This channel corresponds to an electron inversion layer.When the channel is formed in the base zone 14, charge carriers flow between the emitter zone 12 and the drift region.

[0067] In this example, the base zones 14-e are arranged in both end sections of each of the mesa segments 60 along the Y-axis. In this example, one of the areas adjacent to base zone 14-e, located closer to the middle section of the mesa segment 60 on the top side of each of the mesa segments 60, is contact area 15. Additionally, the other area adjacent to base zone 14-e opposite contact area 15 is pot area 11.

[0068] In this example, the contact regions 15 and the emitter zones 12 are arranged alternately along the direction of the Y-axis in a region defined by the base zones 14-e at both ends in the direction of the Y-axis within the mesa section 60-1 of the transistor section 70. Each of the contact regions 15 and each of the emitter zones 12 is formed from one trench section to the other, adjacent to each other.

[0069] The contact area 15, with a larger area than the contact area 15 of mesa section 60-1, is located in one or more mesa sections 60-2 beneath the mesa sections 60 of the transistor section 70, which are situated at the boundary with the diode section 80. The emitter zone 12 cannot be located in mesa section 60-2. In mesa section 60-2 in this example, the contact area 15 is located in the entire area enclosed by the base zones 14-e.

[0070] In this example, contact hole 54 is formed above each of the contact areas 15 and emitter zones 12 in each of the mesa sections 60-1 in the transistor sections 70. Contact hole 54 in mesa section 60-2 is formed above contact area 15. Contact hole 54 is not formed in the areas corresponding to base zone 14-e and pot area 11 in each of the mesa sections 60. The contact holes 54 in the respective mesa sections 60 in the transistor section 70 can have the same length along the Y-axis.

[0071] A cathode region 82 of the N+ type is formed in a region that is in contact with the underside of the semiconductor substrate 10 in the diode section 80. Fig. 2 is the area in which the cathode region 82 is formed, indicated by a dashed line. The collector region of the P+ type can be formed in an area where the cathode region 82 is not formed in the area that is in contact with the underside of the semiconductor substrate 10.

[0072] Transistor section 70 can be a region in which the mesa section 60, containing contact area 15 and emitter zone 12, is formed, and a region in which the trench section adjacent to mesa section 60 is arranged in an area that overlaps with the collector zone in the direction of the Z-axis. However, it is stated that contact area 15 in mesa section 60-2 can be located at the boundary with diode section 80 instead of emitter zone 12.

[0073] Base zone 14 is located on the top side of mesa section 60-3 of diode section 80. However, it is specified that contact area 15 may be located in a region adjacent to base zone 14-e. Contact hole 54 terminates above contact area 15.

[0074] Fig. 3 is a drawing that shows an example of one along BB in Fig. Figure 2 shows the cross-section taken along BB. The cross-section taken along BB is an XZ plane containing the diode section 80 and the transistor section 70, and passing through the emitter region 12.

[0075] The semiconductor device 100 in this example comprises, in cross-section, the semiconductor substrate 10, a dielectric interlayer film 38, the emitter electrode 52, and a collector electrode 24. The dielectric interlayer film 38 is configured to cover at least a portion of the top surface of the semiconductor substrate 10. A through-hole, such as the contact hole 54, is formed in the dielectric interlayer film 38. The top surface of the semiconductor substrate 10 is exposed through the contact hole 54. The dielectric interlayer film 38 can be made of silicate glass, such as PSG or BPSG, or it can be an oxide film, a nitride film, or the like.

[0076] The emitter electrode 52 is formed on the top surfaces of the semiconductor substrate 10 and the dielectric interlayer film 38 in the transistor section 70 and the diode section 80. The emitter electrode 52 is also formed within the contact hole 54 and is in contact with the top surface 21 of the semiconductor substrate 10, which is exposed through the contact hole 54.

[0077] The collector electrode 24 is formed on a bottom surface 23 of the semiconductor substrate 10. The collector electrode 24 can be in contact with the entire bottom surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed from a conductive material, such as a metal. In this description, the direction of the line connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction (direction of the Z-axis). A direction from the collector electrode 24 to the emitter electrode 52 is defined as a positive direction of the Z-axis.

[0078] The P-type base zone 14 is formed on the top side of the semiconductor substrate 10 in the diode section 80 and the transistor section 70. An N-type drift region 18 is arranged below the base zone 14 within the semiconductor substrate 10. Each of the trench sections is arranged such that it penetrates the base zone 14 from the top side of the semiconductor substrate 10 to reach the drift region 18.

[0079] The emitter zone 12 of the N+ type, the base zone 14 of the P- type, and an enrichment region 16 of the N+ type are arranged in cross-section in the order shown, starting from the top side of the semiconductor substrate 10 in each of the mesa sections 60-1 of the transistor section 70. The donor is enriched in the enrichment region 16 at a higher concentration than in the drift region 18. The drift region 18 is located below the enrichment region 16. The enrichment region 16 can be arranged to cover the entire underside of the base zone 14 in each of the mesa sections 60. In other words, the enrichment region 16 can be inset by the trench sections in the direction of the X-axis.If the enrichment region 16 with the higher concentration than the drift region 18 is arranged between the drift region 18 and the base region 14, it is possible to reduce an EIN voltage in the transistor section 70 by increasing a charge carrier injection enrichment effect (IE effect, injection enrichment effect).

[0080] It is stated that in an XZ cross-section passing through contact area 15 of transistor section 70, contact area 15 is located in each of the mesa sections 60-1 of transistor section 70 in place of emitter area 12. Additionally, contact area 15 is located in mesa section 60-2 in place of emitter area 12. Contact area 15 can function as a latch-up suppression layer, suppressing latch-up.

[0081] The base region 14 of the P- type and the enhancement region 16 of the N+ type are arranged sequentially in cross-section from the top side of the semiconductor substrate 10 in each of the mesa sections 60-3 of the diode section 80. The drift region 18 is located below the enhancement region 16. The enhancement region 16 cannot be located within the diode section 80.

[0082] A collector region 22 of the P+ type is arranged in the transistor section 70 in an area adjacent to the underside 23 of the semiconductor substrate 10. The cathode region 82 of the N+ type is arranged in the diode section 80 in the area adjacent to the underside 23 of the semiconductor substrate 10.

[0083] In the semiconductor substrate 10 of this example, an N+-type buffer zone 20 is arranged between the drift region 18 and the collector region 22, and between the drift region 18 and the cathode region 82. The doping concentration of the buffer zone 20 is higher than the doping concentration of the drift region 18. The buffer zone 20 can act as a field-stop layer, preventing a state in which a depleted layer propagating from the bottom of the base region 14 reaches the P+-type collector region 22 and the N+-type cathode region 82.

[0084] One or more gate trench sections 40 and one or more blind trench sections 30 are formed in the vicinity of the top surface 21 of the semiconductor substrate 10. Each of the trench sections penetrates the base zone 14 of the top surface 21 of the semiconductor substrate 10 to reach the drift region 18. In the regions where at least one of the emitter zone 12, the contact zone 15, and the enhancement region 16 is located, each of the trench sections penetrates these regions to reach the drift region 18. A structure in which the trench sections penetrate the doping region is not limited to a structure that is fabricated by first forming the doping region and then forming the trench sections.A structure that is produced by forming the doping area after the trench sections have been formed is also included in the structure in which the trench sections penetrate the doping area.

[0085] The gate trench section 40 comprises a gate trench, a dielectric gate film 42, and a conductive gate section 44, all formed on the top side of the semiconductor substrate 10. The dielectric gate film 42 is configured to cover an inner wall of the gate trench. The dielectric gate film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The conductive gate section 44 is formed on an inner surface facing the dielectric gate film 42 within the gate trench. In other words, the dielectric gate film 42 insulates the conductive gate section 44 from the semiconductor substrate 10. The conductive gate section 44 is made of a conductive material, such as polysilicon.

[0086] The conductive gate section 44 contains regions along the depth direction that face at least the adjacent base zone 14 via the dielectric gate film 42. The gate trench section 40 in cross-section is covered on the top side of the semiconductor substrate 10 with the dielectric interlayer film 38. When a predetermined voltage is applied to the conductive gate section 44, an electron inversion layer-based channel is formed on the surface layer of the interface that is in contact with the gate trench in the base zone 14.

[0087] The blind trench section 30 can have the same cross-sectional structure as the gate trench section 40. The blind trench section 30 contains a blind trench, a dielectric blind film 32, and a conductive blind section 34, which are formed in the vicinity of the top surface 21 of the semiconductor substrate 10. The dielectric blind film 32 is configured to cover an inner wall of the blind trench. The conductive blind section 34 is formed within the blind trench and is also formed on an inner surface facing the dielectric blind film 32. The dielectric blind film 32 insulates the conductive blind section 34 from the semiconductor substrate 10. The conductive blind section 34 can be made of the same material as the conductive gate section 44. For example, the conductive blind section 34 is made of a conductive material such as... B. Polysilicon, formed.The conductive blind section 34 can have the same length in the depth direction as the conductive gate section 44. The blind trench section 30 in cross-section is covered on the top surface 21 of the semiconductor substrate 10 with the dielectric interlayer film 38. It is stated that the bottoms of the blind trench section 30 and the gate trench section 40 can have a curved shape that is convex downwards (curved shape in cross-section).

[0088] Fig. Figure 4 is an enlarged view of an area surrounding a region B in Fig. 1. Region B is an area that includes the terminal area (in this example, the cathode terminal area 117), the second gate runner 51, which is arranged along a first side 132 of the terminal area, the first gate runner 50, and the intermediate terminal area 130. Region B faces the transistor section 70 in the active main section 120 in the direction of the Y-axis and does not face the diode section 80. Additionally, the first side 132 of the cathode terminal area 117 is a side parallel to the direction of the Y-axis.

[0089] The second gate runner 51 is arranged between the first side 132 of the cathode terminal 117 and the intermediate terminal area 130. The pot area 11 can be exposed on the top side of the semiconductor substrate 10 between the second gate runner 51 and the cathode terminal 117.

[0090] As described above, the gate trench section 40 located in the intermediate connection area 130 is directly or indirectly connected to the first gate runner 50. The edge section 41 of the gate trench section 40 in this example is located below and connected to the third gate runner 48.

[0091] The gate trench section 40 located in the intermediate connection area 130 can be a trench section obtained by extending the gate trench section located in the active main section 120 in the direction of the Y-axis 40. In other words, the gate trench section 40 in the active main section 120 can be continuous with the gate trench section 40 in the intermediate connection area 130.

[0092] Additionally, the blind trench section 30 can also be arranged in the intermediate connection area 130. The blind trench section 30, arranged in the active main section 120, can also extend with respect to the blind trench section 30 to the intermediate connection area 130. The pot area 11 is arranged below the first gate runner 50. The pot area 11 extends in the direction of the Y-axis and is also arranged in a section of the intermediate connection area 130. The edge section 31 of the blind trench section 30 is arranged in a position such that it overlaps with the pot area 11. The emitter electrode 52 is also arranged from the active main section 120 to a position such that it overlaps with the pot area 11. The edge section 31 of the blind trench section 30 is connected to the emitter electrode 52 via the contact hole 56.It is stated that the potting area 11 is also located below the second gate runner 51, with the potting area 11 extending in the direction of the X-axis, so that it is also located in a section of the intermediate connection surface area 130.

[0093] The structure of each of the mesa sections 60 in the intermediate connection area 130 can be the same as the structure of the mesa section 60 in the active main section 120, which with respect to Fig. 2 and Fig. 3 has been described. The contact areas 15 and the emitter zones 12 are arranged alternately on the upper side of the mesa section 60-1 in the intermediate connection area 130 in the direction of the Y-axis.

[0094] Additionally, in the intermediate connection area 130, the blind trench section 30 can be arranged between the gate trench section 40, which is the closest to the cathode connection area 117 in the X-axis direction, and the cathode connection area 117. The mesa section 60-2, in which the emitter zone 12 is not located, is arranged such that it is adjacent to the blind trench section 30. Several mesa sections 60-2 can be arranged in the X-axis direction. Consequently, the interval between the connection area and the emitter zone 12 in the intermediate connection area 130 can be increased.

[0095] Additionally, in the intermediate contact area 130, the contact hole 54 can be arranged between the gate trench section 40, which is closest to the cathode contact surface 117 in the X-axis direction, and the cathode contact surface 117. Additionally, in the intermediate contact area 130, the contact hole 54 can be arranged between the blind trench section 30, which is closest to the cathode contact surface 117 in the X-axis direction, and the cathode contact surface 117. In the intermediate contact area 130, the contact hole 54 can be arranged between the trench section, which is closest to the cathode contact surface 117 in the X-axis direction, and the cathode contact surface 117.

[0096] Additionally, the mesa section 60, which is continuously arranged in the direction of the Y-axis from the active main section 120 to the intermediate connection area 130, can have the same structure in the active main section 120 and in the intermediate connection area 130, with the exception of a distal end section in the direction of the Y-axis. The contact areas 15 and the emitter zones 12 can, for example, be arranged alternately in the direction of the Y-axis on the upper surface of the mesa section 60-1 in both the active main section 120 and the intermediate connection area 130.

[0097] Additionally, the structure of the mesa section 60 can vary in the intermediate connection area 130 and the active main section 120. For example, the emitter zone 12 is not located in the intermediate connection area 130 with respect to a section of the mesa sections 60-2, and the contact areas 15 and the emitter zones 12 can also be arranged alternately in the active main section 120.

[0098] Fig. Figure 5 is an enlarged view of an area surrounding a region C in Fig. 1. Region C is a region that includes the connection area (in this example, the cathode connection area 117), the second gate runner 51, which is arranged along a second side 134 of the connection area, and the transistor section 70 and the diode section 80 of the active main section 120. Additionally, the second side 134 of the cathode connection area 117 is one side parallel to the direction of the X-axis and one side facing the active main section 120.

[0099] The second gate runner 51 is arranged between the second side 134 of the cathode terminal 117 and the transistor section 70 and the diode section 80. The pot area 11 can be exposed on the top side of the semiconductor substrate 10 between the second gate runner 51 and the cathode terminal 117.

[0100] As described above, the gate trench section 40, which is positioned so that it faces the second gate runner 51 in the direction of the Y-axis, is directly or indirectly connected to the second gate runner 51. The edge region 41 of the gate trench section 40 in this example is located below the third gate runner 48 and connected to the third gate runner 48.

[0101] Additionally, the potting area 11 is arranged below the second gate runner 51, extending in the direction of the Y-axis and reaching to one side of the active main section 120 with respect to the second gate runner 51. The edge section 31 of the blind trench section 30 is positioned so that it overlaps the potting area 11. The edge section 31 of the blind trench section 30 is connected to the emitter electrode 52 via the contact hole 56.

[0102] In accordance with the in Fig. 4 and Fig. The structures illustrated in Figure 5 promote the direct or indirect connection of each of the gate trench sections 40 to the metallic first gate runner 50 and the metallic second gate runner 51. Consequently, the delay and damping variations of the gate voltages applied to the respective gate trench sections 40 can be reduced.

[0103] Additionally, the distance D1 between the contact pad and the second gate runner 51 in the top view can be 200 µm or less. The distance D1 can be 150 µm or less, 120 µm or less, or 100 µm or less. Furthermore, the distance D1 can be 1.5 times the thickness of the semiconductor substrate 10 in the Z-axis direction or less, or it can be equal to or less than the thickness of the semiconductor substrate 10. The distance D1 in the Y-axis direction can satisfy the condition described above, and the distance D1 in the X-axis direction can also satisfy the condition described above. Reducing the distance between the contact pad and the second gate runner 51 increases the area of ​​the active region.

[0104] Fig. Figure 6 is a drawing showing a top view of an example arrangement of the emitter electrode 52. The emitter electrode 52 can be arranged above the active main section 120 and at least one section of the intermediate connection area 130. In this example, the emitter electrode 52 is not arranged above the intermediate connection area 130 in which the current sensing device 119 is located. Additionally, the emitter electrode 52 can also be arranged in such a way that it overlaps the emitter connection area 115.

[0105] Fig. Figure 7 is a drawing illustrating an example arrangement of the cathode region 82. In this example, the cathode region 82 is not located in the intermediate connection area 130. In other words, the cathode region 82, which is located in the active main section 120, does not extend to the intermediate connection area 130. However, it is stated that the structure of the diode section 80, with the exception of the cathode region 82, can be located in the intermediate connection area 130. In accordance with the structure mentioned above, a relatively deep distance can be ensured between the N+-type cathode region 82 and the P+-type pot region 11, thus suppressing a reduction in holding pressure caused by the device area being located in the intermediate connection area 130.

[0106] It is stated that the cathode region 82-1, which is arranged so that it faces the intermediate connection area 130 in the direction of the Y-axis, can be positioned such that it is longer in the direction of the Y-axis than the cathode region 82-2, which is arranged so that it faces the connection surface or the second gate runner 51 in the direction of the Y-axis. However, it is stated that the cathode region 82-1 does not extend to the intermediate connection area 130. While the area of ​​the cathode region 82 is increased, it is therefore encouraged to ensure the distance between the cathode region 82 and the pot region 11.

[0107] It is stated that each of the several terminal pads arranged along the first end face 142 can be positioned such that the terminal pad faces at least partially towards the diode section 80 (cathode region 82) in the direction of the Y-axis. Consequently, it is recommended that the structure of the transistor section 70, located in the active main section 120, extend to the intermediate terminal pad region 130. For this reason, the area of ​​the transistor section 70 can be easily increased.

[0108] Additionally, the distance D2 between the terminal pad located at the furthest end in the X-axis direction and the first gate runner 50 in the X-axis direction can be 500 µm or less. If the terminal pad is located close to the first gate runner 50, the inter-terminal area 130 in the X-axis direction can be increased. The distance D2 can be 300 µm or less, 200 µm or less, or 100 µm or less. The distance D2 can be 1.5 times the thickness of the semiconductor substrate 10 or less, or equal to the thickness of the semiconductor substrate 10 or less.

[0109] Fig. Figure 8 is an enlarged view of an area surrounding a region D in Fig. 7. The area D is an area which, in the intermediate terminal area 130, faces the diode section 80 and the transistor section 70 of the active main section 120 in the direction of the Y-axis.

[0110] As regarding Fig. As described in Figure 7, the cathode region 82 is not located in the intermediate connection area 130. However, it is stated that the blind trench section 30 of the diode section 80, which is arranged such that it faces the intermediate connection area 130 in the direction of the Y-axis, extends to the intermediate connection area 130. Additionally, the mesa section 60-3 of the diode section 80 is also arranged to extend to the intermediate connection area 130.

[0111] In accordance with the structure mentioned above, the distance between the cathode region 82 and the pot region 11 can be ensured, while structural continuity between the intermediate connection area 130 and the active main section 120 is maintained. Maintaining structural continuity makes it possible to suppress the local concentration of the electric field.

[0112] Fig. Figure 9 is a drawing illustrating another arrangement example of the cathode region 82. In this example, the cathode region 82 is arranged in the intermediate connection area 130. The cathode region 82, which is arranged in the active main section 120, is, for example, arranged to extend to the intermediate connection area 130. In accordance with the structure mentioned above, the area of ​​the cathode region 82 is increased, whereby the device area functioning as the diode section 80 can be enlarged.

[0113] It is stated that if the distance between the cathode region 82 and the well region 11 becomes too small in the X-axis direction, it is preferred that the cathode region 82 of the active main section 120 does not extend to the inter-terminal area 130. In one example, provided that the distance between the cathode region 82 and the well region 11 in the X-axis direction is 200 µm or greater, the cathode region 82 can extend to the inter-terminal area 130. The distance can be 100 µm or greater and can also be greater than the thickness of the semiconductor substrate 10.

[0114] Fig. Figure 10 is an enlarged view of an area surrounding a region E in Fig. 9. The area E is an area which, in the intermediate terminal area 130, is oriented towards the diode section 80 and the transistor section 70 of the active main section 120 in the direction of the Y-axis.

[0115] As regarding Fig. As described in Figure 9, the cathode region 82 is located in the intermediate connection area 130. Additionally, the blind trench section 30 and the mesa section 60-3 extend to the intermediate connection area 130. In accordance with the structure mentioned above, the area of ​​the diode section 80 can be enlarged.

[0116] Fig. Figure 11 illustrates another example of area B in Fig. 1. In this example, emitter zone 12 is not in contact with gate trench section 40-1, which, among the gate trench sections 40 arranged in the intermediate connection area 130, is the closest to the connection surface in the X-axis direction. Consequently, the distance between the connection surface and emitter zone 12 can be further increased. The contact area 15 can be located adjacent to gate trench section 40-1 in mesa section 60 instead of emitter zone 12.

[0117] Fig. Figure 12 is a drawing illustrating an example arrangement of the gate trench sections 40 in the active main section 120 and the intermediate connection area 130. As described above, the gate trench section 40 in the intermediate connection area 130 and the gate trench section 40 in the active main section 120 can be arranged continuously. Similarly, the blind trench sections 30 in the intermediate connection area 130 and in the active main section 120 can also be arranged continuously.

[0118] Fig. Figure 13 illustrates another arrangement example of the gate trench sections 40 in the active main section 120 and the intermediate contact area 130. In this example, the gate trench section 40 in the intermediate contact area 130 is separated from the gate trench section 40 of the active main section 120. The gate trench section 40 in the intermediate contact area 130 can be arranged extending in the direction of the X-axis. The gate trench section 40 in the intermediate contact area 130 can be directly or indirectly connected to the second gate runner 51, which is arranged in the direction of the Y-axis. The gate trench section 40 in this example is directly or indirectly connected to the second gate runner 51, which is arranged in the direction of the X-axis at both ends of the intermediate contact area 130.The blind trench section 30 in the intermediate contact area 130 can also be arranged extending in a direction parallel to the gate trench section 40.

[0119] It is stated that the gate trench section 40 of the active main section 120, which faces the intermediate connection area 130 in the direction of the Y-axis, can be connected to the third gate runner 48, which is arranged between the intermediate connection area 130 and the active main section 120. The third gate runner 48 is connected to the second gate runners 51, which are arranged at both ends of the intermediate connection area 130 in the direction of the X-axis. In accordance with the structure mentioned above, each of the gate trench sections 40 can also be connected to the gate runner section.

[0120] Fig.Figure 14 is a drawing illustrating another arrangement example of the gate trench sections 40 in the active main section 120 and the intermediate connection area 130. In this example, the gate trench section 40 in the intermediate connection area 130 is separated from the gate trench section 40 of the active main section 120. In this example, the gate trench section 40 in the intermediate connection area 130 is arranged extending in the direction of the Y-axis.

[0121] The gate trench section 40 in the intermediate connection area 130 can be connected to the first gate runner 50. The gate trench section 40 of the active main section 120, which faces the intermediate connection area 130 in the direction of the Y-axis, can be connected to the third gate runner 48, which is located between the intermediate connection area 130 and the active main section 120. In accordance with the structure mentioned above, each of the gate trench sections 40 can also be connected to the gate runner section.

[0122] The operations, procedures, steps, and stages of each process performed by a device, system, program, and method shown in the claims, embodiments, or graphical representations may be performed in any order, as long as the order is not specified by "before," "before," or the like, and as long as the output of a preceding process is not used in a subsequent process. Even if the process flow is described in the claims, embodiments, or graphical representations using expressions such as "first" or "next," this does not necessarily mean that the process must be performed in that order. REFERENCE MARK LIST 10 Semiconductor substrate 11 Pot area 12 Emitter zone 14 Base Zone 15 Contact area 16 Enrichment area 18 Drift area 20 Buffer zone 21 Top 22 Collector zone 23 Underside 24 Collector electrode 25 Connecting section 29 linear section 30 Blind trench section 31 Marginal section 32 dielectric blind film 34 conductive blind section 38 dielectric interlayer film 39 linear section 40 Gate Trench Section 41 marginal section 42 dielectric gate film 44 conductive gate section 48 third gate runner 49 contact holes 50 first gate runners 51 second gate runner 52 Emitter electrode 54 contact holes 56 contact holes 60 Mesa Section 70 Transistor section 80 diode section 82 Cathode area 90 edge finish structure section 92 Protective ring 100 semiconductor devices 110 Temperature scanning section 112 Temperature sensing wiring 114 scanning connection area 115 emitter connection area 116 Gate connection area 117 Cathode connection area 118 Anode connection area 119 Current sensing device 120 active main section 130 Intermediate connection area 132 first page 134 second page 140 outer circumference end 142 first front

Claims

Semiconductor device (100) comprising: a semiconductor substrate (10); a transistor section (70) and a diode section (80) arranged on the semiconductor substrate (10), the transistor section (70) comprising a gate-trough section (40) extending in a direction which differs in plan view from the arrangement direction; several terminal pads arranged above a top surface (21) of the semiconductor substrate (10) and arranged in an arrangement direction between a region in which the transistor section (70) or the diode section (80) is arranged and a first end face on the top surface (21) of the semiconductor substrate (10);and a gate runner section that transmits a gate voltage to the transistor section (70), wherein: the gate runner section includes: a first gate runner (50) which is arranged in plan view between the first end face of the semiconductor substrate (10) and at least one of the terminal surfaces;and a second gate runner (51) which, in plan view, is arranged extending between at least two of the multiple terminal pads and the transistor section (70), the transistor section (70) is also arranged in at least one of those intermediate terminal pad areas (130) which, in plan view, are inserted between two terminal pads, the gate trench section (40) which is arranged in the at least one intermediate terminal pad area (130) is connected to the first gate runner (50), and the gate trench section (40) which is arranged such that it faces the second gate runner (51) in its extension direction is connected to the second gate runner (51). Semiconductor device (100) comprising: a semiconductor substrate (10); a transistor section (70) and a diode section (80) arranged on the semiconductor substrate (10), wherein the transistor section (70) includes a gate trench section (40) extending in a direction different in plan view from the orientation of the arrangement; several terminal pads arranged above a top surface (21) of the semiconductor substrate (10) and arranged in an orientation between a region in which the transistor section (70) or the diode section (80) is arranged and a first end face on the top surface (21) of the semiconductor substrate (10); and a gate runner section transmitting a gate voltage to the transistor section (70), wherein: the gate runner section includes: a first gate runner (50),which is arranged in plan view between the first end face of the semiconductor substrate (10) and at least one of the terminal pads; and a second gate runner (51) which is arranged in plan view between at least one of the multiple terminal pads and the transistor section (70); the transistor section (70) is also arranged in at least one of those intermediate terminal pad areas (130) which are inserted in plan view between two terminal pads; the gate trench section (40) which is arranged in the at least one intermediate terminal pad area (130) is connected to the first gate runner (50); the gate trench section (40) which is arranged such that it faces the second gate runner (51) in the direction of extension is connected to the second gate runner (51); at least one of the multiple terminal pads comprises a terminal pad.which is arranged in positions except at the two ends in the direction of arrangement, the second gate runner (51) is arranged in one connection surface along three sides except for one side facing the first end side, and the first gate runner (50) is arranged in one connection surface along three sides except for one side facing the first end side. Semiconductor device (100) comprising: a semiconductor substrate (10); a transistor section (70) and a diode section (80) arranged on the semiconductor substrate (10), the transistor section (70) comprising a gate-trough section (40) extending in a direction which differs in plan view from the arrangement direction; several terminal pads arranged above a top surface (21) of the semiconductor substrate (10) and arranged in an arrangement direction between a region in which the transistor section (70) or the diode section (80) is arranged and a first end face on the top surface (21) of the semiconductor substrate (10);and a gate runner section that transmits a gate voltage to the transistor section (70), wherein: the gate runner section includes: a first gate runner (50) which is arranged in plan view between the first end face of the semiconductor substrate (10) and at least one of the terminal surfaces;and a second gate runner (51) which, in plan view, is arranged extending between at least one of the multiple terminal pads and the transistor section (70), the transistor section (70) is also arranged in at least one of those intermediate terminal pad areas (130) which, in plan view, are each inserted between two terminal pads, the gate trench section (40) which is arranged in the at least one intermediate terminal pad area (130) is connected to the first gate runner (50), the gate trench section (40) which is arranged such that it faces the second gate runner (51) in the direction of extension is connected to the second gate runner (51), and the at least one of the multiple terminal pads comprises a terminal pad which is circularly surrounded by the first gate runner (50) and by the second gate runner (51). Semiconductor device (100) according to one of claims 1 to 3, wherein the second gate runner (51) is arranged along at least two sides of at least one of the terminal surfaces. Semiconductor device (100) according to any one of claims 1 to 4, wherein the distance in plan view between each terminal surface and the second gate runner (51) is 200 µm or less. Semiconductor device (100) according to one of claims 1 to 5, wherein: the diode section (80) contains a cathode region of a first conductivity type, which is exposed on a bottom side (23) of the semiconductor substrate (10); and the cathode region is not arranged in the inter-terminal areas (130). Semiconductor device (100) according to claim 6, wherein: the transistor section (70) comprises an emitter zone (12) of the first conductivity type, which is exposed on the top surface (21) of the semiconductor substrate (10) and is in contact with the gate-trough section (40); the semiconductor device (100) comprises an emitter electrode (52) which is arranged above the top surface (21) of the semiconductor substrate (10) and is connected to the emitter zone (12); the diode section (80) comprises blind-trough sections (30) which are arranged extending in the direction of extension and are connected to the emitter electrode (52); and at least one of the blind-trough sections (30), which are arranged such that they face the intermediate connection areas (130) in the direction of extension, is arranged extending to a corresponding intermediate connection area (130). Semiconductor device (100) according to any one of claims 1 to 5, wherein: the transistor section (70) comprises an emitter region (12) of the first conductivity type, which is exposed on the top side (21) of the semiconductor substrate (10) and is in contact with the gate-trough section (40); the semiconductor device (100) comprises an emitter electrode (52) which is arranged above the top side (21) of the semiconductor substrate (10) and is connected to the emitter region (12); the diode section (80) comprises: a cathode region of the first conductivity type, which is exposed on a bottom side (23) of the semiconductor substrate (10); and a blind trench section (30) which is arranged extending in the direction of extension and is connected to the emitter electrode (52), and the cathode region and the blind trench section (30) are arranged in at least one of the intermediate connection areas (130). Semiconductor device (100) according to one of claims 1 to 8, wherein: the transistor section (70) includes an emitter zone (12) of the first conductivity type, which is exposed on the top side (21) of the semiconductor substrate (10) and is in contact with the gate-trough section (40); and at least the gate-trough section (40) that is nearest to one of the two terminal surfaces in the inter-terminal area (130) does not have the emitter zone (12) that is in contact with the gate-trough section (40) in the inter-terminal area (130). Semiconductor device (100) according to one of claims 1 to 9, wherein the transistor section (70) includes an emitter zone (12) of the first conductivity type, which is exposed on the top side (21) of the semiconductor substrate (10) and is in contact with the gate-trough section (40), the semiconductor device (100) comprises: an emitter electrode (52) which is arranged above the top side (21) of the semiconductor substrate (10) and is connected to the emitter zone (12); and a dielectric interlayer film (38) arranged between the semiconductor substrate (10) and the emitter electrode (52), and a contact hole connecting the emitter electrode (52) to the semiconductor substrate (10), in which the dielectric interlayer film (38) is arranged between the gate trench section (40), which is the nearest to one of the two terminal surfaces in the inter-terminal area (130), and the terminal surface. Semiconductor device (100) according to claim 10, wherein a blind trench section (30) connected to the emitter electrode (52) is arranged between the gate trench section (40), which is the nearest to one of the two terminal surfaces in the intermediate terminal surface area (130), and the terminal surface. Semiconductor device (100) according to one of claims 1 to 11, wherein each of the multiple terminal surfaces is arranged in such a position that the terminal surface is at least partially directed towards the diode section (80) in the direction of extension.

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