Semiconductor device with reinforced integrated circuit and manufacturing process thereof

Abstract

Method for manufacturing a semiconductor device, comprising: Arranging a metallic material completely around each region of a multitude of regions of an integrated circuit on an active surface of a semiconductor chip; wherein at least one section of the metal material remains electrically isolated from each region of an integrated circuit; and Encapsulation of the semiconductor chip and the metal material in an encapsulation material, wherein the encapsulation material extends to a height above the active surface that is higher than a maximum height of the metal material above the active surface.

Description

TECHNICAL AREA

[0001] This disclosure generally relates to semiconductor devices and methods for packing semiconductor devices. More specifically, disclosed embodiments relate to methods for packing semiconductor devices that structurally reinforce the integrated circuit of such devices, better preserve the desired performance characteristics of the integrated circuit, increase the yield, and better match the actual performance of the semiconductor devices to the desired performance. STATE OF THE ART

[0002] Flip-flops are useful in a wide variety of applications that require a non-sinusoidal, repeating output, such as a square, sawtooth, or triangle wave. For example, flip-flops can be used to provide the clock signal for timers, counters, and data communication protocols.

[0003] US 2015 / 0303143 A1 discloses a semiconductor device with an oscillator and a method for its fabrication, in which the cost is low and the design flexibility is high.

[0004] The semiconductor device includes a wiring structure area and an oscillator area, as well as a metal resistance element as the same layer as a conductive layer above the top metal wiring in the wiring structure area.

[0005] US 2005 / 0006771 A1 discloses a semiconductor device comprising a semiconductor substrate, a first wiring formed over the semiconductor substrate with an intermediate first insulating film, a MIM capacitor formed over the first insulating film, a second insulating film formed to cover the MIM capacitor, a second wiring formed on the second insulating film, and a protective ring buried in the second insulating film to surround the MIM capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] While this disclosure concludes with claims that particularly highlight and explicitly claim certain embodiments, various features and advantages of embodiments within the scope of this disclosure can be more easily determined from the following description in conjunction with the accompanying drawings, in which: Fig. Figure 1 is a cross-sectional side view of a semiconductor device housing; Fig. Figure 2 is a perspective side view of a section of the semiconductor device housing of Fig. 1; Fig. Figure 3 is a circuit diagram of a tilting oscillator of the semiconductor device housing of Fig. 1; Fig. Figure 4 is a top view of a first section of an active surface of a semiconductor chip of the semiconductor device package of Fig. 1; Fig. Figure 5 is a top view of a second, different section of the active surface of the semiconductor chip of the semiconductor device package of Fig. 1; Fig. Figure 6 is a diagram of the clock frequency of the tilting oscillator as a function of temperature for a variety of different trim codes; Fig. Figure 7 is a diagram of temperature trim code values ​​required to generate a consistent clock frequency in the tilting oscillator relative to the temperature; Fig. Figure 8 is a diagram of clock frequencies of several tilting oscillators generated according to this disclosure; and Fig. Figure 9 is a schematic representation of a system containing a semiconductor device according to this disclosure. TYPE(S) OF IMPLEMENTATION OF THE INVENTION

[0007] The illustrations shown in this disclosure are not intended to be actual views of any particular semiconductor device, semiconductor device housing, system comprising such semiconductor devices and / or semiconductor device housings, or any component thereof, but are merely idealized representations used to describe the illustrative embodiments. Therefore, the drawings are not necessarily to scale.

[0008] Disclosed embodiments generally relate to methods for packing semiconductor devices that can better amplify integrated circuits, better preserve desired properties of the integrated circuit, increase the yield and better match the actual performance of the semiconductor devices to the desired performance.

[0009] In particular, embodiments of semiconductor devices and semiconductor device housings are disclosed which may include mechanical reinforcement.

[0010] As used herein, the terms “essentially” and “approximately” mean, with respect to a given parameter, property, or condition, and include to such an extent that those skilled in the art would understand that the given parameter, property, or condition is satisfied with some degree of variance, for example, within acceptable manufacturing tolerances. For instance, a parameter that is essentially or approximately a specified value may be at least approximately 90% of the specified value, at least approximately 95% of the specified value, at least approximately 99% of the specified value, or even at least approximately 99.9% of the specified value.

[0011] As used here, the term "integrated circuit" refers to and includes both active and passive circuits. For example, a passive circuit includes resistors and capacitors. For example, an active circuit includes field-effect transistors, power amplifiers, and voltage amplifiers.

[0012] Fig. Figure 1 is a cross-sectional side view of a semiconductor device housing 100. The semiconductor device housing 100 can enclose a semiconductor chip 102 with an active surface 104, and an inactive surface 106 located on one side of the semiconductor chip 102 opposite the active surface 104. The active surface 104 can include a plurality of regions 108 of an integrated circuit embedded in and / or located on the semiconductor material of the semiconductor chip 102 on the active surface 104. The integrated circuit of the active surface 104 of the semiconductor chip 102 can, as a non-limiting example, be configured as a tilting oscillator. More specifically, one or more of the regions 108 of the integrated circuit can include a resistor or a bank of resistors, or a capacitor or a bank of capacitors.As a specific, non-limiting example, one or more of the regions 108 of the integrated circuit may include a resistor or a bank of resistors, and another of the regions 108 of the integrated circuit may include a capacitor or a bank of capacitors. In other words, at least one region 108 of the integrated circuit may include at least one section of a flip-flop. A single region 108 of the integrated circuit may include a flip-flop, or several regions 108 of the integrated circuit may, in combination, include a flip-flop. In embodiments in which one or more of the regions 108 of the integrated circuit are operationally configured and / or connected to operate as a flip-flop, the flip-flop of the semiconductor chip 102 may lack a quartz crystal to regulate the timing of the flip-flop.

[0013] The operating frequency of a tilting oscillator, which includes resistors and capacitors but lacks a quartz crystal to regulate the operating frequency, can depend, at least in part, on the resistance and capacitance values ​​of these resistors and capacitors. These values ​​can deviate from their original values ​​during the processing, handling, and packaging of the semiconductor chip 102. For example, temperature changes can cause different components of the semiconductor device package 100, with their differing coefficients of thermal expansion, to expand and contract at different rates, thus stressing the components and leading to stress-induced artifacts affecting the performance of these components of the semiconductor device package 100.In particular, strain can change the values ​​of the resistors and capacitors in the flip-flop, producing a frequency response that may differ unpredictably from the intended frequency response. As a result, conventional flip-flops that use resistors and capacitors to determine the frequency may exhibit greater power variance compared to flip-flops that use quartz crystals to determine the oscillation frequency.

[0014] Tilting oscillators according to embodiments of this disclosure can better match the actual power output to the desired power output, at least partially as a result of the mechanical reinforcement of the regions 108 of the integrated circuit. For example, reinforcement material (e.g., metal material 110) can at least partially surround at least one of the regions 108 of the integrated circuit laterally. The metal material 110 can be located on the active surface 104 and can extend from the active surface 104 to a maximum height H. M extend above the active surface 104, for example in a direction that is at least substantially perpendicular to the active surface 104. The maximum height H MThe height of the metal material 110 may be at least substantially equal to or greater than the second-largest maximum height H2 of any other structure 113 (e.g., active or passive circuitry, electrical signal routing structures, etc.) resting on the active surface 104. The metal material 110 may extend laterally to completely surround one or more of the regions 108 of the integrated circuit. For example, the metal material 110 may not extend directly over the laterally adjacent regions 108 of the integrated circuit, so that lines extending perpendicularly from the relevant region 108 of the integrated circuit to the active surface 104 may not intersect the metal material 110.

[0015] An encapsulation material 112 can encapsulate the metal material 110, the semiconductor chip 102, and the regions 108 of the integrated circuit's active surface 104. For example, the encapsulation material 112 can directly contact surfaces of each of the metal material 110, the semiconductor chip 102, and the regions 108 of the integrated circuit's active surface 104. Alternatively, the encapsulation material 112 can be located over at least one of the metal material 110, the semiconductor chip 102, and the regions 108 of the integrated circuit in the active surface 104, and be in indirect contact with it via other materials. The term "enclosure" in Fig. Figure 1 serves only to show the extent of the encapsulation material 112 for the sake of simplicity and does not necessarily indicate the presence of a sheath or other enclosure over the encapsulation material 112.

[0016] The semiconductor device package 100 itself, or one or more of the regions 108 of the integrated circuit, can be configured as a clock module. For example, the semiconductor device package 100, or one or more of the regions 108 of the integrated circuit, can be configured to provide clock timing control to synchronize one or more operations of the semiconductor device package 100, or of another system of which the semiconductor device package 100 is a component.

[0017] Fig. Figure 2 is a perspective side view of a section of the semiconductor device housing 100 of Fig. 1. The one in Fig. Section 2 shown represents a single region 108 of the integrated circuit and the metal material 110 that at least partially surrounds region 108. As in Fig. As shown in Figure 2, the metal material 110 can form at least substantially walls extending at least substantially perpendicular to the active surface 104. The walls of the metal material 110 can connect around the region 108 in at least substantially rectangular form. The walls can comprise a laterally continuous, at least substantially continuous mass of the metal material 110, or they can comprise a series of laterally adjoining columns or pillars forming a fence, which can also be described as a cage, around one or more components. While columns or pillars can be laterally separated, furthermore, beams of metal material can be formed between laterally adjoining columns or pillars to provide enhanced shear strength.

[0018] Fig. Figure 3 is a circuit diagram of a tilting oscillator 114 of the semiconductor device housing of Fig. 1. As in Fig. As shown in Figure 3, the tilting oscillator 114 can include one or more resistors 116 and one or more capacitors 118 which are operatively connected to each other to cause each capacitor 118 to be charged and discharged at a set oscillation frequency, so that the resulting signal may not be sinusoidal.

[0019] Fig. Figure 4 is a top view of a section 120 comprising first resistors of the active surface 104, and Fig. Figure 5 is a top view of a second, other, capacitor-comprising section 122 of the active surface 104 of the semiconductor chip 102 of the semiconductor device housing 100 of Fig. 1. As in Fig. 4 and Fig. As shown in Figure 5, the regions 108 can be arranged in a repeating pattern of geometric shapes, such as a grid of rectangles when viewed perpendicular to the active surface 104. The metal material 110 can be placed laterally between different regions 108 of the integrated circuit, superimposed on roads 124 that do not contain an integrated circuit in / on them or have embedded electrical connections to connect different regions 108 to one another. The metal material 110 can also form a repeating pattern of geometric shapes, such as rectangles, that define the outline for the regions 108 of the integrated circuit.

[0020] In summary, with reference to Fig. 1, Fig. 2, Fig. 3, Fig. 4 to Fig. 5. The semiconductor device housing 100 can be formed, for example, by providing or forming the semiconductor chip 102, including the regions 108 of the integrated circuit, which are embedded in or formed on the active surface 104. The metal material 110 can be arranged on the active surface 104, at least partially, around various regions 108 of the integrated circuit. For example, a masking material 126, such as a photoresist, can be arranged on the active surface 104, and grooves or holes 128 can be formed (see Figure 5). Fig. 1) be structured in the masking material 126, for example by photolithography. The metal material 110 can then be arranged (e.g., distributed or deposited) over the roads 124 on the active surface 104 in the grooves or holes 128 using conventional techniques (e.g., plating or sputtering). This process of mask deposition, structuring, and metal material deposition can be repeated over several metallization layers and intermediate via layers to increase the height of the metal material until the metal material 110 reaches the required maximum height H. M has been achieved. The masking material 126 can be removed (e.g. using a solvent) or can remain in place over the active surface 104 and around the metal material 110.

[0021] At least one section of the metal material 110 can remain electrically isolated from region 108 of the integrated circuit. For example, the metal material 110 can be positioned in the channels 124 such that the metal material 110, or a section thereof, is kept electrically isolated from contact and operational connection with the integrated circuit in region 108. As another example, a dielectric material, such as the masking material 126, can be arranged between one or more sections of the metal material 110 and the integrated circuit in region 108. In some embodiments, at least one other section of the metal material 110 can be electrically connected to the integrated circuit of region 108, facilitating the routing of electrical signals between different regions 108.Such a section can be electrically isolated from the rest of the metal material 110 to reduce the likelihood of unintentional electrical connections (i.e., short circuits), for example by positioning one or more sections of a dielectric material (e.g., the masking material 126 or another dielectric material) between the electrically connected sections of the metal material 110 and the electrically isolated sections of the metal material 110.

[0022] The metal material 110 and the semiconductor chip 102 can be encapsulated in an encapsulation material 112, which comprises a molding compound (e.g., a curable polymer material that is then cured), for example by flowing the encapsulation material 112 over the metal material 110 and the semiconductor chip 102 and curing the encapsulation material 112.

[0023] In other words, methods for manufacturing a semiconductor device housing according to this disclosure can involve arranging a metal material at least partially around at least one region of an integrated circuit on an active surface of a semiconductor chip. At least one section of the metal material can remain electrically isolated from the at least one region of the integrated circuit. The semiconductor chip and the metal material can be encapsulated in an encapsulation material, the encapsulation material extending to a height above the active surface that is greater than a maximum height of the metal material above the active surface.

[0024] Furthermore, semiconductor devices according to this disclosure can include a semiconductor chip comprising an active surface and at least one region of an integrated circuit on the active surface. A metallic material can at least partially surround the at least one region of the integrated circuit on the active surface laterally, wherein at least one section of the metallic material is electrically separated from the at least one region of the integrated circuit.

[0025] Semiconductor device packages according to this disclosure can enclose a semiconductor chip comprising an active surface and a region of an integrated circuit on the active surface. A metallic material can at least partially surround the region of the integrated circuit on the active surface laterally, wherein at least a portion of the metallic material is electrically separated from the region of the integrated circuit. An encapsulating material can extend over the active surface and encapsulate at least a portion of the active surface of the semiconductor chip and the metallic material, the encapsulating material extending to a height above the active surface that is greater than a maximum height of the metallic material above the active surface.

[0026] Fig. Figure 6 is a diagram of the clock frequency of an exemplary tilting oscillator according to this disclosure with respect to temperature for a variety of different trim codes. As in Fig. As shown in Figure 6, the clock frequency of the tilting oscillator can remain at least substantially constant between approximately 45 MHz and approximately 50 MHz (e.g., approximately 48 MHz) at temperatures in the range of approximately -40 °C to approximately 94 °C.

[0027] Fig. Figure 7 is a diagram of temperature trim code values ​​required to generate a consistent clock frequency in the tilting oscillator relative to the temperature. As shown in Fig. As shown in Figure 7, trim code values ​​between about 30 and about 35 (e.g. about 32) can produce at least substantially constant frequency responses without requiring any change in the trim codes at temperatures in the range of about -40 °C to about 94 °C.

[0028] Fig. Figure 8 is a diagram of clock frequencies of several tilting oscillators produced according to this disclosure. Batches of tilting oscillators were produced according to this disclosure, including mechanical reinforcement and final packing, and their clock frequencies were measured. As in Fig. As shown in Figure 8, the actual frequencies of the tilting oscillators remained within approximately 0.25% of the target frequency of approximately 48 MHz. More precisely, the actual frequency response lay within 0.1% of the target frequency plus or minus one standard deviation from the mean and within 0.3% of the target frequency plus or minus three standard deviations from the mean.

[0029] Tilting oscillators produced according to this disclosure can represent a significant advance in the cost-efficiency of generating accurate clock frequencies. Manufacturing costs can be reduced by replacing expensive quartz components with integrated circuits and adding mechanical reinforcement. The addition of mechanical reinforcement can also increase the precision with which the final characteristics of the integrated circuit can match the design and target characteristics, thereby achieving more accurate performance results.Cost-effective, high-precision tilting oscillators according to this disclosure can be usefully employed in a wide variety of applications, such as, but not limited to, the internal clocks in microcontroller units (MCUs), external clocks that interface with MCUs, and communication adapters, such as an interface to a host bus for connecting to non-volatile storage / memory. Such MCUs and associated adapters can operate without requiring an external, crystal-based module for the clock signal (e.g., the clock reset signal). In some embodiments, the internal clock of the MCUs can be used to provide a clock frequency for both internal and external functions, and an external, crystal-less clock can be used.As specific, non-restrictive examples, tilting oscillators implemented with MCUs or as external modules for MCUs may be useful in hardware for implementing wired and wireless communication (e.g., according to Universal Serial Bus (USB), Bluetooth®, Ethernet®, FireWire®, etc.) and R-DAC designs.

[0030] Fig.Figure 9 is a schematic representation of a system 180 that includes one or more semiconductor housings 100 according to this disclosure. For example, the system 180 may include a control unit 182 and a probe unit 184. The probe unit 184 may include a sensor device 186 configured to generate an electrical signal representing and responding to a detected physical phenomenon. The probe unit 184 may be a portable device, such as a handheld device. In some embodiments, the probe unit 184 may include a semiconductor device housing 100 according to this disclosure located within the probe unit 184, wherein the semiconductor device housing 100 is configured to process the electrical signal at least partially locally within the probe unit 184 (e.g., to adjust a frequency of a

[0031] to control a signal communication unit configured to transmit data signals from within the probe unit 184 according to an electronic communication protocol. The probe unit 184 can be operationally connected to the control unit 182 (e.g., via a wired or wireless connection) and can send the raw, partially processed, or fully processed electrical signal to the control unit 182. In some embodiments, the control unit 182 can include another semiconductor device housing 100 according to this disclosure or a microprocessor 188 that can receive, decode, or further process the electrical signal. The control unit 182 can include a non-volatile storage device 190 configured to store the results of the fully processed electrical signal. The control unit 182 can optionally include an output device 192 (e.g., a microprocessor).(includes an electronic display, an audio speaker, a printer, etc.) configured to output the results of the fully processed electrical signal.

[0032] The semiconductor device package 100 itself, or one or more of the regions 108 of the integrated circuit, can be configured as a clock module. For example, the semiconductor device package 100, or one or more of the regions 108 of the integrated circuit, can be configured to provide clock timing control to synchronize one or more operations of the semiconductor device package 100, the system 180, another component of the system 180, or a combination thereof. More specifically, the semiconductor device package 100 can include an MCU that has a clock module with a tilting oscillator lacking a crystal oscillator, to synchronize one or more operations of the MCU, another component of the system 180 to which the MCU belongs, or the MCU and one or more other components of the system 180.

[0033] Additional, non-restrictive embodiments within the scope of protection of this disclosure include the following: Embodiment 1: A method for manufacturing a semiconductor device housing, comprising: arranging a metal material at least partially around at least one region of an integrated circuit on an active surface of a semiconductor chip; allowing at least one section of the metal material to remain electrically isolated from the at least one region of the integrated circuit; and encapsulating the semiconductor chip and the metal material in an encapsulation material, wherein the encapsulation material extends to a height above the active surface that is higher than a maximum height of the metal material above the active surface. Embodiment 2: Method according to embodiment 1, wherein the arrangement of the metal material at least partially around the at least one region of an integrated circuit comprises the arrangement of the metal material completely around the at least one region of an integrated circuit, such that the metal material laterally surrounds the at least one region of an integrated circuit. Embodiment 3: Method according to embodiment 1 or embodiment 2, wherein the arrangement of the metal material at least partially around the at least one region of an integrated circuit comprises building up the metal material to the maximum height, wherein the maximum height is greater than or equal to a second-largest maximum height of another structure located above the active surface and encapsulated in the encapsulation material. Embodiment 4: Method according to embodiment 3, wherein the build-up of the metal material comprises successively arranging a masking material over the active surface, structuring the masking material to form trenches or holes, and arranging sections of the metal material in the trenches or holes. Embodiment 5: Method according to one of embodiments 1 to 4, further comprising electrically connecting at least one other section of the metal material to the at least one region of an integrated circuit, wherein the at least one other section of the metal material is electrically separated from the at least one section of the metal material. Embodiment 6: Method according to one of embodiments 1 to 5, wherein the at least one region comprises a plurality of regions, and further comprising arranging the metal material at least partially around each of the plurality of regions of the integrated circuit on the active surface of the semiconductor chip. Embodiment 7: Method according to one of embodiments 1 to 6, further comprising forming the integrated circuit of the at least one region, such that it comprises at least one section of a tilting oscillator. Embodiment 8: Method according to one of embodiments 1 to 7, wherein forming the integrated circuit of the at least one region includes forming a resistor or a capacitor. Embodiment 9: Method according to any one of embodiments 1 to 8, wherein the arrangement of the metal material at least partially around the at least one region of an integrated circuit on the active surface of the semiconductor chip comprises forming a wall, fence or cage of the metal material at least partially around the at least one region. Embodiment 10: Semiconductor device comprising: a semiconductor chip comprising an active surface; at least one region of an integrated circuit on the active surface; and a metal material that at least partially surrounds the at least one region of an integrated circuit on the active surface laterally, wherein at least one section of the metal material is electrically separated from the at least one region of an integrated circuit. Embodiment 11: Semiconductor device according to embodiment 10, wherein the at least one region of an integrated circuit comprises at least one section of a tilting oscillator. Embodiment 12: Semiconductor device according to embodiment 11, wherein the at least one region of an integrated circuit comprises a resistor or a capacitor. Embodiment 13: Semiconductor device according to embodiment 11 or embodiment 12, wherein the metal material is configured to mechanically reinforce the region of an integrated circuit to cause an actual frequency of the tilting oscillator to remain within about 0.25% of a nominal frequency when the semiconductor device is exposed to ambient temperatures in the range of about -40°C to about 94°C. Embodiment 14: Semiconductor device according to one of embodiments 10 to 13, wherein the metal material substantially completely surrounds the at least one region of an integrated circuit laterally. Embodiment 15: Semiconductor device according to one of embodiments 10 to 13, wherein the at least one region comprises a plurality of regions and the metal material at least partially surrounds each of the plurality of regions of an integrated circuit, wherein the metal material forms a lattice when viewed perpendicular to the active surface. Embodiment 16: Semiconductor device according to one of embodiments 10 to 15, wherein at least one other section of the metal material is electrically connected to the at least one region of an integrated circuit, wherein the at least one other section of the metal material is electrically separated from the at least one section of the metal material. Embodiment 17: Semiconductor device according to one of embodiments 10 to 16, wherein the metal material that at least partially surrounds the at least one region of an integrated circuit comprises a wall, fence or cage made of the metal material that extends at least partially around the at least one region. Embodiment 18: Semiconductor device housing comprising: a semiconductor chip comprising an active surface; a region of an integrated circuit on the active surface; a metal material that at least partially surrounds the region of an integrated circuit on the active surface laterally, wherein at least a section of the metal material is electrically isolated from the region of an integrated circuit; and an encapsulation material that extends over the active surface and encapsulates at least a section of the active surface of the semiconductor chip and the metal material, wherein the encapsulation material extends to a height above the active surface that is higher than a maximum height of the metal material above the active surface. Embodiment 19: Semiconductor device housing according to embodiment 18, wherein the region of an integrated circuit comprises at least one section of a tilting oscillator. Embodiment 20: Semiconductor device housing according to embodiment 19, wherein the section of the tilting oscillator comprises a resistor or a capacitor. Embodiment 21: Semiconductor device housing according to embodiment 19 or embodiment 20, wherein the metal material is configured to mechanically reinforce at least one region of an integrated circuit that responds to at least one temperature change induced stress in order to maintain an actual frequency of the tilting oscillator after packing within about 0.25% of a target frequency when the semiconductor device is exposed to ambient temperatures in the region of about -40°C to about 94°C. Embodiment 22: Semiconductor device housing according to one of embodiments 18 to 21, wherein the maximum height is greater than or equal to a second-largest maximum height of another structure located above the active surface and encapsulated in the encapsulation material. Embodiment 23: Semiconductor device housing according to one of embodiments 18 to 22, wherein the metal material completely surrounds the region of an integrated circuit laterally. Embodiment 24: Semiconductor device housing according to one of embodiments 18 to 23, wherein at least one region comprises a plurality of regions and the metal material at least partially surrounds each of the plurality of regions of an integrated circuit on the active surface, wherein the metal material forms a lattice when viewed perpendicular to the active surface. Embodiment 25: Semiconductor device housing according to one of embodiments 18 to 24, wherein the metal material that at least partially surrounds the at least one region of an integrated circuit comprises a wall, fence or cage made of the metal material that extends at least partially around the at least one region. Embodiment 26: Microcontroller unit comprising: a semiconductor device or a semiconductor device housing according to any one of embodiments 10 to 25. Embodiment 27: Microcontroller unit according to embodiment 26, wherein the semiconductor device or semiconductor device housing is configured as a clock module for the microcontroller unit. Embodiment 28: Wired or wireless communication module comprising: a microcontroller unit comprising a semiconductor device or semiconductor device housing according to any one of embodiments 10 to 25. Embodiment 29: Wired or wireless communication module according to embodiment 28, wherein the semiconductor device or semiconductor device housing is configured as a clock module for the microcontroller unit.

Claims

[1] Method for manufacturing a semiconductor device, comprising: Arranging a metallic material completely around each region of a multitude of regions of an integrated circuit on an active surface of a semiconductor chip; wherein at least one section of the metal material remains electrically isolated from each region of an integrated circuit; and Encapsulation of the semiconductor chip and the metal material in an encapsulation material, wherein the encapsulation material extends to a height above the active surface that is higher than a maximum height of the metal material above the active surface. [2] Method according to claim 1, wherein the arrangement of the metal material completely around each region of the plurality of regions of an integrated circuit comprises building up the metal material to the maximum height, wherein the maximum height is greater than or equal to a second-largest maximum height of another structure located above the active surface and encapsulated in the encapsulation material. [3] Method according to claim 2, wherein the build-up of the metal material comprises successively arranging a masking material over the active surface, structuring the masking material to form trenches or holes, and arranging sections of the metal material in the trenches or holes. [4] Method according to any one of claims 1 to 3, further comprising electrically connecting at least one other section of the metal material to at least one region of the plurality of regions of an integrated circuit, wherein the at least one other section of the metal material is electrically separated from the at least one section of the metal material. [5] Method according to any one of claims 1 to 3, further comprising forming the integrated circuit of the plurality of regions, such that it comprises at least one section of a tilting oscillator. [6] Method according to claim 5, wherein forming the integrated circuit of the plurality of regions comprises forming a resistor or a capacitor in at least one region of the plurality of regions. [7] Method according to any one of claims 1 to 3, wherein the arrangement of the metal material completely around each region of the plurality of regions of an integrated circuit on the active surface of the semiconductor chip comprises forming a wall, fence or cage of the metal material completely around each region. [8] Semiconductor device comprising: a semiconductor chip that includes an active surface; a multitude of regions of an integrated circuit on the active surface; and a metallic material that completely surrounds each region of the multitude of regions of an integrated circuit on the active surface laterally, wherein at least one section of the metal material is electrically isolated from each region of an integrated circuit. [9] Semiconductor device according to claim 8, wherein the plurality of regions of an integrated circuit comprises at least one section of a tilting oscillator. [10] Semiconductor device according to claim 9, wherein at least one region of the plurality of regions of an integrated circuit comprises a resistor or a capacitor. [11] Semiconductor device according to claim 9, wherein the metal material is configured to mechanically reinforce the region of an integrated circuit to cause an actual frequency of the tilting oscillator to remain within about 0.25% of a nominal frequency when the semiconductor device is exposed to ambient temperatures in the range of about -40°C to about 94°C. [12] Semiconductor device according to any one of claims 8 to 11, wherein the metal material forms a lattice when viewed perpendicular to the active surface. [13] Semiconductor device according to one of claims 8 to 11, wherein at least one other section of the metal material is electrically connected to at least one region of the plurality of regions of an integrated circuit, wherein the at least one other section of the metal material is electrically isolated from the at least one section of the metal material. [14] Semiconductor device according to any one of claims 8 to 11, wherein the metal material that completely surrounds each region of the plurality of regions of an integrated circuit comprises a wall, fence or cage of metal material that completely extends around each region. [15] Semiconductor device housing, comprising: Semiconductor device according to any one of claims 8 to 11; and an encapsulation material extending over the active surface and encapsulating at least the active surface of the semiconductor chip and the metal material, wherein the encapsulation material extends to a height above the active surface that is higher than a maximum height of the metal material above the active surface. [16] Semiconductor device housing according to claim 15, wherein the plurality of regions of an integrated circuit comprise at least one section of a tilting oscillator. [17] Semiconductor device housing according to claim 16, wherein the section of the tilting oscillator comprises a resistor or a capacitor. [18] Semiconductor device housing according to claim 16, wherein the metal material is configured to mechanically reinforce at least one region of an integrated circuit which responds to at least one temperature change induced stress in order to maintain an actual frequency of the tilting oscillator after packing within about 0.25% of a target frequency when the semiconductor device is exposed to ambient temperatures in the region of about -40°C to about 94°C. [19] Semiconductor device housing according to claim 16, wherein the maximum height is greater than or equal to a second-largest maximum height of another structure located above the active surface and encapsulated in the encapsulation material. [20] Semiconductor device housing according to claim 16, wherein the metal material forms a lattice when viewed perpendicular to the active surface. [21] Semiconductor device enclosure according to claim 16, wherein the metal material that completely surrounds each region of the plurality of an integrated circuit comprises a wall, fence or cage made of the metal material that completely surrounds each region. [22] Clock module, comprising: a semiconductor device according to any one of claims 8 to 11; wherein one or more regions of the plurality of regions of an integrated circuit are operationally configured as a tilting oscillator configured to provide synchronization timing control for the clock module; and an encapsulation material extending over the active surface and encapsulating at least a section of the active surface of the semiconductor chip and the metal material, wherein the encapsulation material extends to a height above the active surface that is higher than a maximum height of the metal material above the active surface. [23] Microcontroller unit comprising: a semiconductor device according to any one of claims 8 to 11; wherein one or more regions of the plurality of regions of the integrated circuit are operationally configured as a tilting oscillator configured to provide synchronization timing control for the microcontroller unit; and an encapsulation material extending over the active surface and encapsulating at least a section of the active surface of the semiconductor chip and the metal material, wherein the encapsulation material extends to a height above the active surface that is higher than a maximum height of the metal material above the active surface.

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