System and method for facilitating operations management in an accelerator network interface controller (NIC)

Abstract

A network interface controller (202, 204, 330, 520), Network Interface Controller - NIC, which includes: a host interface (210, 211, 332) coupling a host device (300); a counter circuit (342) and a trigger logic block (534) for: Receiving a remote direct memory access (RDMA) operation associated with an accelerator (308) of the host device from the host device via the host interface; Determining whether a trigger condition for the RDMA operation has been met based on an indicator received from the accelerator; Increasing a counter value stored by the counter circuit based on the indicator received from the accelerator; Determining whether the trigger condition has been met by comparing the counter value with a threshold indicated by the RDMA operation; and in response to determining that the trigger condition is met: Obtaining a piece of data generated by the accelerator from a predetermined memory location; and Output the RDMA operation, including the data piece as payload or parameter of the RDMA operation.

Description

BACKGROUND area

[0001] This generally relates to the technical field of networking. More specifically, this disclosure relates to systems and methods for facilitating network interface controller (NIC) with efficient operational management for host accelerators. State of the art

[0002] As network-enabled devices and applications become increasingly ubiquitous, different types of traffic and ever-increasing network loads demand ever-increasing performance from the underlying network architecture. For example, applications such as high-performance computing (HPC), media streaming, and the Internet of Things (IoT) can generate different types of traffic with distinct characteristics. As a result, network architects continue to face challenges such as scalability, versatility, and efficiency in addition to traditional network performance metrics such as bandwidth and latency.

[0003] US 2019 / 0042335 A1 relates to technologies for generating triggered conditional event operations.

[0004] US 2017 / 0237672 A1 relates generally to network server systems and, in particular, to systems including servers with hardware accelerator components that can operate independently of server host processors, thus forming a hardware acceleration layer.

[0005] US 2019 / 0042337 A1 refers to technologies for extending the triggered processes.

[0006] Against this background, it is the object of the present disclosure to provide a network interface controller and a method which at least partially solve the disadvantages of known network interface controllers. SUMMARY

[0007] A network interface controller and method having the features of independent claims 1 and 9, respectively, is provided, which is capable of efficiently managing the operation of host accelerators. The network interface controller, hereinafter also referred to as NIC, may be equipped with a host interface and a trigger logic block. During operation, the host interface may connect the NIC to a host device. The trigger logic block may receive an operation from the host device connected to an accelerator of the host device via the host interface. The trigger logic block may determine, based on an indicator received from the accelerator, whether a trigger condition for the operation has been met. If the trigger condition is met, the trigger logic block may obtain a piece of data generated by the accelerator from a memory location and execute the operation using the piece of data. Character list Fig. shows an example network. Fig. shows an example NIC chip with a multitude of NICs. Fig. shows an example architecture of a NIC. Fig. shows an example of the operational management of host accelerators in a NIC. Fig. shows a flowchart of a process for generating a triggered operation in the NIC host device. Fig. shows a flowchart of a triggered operation management process in a NIC. Fig. shows a flowchart of a triggered operation execution process in a NIC. Fig. shows an example computer system equipped with a NIC that enables efficient operation management for host accelerators.

[0008] In the figures, the same numbers refer to the same elements of the figure. DETAILED DESCRIPTION

[0009] Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Therefore, the present invention is not limited to the embodiments shown. Overview

[0010] The present disclosure describes systems and methods that facilitate operational management in a network interface controller (NIC) for host accelerators. The NIC enables a host to communicate with a data-driven network.

[0011] The embodiments described herein solve the problem of facilitating efficient communication operations for an accelerator by (i) having the host processor generate communication operations for the accelerator and (ii) providing the communication operations to the NIC and allowing the accelerator to trigger the operations at the NIC. In this way, the accelerator can communicate without implementing a protocol stack.

[0012] During operation, an application that can run on a NIC host device may issue a command that involves extensive and complex calculations.

[0013] The host device may use an accelerator, such as a graphics processing unit (GPU) or a tensor processing unit (TPU), to efficiently perform such computations. However, an accelerator may facilitate scalar computations, which may not be well-suited to running a communication stack. Furthermore, communicating the computation results to the host processor (e.g., the host device's central processor) may be time-consuming. As a result, issuing communication operations from the accelerator may be inefficient and result in a delay in delivering the computation results to remote devices.

[0014] To solve this problem, the NIC can store communication operations generated by the host processor and allow the accelerator to trigger the operation on the NIC. During operation, the host processor can prepare a communication operation in advance and store the operations in a command queue, which can be stored in the host device's memory. After completing a series of calculations, the accelerator can store the result or output of the calculations in a predetermined location. The storage location can be in the host device's memory or in a memory device of the NIC.

[0015] The NIC may prefetch the operation and store it in a prefetch queue of the NIC. The accelerator may then trigger the operation by notifying the NIC. In response, the NIC may retrieve the communication operation from the NIC's command queue or prefetch queue. The NIC may also retrieve the result from the predetermined location. The NIC may then output the communication operation with the result as a payload or parameter. In some embodiments, the communication operation is a Remote Direct Memory Access (RDMA) operation, such as a "GET" or "PUT" command. In this way, the NIC can facilitate efficient communication operations for the accelerator without requiring the accelerator to implement a communication stack.

[0016] Because the communication operation is a pre-generated operation that can be triggered, such an operation can be referred to as a triggered operation. The NIC can facilitate a triggered operation based on a counter event. The NIC can maintain a counter (e.g., a hardware-implemented counter) and a threshold for the counter event. An interface-based command can cause the NIC to increment the counter. For example, the accelerator can execute multiple threads or processes. When a thread or process completes the assigned computation, the thread or process can issue the interface-based command to the NIC.

[0017] The interface-based command can contain a handle (e.g., a pointer or identifier) to the counter. Upon receiving the command, the NIC can increment the counter. When the counter value becomes greater than or equal to the threshold, the NIC can determine that a trigger condition is met. Accordingly, the NIC can trigger the communication operation. The threshold can correspond to the number of threads (or processes). This allows each thread or process to notify the NIC independently, and the completion of computations for all accelerator threads can serve as a trigger.

[0018] An embodiment of the present invention provides a NIC that can be equipped with a host interface and a trigger logic block. During operation, the host interface can connect the NIC to a host device. The trigger logic block can receive an operation from the host device, which is connected to an accelerator of the host device, via the host interface. The trigger logic block can determine whether a trigger condition for the operation has been met based on an indicator received from the accelerator. If the trigger condition is met, the trigger logic block can obtain a piece of data generated by the accelerator from a memory location and execute the operation using the piece of data.

[0019] In a variation of this embodiment, the memory location comprises one or more of the following: (i) a memory location of a memory device of the host device and (ii) a memory location of a memory device of the NIC.

[0020] In a variation of this embodiment, the NIC may include a counter circuit. The trigger logic block may increment a counter value stored by the counter circuit based on the indicator received from the accelerator.

[0021] In another variant, the trigger logic block can determine whether the trigger condition has been met by comparing the counter value with a threshold specified by the operation.

[0022] In another variant, if the trigger condition has not been met, the trigger logic block can insert the operation into a data structure that stores one or more operations associated with the counter circuit.

[0023] In another variant, the trigger logic block can receive a plurality of indicators from the accelerator and increment the counter value stored by the counter circuit for each indicator.

[0024] In a variation of this embodiment, the trigger logic block may obtain the data based on a DMA (Direct Memory Access) command.

[0025] In a variant of this embodiment, the operation is created before the data is generated.

[0026] In a variation of this embodiment, the trigger logic block may retrieve the operation from a command queue in a storage device of the host device and store the operation in a prefetch queue of the network interface controller.

[0027] In a variation of this embodiment, the host interface may be a PCIe (Peripheral Component Interconnect Express) interface. The trigger logic block may receive the indicator based on a PCIe command.

[0028] In this disclosure, the description in connection with Fig. on the network architecture, and the description in connection with Fig. and following provides further details about the architecture and operations associated with a NIC that supports efficient operations management for host accelerators.

[0029] Fig. shows an example network. In this example, a network 100 of switches, which may also be referred to as a "switch fabric," may include switches 102, 104, 106, 108, and 110. Each switch may have a unique address or ID within the switch fabric 100. Various types of devices and networks may be connected to a switch fabric. For example, a storage array 112 may be connected to the switch fabric 100 via switch 110; an InfiniBand (IB)-based HPC network 114 may be connected to the switch fabric 100 via switch 108; a number of end hosts, such as host 116, may be connected to the switch fabric 100 via switch 104; and an IP / Ethernet network 118 can be connected to the switch fabric 100 via the switch 102. In general, a switch can have edge ports and fabric ports. An edge port can be connected to a device located outside the fabric.A fabric port can be connected to another switch within the fabric via a fabric link. Typically, traffic can enter the switch fabric 100 through an ingress port of an edge switch and exit the switch fabric 100 through an egress port of another (or the same) edge switch. An ingress link can connect a NIC of an edge device (e.g., an HPC end host) to an ingress edge port of an edge switch. The switch fabric 100 can then transport the traffic to an egress edge switch, which can, in turn, forward the traffic to a destination edge device through another NIC. Exemplary NIC architecture

[0030] Fig. shows an example NIC chip with a plurality of NICs. Regarding the example in Fig. A NIC chip 200 may be an application-specific integrated circuit (ASIC) designed for the host 116 to operate with the switch fabric 100. In this example, the chip 200 may provide two independent NICs 202 and 204. A corresponding NIC of the chip 200 may be equipped with a host interface (HI) (e.g., an interface for connecting to the host processor) and a high-speed network interface (HNI) for communicating with a network interface connected to the switch fabric 100. Fig. coupled connection. For example, NIC 202 may include an HI 210 and an HNI 220, and NIC 204 may include an HI 211 and an HNI 221.

[0031] In some embodiments, HI 210 may be a Peripheral Component Interconnect (PCI) or a Peripheral Component Interconnect Express (PCIe) interface. HI 210 may be coupled to a host via a host interconnect 201, which may include N (e.g., N may be 16 for some chips) PCIe Gen 4 lanes capable of operating at signaling rates of up to 25 Gbps per lane. HNI 210 may enable a high-speed network connection 203 that can be coupled to an interconnect in the switch fabric 100 of Fig. can communicate. The HNI 210 can operate at total rates of either 100 Gbit / s or 200 Gbit / s using M (e.g., M can be 4 on some chips) full-duplex serial lanes. Each of the M lanes can operate at 25 Gbit / s or 50 Gbit / s based on non-return-to-zero (NRZ) or pulse amplitude modulation 4 (PAM4), respectively. The HNI 220 supports the Institute of Electrical and Electronics Engineers (IEEE) 802.3 Ethernet-based protocols, as well as an extended frame format that enables higher rates for small messages.

[0032] The NIC 202 can support one or more of the following functions: point-to-point messaging based on the Message Passing Interface (MPI), Remote Memory Access (RMA) operations, offloading and forwarding of bulk data collection operations, and Ethernet packet processing. When the host issues an MPI message, the NIC 202 can correspond to the corresponding message type. In addition, the NIC 202 can implement both the Eager protocol and the Rendezvous protocol for MPI, offloading the corresponding operations from the host.

[0033] Additionally, the RMA operations supported by NIC 202 may include PUT, GET, and Atomic Memory Operations (AMO). NIC 202 may provide reliable transport. For example, if NIC 202 is a source NIC, NIC 202 may provide a retry mechanism for idempotent operations. Furthermore, connection-based error detection and a retry mechanism may be used for ordered operations that may manipulate a target state. The hardware of NIC 202 may maintain the state required by the retry mechanism. In this way, NIC 202 may offload the host (e.g., software). The policy dictating the retry mechanism may be set by the host through the driver software, ensuring the flexibility of NIC 202.

[0034] In addition, the NIC 202 may facilitate triggered operations, a general mechanism for offloading and scheduling dependent sequences of operations, such as bulk data collections. The NIC 202 may support an application programming interface (API) (e.g., libfabric API) that facilitates fabric communication services provided by the switch fabric 100 of Fig. for applications on host 116. NIC 202 may also support a low-level network programming interface, such as Portals API. Furthermore, NIC 202 may provide efficient Ethernet packet processing, which may include efficient transmission when NIC 202 is a sender, flow control when NIC 202 is a destination, and checksum calculation. Furthermore, NIC 202 may support virtualization (e.g., with containers or virtual machines).

[0035] Fig. shows an example architecture of a NIC. In NIC 202, the port macro of HNI 220 may facilitate low-level Ethernet operations, such as Physical Coding Sublayer (PCS) and Media Access Control (MAC). Additionally, NIC 202 may provide support for Link Layer Retry (LLR). Incoming packets may be parsed by parser 228 and stored in buffer 229. Buffer 229 may be a PFC buffer that buffers a threshold (e.g., one microsecond) of delay bandwidth. HNI 220 may also include a control transmit unit 224 and a control receive unit 226 for managing outgoing and incoming packets, respectively.

[0036] The NIC 202 may include a command queuing (CQ) unit 230. The CQ unit 230 may be responsible for fetching and issuing host-side commands. The CQ unit 230 may include command queues 232 and schedulers 234. The command queues 232 may include two independent sets of queues for initiator commands (PUT, GET, etc.) and target commands (Append, Search, etc.), respectively. The command queues 232 may be implemented as circular buffers maintained in the memory of the NIC 202. Applications running on the host may write directly to the command queues 232. The schedulers 234 may include two separate schedulers for initiator commands and target commands, respectively. The initiator commands are sorted into flow queues 236 based on a hash function. One of the flow queues 236 can be assigned to a unique flow.In addition, the CQ unit 230 may include a triggered operations module (or logic block) 238 that is responsible for queuing and dispatching triggered instructions.

[0037] The Outbound Transfer Engine (OXE) 240 may retrieve commands from the expiration queues 236 to process them for dispatch. OXE 240 may include an Address Translation Request Unit (ATRU) 244 that may send address translation requests to the Address Translation Unit (ATU) 212. The ATU 212 may perform virtual-to-physical address translation on behalf of various engines, such as the OXE 240, the Inbound Transfer Engine (IXE) 250, and the Event Engine (EE) 216. The ATU 212 may maintain a large translation cache 214. The ATU 212 may either perform the translation itself or utilize host-based Address Translation Services (ATS). OXE 240 may also include a Message Chopping Unit (MCU) 246 that may fragment a large message into packets of a size equal to a maximum transmission unit (MTU). MCU 246 may include a variety of MCU modules.When an MCU module becomes available, the MCU module can retrieve the next instruction from an allocated execution queue.

[0038] The received data may be written to the data buffer 242. The MCU module may then send the packet header, the corresponding traffic class, and the packet size to the traffic shaper 248. The shaper 248 may determine which of the requests transmitted by the MCU 246 may be forwarded to the network.

[0039] The selected packet may then be sent to the Packet and Connection Trace (PCT) 270. PCT 270 may store the packet in a queue 274. PCT 270 may also maintain status information for outgoing commands and update the status information when responses are returned. PCT 270 may also maintain packet status information (e.g., to match responses with requests), message status information (e.g., to track the progress of messages with multiple packets), initiator completion status information, and retry status information (e.g., to obtain the information needed to retry a command if a request or response is lost). If a response does not return within a specified period of time, the corresponding command may be stored in the retry buffer 272.PCT 270 may facilitate connection management for initiator and target commands based on source tables 276 and target tables 278, respectively. For example, PCT 270 may update its source tables 276 to track the necessary state for reliable packet delivery and message completion notification. PCT 270 may forward outgoing packets to HNI 220, which stores the packets in the outgoing queue 222.

[0040] The NIC 202 may also include an IXE 250, which handles packet processing when the NIC 202 is a target or destination. IXE 250 may retrieve the incoming packets from HNI 220. Parser 256 may parse the incoming packets and forward the appropriate packet information to a List Processing Engine (LPE) 264 or a Message State Table (MST) 266 for matching. LPE 264 may match incoming messages against buffers. LPE 264 may determine the buffer and starting address to be used by each message. LPE 264 may also maintain a pool of list entries 262 used to represent buffers and unexpected messages. MST 266 may store matching results and the information required to generate destination-side completion events. MST 266 can be used by unrestricted operations, including multi-packet PUT instructions and single- or multi-packet GET instructions.

[0041] Parser 256 may then store the packets in packet memory 254. IXE 250 may retrieve the results of the matching for conflict checking. DMA Write and AMO Module 252 may then perform memory updates generated by write and AMO operations. If a packet contains a command that generates target-side memory read operations (e.g., a GET response), the packet may be forwarded to OXE 240. NIC 202 may also include EE 216, which may receive requests to generate event notifications from other modules or devices within NIC 202. An event notification may indicate that either a fill or count event is generated. EE 216 may maintain event queues located in host processor memory to which it writes full events. EE 216 may forward count events to CQ unit 230. Operations management at the NIC

[0042] Fig. shows an example of the operational management of host accelerators in a NIC. In this example, a host device 300 may be equipped with a NIC 330. The device 300 may include a processor 302, a memory device 304, an interface system 306, and a series of accelerators 308. An HI 332 of the NIC 330 may connect to the interface system 306 of the device 330. In some embodiments, the HI 332 may be a PCIe interface, and the interface system 306 may be a PCIe system that provides a slot for the HI 332. The accelerators 308 may include a series of accelerators 312, 314, 316, and 318. An accelerator may be any processing unit capable of performing large-scale and specialized computations, such as a GPU or a TPU.

[0043] Typically, an application capable of running on device 300 may issue a command that involves large and complex computations. Device 300 may use accelerator 312 to efficiently perform such computations. However, accelerator 312 may enable scalar computations that may not be well-suited for executing a communications stack. Furthermore, forwarding the computation results to processor 302 may be time-consuming. As a result, performing communication operations from accelerator 312 may be inefficient and cause a delay in providing the computation results to remote devices via NIC 330.

[0044] To solve this problem, instead of having accelerator 312 maintain a communication stack, processor 302 may generate communication operations for accelerator 312 and forward the communication operations to NIC 330. To communicate with a remote device, accelerator 312 may trigger the operations on NIC 330 and communicate without implementing a communication stack (e.g., a protocol stack). During operation, processor 302 may prepare a communication operation 324 before accelerator 312 needs to trigger operation 324. Processor 302 may store operation 324 in an instruction queue that may be stored in storage device 304. Because operation 324 is a pre-generated operation that can be triggered, operation 324 may be a triggered operation.

[0045] After completing a series of calculations, the accelerator 312 may store the result 322 of the calculations at a predetermined location. The storage location may be in the storage device 304 or in a storage device of the NIC 330. The NIC 330 may prefetch the operation 324 via HI 332 and store the operation 324 in a prefetch queue 334 of the NIC 330. The accelerator 312 may then trigger the operation 324 by notifying the NIC 330. In response, a triggered operation (TO) module 336 may retrieve the operation 324 from the command queue or prefetch queue 334. The TO module 336 may also retrieve the result 322 from the predetermined location. The TO module 336 may then output the operation 324 with the result 322 as a payload or parameter.In this way, the NIC 330 can facilitate efficient communication operations for the accelerator 312 without the accelerator 312 having to implement a communication stack.

[0046] The application does not necessarily need to receive acknowledgment for individual calculations. If NIC 330 can provide acknowledgment indicating that a set of calculations has completed successfully, the application's request can be satisfied. NIC 330 may support an event mechanism, which may be referred to as count events, to enable such cumulative acknowledgment. NIC 330 may facilitate operation 324 based on a count event. TO module 336 may queue and activate triggered operations in NIC 330. NIC 330 may manage a set of hardware-based counters 342 (e.g., a set of 2048 counters). Operation 324 may include a handle (e.g., a pointer or identifier) to a counter 344 in the set of counters 342. Operation 324 may also include a threshold.When counter 344 reaches the threshold, TO module 336 determines that a trigger condition for operation 324 is met. Accordingly, TO module 336 may trigger operation 324.

[0047] After the operation 324 is retrieved from the prefetch queue 334, the TO module 336 may determine whether the operation 324 and the counter 344 belong to the same resource group. If they belong to the same resource group, the TO module 336 may also check whether the current value of the counter 344 is greater than or equal to the threshold. If the threshold is greater, which is typically the case, the TO module 336 may add the operation 324 to the list 340 of triggered operations associated with the counter 344.

[0048] In some embodiments, the list 340 may be sorted based on the corresponding thresholds of the operations in the list 340. Each time the counter 344 is incremented, the TO module 336 may check whether a corresponding operation in the list 340 has reached the threshold set for that operation. In this way, the same counter 344 may be used to represent a plurality of operations. When the value of the counter 344 reaches the threshold associated with the operation 324, the TO module 336 may remove the operation 324 from the list 340 and insert the operation 324 into a corresponding flow queue in the queues for the triggered operation flow 338. NIC 330 may schedule the forwarding of operation 324 from the flow queue, as described in connection with Fig. described.

[0049] In some embodiments, accelerator 312 may perform an interface-based operation (e.g., a PCIe-based transaction) that may increment counter 344. Accelerator 312 may perform the computations by running one or more threads (or processes). Each thread may issue an interface-based command at different stages of the computation. The threads may increment the counter independently of one another without requiring thread synchronization, as each interface-based operation may enable an atomic write via HI 332. Processor 302 may provide a series of triggered operations with different thresholds for the same counter 344. This allows different stages of the computation on accelerator 312 to trigger a corresponding communication operation.

[0050] When counter 344 reaches the threshold of operation 324, NIC 330 may write an indicator to the portion of memory device 304 accessible to threads running on accelerator 312. The indicator may be the threshold. The thread that triggers operation 324 may periodically poll the write-back location. Upon detecting the change in the write-back location, the thread may determine that operation 324 is complete.

[0051] Fig. shows a flowchart of a process for generating a triggered operation in the host device of the NIC. During operation, the host device may generate a triggered operation for an accelerator (operation 402). The host device may then associate a counter event with the triggered operation based on a corresponding counter (operation 404). The host device may then set a threshold for the counter event (operation 406) and store the triggered operation in a local command queue (operation 408).

[0052] Fig. shows a flowchart of a process for managing triggered operations in a NIC. During operation, a TO module of the NIC may retrieve a triggered operation from the command queue and store it in a prefetch queue of the NIC (operation 432). The TO module may then retrieve the triggered operation from the prefetch queue based on the scheduler (operation 434) and identify the counter associated with the triggered operation (e.g., based on the handle) (operation 436). The TO module may determine whether the counter value is less than the threshold (operation 438).

[0053] If the counter value is less than the threshold, the TO module can store the triggered operation in the list of triggered operations (operation 440) and check the counter value at a corresponding increment (operation 442). The TO module can then proceed to determine whether the counter value is less than the threshold (operation 438). If, however, the counter value has reached the threshold, the TO module can set the trigger (operation 444).

[0054] Fig. shows a flowchart of a triggered operation execution process in a NIC. During operation, a TO module of the NIC may determine that an operation has been triggered (operation 452). The TO module may then determine whether the corresponding data is stored in local memory (operation 454). If the data is not stored in local memory, the TO module may obtain the corresponding data from the host device's memory device based on a DMA access (operation 456). Conversely, if the data is stored in local memory, the TO module may obtain the corresponding data from the local memory device based on a DMA access (operation 458). After receiving the corresponding data (operation 456 or 458), the TO module may store the operation and the corresponding data in a corresponding expiration queue (operation 460). Exemplary computer system

[0055] Fig. shows an exemplary computer system equipped with a NIC that enables efficient operation management for host accelerators. Computer system 550 includes a processor 552, a memory device 554, a storage device 556, and an accelerator 558. Memory device 554 may include a volatile memory device (e.g., a dual in-line memory module (DIMM)). Additionally, computer system 550 may be connected to a keyboard 562, a pointing device 564, and a display device 566. Memory device 556 may store an operating system 570. An application 572 may operate with operating system 570.

[0056] Computer system 550 may be equipped with a host interface that couples to a NIC 520, which enables efficient operation management. NIC 520 may provide one or more HNIs to computer system 550. NIC 520 may be coupled to a switch 502 via one of the HNIs. NIC 520 may include a TO logic block 530, as described in connection with Fig. and Fig. described. The TO logic block 530 may include a monitoring logic block 532, a trigger logic block 534, and a forwarding logic block 536.

[0057] Monitor logic block 532 may retrieve a triggered operation from a command queue in memory device 554 and store it in a prefetch queue of NIC 520. The triggered operation may be pre-generated by processor 552 for accelerator 558. Monitor logic block 520 may monitor the state (e.g., a counter for a count event) associated with the triggered operation. Accelerator 558 may change the state of the triggered operation. Trigger logic block 534 may determine from the state whether a condition for triggering the operation has occurred (e.g., the counter has reached a threshold). If the condition has occurred, trigger logic block 534 may trigger the operation and retrieve associated data from a memory location. Forward logic block 536 may then perform a communication operation associated with the triggered operation.

[0058] In summary, the present disclosure describes a NIC that enables efficient operation management for host accelerators. The NIC may be equipped with a host interface and a trigger logic block. During operation, the host interface may connect the NIC to a host device. The trigger logic block may receive an operation from the host device connected to an accelerator of the host device via the host interface. The trigger logic block may determine whether a trigger condition for the operation has been met based on an indicator received from the accelerator. If the trigger condition is met, the trigger logic block may obtain a piece of data generated by the accelerator from a memory location and execute the operation using the piece of data.

[0059] The methods and processes described above may be performed by hardware logic blocks, modules, or devices. The hardware logic blocks, modules, logic blocks, or devices may include, but are not limited to, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), dedicated or shared processors that execute code at a specific time, and other known or later developed programmable logic devices. When activated, the hardware logic blocks, modules, or devices execute the methods and processes contained therein.

[0060] The methods and processes described herein may also be embodied as code or data storable in a memory device or computer-readable storage medium. When a processor reads and executes the stored code or data, the processor may perform these methods and processes.

[0061] The foregoing descriptions of embodiments of the present invention have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the present invention to the forms shown. Accordingly, many modifications and variations will be apparent to those skilled in the art. Furthermore, the present invention is not intended to be limited by the above disclosure. The scope of the present invention is defined by the appended claims.

Claims

[1] A network interface controller (202, 204, 330, 520), Network Interface Controller - NIC, which includes: a host interface (210, 211, 332) coupling a host device (300); a counter circuit (342) and a trigger logic block (534) for: Receiving a remote direct memory access (RDMA) operation associated with an accelerator (308) of the host device from the host device via the host interface; Determining whether a trigger condition for the RDMA operation has been met based on an indicator received from the accelerator; Increasing a counter value stored by the counter circuit based on the indicator received from the accelerator; Determining whether the trigger condition has been met by comparing the counter value with a threshold indicated by the RDMA operation; and in response to determining that the trigger condition is met: Obtaining a piece of data generated by the accelerator from a predetermined memory location; and Output the RDMA operation and include the data piece as payload or parameter of the RDMA operation. [2] The network interface controller of claim 1, wherein the predetermined memory location includes one or more of the following elements: a location of a storage device (304) of the host device and a location of a storage device of the network interface controller. [3] The network interface controller of claim 1, wherein the trigger logic block is further operable, in response to determining that the trigger condition has not been met, to insert the RDMA operation into a data structure storing one or more RDMA operations associated with the counter circuit. [4] The network interface controller of claim 1, wherein the trigger logic block further serves to: to receive a variety of indicators from the accelerator and to increase the counter value stored by the counter circuit for a corresponding indicator. [5] The network interface controller of claim 1, wherein the trigger logic block is further operable to obtain the piece of data based on a direct memory access (DMA) command. [6] The network interface controller of claim 1, wherein the trigger logic block further serves to: to obtain the RDMA operation from a command queue in a memory device of the host device and to store the RDMA operation in a prefetch queue (334) of the network interface controller. [7] The network interface controller of claim 1, wherein the RDMA operation is generated prior to the accelerator generating the piece of data by performing a set of calculations and storing results of the calculations in the predetermined memory location. [8] The network interface controller of claim 1, wherein the host interface is a Peripheral Component Interconnect Express (PCIe) interface; and wherein the trigger logic block is further operable to receive the indicator based on a PCIe command. [9] A method for facilitating efficient operational management in a network interface controller (202, 204, 330, 520), Network Interface Controller - NIC, the method comprising: Obtaining a remote direct memory access (RDMA) operation associated with an accelerator (308) of the host device via a host interface (210, 211, 332) connecting the network interface controller to a host device (300); Determining whether a trigger condition for the RDMA operation has been met based on an indicator received from the accelerator; Increasing a counter value in a counter circuit (342) of the network interface controller based on the indicator received from the accelerator; Receiving a variety of indicators from the accelerator; Increasing the counter value stored by the counter circuit for a corresponding indicator; and in response to determining that the trigger condition is met: Obtaining a piece of data generated by the accelerator from a predetermined memory location and the output of the RDMA operation, including the data piece as payload or parameter of the RDMA operation. [10] The method of claim 9, wherein the storage location includes one or more of the following elements: a location of a storage device (324) of the host device and a location of a storage device of the network interface controller. [11] The method of claim 9, further comprising determining whether the trigger condition has been met by comparing the counter value to a threshold specified by the RDMA operation. [12] The method of claim 9, wherein the method further comprises, in response to determining that the trigger condition has not been met, inserting the RDMA operation into a data structure storing one or more RDMA operations associated with the counter circuit. [13] The method of claim 9, further comprising obtaining the piece of data based on a Direct Memory Access (DMA) command. [14] The method of claim 9, further comprising: Obtaining the RDMA operation from a command queue in a memory device of the host device and Storing the RDMA operation in a prefetch queue (334) of the network interface controller. [15] The method of claim 9, wherein the RDMA operation is generated prior to the accelerator generating the piece of data by performing a set of calculations and storing results of the calculations in the predetermined memory location. [16] The method of claim 9, wherein the host interface is a Peripheral Component Interconnect Express (PCIe) interface; and wherein the method further comprises receiving the indicator based on a PCIe command.

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