NON-LINEAR TOURIST-CONNECTED SLIDING REGISTER
Patent Information
- Application Number
- DE112020003328
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2019-08-28
- Filing Date
- 2020-08-13
- Publication Date
- 2025-03-27
- Estimated Expiration
- 2040-08-13
Smart Images
Figure 00000000_0000_ABST
Abstract
Description
BACKGROUND
[0001] The present invention relates to feedback shift registers and, more particularly, to a nonlinear feedback shift register with sequences of maximum or near maximum length.
[0002] In the field of digital electronic circuits, a linear feedback shift register (LFSR) is a unit for generating sequences of 2 n -1 pseudorandom bits. LFSRs have numerous applications, including cryptography, where they are used for keystream generators, data compression, error detection and correction, and so on.
[0003] An LFSR is a shift register whose input bit is a linear function of its previous state. The most commonly used linear function of individual bits is exclusive-OR (XOR), and the shift register contains an input bit controlled by the XOR of some bits of the entire shift register value. Both hardware and software implementations of LFSRs are common.
[0004] The bit positions that influence the next state are called taps. The rightmost bit of the LFSR is called the output bit. In a Fibonacci LFSR, the taps are sequentially XORed with the output bit and then fed back into the leftmost bit. The sequence of bits in the rightmost position is called the output stream. A maximum-length LFSR produces an n-sequence because it contains all possible 2 n-1 cycles through all states within the shift register, except for the state where all bits are zeros. It is also possible to use XNOR (exclusive NOT OR), which results in an equivalent polynomial counter.
[0005] The arrangement of taps for feedback in an LFSR can be expressed in finite field arithmetic as a polynomial modulo 2, where the coefficients of the polynomial must be 1 or 0, which is called the feedback polynomial.
[0006] LFSRs with maximum period can be generated using a primitive generator polynomial over the binary field. The LFSR has maximum length when the feedback polynomial is primitive, the number of taps is even, and the set of taps is theorem-prime.
[0007] The following table shows the feedback polynomials for n to 24 bits from which maximum-length LFSRs can be constructed. For a given LFSR length, there can be more than one maximum-length tap sequence. Bitnummer (n) der Registerstufe Rückkopplungspolynom Maximum Period (2 n -1) 2 x 2 + x + 1 3 3 x 3 + x 2 + 1 7 4 x 4 + x 3 + 1 15 5 x 5 + x 3 + 1 31 6 x 6 + x 5 + 1 63 7 x 7 + x 6 + 1 127 8 x 8 +x 6 +x 5 +x 4 +1 255 9 x 9 +x 5 +1 511 10 x 10 + x 7 + 1 1023 11 x 11 + x 9 + 1 2047 12 x 12 + x 11 + x 10 + x 4 + 1 4095 13 x 13 + x 12 + x 11 + x 8 + 1 8191 14 x 14 + x 13 + x 12 + x 2 + 1 16383 15 x 15 + x 14 + 1 32767 16 x 16 + x 15 + x 13 + x 4 + 1 65535 17 x 17 + x 14 + 1 131071 18 x 18 + x 11 + 1 262143 19 x 19 + x 18 + x 17 + x 14 + 1 524287 20 x 20 + x 17 + 1 1048575 21 x 21 + x 19 + 1 2097151 22 x 22 + x 21 + 1 4194303 23 x 23 + x 18 + 1 8388607 24 x 24 + x 23 + x 22 + x 17 + 1 16777215
[0008] The "+1" in the polynomial does not correspond to a tap; it corresponds to the input to the first bit. The powers of the expressions refer to the tapped bits, counting from the left. LFSRs with four expressions plus the one require four taps and therefore three XOR gates.
[0009] Now with reference to Fig. 1, an exemplary 8-stage LFSR 100 is shown. The 8 bits 101 to 108 are shown numbered 1 to 8, with the 8th bit being the entire right output bit 108. In the illustrated embodiment, the 8-bit register contains the polynomial x 8 + x 6 + x 5 + x 4+ 1 taps from bits 4, 5, 6, and 8. Each of the taps provides linear feedback using XOR gates 111, 112, 113. Feedback 120 is input to the 1st bit 101.
[0010] One adaptation is a top-down hybrid LFSR generator, where the topmost LFSR tap is XORed with the last tap, and the result is fed to the stage after the topmost tap. The bottommost tap is XORed with the last tap, and the result is fed to the first stage of the shift register. Top-down LFSR generators can be used to reduce the four taps to three (two XORs) as follows: {8,7,−6} {12,9,−4} {13,12,−1} {14,13,−11} {16,14,−7} {19,18,−11} {24,23,−19} where the first number is the number of stages, the second is the top LFSR tap, and the third (specified as negative) is the top LFSR tap.
[0011] With two XOR operations, a hybrid LFSR can in some cases generate a sequence 2 n - 1. However, this requires access to both the middle and the end of the shift register to insert data.
[0012] LFSRs have the disadvantage that their linear complexity is equal to their order. Recently, non-linear feedback shift registers (NLFSRs) have been developed. NLFSRs are a generalization of LFSRs, where a current state is a non-linear function of the previous state. Therefore, the re-entrant bit in NLFSRs is more than just a simple XOR operation of register bits. This removes the rigidity of Galois and Fibonacci taps, as well as other predefined taps, but it must then be ensured that deadlock does not occur and that the registers do not become stuck in a pattern.
[0013] One problem with NLFSRs is to find a systematic procedure for constructing NLFSRs with a guaranteed long period.
[0014] “A List of Maximum Period NLFSRs”, Royal Institute of Technology (KTH), Forum 120, 16440 Kista, Sweden, by Elena Dubrova (hereafter referred to as “Dubrova”) lists NLFSRs that provide sequences of maximum length by using multiple XOR gates and one AND gate. A complete list of n-bit NLFSRs with period 2 is presented. n - 1, n < 25, for three different types of feedback functions with algebraic degree two.
[0015] Dubrova uses many arrangements, one of which is three XOR gates and one AND gate for the bit registers, requiring 4 taps in the maximum-length LFSR, i.e., n = {8, 12, 13, 14, 16, 19, 24} in the range n is less than or equal to 24. Dubrova also uses other arrangements: three XOR gates and two AND gates; five XOR gates and one AND gate; five XOR gates and two AND gates. For the case n = 8, Dubrova shows: three XOR gates and one AND gate with 15 examples; three XOR gates and two AND gates with 18 examples; and five XOR gates and one AND gate with 9 examples.
[0016] Now with reference to Fig. Figure 2 shows an exemplary 8-stage LFSR 200 proposed by Dubrova, yielding a maximum-length sequence, which is just one example of the 15 options she proposes using three XOR and one AND gate. The 8 bits 201 through 208 are shown numbered 1 through 8, with the 8th bit being the entire right output bit 208. The 8-bit register shown contains taps at bits 4, 5, and 8 (T4, T5, T8). The nonlinear feedback 220 is provided with three XORs 211 through 213 and one AND gate 214 as follows: T8 XOR T5 XOR T4 XOR (T5 AND T4). In Dubrova’s notation, where she numbers the taps (7...0), this is “0, 3, 4, (3, 4)”.
[0017] The problem addressed is to minimize the number of gates used in logic feedback while maintaining maximum length sequences in the pseudorandom number generator by using feedback shift registers.
[0018] Feedback shift registers can also be used for problems expressed using Boolean availability. For example, LFSR sequences are used to solve the Hamiltonian cycle problem. Minimizing the number of clauses used to express the LFSR simplifies the problem's solution.
[0019] The document DE 103 47 455 A1 relates to a pseudorandom number generator having the following features: a device for supplying a number of 2n number sequences, where n is greater than or equal to 2; a device for combining the number sequences to obtain an output sequence, the device for combining having the following features: an intermediate processing stage for combining the number sequences to generate an intermediate processing sequence; and a final processing stage for combining a subgroup of k of the number sequences with the intermediate processing sequence to obtain the output sequence, where k is greater than or equal to 1 and less than n.
[0020] Wikipedia entry “Algebraic normal form” concerns algebraic normal forms, their use and the performance of operations on algebraic normal forms (Algebraic normal form. In: Wikipedia, the free encyclopedia. Edited on: September 27, 2018, 16:19 UTC. URL: https: / / en.wikipedia.org / w / index.php?title=Algebraic normal form&oldid=861462217).
[0021] The publication “A List of Maximum Period NLFSRs” concerns a complete list of n-bit NLFSRs with period 2 n -1, n < 25, for three different types of feedback functions with algebraic degree two (D3DUBROVA, Elena: A list of maximum period NLFSRs. 27.03.2012. 9 p. URL: https: / / eprint.iacr.org / 2012 / 166). SUMMARY
[0022] The invention relates to a method according to claim 1 and a system according to claim 5 for using a non-linear feedback shift register (NLFSR) to generate a pseudorandom sequence with at least nearly maximum length for a number of n stages, wherein a maximum length 2 n- 1. The method comprises selecting n, where n requires more than two taps in maximum length linear feedback shift registers; and generating, for the selected n-stage register, a pseudorandom sequence using a logic feedback operation with only a first logic gate and a second logic gate, where two suitable non-end taps are inputs to the first logic gate, an output of the first logic gate and a tap at one end are inputs to the second logic gate, and an output of the second logic gate is used as feedback to a first stage of the n-stage register.
[0023] The first logic gate may be selected from a group consisting of an OR gate and a NAND gate, and the second logic gate is an XOR gate. In other embodiments, the first logic gate is an AND gate and the second logic gate is an XNOR gate.
[0024] For some n, a maximum length sequence with two suitable non-terminal taps can be obtained, and for some other n, a near-maximum length sequence with two suitable non-terminal taps is obtained.
[0025] The method may include acquiring one or more suitable pairs of non-terminal taps by identifying, based on the number of stages n, pair combinations that provide sequences of the n-stage register of at least nearly maximum length. In embodiments, acquiring the one or more suitable pairs of non-terminal taps may include determining a first suitable pair of non-terminal taps comprising a first non-terminal tap A and a second non-terminal tap B; and acquiring a second suitable pair of non-terminal taps as a mirror of the first suitable pair of non-terminal taps in the n-stage register, mirroring a tap sequence [n, A, B] to [n, n - B, n - A].
[0026] Obtaining the one or more suitable pairs of non-terminal taps may comprise using a search program applied to three taps: the terminal tap and two non-terminal taps, using any combination of logical operations except all zeros and subject to an optimization constraint that 1 and 0 are equally likely. The search program may initialize the register to a value other than all zeros and may initialize the register to at most 2 n times until a register state is generated which is an iteration where a length of the sequence is a number of states from a first occasion on which a state was observed to a second occasion on which the state was observed.
[0027] The search program can determine for a sequence with nearly maximum length for a set of taps whether a number of previously observed states 2 n-1 or more. If the number of observed states is 2 n-1 or more, the longest sequence found is the longest possible for this set of taps. If the number of observed states is less than 2 n-1 , a new state is chosen, the sequence is regenerated, and the length is measured; and the search program repeats these steps until all states have been observed or the number of unobserved states is less than the length of the longest sequence found.
[0028] An NLFSR for generating a pseudorandom sequence with at least nearly maximum length for a number of n stages, with a maximum length of 2 n- 1, may comprise an n-stage register, where n requires more than two taps in maximum length linear feedback shift registers; a first logic gate including two inputs, each input connected to a non-end tap of the n-stage register; and a second logic gate including two inputs, a first input connected to an output of the first logic gate and a second input connected to an end tap of the n-stage register, an output of the second logic gate being used as feedback to a first stage of the n-stage register.
[0029] An NLFSR for generating a maximum-length pseudorandom sequence for 8 stages, where the maximum length is 255, may comprise: an 8-stage register; a first logic gate having a first input connected to a first non-end tap A of the 8-stage register and a second input connected to a second non-end tap B of the 8-stage register; and a second logic gate having inputs connected to an output of the first logic gate and to an end tap of the 8-stage register. An output of the second logic gate is used as feedback to a first stage of the 8-stage register, and the first and second non-end taps are located at positions selected from the group consisting of: A = 4, B = 3; A = 5, B = 1; A = 5, B = 4; and A = 7, B = 3.
[0030] An NLFSR for generating a pseudorandom sequence of maximum length for a number of n stages, where the maximum length is 4095, may comprise: a 12-stage register; a first logic gate including a first input connected to a first non-end tap A of the 12-stage register and a second input connected to a second non-end tap B of the 12-stage register; and a second logic gate including inputs connected to an output of the first logic gate and to an end tap of the 12-stage register. An output of the second logic gate is used as feedback to a first stage of the 12-stage register, and the first and second non-end taps are located at positions selected from the group consisting of: A = 7, B = 4; and A = 8, B = 5.
[0031] The foregoing summary is not intended to describe every illustrated embodiment or every implementation of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] The drawings included in this disclosure are incorporated in and constitute a part of the specification. They illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. The drawings merely illustrate typical embodiments and do not limit the disclosure. Fig. Figure 1 is a schematic diagram showing an 8-stage LFSR. Fig. Figure 2 is a schematic diagram showing an 8-stage LFSR with a nonlinear feedback arrangement providing a maximum length sequence. Fig. 3 is a flowchart of an exemplary embodiment of a method for providing an NLFSR according to embodiments of the present disclosure. Fig. 4 is a schematic diagram of a generalized stage NLFSR according to a first embodiment of the present disclosure. Fig. 5 is a schematic diagram of a mirror NLFSR with generalized stages according to a second embodiment of the present disclosure. Fig. 6 is a schematic diagram of a generalized stage completion NLFSR according to a third embodiment of the present disclosure. Fig. 7 is a schematic diagram of a generalized stage completion NLFSR according to a fourth embodiment of the present disclosure. Fig. Figure 8 is a schematic diagram of an 8-stage NLFSR according to the first embodiment of Fig. 4. Fig. 9 is a schematic diagram of an 8-stage NLFSR according to the second embodiment of Fig. 5. Fig. 10 is a schematic diagram of an 8-stage NLFSR according to the third embodiment of Fig. 6. Fig. 11 is a schematic diagram of an 8-stage NLFSR according to the fourth embodiment of Fig. 7. The Fig. 12A to 12C are schematic diagrams showing further details of the registers of the Fig. 8, Fig. 10 and Fig. 11 according to embodiments of the present disclosure. Fig. 13 is a block diagram of an exemplary embodiment of a system according to embodiments of the present disclosure. Fig. 14 is a block diagram of one embodiment of a computer system in which embodiments of the present disclosure may be implemented.
[0033] While various modifications may be made to the embodiments described herein, and the embodiments may take alternative forms, specifics thereof are shown by way of example in the drawings and will be described in detail. It should be understood, however, that the particular embodiments described are not to be construed in a limiting sense. On the contrary, the disclosure is intended to include all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. DETAILED DESCRIPTION
[0034] The described method and system provide a nonlinear feedback shift register (NLFSR) with maximum or near-maximum length sequences for generating a pseudorandom sequence for some registers containing n stages, which, for the maximum length, require more than two taps, typically four or more, for linear feedback shift registers (LFSRs). The four taps for LFSRs use three XOR gates.
[0035] The number of sequences with maximum length is 2 n - 1, where the missing state consists of zeros or, in the case of a complementary logical operation, of ones. "Nearly maximum" is defined in this specification as less than 4% deviation from the maximum length.
[0036] The method and system have been tested up to n = 24, and maximum-length sequences are achieved using the described nonlinear feedback at n = 8 and n = 12 of the group of n-stage registers that require more than two taps for maximum-length sequences in linear feedback arrangements in LFSRs. However, other n-stage registers that require more than two taps for maximum-length sequences in LFSRs may exist for n > 24, and the described arrangements can also be used for these larger values of n.
[0037] The described two-gate nonlinear feedback arrangement can be used by other n-stage registers that require more than two taps for maximum-length sequences in LFSRs, but may only yield sequences of near-maximum length. These can also be useful as a two-gate nonlinear feedback arrangement in a simplified feedback loop.
[0038] A simplified logic operation is provided as feedback in an NLFSR, which provides a minimum number of gates with a maximum or near-maximum length sequence. Instead of three XOR gates of an LFSR, a logical feedback operation of an NLFSR uses a single XOR gate and a single OR gate. The logical feedback of only one OR and only one XOR gate uses the logical OR of two selected non-end taps and XORs this with the end tap as feedback to the first stage. An alternative to XOR and OR is to use XNOR and NOR in an equivalent logical operation.
[0039] As equivalent alternatives to the single XOR gate and the single OR gate in the described NLFSR, their complementary arrangements consisting of a single XNOR gate and a single AND gate, or of a single XOR gate and a single NAND gate, can be used. Complementary arrangements utilize the inverse inputs.
[0040] The complementary representations involve a slightly different but equally useful sequence. The missing state for the maximum length of the original circuit consists only of zeros, since 0 XOR (0 OR 0) = 0, so the entire register remains zeros. The complementary circuit contains only ones as the missing state, since 1 XOR (1 NAND 1) = 1 XOR (0) = 1.
[0041] The inversion can be performed at the output of the XOR (= XNOR) or at the output of the AND (= NAND). Other variations use one or more of the inverted outputs of the flip-flop element shift registers, the Q outputs, to provide the inversions.
[0042] A wide variety of arrangements can be used for equivalent logic arrangements to compute the same operation, such as T8 XOR (!T4 NAND !T5), and the !T4 and !T5 signals can be generated directly from the flip-flop Q outputs. The registers described are intended to handle all two-gate equivalents in their logical operations.
[0043] Considering the logical feedback of only one OR gate and only one XOR gate for a number of n stages (numbered 1 to n), inputs to the XOR gate are the output of stage n and the output of the OR gate, inputs to the OR gate are the output of two suitable stages y1, y2 (y1 < n)), (y2 < n)) and y1 not equal to y2) and the input to stage 1 is the output of the XOR gate.
[0044] Now with reference to Fig. 3, the flowchart shows an exemplary embodiment of the described method 300 for providing an NLFSR.
[0045] In embodiments, method 300 begins by selecting n as the number of stages in the register. This is illustrated at step 301. n requires more than two taps in a maximum-length linear feedback shift register. A standard Fibonacci LFSR requires four or more taps, but can be implemented with three taps using a hybrid LFSR, so n requires more than two taps.
[0046] For a selected n-stage register, method 300 uses logical feedback expressions of only one OR gate and only one XOR gate, where the logical OR of two non-end taps is taken and XORed with the end tap to provide feedback to the first stage at the output. This is illustrated at step 302. In embodiments, the same logical operation is used with an XNOR gate and a NOR gate. In other embodiments, method 300 may use a complementary arrangement of only one XNOR and only one AND, or a complementary arrangement of only one XOR and only one NAND. This is illustrated at step 303.
[0047] The method 300 continues by testing different combinations of candidate pairs of non-terminal taps to determine pair combinations that provide sequences of the n-stage register of maximum or near-maximum length by searching for suitable pairs of non-terminal taps using three taps: the terminal tap and candidate pairs of non-terminal taps, each using three-bit logic operation, subject to the optimization constraint that 1 and 0 are equally likely. This is illustrated at step 304. If 1s were more likely than 0s as outputs for all possible inputs, the outputs would generally contain more 1s than 0s, so the counter could not handle nearly all states.
[0048] For an n-stage register, (n - 1)*(n - 2) / 2 possibilities would have to be considered. The number of possible pairs to search can be determined as follows: selecting the last tap for the XOR, selecting at least one of the n - 1 other taps for the first OR input, selecting at least one of the n - 2 remaining taps for the second input, and dividing the possibilities by 2, since the order of the OR inputs does not matter.
[0049] The register can be initialized to a value other than 0000 (or 1111 in the case of a complementary arrangement of taps) and the register can be used for a maximum of 2 n Execute the function until it generates a previously observed register state. The length of the sequence is the number of states from the first occasion on which this repeated state was encountered to the second occasion.
[0050] If all but one of the possible 2 n were found (all 0000) and the first state follows the last new state found, it is a sequence of maximum length.
[0051] For a sequence with almost maximum length, it can be determined whether the number of states observed so far 2 n -1 or more. If this is the case, any other sequence generated from a different initial state cannot be as long. If this is not the case, a previously unobserved state is chosen, and the sequence is generated again. The length of this sequence is measured, and the process is repeated until all states have been observed or the number of unobserved states is less than the length of the longest sequence found so far.
[0052] The method 300 continues by acquiring one or more suitable pairs of non-terminal taps. This is illustrated at step 305. For each suitable pair of non-terminal taps, the method 300 may identify another suitable pair of non-terminal taps as a mirror of the taps in the n-stage register, mirroring a tap sequence [n, A, B] to [n, n - B, n - A]. This is illustrated at step 306.
[0053] Method 300 continues by using an appropriate pair of non-terminal taps in the register's feedback logic array. This is illustrated at step 307.
[0054] The Fig. 4 to 7 show generalized n-stage NLFSRs 400, 500, 600, 700 with logical feedback operations according to embodiments of the present invention. n is restricted to n-stage registers that require more than two taps for maximum-length sequences in linear feedback arrangements in LFSRs and for which suitable non-terminal taps are found, for example, using the method 300 of Fig. 3.
[0055] Now with reference to Fig. 4, there is shown an exemplary register 400 with a first embodiment of the described logical feedback of only one OR 411 and only one XOR gate 412 for a number of n stages, which are numbered from left to right in the register with "1" 401 to "n" 404.
[0056] The inputs to OR gate 411 are the outputs of two suitable stages "A" 402 and "B" 403, where A, B < n, and A ≠ B, and where A and B are suitable non-terminal taps. The inputs to XOR gate 412 are the outputs of stage n 404 and the output of OR gate 411. The input 420 for stage 1 401 is the output of XOR gate 412.
[0057] Now with reference to Fig. 5, an exemplary register 500 is shown with a second embodiment of the described logical feedback of only one OR gate 511 and only one XOR gate 512 for a number of n stages, numbered from left to right in the register as "1" 501 to "n" 504. The second embodiment is a mirror or inversion of the logical arrangement of the first embodiment.
[0058] The inputs to the OR gate 511 are the outputs of two mirror-like stages, "n - B" 502 and "n - A" 503. The inputs to the XOR gate 512 are the outputs of stage n 504 and the output of the OR gate 511. The input 520 for stage 1 501 is the output of the XOR gate 512.
[0059] Now with reference to Fig. 6, an exemplary register 600 is shown with a third embodiment of a counterpart of the first embodiment. In particular, the described logical feedback of only one AND gate 611 and only one XNOR gate 612 is shown for a number of n stages, numbered from left to right in the register as "1" 601 to "n" 604.
[0060] The inputs to AND gate 611 are the outputs of two suitable stages "A" 602 and "B" 603, where A, B < n, and A ≠ B, and where A and B are suitable non-terminal taps. The inputs to XNOR gate 612 are the outputs of stage n 604 and the output of AND gate 611. The input 620 for stage 1 601 is the output of XNOR gate 612.
[0061] Now with reference to Fig. 7, an exemplary register 700 is shown with a fourth embodiment of a counterpart of the first embodiment. In particular, the described logic feedback of only one NAND gate 711 and only one XOR gate 712 is shown for a number of n stages, numbered from left to right in the register as "1" 701 to "n" 704.
[0062] The inputs to NAND gate 711 are the outputs of two suitable stages "A" 702 and "B" 703, where A, B < n, and A ≠ B, and where A and B are suitable non-terminal taps. The inputs to XOR gate 712 are the outputs of stage n 704 and the output of NAND gate 711. The input 720 for stage 1 701 is the output of XOR gate 712.
[0063] Complementary arrangements of the mirror design of Fig. 5 can also be used. In other words, mirror arrangements of the complementary arrangements of the Fig. 6 and Fig. 7 can also be used.
[0064] In the example of an n-stage register with n up to 24, the set n = {8, 12, 13, 14, 16, 19, 24} represents the registers that require four taps in an LFSR. However, it can be extended to more than 24.
[0065] Examples of existing taps for LFSRs with a maximum length of 2 to 24 are as follows. Note that generators with 8, 12, 13, 14, 16, and 24 bits require 4 taps, and these registers are the focus of the described method and apparatus, although the disclosed methods and apparatus may also apply to generators with other bits. {2,1} {3,2} {4,3} {5,3} {6.5} {7,6} {8,6,5,4} {9.5} {10.7} {11.9} {12,11,8,6} {13,12,10,9} {14,13,11,9} {15,14} {16,14,13,11} {17,14} {18.11} {19,18,17,14} {20.17} {21.19} {22,21} {23.18} {24,23,21,20}
[0066] In this description, taps are designated by a number in a register, with the first stage of the input designated "1" and the final stage designated "n." When describing two consecutive register inputs, "A1" through "An" and "B1" through "Bn" are used.
[0067] Now with reference to Fig. 8 there is an exemplary 8-stage register 800 with the described logical feedback of the first embodiment of Fig. 4. Suitable taps that achieve a maximum length for an 8-stage register 800 using the described logic feedback are as follows: n=8 a=3 b=4, length=255; n=8 a=1 b=5, length=255; n=8 a=4 b=5,length=255; n=8 a=3 b=7,length=255.
[0068] Fig. Figure 8 shows the exemplary suitable non-terminal taps A = 4 804 and B = 5 805. Inputs to the OR gate 811 are the outputs of two suitable stages A = 4 804 and B = 5 805. Inputs to the XOR gate 812 are the outputs of stage n = 8 808 and the output of the OR gate 811. The input 820 for stage 1 801 is the output of the XOR gate 812.
[0069] A1 to A8 are the current states of an 8-stage shift register and B1 to B8 are the corresponding next states: B1=(A4 OR A5) XOR A8 B2=A1 B3=A2 B4=A3 B5=A4 B6=A5 B7=A6 B8=A7
[0070] The illustrated embodiment requires an OR gate and an XOR gate. The taps must be chosen accordingly, but if they are operational, you can use a sequence of 2 n - 1. An 8-level register can generate a maximum of 255 values before repeating.
[0071] After one set of taps has been obtained, others can be generated by mirroring or inverting, e.g. given T8 XOR (T5 OR T4) the result T8 XOR (T3 OR T4) as in Fig. 9 is presented in detail.
[0072] Now with reference to Fig. 9 there is an exemplary 8-stage register 900 with the described logical feedback of the second embodiment of Fig. 5 as a mirror of the embodiment of Fig. 8. The exemplary mirrored suitable non-end taps are n - B = 3 903 and n - A = 4 904. Inputs to OR gate 911 are the outputs of mirrors 3 903 and 4 904. Inputs to XOR gate 912 are the outputs of stage n = 8 908 and the output of OR gate 911. Input 920 for stage 1 901 is the output of XOR gate 912.
[0073] Now with reference to Fig. 10 there is an exemplary 8-stage register 1000 with the described logical feedback of the third embodiment of Fig. 6 a complementary arrangement is shown. Fig. 10 shows a counterpart of the register of Fig. 8.
[0074] Fig. 10 uses the exemplary suitable, non-terminal taps A = 4 1004 and B = 5 1005, which are shown in Fig. 8 can be used. The inputs to the AND gate 1011 are the two outputs of two suitable stages A = 4 1004 and B = 5 1005. The inputs to the XNOR gate 1012 are the outputs of stage n = 8 1008 and the output of the OR gate 1011. The input 1020 for stage 1 1001 is the output of the XNOR gate 1012.
[0075] This complementary arrangement of T8 XNOR (T5 AND T4) can also be mirrored to provide T8 XNOR (T3 AND T4).
[0076] Now with reference to Fig. 11 there is an exemplary 8-stage register 1100 with the described logical feedback of the fourth embodiment of Fig. 7 shows an alternative complementary arrangement. Fig. 11 shows another counterpart of the register of Fig. 8.
[0077] Fig. 11 uses the exemplary suitable, non-terminal taps A = 4 1104 and B = 5 1105, which are shown in Fig. 8 can be used. The inputs to the NAND gate 1111 are the two outputs of two suitable stages A = 4 1104 and B = 5 1105. The inputs to the XOR gate 1112 are the outputs of stage n = 8 1108 and the output of the OR gate 1111. The input 1120 for stage 1 1101 is the output of the XOR gate 1112.
[0078] This complementary arrangement of T8 XOR (T5 NAND T4) can also be mirrored to provide T8 XOR (T3 NAND T4).
[0079] There is a second suitable pair of taps for an 8-bit register and the logical operations are: T8 XOR(T7 OR T3) with mirrors as follows: T8 XOR(T5 OR T1) and counterparts as follows: T8 XNOR(T7 AND T3) T8 XNOR(T5 AND T1) T8 XOR(T7 NAND T3) T8 XOR(T5 NAND T1)
[0080] A maximum length was achieved for a 12-step register as follows: n=12 a=4 b=7,length=4095; n=12 a=5 b=8,length=4095.
[0081] For a 12-stage counter, the described procedure includes an exemplary suitable non-terminal pair of 5 and 8: B1=(A5 OR A8) XOR A12 B2=A1 B3=A2 B4=A3 B5=A4 B6=A5 B7=A6 B8=A7 B9=A8 B10=A9 B11=A10 B12=A11
[0082] For the 12-level register, the logical operations for the appropriate pair of 8 and 5 are: T12 XOR (T8 OR T5) or logical equivalent T12 XNOR (T8 NOR T5) with mirrors as follows: T12 XOR (T7 OR T4) or logical equivalent T12 XNOR (T7 NOR T4) and counterparts as follows: T12 XNOR(T8 AND T5) T12 XNOR(T7 AND T4) T12 XOR(T8 NAND T5) T12 XOR(T7 NAND T4)
[0083] LFSRs can also be used for problems expressed using Boolean availability. For example, LFSR sequences are used to solve the Hamiltonian cycle problem. Minimizing the number of clauses used to express the LFSR simplifies the problem's solution.
[0084] The expression (A4 OR A5) XOR A8 can be coded as just 6 clauses in the conjunctive normal form, for example, all of these 6 clauses must be true: A8|!A4|B1 A8|!A5|B1 !A8|A4|A5|B1 A8|A4|A5|!B1 !A8|A4|!B1 !A8|A5|!B1
[0085] The following table summarizes the suitable taps found at n = 8 and n = 12 that provide sequences of maximum length. Stufe Abgriffe Länge Maximal 8 8,4,3 255 255 8 8,5,1 255 255 8 8,5,4 255 255 8 8,7,3 255 255 12 12,7,4 4095 4095 12 12,8,5 4095 4095
[0086] The Fig. 12A, Fig. 12B and Fig. 12C shows the registers 800, 1000 and 1100 of the Fig. 8, Fig. 10 and 11 in more detail.
[0087] Now with reference to Fig. 12A is the register of Fig. 8800 is shown with the eight stages provided by the D flip-flops 1201 through 1208. Each flip-flop 1201 through 1208 includes a clock input (CLK) 1211, a data input (D) 1212, outputs (Q) 1213, and an inverted output (Q) 1214.
[0088] Fig. Figure 12A shows register 800 with non-terminal taps 804 and 805, terminal tap 808, and the logical feedback operation provided by an OR gate 811 and an XOR gate 812. Register output 1215 is also shown.
[0089] Now with reference to Fig. 12B is the register of Fig. 10 1000 of the first complementary arrangement with the eight stages provided by the D flip-flops 1221 to 1228. Each flip-flop 1221 to 1228 includes a clock input (CLK) 1231, a data input (D) 1232, outputs (Q) 1233, and an inverted output (Q) 1234.
[0090] Fig. Figure 12B shows register 1000 with non-terminal taps 1004 and 1005, terminal tap 1008, and the logical feedback operation provided by an XNOR gate 1012 and an AND gate 1011. Register output 1235 is also shown.
[0091] Now with reference to Fig. 12C is the register of Fig. 11 1100 of the second complementary arrangement is shown with the eight stages provided by the D flip-flops 1241 to 1248. Each flip-flop 1241 to 1248 includes a clock input (CLK) 1251, a data input (D) 1252, outputs (Q) 1253, and an inverted output (Q) 1254.
[0092] Fig. Figure 12C shows register 1100 with non-terminal taps 1104 and 1105, terminal tap 1108, and the logical feedback operation provided by an XOR gate 1112 and a NAND gate 1111. Register output 1255 is also shown.
[0093] The described two-gate nonlinear feedback arrangement can be used by other n-stage registers that require more than two taps for maximum-length sequences in LFSRs, but may only yield sequences of near-maximum length. These can also be useful because the two-gate nonlinear feedback arrangement is a simplified feedback arrangement.
[0094] The following tap and the following sequences of near maximum length were found. Length 8135 (compared to 8191): for n = 13: A = 7, B = 3; A = 8, B = 4 and mirrors A = 10, B = 6; A = 9, B = 5 Length 16244 (compared to 16383) with n = 14: A = 6, B = 1 and mirror A = 13, B = 8 Length 63724 (compared to 65535) with n = 16: A = 12, B = 1 and mirror A = 15, B = 4 Length 508357 (compared to 524287) with n = 19: A = 12, B = 3 and mirrors A = 16, B = 7 Length 16570233 (compared to 16777215) with n = 24: A = 20, B = 3 and mirror A = 21, B = 4 Length 66542149 (compared to 67108863) with n = 26: A = 9, B = 2 and mirrors A = 24, B = 17 Length 133072290 (compared to 134217727) at n = 27: A = 16, B = 4 and mirrors A = 23, B = 11
[0095] In some cases, a hybrid LFSR with two XOR operations can produce a sequence 2 n - 1. However, this has the disadvantage that access to both the middle of the shift register and the end is required to insert data. The NLFSR described only requires access to the end to insert data (although data is read from taps in the middle of the register).
[0096] Based on tests, the following provides examples of the longest non-maximum length sequences with 2 taps, with the maximum possible with 3 (hybrid) or 4 taps given in parentheses. {8,5}:217(255) {12,11}:3255(4095) {13,10}:8001(8191) {14,13}:11811(16383) {16,9}:63457(65535) {19,12}520065(524287) {19,13}520065(524287) {24.19}16766977(16777215) and mirrors (reversals): {8,3}:217(255) {12,1}:3255(4095) {13,1}:8001(8191) {14,1}:11811(16383) {16,7}:63457(65535) {19.6}520065(524287) {19.7}520065(524287) {24.5}16766977(16777215)
[0097] Previously, the minimum consisted of two XOR gates and the longest non-maximum-length sequences with as few taps as specified above. The described method provides a maximum-length sequence or a near-maximum-length sequence with only one OR gate and one XOR gate.
[0098] The described method results in a useful increase in cycle length for a small number of gates.
[0099] The state-of-the-art NLFSR according to Dubrova comprises the following, where the numbers between the commas are taps that are XORed and inside parentheses they are ANDed. 0,1,6,(4,5)x0 XOR x1 XOR x5 XOR(x4 AND x5) 0,3,4,(3,4)x0 XOR x3 XOR x4 XOR(x3 AND x4). 0,3,8,(3,9)x0 XOR x3 XOR x8 XOR(x3 AND x9) 0,4,7,(4,7)x0 XOR x4 XOR x7 XOR(x4 AND x7).
[0100] Dubrova uses the shift register in the other direction, taking the first tap as tap 0, so this can be converted by replacing each number x with n - x.
[0101] Dubrova states this as: A8 XOR A5 XOR A4 XOR (A5 AND A4) compared to the described procedure: A8 XOR(A5 OR A4)
[0102] The described method uses a simpler logical function consisting of an OR and an XOR instead of 3 XOR operations and 1 AND.
[0103] A XOR B XOR C XOR (B AND C) can be simplified as follows: ABC 000=0 001=1 010=1 011=1 100=1 101=1 110=0 111=0 This is the same as: A XOR (B or C)
[0104] Although they are logically equivalent, it was not obvious to Dubrova, an expert, that this simplification was possible. Dubrova's taps, with the exception of those of the form: n, a, b, (a, b), cannot generally be simplified to those of the described procedure.
[0105] These few can be simplified to the described procedure, but this is not obvious. For n = 8, it lists 42 sets of taps, of which only 2 could be simplified to the described procedure, and fails to note these special cases. For n = 12, it lists 36 sets of taps, of which only 1 could be simplified to the described procedure, and fails to note this set as a special case.
[0106] Simplification is the key to the described procedure and the appropriate taps must be chosen to make this possible.
[0107] With reference to Fig. 13 shows a block diagram of a computer system 1300, including a system for providing nonlinear NLFSR arrays with maximum length sequences 1310.
[0108] Computer system 1300 may include at least one processor 1301, a hardware module, or circuitry for performing the functions of the described components, which may be software units executing on the at least one processor. Multiple processors executing parallel processing threads may be provided, enabling parallel processing of some or all of the functions of the components. Main memory 1302 may be configured to provide computer instructions 1303 to the at least one processor 1301 to implement the functionality of the components.
[0109] The system for providing nonlinear NLFSR devices 1310 may include a selection component 1311 for selecting n, where n requires more than two taps in maximum length linear feedback shift registers.
[0110] The system 1310 includes a feedback arrangement component 1312 for arranging a logical feedback operation with only one OR gate and only one XOR gate, wherein the logical OR of two suitable non-terminal taps is utilized and XORed with the terminal tap for feedback to the first stage or a complementary logical operation. A first complementary logical operation consists of only one NAND gate and only one XOR gate, in which the logical operation utilizes the logical NAND of two suitable non-terminal taps and XORed with the terminal tap for feedback to the first stage.A second complementary logical operation consists of only one AND gate and only one XNOR gate, in which the logical operation uses logical AND of two suitable non-end taps and connects them to the end tap via logical XNOR for feedback to the first stage.
[0111] The system 1310 may include a test component 1313 for acquiring one or more suitable pairs of non-terminal taps by testing different combinations of two non-terminal taps to determine pair combinations that provide maximum-length sequences of the n-stage register. The test component 1313 may include a search program 1314 applied to three taps: the terminal tap and two non-terminal taps, using any combination of logical operations, subject to the optimization constraint that 1 and 0 are equally likely. The system 1310 may include a suitable tap pair output component 1315 for outputting pairs of suitable non-terminal taps for use in the feedback arrangement component 1312.
[0112] The system 1310 may use a mirror component 1316 for taking an appropriate pair of non-terminal taps and obtaining another appropriate pair of non-terminal taps as a mirror of the taps in the n-stage register, mirroring the tap sequence [n, A, B] to [n, n - B, n - A].
[0113] Fig. 14 illustrates a block diagram of components of the computer system 1300 of Fig. 13 according to an embodiment of the present invention. It should be clear that Fig. 14 is merely illustrative of one embodiment and is not intended as a limitation on the environments in which different embodiments may be realized. Many modifications may be made to the depicted environment.
[0114] Computer system 1300 may include one or more processors 1402, one or more computer-readable RAMs 1404, one or more computer-readable ROMs 1406, one or more computer-readable storage media 1408, device drivers 1412, a read / write drive or interface 1414, and a network adapter or interface 1416, all interconnected via a communications network 1418. Communications structure 1418 may be implemented using any architecture designed to pass data and / or control information between processors (e.g., microprocessors, communications and network processors, etc.) and system main memory, peripherals, and any other hardware components within the system.
[0115] One or more operating systems 1410 and application programs 1411, such as the NLFSR array provisioning system 1310, are stored on one or more of the computer-readable storage media 1408 for execution by one or more of the processors 1402 via one or more of the respective RAMs 1404 (which typically include cache memory). In the illustrated embodiment, each of the computer-readable storage media 1408 may be a magnetic disk storage device of an internal hard disk, a CD-ROM, a DVD, a memory stick, a magnetic tape, a magnetic disk, an optical disk, a semiconductor storage device such as a RAM, a ROM, an EPROM, a flash memory, or any other computer-readable storage medium capable of storing a computer program and digital information in accordance with embodiments of the invention.
[0116] Computer system 1300 may also include a read / write drive or read / write interface 1414 for reading or writing data to one or more portable, computer-readable storage media 1426. Application programs 1411 on computer system 1300 may be stored on one or more of the portable, computer-readable storage media 1426, read via the respective read / write drive or read / write interface 1414, and loaded into the respective computer-readable storage medium 1408.
[0117] Computer system 1300 may also include a network adapter or network interface 1416, such as a TCP / IP adapter card or a wireless communications adapter. Application programs 1411 on computer system 1300 may be downloaded from an external computer or external storage device over a network (e.g., over the Internet, a local area network, or other wide area or wireless networks) and to the computing device via network adapter or network interface 1416. From network adapter or network interface 1416, the programs may be loaded into computer-readable storage medium 1408. The network may include copper wires, fiber optic cables, wireless transmission, routers, firewalls, switches, gateway computers, and edge servers.
[0118] Computer system 1300 may also include a display screen 1420, a keyboard or keypad 1422, and a computer mouse or touchpad 1424. Device drivers 1412 connect to the display screen 1420 for display, to the keyboard or keypad 1422, to the computer mouse or touchpad 1424, and / or to the display screen 1420 for pressure-sensitive sensing of alphanumeric character input and user selections. Device drivers 1412, the read / write drive or interface 1414, and the network adapter or interface 1416 may include hardware and software stored in the computer-readable storage medium 1408 and / or in the ROM 1406.
[0119] The present invention may be a system, a method, and / or a computer program product with any possible level of integration of technical details. The computer program product may include computer-readable storage medium(s) storing computer-readable program instructions for causing a processor to perform aspects of the present invention.
[0120] The computer-readable storage medium may be any tangible device on which instructions can be stored and retained for use by an instruction-executing device. The computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing.A non-exhaustive list of more specific examples of the computer-readable storage medium includes the following: a portable computer diskette, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable read-only memory in the form of a compact disc (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punched cards or raised structures in a groove with instructions recorded thereon, or any suitable combination of the foregoing.A computer-readable storage medium as used herein shall not be construed as including transient signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., pulses of light traveling through a fiber optic cable), or electrical signals transmitted over a cable.
[0121] Computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to respective computing / processing units or to an external computer or storage unit over a network, for example, the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, fiber optic transmission lines, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface at each computing / processing unit receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing unit.
[0122] Computer-readable program instructions for performing operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including, but not limited to, object-oriented programming languages such as Smalltalk, C++, or the like, and procedural programming languages such as the C programming language or similar programming languages.The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer over any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (for example, over the Internet using an Internet service provider).In some embodiments, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), that execute computer-readable program instructions may be configured to personalize the electronic circuit by utilizing state information of the computer-readable program instructions to perform aspects of the present invention.
[0123] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be appreciated that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, may be implemented using computer-readable program instructions.
[0124] These computer program instructions may be provided to a processor of a computer or other programmable data processing device to produce a machine, such that the instructions, executing via the processor of the computer or other programmable data processing device, provide means for implementing the functions / acts specified in a block(s) of the flowchart(s) and / or block diagram(s). These computer-readable program instructions may also be stored in a computer-readable medium that can direct a computer, other programmable data processing device, or other devices to function in a particular manner, such that the computer-readable medium having instructions stored thereon comprises an article of manufacture containing instructions that implement the functions / acts specified in a block(s).implement the function / action specified in the blocks of the flowcharts and / or block diagrams.
[0125] The computer-readable program instructions may also be loaded into a computer, other programmable data processing apparatus, or other devices to cause a series of operations to be performed on the computer, other programmable devices, or other devices to create a computer-implemented process, such that the instructions executing on the computer, other programmable devices, or devices implement the functions / acts specified in a block or blocks of the flowcharts and / or block diagrams.
[0126] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this context, each block in the flowcharts or block diagrams may represent a module, segment, or section of instructions comprising one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions specified in the block may be executed in a different order than the order specified in the figures.For example, two blocks shown in sequence may actually be executed as one step, executed concurrently, substantially concurrently, in a partially or completely temporally overlapping manner, or the blocks may sometimes be executed in reverse order depending on the functionality associated with the blocks. Furthermore, it should be noted that each block of the block diagrams and / or flowchart illustrations, as well as combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented using dedicated hardware-based systems for performing the specified functions or acts, or using combinations of dedicated hardware and dedicated computer instructions.
[0127] According to a first aspect of the present invention, a method is provided for using a non-linear feedback shift register (NLFSR) with sequences of maximum or near maximum length to generate a pseudorandom sequence for a number of n stages, with a maximum length of 2 n - 1, the method comprising: selecting n, where n requires more than two taps in maximum length linear feedback shift registers; and for the selected n-stage register, using a feedback logic operation with only one OR gate and only one XOR gate, in which the logic operation uses the logical OR of two suitable non-terminal taps and logically XORs them with the terminal tap to feed back to the first stage, or an equivalent logical operation with an XNOR gate and a NOR gate, or a complementary logical operation.
[0128] The method provides the advantage of a simple two-gate logic operation in an NLFSR, providing maximum or near-maximum length sequences for n-stage registers that typically require more than two taps. The method minimizes the number of gates without center feedback to the register, which is required when providing long pseudorandom sequences.
[0129] A first complementary logical operation can consist of only one NAND gate and only one XOR gate, in which the logical operation uses the logical NAND of two suitable, non-terminal taps and connects them with the terminal tap via a logical XOR for feedback to the first stage. Another complementary logical operation can consist of only one AND gate and only one XNOR gate, in which the logical operation uses the logical AND of two suitable, non-terminal taps and connects them with the terminal tap via a logical XNOR for feedback to the first stage.
[0130] For some n, a maximum length sequence with two suitable non-terminal taps or a complementary arrangement is obtained, and for some other n, a best near-maximum length sequence with two suitable non-terminal taps or a complementary arrangement is obtained.
[0131] According to a further aspect of the present invention, a non-linear feedback shift register (NLFSR) is provided with sequences of maximum or near maximum length to generate a pseudorandom sequence for a number of n stages, with a maximum length of 2 n- 1, the method comprising: an n-stage register n, where n requires more than two taps in linear feedback shift registers of maximum length; a logical feedback operation with only one OR gate and only one XOR gate, wherein the logical OR of two suitable non-terminal taps is used and logically XORed with the terminal tap for feedback to the first stage, or an equivalent logical operation with an XNOR gate and a NOR gate, or a complementary logical operation, where the suitable non-terminal taps provide sequences of the n-stage register of maximum or near maximum length.
[0132] A complementary logic operation can consist of only one NAND gate and only one XOR gate, where the logic operation uses the logical NAND of two suitable non-end taps and connects them with the end tap via a logical XOR for feedback to the first stage. Another complementary logic operation can consist of only one AND gate and only one XNOR gate, where the logic operation uses the logical AND of two suitable non-end taps and connects them with the end tap via a logical XNOR for feedback to the first stage. Another counterpart.
[0133] For some n, a maximum length sequence with two suitable non-terminal taps or a complementary arrangement is obtained, and for some other n, a best near-maximum length sequence with two suitable non-terminal taps or a complementary arrangement is obtained.
[0134] According to a further aspect of the present invention, a nonlinear feedback shift register (NLFSR) with maximum length sequences is provided to generate a pseudorandom sequence for a number of n stages, with a maximum length of 2 n- 1, wherein the shift register comprises: an n-stage register, where n is 8 or 12, each requiring more than two taps in linear feedback shift registers of maximum length or; and a logical feedback operation with only one OR gate and only one XOR gate, wherein the logical OR of two suitable non-terminal taps A, B is used and logically XORed with the terminal tap for feedback to the first stage, or an equivalent logical operation with an XNOR gate and a NOR gate, or a complementary logical operation, wherein the suitable non-terminal taps provide sequences of the n-stage maximum length register; wherein the two suitable non-terminal taps are taken from the group consisting of: for n = 8: A = 4, B = 3; A = 5, B = 1; and mirrors A = 5, B = 4; A = 7, B = 3; with n = 12: A = 7, B = 4;and mirrors A = 8, B = 5.;
[0135] The NLFSR for 8-stage and 12-stage registers provides the maximum length sequences with the defined non-end taps.
[0136] A complementary logic operation consists of only one NAND gate and only one XOR gate, in which the logic operation uses the logical NAND of two suitable, non-end taps A, B and connects it with the end tap via logical XOR for feedback to the first stage. Another complementary logic operation consists of only one AND gate and only one XNOR gate, in which the logic operation uses the logical AND of two suitable, non-end taps A, B and connects it with the end tap via logical XNOR for feedback to the first stage.
[0137] According to a further aspect of the present invention, a method is provided for providing a non-linear feedback shift register (NLFSR) with sequences of maximum or near maximum length to generate a pseudorandom sequence for a number of n stages, wherein a maximum length 2 n- 1, the method comprising: selecting n, where n requires more than two taps in maximum-length linear feedback shift registers; for a selected n-stage register, using a logical feedback operation with only one OR gate and only one XOR gate, wherein the logical OR of two suitable non-terminal taps is used and XORed with the terminal tap for feedback to the first stage, or an equivalent logical operation with an XNOR gate and a NOR gate, or a complementary logical operation; and obtaining one or more suitable pairs of non-terminal taps by testing different combinations of two non-terminal taps to determine pair combinations that provide maximum or near-maximum-length sequences of the n-stage register.
[0138] The method may comprise acquiring a suitable pair of non-terminal taps and acquiring another suitable pair of non-terminal taps as a mirror of the taps in the n-stage register, mirroring the tap sequence [n, A, B] to [n, n - B, n - A].
[0139] Obtaining one or more suitable pairs of non-terminal taps may comprise using a search program applied to three taps: the terminal tap and two non-terminal taps, using any combination of logical operations except all zeros and subject to the optimization constraint that 1 and 0 are equally likely.
[0140] The search program initializes the register to a value other than all zeros or all ones in a complementary logical operation and maintains the register at most 2n times until a register state is generated, which is a repetition with the length of the sequence, which is the number of states from a first occasion on which a state was observed to a second occasion on which the state was observed.
[0141] For a sequence with almost maximum length, the search program can determine whether the number of previously observed states 2 n-1 or more; if this is the case, the longest sequence found is the longest possible for this set of taps; if this is not the case, an unobserved state is chosen, the sequence is regenerated, and the length is measured; and these steps can be repeated until all states have been observed or the number of unobserved states is less than the length of the longest sequence found.
[0142] A complementary logic operation consists of only one NAND gate and only one XOR gate, in which the logic operation uses the logical NAND of two suitable, non-end taps and connects them with the end tap via a logical XOR for feedback to the first stage. Another complementary logic operation consists of only one AND gate and only one XNOR gate, in which the logic operation uses the logical AND of two suitable, non-end taps and connects them with the end tap via a logical XNOR for feedback to the first stage.
[0143] According to a first aspect of the present invention, a system is provided for providing a non-linear feedback shift register (NLFSR) with sequences of maximum or near maximum length to generate a pseudorandom sequence for a number of n stages, wherein a maximum length 2 n- 1, the system comprising: selecting a component for selecting n, where n requires more than two taps in maximum length linear feedback shift registers; a feedback arrangement component for arranging a logical feedback operation with only one OR gate and only one XOR gate, using the logical OR of two suitable non-terminal taps and XORing them with the terminal tap for feedback to the first stage, or an equivalent logical operation with an XNOR gate and a NOR gate, or a complementary logical operation;and a test component for acquiring one or more suitable pairs of non-terminal taps by testing different combinations of two non-terminal taps to determine pair combinations that provide sequences of the n-stage register of maximum or near maximum length;
[0144] The system may use a mirror component for using a suitable pair of non-terminal taps and obtaining another suitable pair of non-terminal taps as a mirror of the taps in the n-stage register, mirroring the tap sequence [n, A, B] to [n, n - B, n - A].
[0145] The test component for obtaining one or more suitable pairs of non-terminal taps may comprise a search program applied to three taps: the terminal tap and two non-terminal taps, using any combination of the logical operation except all zeros and subject to the optimization constraint that 1 and 0 are equally likely.
[0146] The search program can be configured to initialize the variables representing the register to a value other than all zeros or all ones in a complementary logical operation and to initialize the register to at most 2 ntimes until a register state is generated, which is a repetition with the length of the sequence, which is the number of states from a first occasion on which a state was observed to a second occasion on which the state was observed.
[0147] The search program can be configured to determine, for a sequence with almost maximum length, whether the number of states detected so far is 2 n-1 or more; if so, the longest sequence found is the longest possible for that set of taps; if not, an unobserved state is chosen, the sequence is regenerated, and the length is measured; and these steps are repeated until all states have been observed or the number of unobserved states is less than the length of the longest sequence found.
[0148] A complementary logic operation consists of only one NAND gate and only one XOR gate, in which the logic operation uses the logical NAND of two suitable, non-end taps and connects them with the end tap via a logical XOR for feedback to the first stage. Another complementary logic operation consists of only one AND gate and only one XNOR gate, in which the logic operation uses the logical AND of two suitable, non-end taps and connects them with the end tap via a logical XNOR for feedback to the first stage.
[0149] According to a further aspect of the present invention, a method is provided for providing a non-linear feedback shift register (NLFSR) with sequences of maximum or near maximum length to generate a pseudorandom sequence for a number of n stages, wherein a maximum length 2 n- 1, wherein the computer program product comprises a computer-readable storage medium containing program instructions embodied thereon, the program instructions being executable by a processor to cause the processor to: select n, where n requires more than two taps in maximum length linear feedback shift registers; for a selected n-stage register, using a logical feedback operation with only one OR gate and only one XOR gate, using the logical OR of two suitable non-terminal taps and XORing them with the terminal tap for feedback to the first stage, or an equivalent logical operation with an XNOR gate and a NOR gate, or a complementary logical operation;and obtaining one or more suitable pairs of non-terminal taps by testing different combinations of two non-terminal taps to determine pair combinations that provide sequences of the n-stage register of maximum or near maximum length;
Claims
[1] Method (300) for using a non-linear feedback shift register (NLFSR) (400; 500; 600; 700; 800; 900; 1000; 1100) to generate a pseudorandom sequence of at least nearly maximum length for a number of n stages (401, 402, 403, 404; 501, 502, 503, 504; 601, 602, 603, 604; 701, 702, 703, 704; 801, 804, 805, 808; 901, 903, 904, 908; 1001, 1004, 1005, 1008; 1101, 1104, 1105, 1108; 1201 - 1208; 12221 - 1228; 1241 - 1248), with a maximum length of 2 n - 1, wherein the method comprises: Selecting (301) n as a number of n stages in the NLFSR, where n requires more than two taps in maximum length linear feedback shift registers; and Generating, for the selected n-stage NLFSR, the pseudorandom sequence using a logic feedback operation with only a first logic gate (411; 511; 611; 711; 811; 911; 1011; 1111) and a second logic gate (412; 512; 612; 712; 812; 912; 1012; 1112), where two non-terminal taps suitable for providing the pseudorandom sequence with at least nearly maximum length are inputs for the first logic gate, where an output of the first logic gate and a tap at one end are inputs for the second logic gate, wherein an output (420; 520; 620; 720; 820; 920; 1020, 1120) of the second logic gate is used as feedback to a first stage (401; 501; 601; 701; 801; 901; 1001; 1101; 1201; 1221; 1241) of the n-stage NLFSR, and the method further comprising: Obtaining one or more pairs of non-terminal taps by detecting, based on the number of stages n, pair combinations that provide sequences of the n-stage NLFSR with at least nearly maximum length, wherein obtaining the one or more pairs of non-terminal taps comprises: Determining (305) a first pair of non-terminal taps comprising a first non-terminal tap A and a second non-terminal tap B; and Obtaining a second pair of non-terminal taps as a mirror of the first pair of non-terminal taps in the n-stage NLFSR, mirroring a tap sequence [n, A, B] to [n, n - B, n - A], where the search program initializes the n-level NLFSR to a value other than all zeros and the n-level NLFSR is at most 2 ntimes until a register state is generated, which is a repetition, where a length of the sequence is a number of states from a first occasion on which a state was observed to a second occasion on which the state was observed, where, for a sequence of near-maximum length at a set of taps, the search program: determines whether a number of previously observed states 2 n-1 or more; if the number of observed states is 2 n-1 or more, the longest sequence found is the longest possible for that set of taps; if the number of observed states is less than 2 n -1, a new state is chosen, the sequence is regenerated, and the length is measured; and These steps are repeated until all states have been observed or the number of unobserved states is less than the length of the longest sequence found. [2] The method of claim 1, wherein a maximum length sequence is obtained with two non-terminal taps. [3] A method according to claim 1 or 2, wherein: the second logic gate is an XOR gate (412; 512; 712; 812; 912; 1112) and the first logic gate is selected from a group consisting of an OR gate (411; 511; 811; 911) and a NAND gate (711; 1111), or the first logic gate is an AND gate (611; 1011) and the second logic gate is an XNOR gate (612; 1012), [4] A method according to any one of the preceding claims, wherein obtaining the one or more pairs of non-terminal taps comprises using a search program applied to three taps: the terminal tap and two non-terminal taps, using any combination of logical operations except all zeros and subject to an optimization constraint that 1 and 0 are equally likely. [5] System for providing a nonlinear feedback shift register (NLFSR) with sequences of maximum or near maximum length to generate a pseudorandom sequence for a number of n stages, with a maximum length of 2 n - 1, where the system has: a processor; and a computer-readable storage medium connected to the processor for data transmission purposes and having stored thereon program instructions which, when executed by the processor, cause the processor to perform a method according to any one of claims 1 to 4.
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Patent Citations
pseudorandom number generator for a stream cipher
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